WO2018149142A1 - 薄膜晶体管及其制备方法、阵列基板、显示面板 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示面板 Download PDF

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Publication number
WO2018149142A1
WO2018149142A1 PCT/CN2017/103911 CN2017103911W WO2018149142A1 WO 2018149142 A1 WO2018149142 A1 WO 2018149142A1 CN 2017103911 W CN2017103911 W CN 2017103911W WO 2018149142 A1 WO2018149142 A1 WO 2018149142A1
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Prior art keywords
substrate
layer
light blocking
film transistor
thin film
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PCT/CN2017/103911
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English (en)
French (fr)
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高吉磊
蒋学兵
孙松梅
吴鹏
赵剑
张杨
陈沫
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/766,570 priority Critical patent/US10636816B2/en
Publication of WO2018149142A1 publication Critical patent/WO2018149142A1/zh
Priority to US16/827,151 priority patent/US11233070B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • At least one embodiment of the present disclosure is directed to a thin film transistor and a method of fabricating the same, an array substrate, and a display panel.
  • a thin film transistor is used as a driving element of a display panel.
  • the active layer in the thin film transistor is irradiated with light, photo-generated carriers are generated, which causes an increase in leakage current of the thin film transistor, thereby affecting the quality of the display screen of the display panel, for example, crosstalk, afterimage, and the like.
  • At least one embodiment of the present disclosure provides a thin film transistor including: a substrate substrate; and a gate electrode, a gate insulating layer, an active layer, and a source/drain electrode layer disposed on the substrate, the source and drain electrodes
  • the layer includes a source electrode and a drain electrode, wherein the thin film transistor further includes a light blocking layer disposed around the active layer.
  • the light blocking layer and the source/drain electrode layer may be disposed in the same layer and the same material; or the light blocking layer and the active layer may be in the same layer. And the same material settings.
  • the light blocking layer may be connected to one of the source electrode and the drain electrode, and one of the source electrode and the drain electrode Interspersed.
  • the light blocking layer in a case where the light blocking layer is disposed in the same layer as the active layer, the light blocking layer is spaced apart from the active layer.
  • the light blocking layer may include an insulating material.
  • a distance from a surface of the light blocking layer away from the substrate substrate to the substrate substrate is greater than or equal to a distance from the lining of the active layer.
  • a distance from a surface of the base substrate to the base substrate; and/or a distance from a surface of the light blocking layer adjacent to the base substrate to the base substrate is less than or equal to a proximity of the active layer The distance from the surface of the base substrate to the substrate substrate.
  • an orthographic projection of the light blocking layer on the base substrate is located within an orthographic projection of the gate electrode on the substrate.
  • an orthographic projection of the light blocking layer on the base substrate is outside an orthographic projection of the gate electrode on the base substrate.
  • the light blocking layer may include a plurality of divided portions that are disposed apart from each other in a direction parallel to the base substrate. The active layer is blocked by the light blocking layer.
  • At least one embodiment of the present disclosure provides an array substrate including any of the thin film transistors described above.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines and the plurality of data lines cross each other to define a plurality of sub-pixel regions.
  • Each of the sub-pixel regions includes the thin film transistor and a pixel electrode, the gate electrode of the thin film transistor is electrically connected to a corresponding one of the gate lines, and the source electrode is electrically connected to a corresponding one of the data lines, and The drain electrode is electrically connected to the pixel electrode; and each of the sub-pixel regions includes a display region and a non-display region, and the light blocking layer is located in the non-display region of each of the sub-pixel regions.
  • one end of the light blocking layer is connected to the data line, and the other end is spaced apart from the drain electrode.
  • the light blocking layer may be disposed around the thin film transistor.
  • At least one embodiment of the present disclosure provides a display panel including any of the above array substrates and a counter substrate disposed on the array substrate.
  • a spacer may be disposed between the opposite substrate and the array substrate, and the spacer is perpendicular to the thin film transistor on the array substrate. Opposed in the direction of the array substrate, and the spacer may include a light shielding material.
  • the light shielding material may include carbon black and/or black resin.
  • At least one embodiment of the present disclosure provides a method of fabricating a thin film transistor, including: providing a base substrate; and forming a gate electrode, a gate insulating layer, an active layer, and a source/drain electrode layer on the base substrate, the source The drain electrode layer includes a source electrode and a drain electrode; wherein the method further includes forming a light blocking layer around the active layer.
  • 1a is a top plan view of a sub-pixel region of an array substrate
  • FIG. 1b is a schematic cross-sectional view of the thin film transistor in the sub-pixel region shown in FIG. 1a along the A-B direction;
  • FIG. 2a is a top view of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2b is a schematic cross-sectional view of the thin film transistor of FIG. 2a along the C-D direction;
  • FIG. 2c is another schematic cross-sectional view of the thin film transistor of FIG. 2a along the C-D direction;
  • 3(a) to 3(c) are schematic views of a light blocking layer in a thin film transistor according to an embodiment of the present disclosure
  • FIG. 4 is another schematic diagram of a light blocking layer in a thin film transistor according to an embodiment of the present disclosure
  • FIG. 5 is a top view of a sub-pixel region in an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a process diagram of a method of fabricating a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 1a is a top plan view of a sub-pixel region of an array substrate.
  • the gate line 1 and the data line 2 cross each other to define a sub-pixel area
  • the sub-pixel area includes a thin film transistor and a pixel electrode 200
  • the thin film transistor is connected to the pixel electrode 200.
  • FIG. 1b is a schematic cross-sectional view of the thin film transistor in the sub-pixel region shown in FIG. 1a along the A-B direction.
  • the gate electrode 110 disposed under the active layer 130 may block light incident on the active layer 130 from below the active layer 130.
  • a black matrix (not shown) may be disposed over the active layer 130 to block light incident on the active layer 130 from above the active layer 130.
  • the gate insulating layer 120 and the passivation layer 160 are generally transparent materials, the side surface of the active layer 130 is still exposed to light (indicated by an arrow in FIG. 1b). Therefore, it is still impossible to prevent the light from being irradiated to the side surface of the active layer 130 in the thin film transistor shown in FIGS. 1a and 1b, and a large amount of photogenerated carriers are still generated in the active layer 130.
  • At least one embodiment of the present disclosure provides a thin film transistor, a method of fabricating the same, an array substrate, and a display panel to solve the above problems.
  • the thin film transistor includes a base substrate and a gate electrode, a gate insulating layer, an active layer, and a source/drain electrode layer disposed on the base substrate, the source/drain electrode layer including a source electrode and a drain electrode, wherein the thin film transistor further A light blocking layer disposed around the active layer is included.
  • each direction is based on the substrate substrate in the thin film transistor.
  • the "upper surface” is a surface away from the substrate
  • the “lower surface” is a surface close to the substrate
  • its “side surface” The surface is a surface sandwiched between the upper surface and the lower surface.
  • the direction of "lateral” is parallel to the surface of the substrate substrate, and the directions of "above” and “below” It is perpendicular to the surface direction of the base substrate, and “above” is the side of the active layer away from the substrate, and “below” is the side of the active layer close to the substrate.
  • FIG. 2a is a top view of a structure of a thin film transistor according to an embodiment of the present disclosure.
  • the thin film transistor includes an active layer 130, a source/drain electrode layer 140, and a light blocking layer 150.
  • the source/drain electrode layer 140 includes a source electrode 141 and a drain electrode 142 electrically connected to the active layer 130, respectively.
  • the light blocking layer 150 is disposed around the active layer 130 to block light from being irradiated onto the side surface of the active layer 130.
  • the thin film transistor may further include a structure of a base substrate, a gate electrode, a gate insulating layer, and the like; further, embodiments of the present disclosure do not limit the type of the thin film transistor, for example, the above implementation.
  • the light blocking layer 150 in the example can be applied to a bottom gate type thin film transistor, a top gate type thin film transistor, or a double gate type thin film transistor, etc., as long as the light blocking layer can block light from entering the side of the active layer 130 of the thin film transistor. It can be on the surface.
  • the light shielding layer 150 is disposed to block the light from being irradiated onto the side surface of the active layer 130.
  • the light blocking layer 150 is disposed such that a part of the side surface of the active layer 130 is not irradiated with light; or the light blocking layer 150 It is set such that all side surfaces of the active layer 130 are not irradiated with light.
  • the embodiment of the present disclosure does not limit the range in which the light blocking layer 150 can block the side surface of the light-irradiating active layer 130, as long as the arrangement of the light blocking layer 150 can reduce the irradiation of the active layer 130 by light.
  • the light blocking layer 150 can block light from being irradiated onto the upper surface and/or the lower surface of the active layer 130 except that the blocking light is irradiated onto the side surface of the active layer 130.
  • the manner in which the light blocking layer 150 is disposed is not limited.
  • the light blocking layer 150 may be separately provided; for example, in other embodiments of the present disclosure, the light blocking layer 150 may be simultaneously prepared during the process of preparing the thin film transistor.
  • different ways of setting the light blocking layer 150 will be described separately.
  • the light blocking layer 150 may be disposed around the active layer 130 alone.
  • the light blocking layer 150 may be formed of any material having a light blocking function.
  • the light blocking layer 150 may be formed of an insulating material having a light blocking function, such as a black resin.
  • the light blocking layer may be formed of a conductive material (for example, metal) or a semiconductor material having a light blocking function.
  • the light blocking layer 150 and the active layer 130 are formed of the same material and disposed in the same layer, or the light blocking layer 150 and the source and drain electrode layer 140 are formed of the same material and are disposed in the same layer. .
  • the active layer 130 and the light blocking layer 150 can be simultaneously formed by the same patterning process or the source/drain electrode layer 140 and the light blocking layer 150 can be simultaneously formed by the same patterning process.
  • providing the light blocking layer 150 in the thin film transistor does not increase the manufacturing process steps of the thin film transistor, and the cost can be saved.
  • the light blocking layer 150 is in the same layer as the active layer 130 and is of the same material.
  • the light-blocking layer 150 prepared from the same material as the active layer 130 generates photo-generated carriers under the illumination of light, so it is necessary to space the light-blocking layer 150 from the active layer 130 to avoid the light-blocking layer 150.
  • the photogenerated carriers generated in the movement move into the active layer 130.
  • the thickness of the light blocking layer 150 and the thickness of the active layer 130 are the same, whereby the light blocking layer 150 and the active layer 130 can be easily formed simultaneously by one patterning process.
  • the light blocking layer 150 is in the same layer and the same material as the active layer 130, and the thickness of the light blocking layer 150 is greater than the thickness of the active layer 130, so that not only can be blocked parallel to the lining.
  • Light of the base substrate is irradiated to the side surface of the active layer 130 and light that is incident in the oblique direction with respect to the base substrate 100 can be blocked from being irradiated onto the side surface of the active layer 130 to further increase the shading of the active layer 130. effect.
  • a semi-conductive film for forming the active layer 130 may be patterned using a two-tone mask (for example, a halftone mask or a gray tone mask) to simultaneously form the light blocking layer 150 and the active layer 130.
  • the thickness of the light layer 150 is greater than the thickness of the active layer 130.
  • a semiconductor thin film is formed on the base substrate 100; a photoresist is coated on the semiconductor thin film, and the photoresist is exposed and developed using a two-tone mask to obtain a completely retained portion of the photoresist, and the photoresist portion is retained.
  • a portion and a photoresist completely removed portion a photoresist completely remaining portion corresponding to a region where the light blocking layer 150 is to be formed, a photoresist portion remaining region corresponding to a region where the active layer 130 is to be formed, and a photoresist completely removed region corresponding to In other regions; performing a first etching to remove a portion of the semiconductor film from which the photoresist is completely removed; performing an ashing process to remove the photoresist remaining in the photoresist portion and leaving the photoresist completely retained by the portion of the photoresist The encapsulation is thinned; a second etching is performed to remove a portion of the semiconductor film remaining in the photoresist portion to obtain the active layer 130; and the photoresist remaining in the photoresist is removed to obtain the light blocking layer 150.
  • the light blocking layer 150 is in the same layer as the source and drain electrode layer 140 and is of the same material.
  • the source/drain electrode layer 140 and the light blocking layer 150 may be formed of metal.
  • the thickness of the light blocking layer 150 is the same as the thickness of the active layer 130.
  • the thickness of the light blocking layer 150 is greater than the thickness of the active layer 130, so that not only the light parallel to the base substrate 100 is irradiated to the side surface of the active layer 130 but also the oblique direction with respect to the base substrate 100 can be blocked. The incident light is irradiated onto the side surface of the active layer 130 to further enhance the light shielding effect on the active layer 130.
  • the thickness of the light blocking layer 150 and the active layer 130 can be made larger than that of the active layer 130.
  • the light blocking layer 150 does not need to use a two-tone mask, so that the manufacturing process can be further simplified.
  • the light blocking layer 150 in a case where the light blocking layer 150 is disposed in the same layer and the same material as the source/drain electrode layer 140, the light blocking layer 150 is spaced apart from at least one of the source electrode 141 and the drain electrode 142. .
  • the light blocking layer 150 in the case where the light blocking layer 150 is disposed in the same layer and the same material as the source/drain electrode layer 140, the light blocking layer 150 cannot be connected to both the source electrode 141 and the drain electrode 142 to prevent the light blocking layer from being the source electrode and The drain electrode is connected.
  • the light blocking layer 150 is spaced apart from one of the source electrode 141 and the drain electrode 142 included in the source/drain electrode layer 140 to be connected to the other; in this case, The light blocking layer 150 is connected to one of the source electrode 141 and the drain electrode 142, so the light blocking layer 150 may be integrally formed with one of the source electrode 141 and the drain electrode 142 to further simplify the fabrication process, and the light blocking layer 150 may be The connected source electrode 141 or drain electrode 142 cooperate to better block light from being incident on the active layer 130. For example, as shown in FIG. 2a, the light blocking layer 150 is connected or integrally formed with the source electrode 141, and is disconnected from the drain electrode 142.
  • the light blocking layer 150 is disconnected from the drain electrode 142, so that there is a gap 170 between the light blocking layer 150 and the drain electrode 142, and light may be incident on the active layer 130 through the gap 170;
  • the width of the gap 170 is made as small as possible, for example the width of the gap 170 can be on the order of a few microns.
  • the thin film transistor may include a base substrate 100 and a gate electrode 110, a gate insulating layer 120, an active layer 130, and a source/drain electrode layer (on the 2b in FIG. 2b), which are sequentially disposed on the base substrate 100. ), the light blocking layer 150 and the passivation layer 160.
  • FIG. 2c is another schematic cross-sectional view of the thin film transistor of FIG. 2a along the C-D direction.
  • the distance of the surface of the light blocking layer 150 away from the substrate 100 to the substrate 100 is greater than or equal to the distance from the substrate 100 of the active layer 130 .
  • the distance from the surface to the substrate 100; and/or the distance of the surface of the light blocking layer 150 from the substrate 100 to the substrate 100 is less than or equal to the surface of the active layer 130 close to the substrate 100 to the substrate The distance of the substrate 100. In this way, it is possible to block light from being irradiated onto the active layer 130 more effectively.
  • the light blocking layer 150 is disposed to overlap with the gate electrode 110.
  • an orthographic projection of the light blocking layer 150 on the substrate substrate 100 is located on the gate electrode 110.
  • the height of the light blocking layer 150 is increased to block the irradiation of the active layer 130 from above the light blocking layer 150.
  • the light blocking layer 150 is disposed not to overlap the gate electrode 110.
  • the orthographic projection of the light blocking layer 150 on the substrate substrate 100 is outside the orthographic projection of the gate electrode 110 on the substrate substrate 100, so that the end of the light blocking layer 150 close to the substrate substrate 100 can be reduced to the lining.
  • the distance of the base substrate 100 reduces the gap between the light blocking layer 150 and the base substrate 100, thereby further blocking the irradiation of the active layer 130 from below the light blocking layer 150.
  • the pattern shape of the light blocking layer 150 can be of various types.
  • the shape of the light blocking layer 150 parallel to the cross section of the base substrate 100 may include one or a combination of an elongated shape, an L shape, a circular arc shape, and the like.
  • the embodiment of the present disclosure does not limit the pattern shape of the light blocking layer 150 as long as it can shield the side surface of the active layer 130 from light without affecting the performance of the thin film transistor.
  • the cross-sectional shape of the light blocking layer 150 may be an elongated shape, an L shape, and a circular arc shape, respectively.
  • the cross-sectional shape of the light-blocking layer 150 may be a combination of the above-mentioned various pattern types.
  • the light-blocking layer 150 in the thin film transistor in FIG. 3( a ) is taken as an example, and the first portion 151 is taken as an example.
  • the second portion 152 may be replaced by the elongated shape shown in FIG. 3(a) to the L shape shown in FIG. 3(b) or the circular arc shape shown in FIG. 3(c).
  • the light blocking layer 150 may be connected end to end to form a seal. Closed patterns, such as the "mouth" shape.
  • the light blocking layer 150 includes a plurality of sub-sections separated from each other, and the light blocking layer 150 including the plurality of sub-sections may block the active layer 130 in a direction parallel to the substrate.
  • the plurality of sections may be arranged such that the active layer may be blocked by the light blocking layer 150 in all directions parallel to the substrate.
  • the plurality of sections of the light blocking layer 150 do not overlap in a direction parallel to the base substrate 100. In this way, the footprint of the light blocking layer 150 can be reduced.
  • the plurality of sections of the light blocking layer 150 are overlapped in a direction parallel to the base substrate 100 such that the active layer 130 is in all directions parallel to the base substrate 100. Blocked by the light blocking layer 150.
  • FIG. 4 is another schematic diagram of a light blocking layer of a thin film transistor according to an embodiment of the present disclosure.
  • the light blocking layer 150 includes a first portion 151 and a second portion 152 which are sequentially disposed in a direction parallel to the substrate 100 on one side of the active layer 130, and block the light.
  • the layer 150 includes, on the other side of the active layer 130, a third portion 153 and a fourth portion 154 which are disposed in an overlapping manner in a direction parallel to the substrate 100, and the first portion 151, the second portion 152, and the third portion
  • the sub-portion 153 and the fourth sub-portion 154 cooperate to block the active layer 130 from being blocked by the light-blocking layer 150 in all directions parallel to the base substrate 100, so that light can be more effectively prevented from being irradiated onto the active layer 130, In particular, it is more effective to prevent light from being irradiated onto the side surface of the active layer 130. For example, as shown in FIG.
  • the first portion 151 of the light blocking layer 150 is connected to the source electrode 141 and disconnected from the drain electrode 142, and the second portion 152 of the light blocking layer 150 is disconnected from the source electrode 141 and is connected to the drain electrode.
  • the first sub-section 151 and the second sub-section 152 are overlapped in a direction parallel to the base substrate 100; in this case, the first sub-section 151 may block between the second sub-section 151 and the source electrode 141
  • the gap of the second portion 152 can block the gap between the first portion 151 and the drain electrode 142, such that the light blocking layer 150 can completely block the illumination of the side surface of the active layer 130 by light.
  • Embodiments of the present disclosure provide an array substrate, which may include the thin film transistor of any of the above embodiments.
  • the array substrate may further include a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines crossing each other to define a plurality of sub-pixel regions, each of the sub-pixel regions including the a thin film transistor and a pixel electrode, wherein a gate electrode of the thin film transistor is electrically connected to a corresponding gate line, a source electrode is electrically connected to a corresponding data line, and a drain electrode is electrically connected to the pixel electrode; and each sub-pixel region includes a display area and a non-display Area, light barrier is located in each A non-display area of a sub-pixel area.
  • the gate lines, the data lines, and the thin film transistors may all be located in the non-display area of the sub-pixel area, and the pixel electrodes may be located in the display area of the sub-pixel area.
  • FIG. 5 is a schematic structural diagram of a sub-pixel region in an array substrate according to an embodiment of the present disclosure, which is a partial schematic diagram of a sub-pixel region.
  • the sub-pixel region of the array substrate includes gate lines 1 and data lines 2, pixel electrodes 200, and thin film transistors (including the active layer 130, The source/drain electrode layer 140) and the light blocking layer 150 include a source electrode 141 and a drain electrode 142.
  • the source electrode 141 is electrically connected to the data line 2, and the gate electrode of the thin film transistor (not shown in FIG. 5)
  • the gate line 1 is electrically connected
  • the drain electrode 142 is electrically connected to the pixel electrode 200
  • the thin film transistor functions as a switching element to control the switching of the pixel electrode 200.
  • each sub-pixel region of the array substrate includes a display region and a non-display region
  • the pixel electrode 200 is disposed in the display region
  • the thin film transistor and the light blocking layer 150 are disposed in the non-display region.
  • the light blocking layer 150 may be disposed around the active layer 130 as in the above embodiment regarding the thin film transistor; in this case, the light blocking layer 150 may be disposed to be parallel to Only the side surface of the active layer 130 is blocked in the direction of the base substrate 100 without blocking the side surfaces of the source electrode 141, the drain electrode 142, and/or the gate electrode 110, in other words, the light blocking layer 150 may be disposed to surround only the active layer. 130 does not surround the source electrode 141, the drain electrode 142, and/or the gate electrode 110.
  • the light blocking layer 150 is disposed around the thin film transistor; in this case, the light blocking layer 150 may be disposed to block the active layer 130, the source electrode 141, the drain electrode 142, and the gate in a direction parallel to the base substrate 100.
  • the side surface of the electrode 110 in other words, the light blocking layer 150 may be disposed to surround the source layer 130, the source electrode 141, the drain electrode 142, and the gate electrode 110.
  • the dotted line region T indicates the region where the thin film transistor is located, and the light blocking layer 150 may be disposed around the region T to shield the side surface of the entire thin film transistor from light.
  • the fifth portion 155 and the sixth portion 156 of the light blocking layer 150 as shown in FIG. 5 are located around the thin film transistor to block the side surface of the thin film transistor, so that the active layer 130 in the thin film transistor can also be blocked. The side surface is protected from light.
  • the thin film crystal is disposed.
  • the pattern type of the light blocking layer 150 around the tube reference may be made to the pattern type of the light blocking layer in the foregoing embodiment (the embodiment of the present disclosure regarding the thin film transistor), which will not be described herein.
  • one end of the light blocking layer 150 may be connected to the data line, and the other end may be spaced apart from the drain electrode.
  • the fifth sub-section 155 of the light-blocking layer 150 is taken as an example; one end of the fifth sub-section 155 is connected to the data line 2, and the other end of the fifth sub-section 155 is connected to the thin film transistor.
  • the drain electrodes 142 are spaced apart, so that the drain electrode 142 and the data line can be avoided while improving the light blocking effect of the light blocking layer 150 (the gap between the end of the fifth portion 155 connected to the data line 2 and the data line 2). 2 connected.
  • At least one embodiment of the present disclosure provides a display panel including the array substrate provided by any of the above embodiments.
  • the display panel provided by at least one embodiment of the present disclosure may further include an opposite substrate disposed on the array substrate.
  • the display panel may be a liquid crystal display panel, for example, the array substrate and the opposite substrate of the liquid crystal display panel are opposed to each other to form a liquid crystal cell filled with a liquid crystal material.
  • the counter substrate may be, for example, a color filter substrate.
  • the electric field formed between the pixel electrode and the common electrode of the array substrate controls the degree of rotation of the liquid crystal material to perform image display.
  • the common electrode may be disposed on the array substrate or the opposite substrate.
  • the display panel may be an organic light emitting diode (OLED) display panel, wherein an organic light emitting material may be formed in a sub-pixel region of the display panel, and the pixel electrode is used as an anode or a cathode for driving The organic luminescent material emits light for image display.
  • OLED organic light emitting diode
  • the display device may be an electronic paper display panel, wherein an electronic ink layer may be formed on the array substrate of the display panel, and the pixel electrode is used to apply the charged micro in the driving electronic ink. The voltage at which the particles move to display the image.
  • the upper side of the active layer 130 of the thin film transistor may still be affected by the illumination.
  • a spacer may be disposed between the opposite substrate and the array substrate, and the spacer and the thin film transistor on the array substrate are oppositely disposed in a direction perpendicular to the array substrate.
  • the spacer may include a light shielding material.
  • the spacer may be disposed to cover the entire area of the thin film transistor, or may be disposed to cover at least the active layer 130 in the thin film transistor, such that the spacer may block the light that illuminates the active layer 130 of the thin film transistor from above. .
  • FIG. 6 is a schematic cross-sectional structural view of a display panel according to an embodiment of the present disclosure
  • the display panel is, for example, a liquid crystal display panel.
  • a liquid crystal layer 500 is disposed between the array substrate and the opposite substrate 300 disposed in the cartridge to form a liquid crystal cell
  • the spacer 400 is disposed between the array substrate and the opposite substrate 300, and the spacer 400
  • the light shielding material is disposed overlapping the thin film transistor, and thus the spacer 400 can block light that illuminates the active layer 130 from above the active layer 130 of the thin film transistor.
  • the material for preparing the spacer is not limited.
  • the spacer includes a light shielding material, and the light shielding material may be a material that can block light such as carbon black and/or black resin.
  • a common electrode may be disposed on the opposite substrate 300, and an electric field that drives the rotation of the liquid crystal layer 500 may be formed between the common electrode and the pixel electrode 200.
  • At least one embodiment of the present disclosure provides a method of fabricating a thin film transistor, the method comprising: providing a substrate; forming a gate electrode, a gate insulating layer, an active layer, and a source/drain electrode layer on the substrate, the source and drain electrodes
  • the layer includes a source electrode and a drain electrode; a light blocking layer is formed around the active layer.
  • FIG. 7 is a process diagram of a method of fabricating a thin film transistor according to an embodiment of the present disclosure.
  • a method of fabricating a thin film transistor may include the following process.
  • S1 providing a base substrate, and depositing a gate metal film on the base substrate, and forming a gate electrode by patterning the gate metal film.
  • the base substrate may be a glass substrate or the like.
  • the material of the gate electrode may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/ Mo/Ti), copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; the material of the gate electrode may also be a chromium-based metal, for example, a chromium-molybdenum alloy (Cr/ Mo), chrome-titanium alloy (Cr/Ti), chrome-molybdenum-titanium alloy (Cr/Mo/Ti), etc.; the material of the gate electrode may also be aluminum or aluminum alloy.
  • Cu copper
  • Cu/Mo copper-molybdenum alloy
  • Cu/Ti copper-titanium alloy
  • Cu/ Mo/Ti copper-molybden
  • the patterning process may be, for example, a photolithography patterning process, which may include, for example, coating a photoresist layer on a structural layer that needs to be patterned, and exposing the photoresist layer using a mask.
  • the exposed photoresist layer is developed to obtain a photoresist pattern, the structural layer is etched using the photoresist pattern as a mask, and then the photoresist pattern is optionally removed.
  • the material of the gate insulating layer may include silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • S3 depositing a semiconductor thin film on the gate insulating layer and patterning it to form an active layer.
  • the light blocking layer may be formed in the same layer as the active layer and formed of the same material.
  • a patterning process is performed to simultaneously form an active layer and a light blocking layer.
  • a light blocking layer is formed around the active layer to prevent the side surface of the active layer from being irradiated with light.
  • the material of the active layer may include amorphous silicon, polycrystalline silicon, and metals such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), and the like. Oxide, etc.
  • S4 depositing a source/drain metal layer on the underlying substrate on which the active layer is formed and patterning the same to form a source/drain electrode layer, which may include a source electrode and a drain electrode.
  • the light blocking layer may be formed in the same layer and the same material as the source and drain electrode layers.
  • a source/drain metal layer is deposited on a base substrate and then patterned to simultaneously form a source/drain electrode layer and a light blocking layer.
  • a light blocking layer is formed around the active layer to prevent the side surface of the active layer from being irradiated with light.
  • the source-drain electrode layer may include a metal material, which may be formed in a single layer or a multilayer structure, for example, formed as a single-layer aluminum structure, a single-layer molybdenum structure, or a layer of aluminum sandwiched between two layers of molybdenum. structure.
  • the formation of the light blocking layer is not limited to the preparation method provided in the above examples, and may be formed separately.
  • a light blocking layer is separately formed around the active layer, for example, by depositing a thin film and a patterning process to prevent the side surface of the active layer from being irradiated with light; the type of pattern of the formed light blocking layer can be referred to the foregoing embodiment, Do not repeat them.
  • the material of the passivation layer may be silicon nitride (SiNx), silicon oxide (SiOx), an acrylic resin, or the like.
  • Embodiments of the present disclosure provide a thin film transistor and a method of fabricating the same, an array substrate, a display panel, and may have at least one of the following beneficial effects:
  • the light blocking layer can prevent the side surface of the active layer from being irradiated with light, thereby reducing or eliminating In addition to problems such as poor display due to photo-generated carriers generated by light irradiation of the active layer.
  • the spacer includes a light shielding material and is disposed to overlap the thin film transistor so that the active layer can be shielded from above the active layer.
  • the light blocking layer can be formed simultaneously in the process of preparing the active layer or the source/drain electrodes of the thin film transistor without increasing the preparation process steps.

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Abstract

一种薄膜晶体管及其制备方法、阵列基板、显示面板。该薄膜晶体管包括：衬底基板；以及设置于所述衬底基板上的栅电极(110)、栅绝缘层(120)、有源层(130)、和源漏电极层(140)，所述源漏电极层(140)包括源电极(141)和漏电极(142)，其中所述薄膜晶体管还包括设置在所述有源层(130)周围的挡光层(150)。该挡光层(150)设置在有源层(130)的周围，可以防止有源层(130)的侧表面受到光的照射，从而减小因光照射有源层(130)产生的光生载流子导致的薄膜晶体管漏电流。

Description

薄膜晶体管及其制备方法、阵列基板、显示面板
本申请要求于2017年2月17日递交的中国专利申请第201710086370.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种薄膜晶体管及其制备方法、阵列基板、显示面板。
背景技术
通常，薄膜晶体管被用作显示面板的驱动元件。薄膜晶体管中的有源层受到光照射后会产生光生载流子，导致薄膜晶体管的漏电流增加，从而影响显示面板的显示画面的质量，例如会产生串扰、残像等现象。
发明内容
本公开至少一实施例提供一种薄膜晶体管，包括：衬底基板；以及设置于所述衬底基板上的栅电极、栅绝缘层、有源层、和源漏电极层，所述源漏电极层包括源电极和漏电极，其中所述薄膜晶体管还包括设置在所述有源层周围的挡光层。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层与所述源漏电极层可以同层且同材料设置；或者所述挡光层与所述有源层可以同层且同材料设置。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层可以与所述源电极和所述漏电极中的一个连接，且与所述源电极和所述漏电极中的一个间隔开。
例如，在本公开至少一实施例提供的薄膜晶体管中，在所述挡光层与所述有源层同层设置的情形下，所述挡光层与所述有源层间隔开。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层可以包括绝缘材料。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层的远离所述衬底基板的表面至所述衬底基板的距离大于或等于所述有源层的远离所述衬底基板的表面至所述衬底基板的距离；和/或所述挡光层的靠近所述衬底基板的表面至所述衬底基板的距离小于或等于所述有源层的靠近所述衬底基板的表面至所述衬底基板的距离。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层在所述衬底基板上的正投影位于所述栅电极在所述衬底基板上的正投影之内。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层在所述衬底基板上的正投影位于所述栅电极在所述衬底基板上的正投影之外。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述挡光层可以包括多个彼此分离的分部，该多个分部设置为在平行于所述衬底基板的方向上所述有源层被所述挡光层遮挡。
本公开至少一实施例提供一种阵列基板，该阵列基板包括上述任一的薄膜晶体管。
例如，本公开至少一实施例提供的阵列基板，还可以包括多条栅线和多条数据线，其中，所述多条栅线和所述多条数据线彼此交叉以限定多个子像素区域，每个所述子像素区域包括所述薄膜晶体管和像素电极，所述薄膜晶体管的所述栅电极与对应的所述栅线电连接，所述源电极与对应的所述数据线电连接，且所述漏电极与所述像素电极电连接；并且每个所述子像素区域包括显示区域和非显示区域，所述挡光层位于每个所述子像素区域的所述非显示区域。
例如，在本公开至少一实施例提供的阵列基板中，所述挡光层的一端与所述数据线连接，另一端与所述漏电极间隔开。
例如，在本公开至少一实施例提供的阵列基板中，所述挡光层可以设置在所述薄膜晶体管周围。
本公开至少一实施例提供一种显示面板，包括上述任一的阵列基板和与所述阵列基板对盒设置的对置基板。
例如，在本公开至少一实施例提供的显示面板中，所述对置基板和所述阵列基板之间可以设置有隔垫物，所述隔垫物与所述阵列基板上的薄膜晶体管在垂直于所述阵列基板的方向上相对设置，并且所述隔垫物可以包括遮光材料。
例如，在本公开至少一实施例提供的显示面板中，所述遮光材料可以包括为炭黑和/或黑色树脂。
本公开至少一实施例提供一种薄膜晶体管的制备方法，包括：提供衬底基板；以及在所述衬底基板上形成栅电极、栅绝缘层、有源层和源漏电极层，所述源漏电极层包括源电极和漏电极；其中所述方法还包括在所述有源层周围形成挡光层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为一种阵列基板的子像素区域的俯视示意图；
图1b为图1a所示子像素区域中的薄膜晶体管沿A-B方向的截面示意图；
图2a为本公开一实施例提供的一种薄膜晶体管的俯视图；
图2b为图2a所示薄膜晶体管沿C-D方向的截面示意图；
图2c为图2a所示薄膜晶体管沿C-D方向的另一截面示意图；
图3(a)至图3(c)为本公开一实施例提供的薄膜晶体管中的挡光层的示意图；
图4为本公开一实施例提供的薄膜晶体管中的挡光层的另一示意图；
图5为本公开一实施例提供的一种阵列基板中的子像素区域的俯视图；
图6为本公开一实施例提供的一种显示面板的截面结构示意图；以及
图7为本公开一个实施例提供的薄膜晶体管的制备方法的过程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1a为一种阵列基板的子像素区域的俯视示意图。如图1a所示，栅线1和数据线2彼此交叉限定出子像素区域，子像素区域包括薄膜晶体管和像素电极200，薄膜晶体管与像素电极200连接。薄膜晶体管的有源层130受到光照后会产生大量的光生载流子，导致薄膜晶体管在关态下的漏电流增加，由此导致包括该阵列基板的显示装置产生残像、串扰等不良。
图1b为图1a所示子像素区域中的薄膜晶体管沿A-B方向的截面结构示意图。如图1b所示，设置在有源层130下方的栅电极110可以阻挡从有源层130的下方入射到有源层130上的光。另外，可以在有源层130上方设置黑矩阵(未示出)以阻挡从有源层130的上方入射到有源层130上的光。然而，如图1b所示，由于栅绝缘层120和钝化层160通常为透明材料，有源层130侧表面仍然会受到光(以图1b中箭头表示)的照射。因此，在图1a和图1b所示的薄膜晶体管中仍不能防止光对有源层130的侧表面的照射，有源层130中仍然会有大量的光生载流子产生。
本公开至少一实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示面板以解决上述问题。该薄膜晶体管包括衬底基板以及设置于该衬底基板上的栅电极、栅绝缘层、有源层、和源漏电极层，该源漏电极层包括源电极和漏电极，其中该薄膜晶体管还包括设置在有源层周围的挡光层。通过设置挡光层，可以阻挡照射到有源层的侧表面上的光，从而可以有效地减小由光生载流子引起的漏电流。
需要说明的是，在本公开的所有实施例中，对各个方向的指定是以薄膜晶体管中的衬底基板为参考的。示例性的，以有源层为例，其“上表面”为远离衬底基板的表面，其“下表面”为靠近衬底基板的表面，其“侧表 面”为夹设在上表面和下表面之间的表面。另外，以有源层为例，其“侧向”的方向为平行于衬底基板表面，其“上方”和“下方”的方向为垂直于衬底基板的表面方向，且“上方”为有源层的远离衬底基板的一侧方向，“下方”为有源层的靠近衬底基板的一侧方向。
下面，结合附图对根据本公开实施例中的薄膜晶体管及其制备方法、阵列基板、显示面板进行说明。
本公开至少一个实施例提供了一种薄膜晶体管，图2a为本公开一实施例提供的一种薄膜晶体管的结构俯视图。例如，如图2a所示，薄膜晶体管包括有源层130、源漏电极层140和挡光层150，源漏电极层140包括分别与有源层130电连接的源电极141和漏电极142，挡光层150设置于有源层130的周围以阻挡光照射到有源层130的侧表面上。
需要说明的是，在本公开实施例中，薄膜晶体管还可以包括衬底基板、栅电极、栅绝缘层等结构；此外，本公开的实施例对薄膜晶体管的类型不做限制，例如，上述实施例中的挡光层150可以适用于底栅型的薄膜晶体管、顶栅型的薄膜晶体管或者双栅型的薄膜晶体管等，只要挡光层可以阻挡光线入射到薄膜晶体管的有源层130的侧表面上即可。
下面，以薄膜晶体管为底栅型薄膜晶体管为例，对本公开下述实施例中的技术方案进行说明。
需要说明的是，设置挡光层150以阻挡光照射到有源层130的侧表面上包括：挡光层150设置为使得有源层130的一部分侧表面不被光照射；或者挡光层150设置为使得有源层130的全部侧表面不被光照射。本公开的实施例对挡光层150可以遮挡光照射有源层130的侧表面的范围不做限制，只要挡光层150的设置可以减少光对有源层130的照射即可。
需要说明的是，挡光层150除了阻挡光照射到有源层130的侧表面上也可以阻挡光照射到有源层130的上表面和/或下表面上。
在本公开的实施例中，对挡光层150的设置方式不做限制。例如，在本公开的一些实施例中，可以单独设置挡光层150；例如，在本公开的另一些实施例中，可以在制备薄膜晶体管的过程中同步制备挡光层150。下面，对挡光层150的不同设置方式分别进行说明。
例如，在本公开至少一个实施例中，可以单独在有源层130的周围设置挡光层150。例如，挡光层150可以由任何具有挡光功能的材料形成。 例如，挡光层150可以由具有挡光功能的绝缘材料形成，例如黑色树脂。例如，挡光层可以由具有挡光功能的导电材料(例如，金属)或半导体材料形成。
例如，在本公开至少一个实施例中，挡光层150与有源层130由相同的材料形成且同层设置，或者挡光层150与源漏电极层140由相同的材料形成且同层设置。这样一来，可以通过同一构图工艺同时形成有源层130和挡光层150或者通过同一构图工艺同时形成源漏电极层140和挡光层150。如此，在薄膜晶体管中设置挡光层150并不会增加薄膜晶体管的制备工艺步骤，可以节省成本。
例如，在本公开至少一个实施例中，挡光层150与有源层130为同层且同材料设置。在此情形下，与有源层130同材料制备的挡光层150在光的照射下会产生光生载流子，因此需要将挡光层150与有源层130间隔开以避免挡光层150中产生的光生载流子运动到有源层130中。例如，挡光层150的厚度和有源层130的厚度是一样的，由此可以容易地通过一次构图工艺同时形成挡光层150和有源层130。
例如，在本公开至少一个实施例中，挡光层150与有源层130为同层且同材料设置，并且挡光层150的厚度大于有源层130的厚度，如此不仅能阻挡平行于衬底基板的光照射到有源层130的侧表面而且还可以阻挡相对于衬底基板100以倾斜方向入射的光照射到有源层130的侧表面上，以进一步提高对有源层130的遮光效果。例如，可以采用双色调掩模板(例如，半色调掩模板或者灰色调掩模板)对用于形成有源层130的半导薄膜进行图案化以同时形成挡光层150和有源层130且挡光层150的厚度大于有源层130的厚度。例如，在衬底基板100上形成半导体薄膜；在半导体薄膜上涂覆光刻胶，并采用双色调掩模板对光刻胶进行曝光和显影以得到光刻胶完全保留部分、光刻胶部分保留部分和光刻胶完全去除部分，光刻胶完全保留部分对应于要形成挡光层150的区域，光刻胶部分保留区域对应于要形成有源层130的区域，光刻胶完全去除区域对应于其他区域；进行第一次刻蚀，以去除光刻胶完全去除部分的半导体薄膜；进行灰化工艺，以去除光刻胶部分保留部分的光刻胶并使光刻胶完全保留部分的光刻胶减薄；进行第二次刻蚀，以去除光刻胶部分保留部分的一部分半导体薄膜，得到有源层130；去除光刻胶完全保留部分的光刻胶以得到挡光层150。
例如，在本公开至少一个实施例中，挡光层150与源漏电极层140为同层且同材料设置。例如，源漏电极层140和挡光层150可以由金属形成。例如，挡光层150的厚度和有源层130的厚度是一样的。例如，挡光层150的厚度大于有源层130的厚度，如此不仅能阻挡平行于衬底基板100的光照射到有源层130的侧表面而且还可以阻挡相对于衬底基板100以倾斜方向入射的光照射到有源层130的侧表面上，以进一步提高对有源层130的遮光效果。在挡光层150与源漏电极层140为同层且同材料设置的情形下，由于挡光层150和有源层130分开制备，因此采用单色调掩模板即可得到厚度大于有源层130的挡光层150而无需采用双色调掩模板，从而可以进一步简化制作工艺。
例如，在本公开至少一个实施例中，在挡光层150与源漏电极层140同层且同材料设置的情形下，挡光层150与源电极141和漏电极142中的至少一个间隔开。例如，在挡光层150与源漏电极层140同层且同材料设置的情形下，挡光层150不能与源电极141和漏电极142二者均连接，以防止挡光层将源电极和漏电极连通。例如，在本公开实施例提供的薄膜晶体管中，挡光层150与源漏电极层140所包括的源电极141和漏电极142中的一个间隔开而与另一个连接；在此情形下，由于挡光层150与源电极141和漏电极142中的一个连接，所以挡光层150可以与源电极141和漏电极142中的一个一体形成以进一步简化制作工艺，并且挡光层150可以和与其连接的源电极141或漏电极142相配合以更好地阻挡光照射到有源层130上。例如，如图2a所示，挡光层150与源电极141连接或者一体形成，而与漏电极142断开，在此情形下，在挡光层150和源电极141之间没有间隙，从而可以更好地阻挡光照射到有源层130的侧表面上。如图2a所示，挡光层150与漏电极142断开，使得挡光层150与漏电极142之间具有间隙170，光可能会通过该间隙170入射到有源层130上；因此需要将该间隙170的宽度制作得尽可能小，例如该间隙170的宽度可以为几个微米级别。
图2b为图2a所示薄膜晶体管沿C-D方向的截面示意图。如图2b所示，薄膜晶体管可以包括衬底基板100以及依次设置在衬底基板100上的栅电极110、栅绝缘层120、有源层130、源漏电极层(图中2b中未示出)、挡光层150和钝化层160。
图2c为图2a所示薄膜晶体管沿C-D方向的另一截面示意图。例如，在本公开实施例中，如图2b和图2c所示，挡光层150的远离衬底基板100的表面至衬底基板100的距离大于或等于有源层130的远离衬底基板100的表面至衬底基板100的距离；和/或挡光层150的靠近衬底基板100的表面至衬底基板100的距离小于或等于有源层130的靠近衬底基板100的表面至衬底基板100的距离。如此一来，可以更有效地阻挡光照射到有源层130上。
例如，在本公开至少一个实施例中，如图2b所示，挡光层150设置为与栅电极110重叠，例如，挡光层150在衬底基板100上的正投影位于栅电极110在衬底基板100上的正投影之内。如此，挡光层150的高度(挡光层150的远离衬底基板100的一端至衬底基板100的距离)增加，从而阻挡光从挡光层150的上方对有源层130的照射。
例如，在本公开至少一个实施例中，如图2c所示，挡光层150设置为不与栅电极110重叠。例如，挡光层150在衬底基板100上的正投影位于栅电极110在衬底基板100上的正投影之外，如此，可以减小挡光层150的靠近衬底基板100的一端至衬底基板100的距离，减小挡光层150和衬底基板100之间的缝隙，从而进一步阻挡光从挡光层150的下方对有源层130的照射。
例如，在本公开至少一个实施例中，挡光层150的图案形状可以有多种类型。示例性的，例如挡光层150的平行于衬底基板100的截面的形状可以包括长条形、L形和圆弧形等中的一种或者组合。本公开的实施例对挡光层150的图案形状不做限制，只要其可以在不影响薄膜晶体管性能的情况下能够对有源层130的侧表面进行遮光即可。
图3(a)至图3(c)为本公开一实施例提供的薄膜晶体管中挡光层的示意图。例如，如图3(a)至图3(c)所示，挡光层150的截面形状可以分别为长条形、L形和圆弧形。需要说明的是，挡光层150的截面形状可以为上述多种图案类型的组合，示例性的，以图3(a)中的薄膜晶体管中的挡光层150为例，第一分部151为长条形的同时，第二分部152可以由图3(a)所示的长条形替换为图3(b)所示的L形或图3(c)所示的圆弧形。
例如，在本公开至少一个实施例中，挡光层150可以首尾连接形成封 闭的图案，例如“口”字形等。例如，在本公开的实施例中挡光层150包括彼此分离的多个分部，包含该多个分部的挡光层150可以在平行于衬底基板的方向上对有源层130进行遮挡；例如，该多个分部可以设置为在平行于衬底基板的所有方向上有源层都可以被挡光层150遮挡。
例如，在本公开至少一个实施例中，如图3(a)所示，挡光层150的多个分部在平行于衬底基板100的方向上不重叠。如此，可以减少挡光层150的占用面积。
例如，在本公开至少一个实施例中，挡光层150的多个分部在平行于衬底基板100的方向上重叠设置，以在平行于衬底基板100的所有方向上有源层130均被挡光层150遮挡。图4为本公开一实施例提供的薄膜晶体管的挡光层的另一示意图。示例性的，如图4所示，挡光层150在有源层130的一侧包括沿平行于衬底基板100的方向依次重叠设置的第一分部151和第二分部152，挡光层150在有源层130的另一侧包括沿平行于衬底基板100的方向重叠设置的第三分部153和第四分部154，第一分部151、第二分部152、第三分部153和第四分部154相互配合以在平行于衬底基板100的所有方向上有源层130均被挡光层150遮挡，从而可以更加有效地防止光照射到有源层130上，尤其是更加有效地防止光照射到有源层130的侧表面上。例如如图4所示，挡光层150的第一分部151与源电极141连接并且与漏电极142断开，挡光层150的第二分部152与源电极141断开并且与漏电极142连接，第一分部151与第二分部152在平行于衬底基板100的方向上重叠设置；在此情况下，第一分部151可以遮挡第二分部151与源电极141之间的间隙，第二分部152可以遮挡第一分部151与漏电极142之间的间隙，如此挡光层150可以完全遮挡光对有源层130侧表面的照射。
本公开的实施例提供一种阵列基板，该阵列基板可以包括上述任一实施例中的薄膜晶体管。
例如，在本公开至少一个实施例中，阵列基板还可以包括多条栅线和多条数据线，多条栅线和多条数据线彼此交叉以限定多个子像素区域，每个子像素区域包括所述薄膜晶体管和像素电极，薄膜晶体管的栅电极与对应的栅线电连接，源电极与对应的数据线电连接，且漏电极与像素电极电连接；并且每个子像素区域包括显示区域和非显示区域，挡光层位于每个 子像素区域的非显示区域。需要说明的是，栅线、数据线和薄膜晶体管可以均位于子像素区域的非显示区域，而像素电极可以位于子像素区域的显示区域。
下面，以一个子像素区域为例对本公开下述实施例中的技术方案进行说明。
图5为本公开实施例提供的一种阵列基板中的一个子像素区域的结构示意图，其为一个子像素区域的局部示意图。例如，在本公开至少一个实施例中，如图5所示，该阵列基板的子像素区域包括彼此交叉设置的栅线1和数据线2、像素电极200、薄膜晶体管(包括有源层130、源漏电极层140)和挡光层150，源漏电极层140包括源电极141和漏电极142，源电极141与数据线2电连接，薄膜晶体管的栅电极(图5中未示出)与栅线1电连接，漏电极142与像素电极200电连接，薄膜晶体管作为开关元件控制像素电极200的开关。
例如，在本公开至少一个实施例中，阵列基板的每个子像素区域包括显示区域和非显示区域，像素电极200设置在显示区域中，薄膜晶体管和挡光层150设置在非显示区域中。
例如，在本公开至少一个实施例中，与上述关于薄膜晶体管的实施例相同，挡光层150可以设置在有源层130的周围；在此情形下，挡光层150可以设置为在平行于衬底基板100的方向上仅遮挡有源层130的侧表面而不遮挡源电极141、漏电极142和/或栅电极110的侧表面，换言之，挡光层150可以设置为仅围绕有源层130而不围绕源电极141、漏电极142和/或栅电极110。例如，挡光层150设置在薄膜晶体管的周围；在此情形下，挡光层150可以设置为在平行于衬底基板100的方向上遮挡有源层130、源电极141、漏电极142以及栅电极110的侧表面，换言之，挡光层150可以设置为围绕源层130、源电极141、漏电极142以及栅电极110。例如如图5所示，虚线区域T表示薄膜晶体管所在区域，挡光层150可以设置在区域T的周围以对整个薄膜晶体管的侧表面进行遮光。例如如图5所示的挡光层150的第五分部155和第六分部156位于薄膜晶体管的周围，以遮挡薄膜晶体管的侧表面，从而也可以遮挡薄膜晶体管中的有源层130的侧表面以防止其受到光的照射。
例如，在本公开至少一个实施例提供的阵列基板中，设置于薄膜晶体 管周围的挡光层150的图案类型可以参考前述实施例(本公开提供的关于薄膜晶体管的实施例)中的挡光层的图案类型，在此不做赘述。
例如，在本公开至少一个实施例提供的阵列基板中，挡光层150的一端可以与数据线连接，另一端可以与漏电极间隔开。示例性的，如图5所示，以挡光层150的第五分部155为例进行说明；第五分部155的一端与数据线2相连，第五分部155的另一端与薄膜晶体管的漏电极142间隔开，如此可以在提高挡光层150遮光效果(第五分部155的与数据线2连接的一端与数据线2之间无间隙)的同时避免将漏电极142与数据线2连通。
本公开至少一个实施例提供一种显示面板，该显示面板包括上述任一实施例提供的阵列基板。例如，本公开至少一个实施例提供的显示面板还可以包括与阵列基板对盒设置的对置基板。
例如，在本公开至少一个实施例中，该显示面板可以为液晶显示面板，例如该液晶显示面板的阵列基板和对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如可以为彩膜基板。阵列基板的像素电极与公共电极之间形成的电场对液晶材料的旋转的程度进行控制从而进行图像显示。例如，公共电极可以设置在阵列基板或对置基板上。
例如，在本公开至少一个实施例中，该显示面板可以为有机发光二极管(OLED)显示面板，其中，该显示面板的子像素区域中可以形成有机发光材料，像素电极作为阳极或阴极用于驱动有机发光材料发光以进行图像显示。
例如，在本公开至少一个实施例中，该显示装置可以为电子纸显示面板，其中，在该显示面板的阵列基板上可以形成有电子墨水层，像素电极用于施加驱动电子墨水中的带电微颗粒移动以进行图像显示的电压。
在本公开提供的实施例中，薄膜晶体管的有源层130的上方(远离衬底基板的一侧)仍有可能受到光照影响。例如，在本公开至少一个实施例提供的显示面板中，对置基板和阵列基板之间可以设置有隔垫物，隔垫物与阵列基板上的薄膜晶体管在垂直于阵列基板的方向上相对设置，并且隔垫物可以包括遮光材料。例如隔垫物可以设置为覆盖整个的薄膜晶体管所在区域，也可以设置为至少覆盖薄膜晶体管中的有源层130，如此隔垫物可以遮挡从上方对薄膜晶体管的有源层130进行照射的光。
图6为本公开一实施例提供的一种显示面板的横截面结构示意图，该 显示面板例如为液晶显示面板。例如如图6所示，对盒设置的阵列基板和对置基板300之间设置有液晶层500以形成液晶盒，隔垫物400设置于阵列基板和对置基板300之间，隔垫物400与薄膜晶体管重叠设置并包括遮光材料，因此隔垫物400可以遮挡从薄膜晶体管的有源层130的上方对有源层130进行照射的光。
在本公开的实施例中，对隔垫物的制备材料不做限制。例如，在本公开至少一个实施例提供的显示面板中，隔垫物包括遮光材料，该遮光材料可以为炭黑和/或黑色树脂等可以挡光的材料。
例如，在本公开至少一个实施例中，如图6所示，对置基板300上可以设置有公共电极，公共电极和像素电极200之间可以形成驱动液晶层500旋转的电场。
本公开至少一个实施例提供一种薄膜晶体管的制备方法，该方法包括：提供衬底基板；在衬底基板上形成栅电极、栅绝缘层、有源层和源漏电极层，该源漏电极层包括源电极和漏电极；在所述有源层周围形成挡光层。
为便于理解本公开实施例中的技术方案，本实施例提供一种薄膜晶体管的制备过程作为示例。图7为本公开一个实施例提供的薄膜晶体管的制备方法的过程图。例如，在本公开实施例的一个示例中，如图7所示，制备薄膜晶体管的方法可以包括以下过程。
S1：提供衬底基板，并在该衬底基板上沉积栅金属薄膜，通过对该栅金属薄膜进行构图工艺以形成栅电极。
例如，该衬底基板可以为玻璃基板等。
例如，在本示例中，该栅电极的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；该栅电极的材料也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等；该栅电极的材料还可以为铝或铝合金等。
在本公开的实施例中，构图工艺例如可以为光刻构图工艺，其例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案作为掩模对结构层进行蚀刻，然后可选地去除光刻胶图案。
S2：在形成有栅电极的衬底基板上沉积栅绝缘层。
例如，在本示例中，栅绝缘层的材料可以包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料等。
S3：在栅绝缘层上沉积半导体薄膜并对其进行构图工艺以形成有源层。
例如，在本示例提供的制备方法中，挡光层可以与有源层同层且同材料形成。示例性的，例如，在衬底基板上沉积有源层薄膜后，对其进行构图工艺以同时形成有源层和挡光层。例如，挡光层形成在有源层的周围以防止有源层的侧表面受到光的照射。
例如，在本示例中，有源层的材料可以包括非晶硅、多晶硅、以及氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物等。
S4：在形成有有源层的衬底基板上沉积源漏金属层并对其进行构图工艺以形成源漏电极层，该源漏电极层可以包括源电极和漏电极。
例如，在本示例提供的制备方法中，挡光层可以与源漏电极层同层且同材料形成。示例性的，例如，在衬底基板上沉积源漏金属层后对其进行构图工艺以同时形成源漏电极层和挡光层。例如，挡光层形成在有源层的周围以防止有源层的侧表面受到光的照射。
例如，在本示例中，源漏电极层可以包括金属材料，可以形成单层或多层结构，例如，形成为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的结构。
需要说明的是，在本示例中，挡光层的形成不限于上述示例中提供的制备方法，也可以单独形成。例如，在有源层的周围例如通过沉积薄膜和构图工艺单独形成挡光层以防止有源层的侧表面受到光的照射；形成的挡光层的图案的类型可以参考前述实施例，在此不做赘述。
S5：在源漏电极层上形成钝化层。
例如，在本示例中，钝化层的材料可以为氮化硅(SiNx)、氧化硅(SiOx)以及丙烯酸类树脂等。
本公开的实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示面板，并且可以具有以下至少一项有益效果：
(1)挡光层可以防止有源层的侧表面受到光的照射，从而降低或消 除因光照射有源层产生的光生载流子所导致的显示不良等问题。
(2)隔垫物包括遮光材料并与薄膜晶体管重叠设置，从而可以从有源层的上方为有源层提供遮挡。
(3)挡光层可以在制备薄膜晶体管的有源层或源漏电极的过程中同步形成，不会增加制备工艺步骤。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种薄膜晶体管，包括：
    衬底基板；以及
    设置于所述衬底基板上的栅电极、栅绝缘层、有源层、和源漏电极层，所述源漏电极层包括源电极和漏电极，
    其中，所述薄膜晶体管还包括设置在所述有源层周围的挡光层。
  2. 根据权利要求1所述的薄膜晶体管，其中，
    所述挡光层与所述源漏电极层同层且同材料设置；或者
    所述挡光层与所述有源层同层且同材料设置。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述挡光层与所述源电极和所述漏电极中的一个连接，且与所述源电极和所述漏电极中的一个间隔开。
  4. 根据权利要求1或2所述的薄膜晶体管，其中，在所述挡光层与所述有源层同层设置的情形下，所述挡光层与所述有源层间隔开。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述挡光层包括绝缘材料。
  6. 根据权利要求1-5任一所述的薄膜晶体管，其中，
    所述挡光层的远离所述衬底基板的表面至所述衬底基板的距离大于或等于所述有源层的远离所述衬底基板的表面至所述衬底基板的距离；和/或
    所述挡光层的靠近所述衬底基板的表面至所述衬底基板的距离小于或等于所述有源层的靠近所述衬底基板的表面至所述衬底基板的距离。
  7. 根据权利要求6所述的薄膜晶体管，其中，
    所述挡光层在所述衬底基板上的正投影位于所述栅电极在所述衬底基板上的正投影之内。
  8. 根据权利要求6所述的薄膜晶体管，其中，
    所述挡光层在所述衬底基板上的正投影位于所述栅电极在所述衬底基板上的正投影之外。
  9. 根据权利要求1-8任一项所述的薄膜晶体管，其中，所述挡光层包括多个彼此分离的分部，该多个分部设置为在平行于所述衬底基板的方向 上所述有源层被所述挡光层遮挡。
  10. 一种阵列基板，包括权利要求1-9任一所述的薄膜晶体管。
  11. 根据权利要求10所述的阵列基板，还包括多条栅线和多条数据线，其中，
    所述多条栅线和所述多条数据线彼此交叉以限定多个子像素区域，每个所述子像素区域包括所述薄膜晶体管和像素电极，所述薄膜晶体管的所述栅电极与对应的所述栅线电连接，所述源电极与对应的所述数据线电连接，且所述漏电极与所述像素电极电连接；并且
    每个所述子像素区域包括显示区域和非显示区域，所述挡光层位于每个所述子像素区域的所述非显示区域。
  12. 根据权利要求11所述的阵列基板，其中，所述挡光层的一端与所述数据线连接，另一端与所述漏电极间隔开。
  13. 根据权利要求10-12任一所述的阵列基板，其中，所述挡光层设置在所述薄膜晶体管周围。
  14. 一种显示面板，包括权利要求10-13任一所述的阵列基板和与所述阵列基板对盒设置的对置基板。
  15. 根据权利要求14所述的显示面板，其中，所述对置基板和所述阵列基板之间设置有隔垫物，所述隔垫物与所述阵列基板上的薄膜晶体管在垂直于所述阵列基板的方向上相对设置，并且所述隔垫物包括遮光材料。
  16. 根据权利要求15所述的显示面板，其中，所述遮光材料包括炭黑和/或黑色树脂。
  17. 一种薄膜晶体管的制备方法，包括：
    提供衬底基板；以及
    在所述衬底基板上形成栅电极、栅绝缘层、有源层和源漏电极层，所述源漏电极层包括源电极和漏电极，
    其中所述方法还包括在所述有源层周围形成挡光层。
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CN106876386A (zh) * 2017-02-17 2017-06-20 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示面板

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WO2020166320A1 (ja) * 2019-02-14 2020-08-20 株式会社ジャパンディスプレイ 表示装置
JP2020134583A (ja) * 2019-02-14 2020-08-31 株式会社ジャパンディスプレイ 表示装置
JP7237633B2 (ja) 2019-02-14 2023-03-13 株式会社ジャパンディスプレイ 表示装置
US11846854B2 (en) 2019-02-14 2023-12-19 Japan Display Inc. Display device
JP2020160253A (ja) * 2019-03-26 2020-10-01 株式会社ジャパンディスプレイ 表示装置
JP7240921B2 (ja) 2019-03-26 2023-03-16 株式会社ジャパンディスプレイ 表示装置

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