WO2018133391A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2018133391A1
WO2018133391A1 PCT/CN2017/096628 CN2017096628W WO2018133391A1 WO 2018133391 A1 WO2018133391 A1 WO 2018133391A1 CN 2017096628 W CN2017096628 W CN 2017096628W WO 2018133391 A1 WO2018133391 A1 WO 2018133391A1
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Prior art keywords
gate
pattern
light absorbing
active layer
layer
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French (fr)
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曹可
姜涛
杨成绍
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • Embodiments of the present invention generally relate to the field of display technologies, and in particular, to an array substrate, a method of fabricating the same, and a display device.
  • the exposure process has been the focus of cost control in the manufacture of semiconductor devices, including display screens.
  • the thin film transistor (TFT) preparation process of many array substrates currently uses the active layer and the source/drain to be formed by one exposure. This process saves a mask process, so There are significant advantages in saving production process steps and exposure equipment costs.
  • TFTs thin film transistors
  • the present disclosure has been made to overcome or eliminate at least one of the above and other problems and disadvantages of the prior art.
  • embodiments of the present invention provide an array substrate including a substrate and a transistor disposed on the substrate, the transistor including a gate and an active layer; wherein the gate faces One side of the active layer is formed with a light absorbing layer configured to absorb light irradiated thereto.
  • the surface of the light absorbing layer is uneven.
  • the light absorbing layer comprises microcrystallites of copper oxide and/or microcrystallites of copper sulfide.
  • the material of the gate comprises copper.
  • the light absorbing layer comprises microcrystallites of copper oxide and/or microcrystallites of copper sulfide.
  • the light absorbing layer is formed as a unitary structure with the gate electrode or the light absorbing layer is separately formed on the surface of the gate electrode.
  • the color of the light absorbing layer is black or black gray.
  • the light absorbing layer has a thickness in the range of 10 nm to 30 nm.
  • the transistor further includes a source and a drain that are disposed in the same layer and are respectively located at opposite ends of the same side of the active layer.
  • the gate is disposed above or below the active layer.
  • an embodiment of the present invention further provides a display device comprising the array substrate provided by any of the embodiments of the present invention.
  • an embodiment of the present invention further provides a method for fabricating an array substrate, comprising the steps of separately forming a pattern including a gate electrode and a pattern of an active layer on a substrate by a patterning process, the method further comprising A side of the pattern of the gate electrode facing the active layer forms a light absorbing layer.
  • forming a light absorbing layer on a side of the pattern of the gate facing the active layer includes: processing a surface material of a side of the gate facing the active layer to A light absorbing layer is formed.
  • processing a surface layer material of a side of the gate facing the active layer to form a light absorbing layer comprises: patterning the gate when forming a pattern of the gate After the photoresist is ashed, the pattern of the gate is further subjected to an ashing process to form a light absorbing layer on a side of the pattern of the gate facing the active layer.
  • the material of the gate includes copper;
  • the ashing process for the pattern of the gate includes: using a plasma generated by sulfur hexafluoride gas and/or oxygen in a dry etching apparatus The patterned area of the gate is etched to cause the surface layer material of the patterned region of the gate to react to form micro-grains comprising micro-grains of copper oxide and/or copper sulfide.
  • treating the surface layer material of the side of the gate facing the active layer includes making the surface of the light absorbing layer uneven.
  • forming a light absorbing layer on a side of the pattern of the gate facing the active layer includes depositing a light absorbing layer on a surface of the pattern of the gate facing the active layer .
  • the method further includes the step of forming a pattern including gate lines, the pattern of the gate lines
  • the pattern of the gate is simultaneously formed by a gray tone mask process.
  • 1 is a cross-sectional view showing the structure of a thin film transistor
  • FIG. 2 is a cross-sectional view showing the structure of an array substrate in accordance with an embodiment of the present invention
  • Figure 3 is a schematic view showing absorption of light rays irradiated thereto by the light absorbing layer of Figure 2;
  • 4-9 are schematic cross-sectional views showing a method of fabricating an array substrate according to an embodiment of the present invention, respectively showing structures formed in a plurality of steps of the preparation method.
  • An embodiment of the present invention provides an array substrate, as shown in FIGS. 1-3, comprising a substrate 1 and a transistor 2 disposed on the substrate 1, the transistor 2 including a gate electrode 21 and an active layer 22.
  • the transistor is a thin film transistor (TFT).
  • the gate 21 may not completely block the illumination of the active layer 22 by the backlight, and the backlight light entering the active layer may cause a change in the switching characteristics of the transistor, so that it is in operation. Unstable, affecting the display performance and reliability of the display; in addition, the backlight may reflect the backlight light reflected from the active layer again, and the backlight light returns to the active layer, so that the active layer is subjected to "secondary illumination. This further increases the adverse effects of backlight light on the active layer.
  • a side of the gate electrode 21 facing the active layer 22 is formed with a light absorbing layer 23 which is capable of absorbing light irradiated thereon.
  • the light absorbing layer 23 is capable of absorbing ambient light, particularly backlight light, that is incident thereon.
  • the light absorbing layer can absorb the backlight light irradiated thereon to prevent the backlight light on the active layer from being reflected on the gate, and the gate reflects the part of the light again to the active layer, thereby reducing the illumination.
  • the backlight light on the active layer reduces the adverse effects of backlight light on the switching characteristics of the transistor, and finally ensures the switching stability of the transistor and the display effect and reliability of the display device using the array substrate.
  • the material of the gate includes copper.
  • the light absorbing layer can include micro-grains of copper oxide and/or micro-grains of copper sulfide.
  • the surface of the light absorbing layer may be uneven.
  • the microcrystal grains inside the light absorbing layer are not well crystallized, so that there are many irregularities on the surface of the light absorbing layer, and the light absorbing layer of this structure has a good absorption effect on the backlight light irradiated thereon. , thereby preventing the backlight light that is irradiated thereon from being reflected again.
  • the light absorbing layer is formed by ashing (ie, dry etching) the surface material of the gate facing the active layer side.
  • the material of the gate electrode is not limited to copper, and other conductive materials may be used; correspondingly, the material of the light absorbing layer may also be some other material component formed by the material of the gate during the dry etching process;
  • the surface material of the gate facing the active layer side can be dry etched or processed by other processes to form a structure that absorbs the backlight light well.
  • the color of the light absorbing layer is black or black gray.
  • Black or black gray can further enhance the absorption of the backlight by the light absorbing layer, and improve the absorption of the backlight by the light absorbing layer.
  • the gate 21 is disposed below the active layer 22, as shown in FIGS. 1-3. That is, the transistor in this embodiment is a bottom gate type transistor.
  • the light absorbing layer has a thickness of 10-30 nm.
  • the light absorbing layer of the thickness range is capable of relatively more absorbing the backlight light that is irradiated thereon, thereby preventing the backlight light that is incident on the gate from being reflected again to the active layer.
  • the array substrate further includes a gate line, the gate line and the gate 21 are made of the same material and are disposed in the same layer; the source 24 and the drain 25 of the transistor 2 are disposed in the same layer and are respectively located in the same layer of the active layer 22 The opposite ends of the side are shown in Figure 1-3.
  • the source 24, the drain 25, and the active layer 22 are formed by a single exposure and patterning process, which saves a mask compared to the current preparation method in which the active layer and the source and drain are respectively formed by one exposure.
  • the active layer thus formed has an excessive amount of protrusion relative to the corresponding gate pattern, that is, the pattern size of the active layer is much larger than that of the gate Inch, this will make the gate located on the side close to the backlight light completely unable to block the illumination of the active layer by the backlight.
  • Some of the backlight will directly illuminate the active layer and reflect from the active layer to the gate. .
  • the light absorbing layer 23 formed on the side of the gate 21 facing the active layer 22 can absorb the partially reflected light well, and the reflected light is prevented from being reflected again onto the active layer 22, thereby Avoiding the reflected backlight light further affects the switching characteristics of transistor 2.
  • the array substrate further includes a passivation layer 4 and a pixel electrode 5, the passivation layer 4 is disposed on the source electrode 24 and the drain electrode 25, and the pixel electrode 5 is disposed on the passivation layer. 4, and the pixel electrode 5 is connected to the drain electrode 25 through a via hole opened in a region of the passivation layer 4 corresponding to the drain electrode 25.
  • the array substrate further includes a common electrode 8, a common electrode line 9, and a gate insulating layer 7, and the common electrode 8 is located below the common electrode line 9 and the two are electrically connected to each other.
  • the gate insulating layer 7 is disposed between the gate electrode 21 and the active layer 22.
  • the common electrode lines 9 are disposed in the same layer as the gate lines and insulated from each other.
  • an embodiment of the present invention further provides a method for fabricating the array substrate, as shown in FIG. 4 to FIG. 9 , including forming a pattern including the gate electrode 21 on the substrate 1 by using a patterning process.
  • the process is to form the light absorbing layer 23 on the side of the pattern of the gate electrode 21 facing the active layer.
  • the method for fabricating the array substrate further includes the step of forming a pattern including the gate lines 3, and the pattern of the gate lines 3 and the pattern of the gate electrodes 21 are simultaneously formed by a gray tone mask process.
  • forming the pattern of the gate 21 may include the following steps:
  • Step S101 depositing a gate film layer 26 on the substrate 1, and applying a photoresist 6 on the gate film layer 26 (as shown in FIG. 4).
  • the photoresist 6 is a positive photoresist. Negative photoresists may also be used in other examples, which may be determined according to process requirements such as exposure, development, and the like.
  • Step S102 exposing the photoresist 6 with a gray tone mask, and removing the portion of the photoresist 6 other than the portion corresponding to the pattern of the gate, the pattern of the gate line, and the pattern of the common electrode line (as shown in FIG. 5).
  • the portion 61) shown is subjected to full exposure; a portion of the photoresist 6 corresponding to the pattern of the gate electrode (such as portion 62 in FIG. 5) is partially exposed; a pattern corresponding to the gate line of the photoresist 6 is applied The portion of the pattern of the common electrode lines (such as portion 63 in Fig. 5) is not exposed (as shown in Fig. 5).
  • Step S103 After the step S102 is completed, the photoresist 6 on the substrate 1 is subjected to a development process to remove portions of the photoresist 6 except the pattern corresponding to the gate, the pattern of the gate lines, and the pattern of the common electrode lines. a portion other than the portion of the photoresist 6 that corresponds to the pattern of the gate electrode; the portion of the photoresist 6 corresponding to the pattern of the gate line and the portion of the pattern of the common electrode line (shown in FIG. 6) is completely retained.
  • Step S104 The portion of the gate film layer 26 corresponding to the pattern of the gate electrode 21, the pattern of the gate line 3, and the portion of the pattern of the common electrode line 9 (as shown in FIG. 7) is removed.
  • an etch process such as a wet etch, can be performed to remove portions of the gate film layer.
  • Step S105 After completing step S104, the photoresist 6 on the substrate 1 is subjected to an ashing process to remove a portion of the photoresist 6 corresponding to the pattern of the gate electrode 21; a portion of the remaining photoresist 6 corresponding to the gate The pattern of line 3 and the portion of the pattern of common electrode line 9 (shown in Figure 8).
  • Step S106 after the step S105 is completed, a portion of the photoresist 6 on the pattern of the gate electrode 21 on the substrate 1 is removed (for example, by an ashing process), and a light absorbing layer 23 is formed on the surface of the gate electrode 21. Finally, the pattern of the gate line 3 and the photoresist 6 on the pattern of the common electrode line 9 are removed (as shown in FIG. 9).
  • the patterned skin material of the gate 21 can be processed to form the light absorbing layer 23.
  • the material of the gate 21 may include copper.
  • the step of processing the surface material of the pattern of the gate 21 to form the light absorbing layer 23 may include: using a plasma generated by sulfur hexafluoride gas and/or oxygen in the dry etching apparatus to the gate 21 The pattern regions are etched such that the surface material of the pattern of the gate 21 reacts to form microcrystallites comprising copper oxide and/or copper sulfide.
  • the light absorbing layer 23 can absorb the backlight light irradiated thereon well to prevent the backlight light that is irradiated to the side of the active layer on the gate 21 from being reflected again onto the active layer, thereby reducing the illumination to the active layer. Backlighting light on the layer, which in turn reduces the adverse effects of backlighting on transistor switching characteristics.
  • a light absorbing material may also be used to form (e.g., deposit) a suitable light absorbing layer on the pattern of the gate 21.
  • the pattern of the gate line 3 and the photoresist 6 on the pattern of the common electrode line 9 may be removed while the pattern of the gate electrode 21 is processed (eg, dry etching).
  • the pattern processing of the gate electrode 21 or the light absorbing layer is formed on the pattern of the gate electrode 21 it may be peeled off by a lift-off process.
  • the ashing process in step S105 may also be to etch the photoresist 6 by using a plasma generated by sulfur hexafluoride gas and oxygen in a dry etching apparatus, and etching after etching.
  • the glue 6 is removed.
  • the method of fabricating the array substrate further includes the steps of sequentially forming a source, a drain, a passivation layer, and a pixel electrode on the substrate 1 on which the pattern of the active layer is formed using a patterning process; in some examples
  • the method for preparing the array substrate further includes the step of forming a common electrode on the substrate 1 by a patterning process before forming the pattern of the gate electrode 21 and the pattern of the gate line 3; the method of fabricating the array substrate in forming the pattern and gate of the gate electrode 21
  • the pattern of the line 3 may further include a step of forming a gate insulating layer on the substrate 1 on which the gate electrode 21 and the gate line 3 are formed by a patterning process.
  • Another embodiment of the present invention provides an array substrate.
  • the gate is disposed above the active layer, that is, the transistor in this embodiment is a top gate transistor.
  • a light absorbing layer is also formed on the side of the gate facing the active layer.
  • the light absorbing layer disposed on the side of the gate facing the active layer can also absorb the backlight light that is irradiated thereon, thereby preventing the backlight light that is irradiated to the side of the active layer of the gate from being reflected again to the active layer. Further, the backlight light that is irradiated onto the active layer is reduced, and finally the adverse effect of the backlight light on the switching characteristics of the transistor is reduced.
  • the method for preparing the array substrate in this embodiment is different from the above embodiment in that an active layer is first formed on a substrate by a patterning process; then a gate insulating layer is formed, and then a gate insulating layer is formed by a patterning process.
  • a pattern of the light absorbing layer and the gate is formed on the substrate of the layer such that the light absorbing layer is located on a side of the gate facing the active layer (facing the gate insulating layer).
  • the step of forming a pattern of the light absorbing layer and the gate on the substrate on which the gate insulating layer is formed may include first forming (eg, depositing) a layer of the film material on the substrate on which the gate insulating layer is formed. And coating a photoresist on the film material; in some examples, the film material may be the same as the material of the gate to be formed, and the formed film material may be a thin layer, for example, 10 nm to 30 nm.
  • a light absorbing layer by processing (such as ashing, dry etching, etc.); then removing portions of the photoresist other than the portion corresponding to the pattern of the gate by exposure and development; then using ashing
  • the process ashes the portion of the photoresist corresponding to the pattern of the gate, and after the ash is completed, the portion of the pattern corresponding to the pattern of the gate material is processed (for example, ashing or dry etching) ), the pattern of the light absorbing layer is finally formed.
  • the specific method of processing the portion of the pattern corresponding to the pattern of the gate material may be the same as the above embodiment, and details are not described herein again.
  • the pattern for forming the gate and the gate line can be a conventional patterning process, and details are not described herein.
  • the film material may also be a light absorbing material so that the light absorbing layer can be formed without the above treatment.
  • the backlight light irradiated thereon can be absorbed, thereby avoiding irradiation onto the active layer.
  • the gate reflects the part of the light again to the active layer, thereby reducing the backlight light that is irradiated onto the active layer, thereby reducing the influence of the backlight light on the switching characteristics of the transistor, and finally ensuring the transistor. Switching stability and display performance and reliability of a display device using the array substrate.
  • Embodiments of the present invention also provide a display device comprising the array substrate provided in any of the embodiments of the present invention.
  • the display stability of the display device is improved, thereby improving the display effect and reliability of the display device.
  • the display device provided by the present invention may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a display, a mobile phone, a navigator or the like.

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Abstract

一种阵列基板及其制备方法和显示装置。阵列基板包括衬底（1）和设置在衬底（1）上的晶体管（2），晶体管（2）包括栅极（21）和有源层（22）；栅极（21）的面向有源层（22）的一侧形成有光线吸收层（23），光线吸收层（23）被构造成吸收照射到其上的光线。

Description

阵列基板及其制备方法和显示装置
本申请主张在2017年1月20日在中国专利局提交的中国专利申请No.201710042098.0的优先权，其全部内容通过引用包含于此。
技术领域
本发明的实施例一般地涉及显示技术领域，并且具体地，涉及一种阵列基板及其制备方法和显示装置。
背景技术
由于曝光设备的昂贵，曝光环节一直是包括显示屏在内的半导体器件制造中成本控制的重点。
为节省曝光成本，目前较多阵列基板的薄膜晶体管(TFT)制备工艺流程将有源层和源/漏极用一次曝光做成，这种工艺方法节省了一道掩模(Mask)工艺，因此在节省生产工艺步骤和曝光设备成本上有明显的优势。
但是，这种工艺会导致有源层相对位于其下方的栅极图形伸出量过多，使得底部栅极无法完全遮挡背光源对有源层的照射，进入到有源层的背光光线会造成薄膜晶体管(TFT)开关特性的改变，使之在工作中不稳定，影响显示器的显示效果和可信赖性。
发明内容
为了克服或消除现有技术存在的上述和其它问题和缺陷中的至少一种，提出了本公开。
在一个方面中，本发明的实施例提供一种阵列基板，包括衬底和设置在所述衬底上的晶体管，所述晶体管包括栅极和有源层；其中，所述栅极的面向所述有源层的一侧形成有光线吸收层，所述光线吸收层被构造成吸收照射到其上的光线。
在一个实施例中，所述光线吸收层的表面呈凹凸不平状。
在一个实施例中，所述光线吸收层包含铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。
在一个实施例中，所述栅极的材料包括铜。
在一个实施例中，所述光线吸收层包含铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。
在一个实施例中，光线吸收层与栅极形成为一体结构或光线吸收层单独地形成在栅极的表面上。
在一个实施例中，所述光线吸收层的颜色为黑色或黑灰色。
在一个实施例中，所述光线吸收层的厚度在10nm至30nm的范围内。
在一个实施例中，所述晶体管还包括同层设置且分别位于所述有源层的同一侧的相对两端的源极和漏极。
在一个实施例中，所述栅极设置于所述有源层的上方或下方。
在另一个方面中，本发明的实施例还提供一种显示装置，包括本发明的任一实施例提供的阵列基板。
在又一方面中，本发明的实施例还提供一种阵列基板的制备方法，包括采用构图工艺在衬底上分别形成包括栅极的图形和有源层的图形的步骤，该方法还包括在所述栅极的图形的面向所述有源层的一侧形成光线吸收层。
在一个实施例中，在所述栅极的图形的面向所述有源层的一侧形成光线吸收层包括：对所述栅极的面向所述有源层的一侧的表层材料进行处理以形成光线吸收层。
在一个实施例中，对所述栅极的面向所述有源层的一侧的表层材料进行处理以形成光线吸收层包括：在形成所述栅极的图形时，将所述栅极的图形上的光刻胶灰化完毕后，继续对所述栅极的图形进行灰化工艺，以在所述栅极的图形的面向所述有源层的一侧形成光线吸收层。
在一个实施例中，所述栅极的材料包括铜；对所述栅极的图形的灰化工艺包括：在干刻设备中采用六氟化硫气体和/或氧气产生的等离子体对所述栅极的图形区域进行刻蚀，以使所述栅极的图形区域的表层材料反应生成包括铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。
在一个实施例中，对所述栅极的面向所述有源层的一侧的表层材料进行处理包括使所述光线吸收层的表面呈凹凸不平状。
在一个实施例中，在所述栅极的图形的面向所述有源层的一侧形成光线吸收层包括：在所述栅极的图形的面向所述有源层的表面上沉积光线吸收层。
在一个实施例中，还包括形成包括栅线的图形的步骤，所述栅线的图形和 所述栅极的图形通过灰色调掩模工艺同时形成。
附图说明
图1为一种薄膜晶体管的结构剖视图；
图2为示出根据本发明的一种实施例的阵列基板的结构的剖视图；
图3为示出图2中的光线吸收层对照射到其上的光线的吸收的示意图；以及
图4-9为根据本发明的一个实施例的阵列基板的制备方法的剖面示意图，分别示出了在该制备方法的多个步骤中形成的结构。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
本发明的实施例提供一种阵列基板，如图1-3所示，包括衬底1和设置在衬底1上的晶体管2，晶体管2包括栅极21和有源层22。在一些示例中，该晶体管是薄膜晶体管(TFT)。
在一些情况中，如图1所示，栅极21可能无法完全遮挡背光源对有源层22的照射，进入到有源层的背光光线会造成晶体管的开关特性的改变，使之在工作中不稳定，影响显示器的显示效果和可信赖性；此外，栅极可能对从有源层反射回来的背光光线会再次反射，背光光线重新回到有源层，使得有源层受到“二次照射”，这进一步增加了背光源光线对有源层的不利影响。
在本发明的一些实施例中，如图2和3所示，栅极21面向有源层22的一侧形成有光线吸收层23，光线吸收层23能对照射到其上的光线进行吸收。示例性地，光线吸收层23能对照射到其上的外界光线特别是背光光线进行吸收。
根据本发明的实施例，通过在栅极的面向有源层的一侧形成光线吸收层， 该光线吸收层能够将照射到其上的背光光线进行吸收，从而避免照射到有源层上的背光光线反射到栅极上之后，栅极将该部分光线再次反射到有源层，进而减少照射到有源层上的背光光线，以减少背光光线对晶体管的开关特性造成的不利影响，最终确保晶体管的开关稳定性和采用该阵列基板的显示装置的显示效果和可信赖性。
在一个示例性实施例中，栅极的材料包括铜。在一些示例中，光线吸收层可以包括铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。在另一些示例中，光线吸收层的表面可以呈凹凸不平状。例如，光线吸收层内部的微晶粒没有很好地结晶，所以使光线吸收层表面存在很多凹凸不平的缺陷，这种结构的光线吸收层对照射到其上的背光光线有很好的吸收作用，从而防止照射到其上的背光光线发生再次反射。
在一种实施例中，光线吸收层是对栅极的面向有源层一侧的表层材料进行灰化(即干法刻蚀)后所形成的。栅极的材料不仅仅局限于铜，也可以采用其他的一些导电材料；相应地，光线吸收层的材料也可以是栅极的材料在干法刻蚀过程中形成的一些其他材料成分；只要确保使栅极的面向有源层一侧的表层材料干法刻蚀或通过其它工艺处理后能够形成很好的吸收背光光线的结构即可。
在一个示例中，光线吸收层的颜色为黑色或黑灰色。黑色或黑灰色能够进一步增强光线吸收层对背光光线的吸收作用，提高光线吸收层对背光光线的吸收效果。
在一个实施例中，栅极21设置于有源层22的下方，如图1-3所示。即本实施例中的晶体管为底栅型晶体管。
在一个示例中，光线吸收层的厚度为10-30nm。该厚度范围的光线吸收层能够对照射到其上的背光光线进行比较彻底的吸收，从而避免照射到栅极上的背光光线被再次反射到有源层。
在一些实施例中，阵列基板还包括栅线，栅线与栅极21采用相同材料且同层设置；晶体管2的源极24和漏极25同层设置，且分别位于有源层22的同一侧的相对两端，如图1-3所示。在一些示例中，源极24、漏极25和有源层22采用一次曝光和图案化工艺形成，相对于目前有源层与源极和漏极分别采用一次曝光形成的制备方法节省了一道掩模工艺，但这样形成的有源层相对于与其对应的栅极图形伸出量过多，即有源层的图形尺寸远大于栅极的图形尺 寸，这会使得位于靠近背光光线一侧的栅极无法完全遮挡住背光光线对有源层的照射，背光光线有一部分会直接照射到有源层上，并从有源层反射到栅极上。在本发明的实施例中，栅极21的面向有源层22一侧形成的光线吸收层23能够很好地吸收这部分反射光线，避免这部分反射光线再次反射到有源层22上，从而避免反射的背光光线对晶体管2开关特性的进一步影响。
在一些实施例中，如图1-3所示，阵列基板还包括钝化层4和像素电极5，钝化层4设置于源极24和漏极25上，像素电极5设置于钝化层4上，且像素电极5通过开设在钝化层4中对应漏极25所在区域的过孔与漏极25连接。在另一些实施例中，如图1-3所示，阵列基板还包括公共电极8、公共电极线9和栅极绝缘层7，公共电极8位于公共电极线9的下方且二者相互电连接，栅极绝缘层7设置于栅极21和有源层22之间。在一个示例中，公共电极线9与栅线同层设置且相互绝缘。
基于阵列基板的上述结构，本发明的实施例还提供一种该阵列基板的制备方法，如图4-图9所示，包括采用构图工艺在衬底1上分别形成包括栅极21的图形和有源层的图形的步骤，在形成栅极21的图形时，将栅极21的图形上的光刻胶6灰化完毕后，继续对栅极21的图形进行灰化(如干法刻蚀)工艺，以在栅极21的图形的面向有源层的一侧形成光线吸收层23。
本实施例中，该阵列基板的制备方法还包括形成包括栅线3的图形的步骤，栅线3的图形和栅极21的图形通过灰色调掩模工艺同时形成。
在一个实施例中，形成栅极21的图形可以包括以下步骤：
步骤S101：在衬底1上沉积形成栅极膜层26，并在栅极膜层26上涂敷光刻胶6(如图4所示)。
在一个示例中，光刻胶6为正性光刻胶。在其它示例中也可以采用负性光刻胶，这可以根据曝光、显影等工艺要求确定。
步骤S102：采用灰色调掩模板对光刻胶6进行曝光，对光刻胶6的除对应于栅极的图形、栅线的图形和公共电极线的图形的部分以外的部分(如图5中示出的部分61)进行完全曝光；将光刻胶6的对应于栅极的图形的的部分(如图5中的部分62)进行部分曝光；对光刻胶6的对应于栅线的图形和公共电极线的图形的部分(如图5中的部分63)不曝光(如图5所示)。
步骤S103：在完成步骤S102后，对衬底1上的光刻胶6进行显影工艺，去除光刻胶6的除对应于栅极的图形、栅线的图形和公共电极线的图形的部分 以外的部分；部分保留光刻胶6的对应于栅极的图形的部分；完全保留光刻胶6对应于栅线的图形和公共电极线的图形的部分(如图6所示)。
步骤S104：去除栅极膜层26的对应于栅极21的图形、栅线3的图形和公共电极线9的图形的部分以外的部分(如图7所示)。在一个示例中，可以刻蚀工艺，如湿法刻蚀，去除栅极膜层的这些部分。
步骤S105：在完成步骤S104后，对衬底1上的光刻胶6进行灰化工艺，去除光刻胶6的对应于栅极21的图形的部分；部分保留光刻胶6的对应于栅线3的图形和公共电极线9的图形的部分(如图8所示)。
步骤S106：在完成步骤S105之后，(例如通过灰化工艺)去除光刻胶6的位于衬底1上的栅极21的图形上的部分，并在栅极21的表面上形成光线吸收层23；最后，去除栅线3的图形和公共电极线9的图形上的光刻胶6(如图9所示)。
在一些实施例中，可以对栅极21的图形的表层材料进行处理以形成光线吸收层23。例如，栅极21的材料可以包括铜。示例性地，对栅极21的图形的表层材料进行处理以形成光线吸收层23的步骤可以包括：在干刻设备中采用六氟化硫气体和/或氧气产生的等离子体对栅极21的图形区域进行刻蚀，以使栅极21的图形的表层材料反应生成包括铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。这些微晶粒无法很好地结晶，所以使栅极21的图形的表层最终形成凹凸不平的缺陷，同时，处理后的栅极21的图形的表层材料呈黑色或黑灰色，这种结构和颜色的光线吸收层23能够很好地对照射到其上的背光光线进行吸收，以避免照射到栅极21面向有源层一侧的背光光线再次反射到有源层上，从而减少照射到有源层上的背光光线，进而减少背光光线对晶体管开关特性的不良影响。在其它实施例中，也可以采用光吸收材料在栅极21的图形上形成(如沉积)合适的光线吸收层。
需要说明的是，该步骤中，栅线3的图形和公共电极线9的图形上的光刻胶6可以是在对栅极21的图形进行处理(如干法刻蚀)完毕的同时被去除，也可以是在对栅极21的图形处理完毕或在栅极21的图形上形成光线吸收层后再通过剥离工艺被剥离掉。
另外，在一些示例中，步骤S105中的灰化工艺同样可以是在干刻设备中采用六氟化硫气体和氧气产生的等离子体对光刻胶6进行刻蚀，经刻蚀后的光刻胶6被去除。
在一些实施例中，该阵列基板的制备方法还包括采用构图工艺在形成有源层的图形的衬底1上依次形成源极、漏极、钝化层和像素电极的步骤；在一些示例中，该阵列基板的制备方法在形成栅极21的图形和栅线3的图形之前还包括采用构图工艺在衬底1形成公共电极的步骤；阵列基板的制备方法在形成栅极21的图形和栅线3的图形之后还可以包括：采用构图工艺在形成栅极21和栅线3的衬底1上形成栅极绝缘层的步骤。
本发明的另一种实施例提供一种阵列基板，与上述实施例不同的是，栅极设置于有源层的上方，即本实施例中的晶体管为顶栅型晶体管。同样，在本实施例中，在栅极的面向有源层一侧形成也形成有光线吸收层。设置在栅极的面向有源层一侧的光线吸收层同样能对照射到其上的背光光线进行吸收，从而避免照射到栅极的面向有源层一侧的背光光线再次反射到有源层上，进而减少照射到有源层上的背光光线，最终减少背光光线对晶体管开关特性的不良影响。
相应地，本实施例中阵列基板的制备方法与上述实施例不同之处是，首先采用构图工艺在衬底上形成有源层；然后形成栅极绝缘层，其次采用构图工艺在形成栅极绝缘层的衬底上形成光线吸收层和栅极的图形，使得光线吸收层位于栅极的面向有源层(面向栅极绝缘层)的一侧。
在一些示例中，在形成栅极绝缘层的衬底上形成光线吸收层和栅极的图形的步骤可以包括：首先在形成栅极绝缘层的衬底上形成(如沉积)一层膜层材料，并在该膜层材料上涂敷光刻胶；在一些示例中，该膜层材料可以与将形成的栅极的材料相同，所形成的膜层材料可以是一薄层，例如10nm至30nm，以便于通过处理(如灰化，干法刻蚀等)而形成光线吸收层；然后通过曝光和显影将光刻胶的除对应于栅极的图形的部分以外的部分去除；接着采用灰化工艺对光刻胶的对应于栅极的图形的部分进行灰化，光刻胶灰化完毕后继续对膜层材料对应于栅极的图形的部分进行处理(例如，灰化或干法刻蚀)，最终形成光线吸收层的图形。在一些示例中，对膜层材料对应于栅极的图形的部分进行处理的具体方法可以与上述实施例相同，这里不再赘述。之后，再采用构图工艺在形成光线吸收层的衬底上形成栅极和栅线的图形。形成栅极和栅线的图形可以采用传统的构图工艺，具体不再赘述。在其它示例中，该膜层材料也可以是光吸收材料，从而无需对其进行上述处理就可以形成光线吸收层。
本实施例中阵列基板的其他结构及其制备方法的其他步骤与上述实施例中相同，此处不再赘述。
在本发明的实施例所提供的阵列基板中，通过在栅极的面向有源层的一侧形成光线吸收层，能够将照射到其上的背光光线进行吸收，从而避免照射到有源层上的背光光线反射到栅极上之后，栅极将该部分光线再次反射到有源层，进而减少照射到有源层上的背光光线，以减少背光光线对晶体管的开关特性造成影响，最终确保晶体管的开关稳定性和采用该阵列基板的显示装置的显示效果和可信赖性。
本发明的实施例还提供一种显示装置，包括本发明的任一实施例中提供的阵列基板。
通过采用本发明实施例提供的阵列基板，提升了该显示装置的显示稳定性，从而提升了该显示装置的显示效果和可信赖性。
本发明所提供的显示装置可以为液晶面板、液晶电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (17)

  1. 一种阵列基板，包括衬底和设置在所述衬底上的晶体管，所述晶体管包括栅极和有源层，其中，
    所述栅极的面向所述有源层的一侧形成有光线吸收层，所述光线吸收层被构造成吸收照射到其上的光线。
  2. 根据权利要求1所述的阵列基板，其中，所述光线吸收层的表面呈凹凸不平状。
  3. 根据权利要求1或2所述的阵列基板，其中，所述光线吸收层包含铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，所述栅极的材料包括铜。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，光线吸收层与栅极形成为一体结构或光线吸收层单独地形成在栅极的表面上。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述光线吸收层的颜色为黑色或黑灰色。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中，所述光线吸收层的厚度在10nm至30nm的范围内。
  8. 根据权利要求1-7中任一项所述的阵列基板，其中，所述晶体管还包括同层设置且分别位于所述有源层的同一侧的相对两端的源极和漏极。
  9. 根据权利要求1-8中任一项所述的阵列基板，其中，所述栅极设置于所述有源层的上方或下方。
  10. 一种显示装置，包括权利要求1-9中任一项所述的阵列基板。
  11. 一种如权利要求1-9中任一项所述的阵列基板的制备方法，包括采用构图工艺在衬底上分别形成包括栅极的图形和有源层的图形的步骤，其中
    该方法还包括在所述栅极的图形的面向所述有源层的一侧形成光线吸收层。
  12. 根据权利要求11所述的制备方法，其中在所述栅极的图形的面向所述有源层的一侧形成光线吸收层包括：
    对所述栅极的面向所述有源层的一侧的表层材料进行处理以形成光线吸收层。
  13. 根据权利要求12所述的制备方法，其中对所述栅极的面向所述有源层的一侧的表层材料进行处理以形成光线吸收层包括：
    在形成所述栅极的图形时，将所述栅极的图形上的光刻胶灰化完毕后，继续对所述栅极的图形进行灰化工艺，以在所述栅极的图形的面向所述有源层的一侧形成光线吸收层。
  14. 根据权利要求13所述的制备方法，其中，所述栅极的材料包括铜；对所述栅极的图形的灰化工艺包括：在干刻设备中采用六氟化硫气体和/或氧气产生的等离子体对所述栅极的图形进行刻蚀，以使所述栅极的图形的表层材料反应生成包括铜的氧化物的微晶粒和/或铜的硫化物的微晶粒。
  15. 根据权利要求12-14中任一项所述的制备方法，其中对所述栅极的面向所述有源层的一侧的表层材料进行处理包括使所述光线吸收层的表面呈凹凸不平状。
  16. 根据权利要求11所述的制备方法，其中在所述栅极的图形的面向所述有源层的一侧形成光线吸收层包括：
    在所述栅极的图形的面向所述有源层的表面上沉积光线吸收层。
  17. 根据权利要求11-16中任一项所述的制备方法，还包括形成包括栅线的图形的步骤，所述栅线的图形和所述栅极的图形通过灰色调掩模工艺同时形成。
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