WO2016145822A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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WO2016145822A1
WO2016145822A1 PCT/CN2015/090687 CN2015090687W WO2016145822A1 WO 2016145822 A1 WO2016145822 A1 WO 2016145822A1 CN 2015090687 W CN2015090687 W CN 2015090687W WO 2016145822 A1 WO2016145822 A1 WO 2016145822A1
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region
photoresist
layer
barrier layer
gate insulating
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PCT/CN2015/090687
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English (en)
French (fr)
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陈江博
成军
姜春生
刘晓娣
孔祥永
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京东方科技集团股份有限公司
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Priority to US15/122,172 priority Critical patent/US9837477B2/en
Publication of WO2016145822A1 publication Critical patent/WO2016145822A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • a pixel driving circuit of an AMOLED (Active Matrix Driving Organic Light Emitting Diode) display panel generally includes at least two TFTs (Thin Film Transistors) and one storage capacitor, one of which is a switching TFT (Switching) TFT), the other is a driving TFT (Driving TFT).
  • TFTs Thin Film Transistors
  • switching TFT switching
  • driving TFT Driving TFT
  • 1 is a schematic structural view of an AMOLED array substrate including a pixel driving circuit at one pixel, the array substrate including a substrate 1, a gate pattern formed on the substrate 1, and the gate pattern is formed by a switching TFT in the figure.
  • a gate electrode 2a and a gate electrode 2b of the driving TFT a gate insulating layer 3 is formed over the gate pattern, and an active layer pattern 4 is formed over the gate insulating layer 3 in a region above the gate electrode 2a.
  • an etch barrier layer 5 is formed over the active layer pattern 4 and the gate insulating layer 3, in the etch barrier
  • An active drain electrode pattern is formed above the layer 5, and the drain electrode pattern includes a source/drain electrode 6a of the switching TFT and a source/drain electrode 6b of the driving TFT.
  • the source and drain electrodes 6a of the switching TFT are connected to the active layer pattern 4 through the source via hole A11 and the drain via hole A12 on the etch barrier layer 5, and the drain passes through the via hole A12 on the etch barrier layer 5 and
  • the source layer pattern 4 is connected, and the source and drain electrodes 6b of the driving TFT are connected to the gate electrode 2b through the gate insulating layer 3 and the via hole B1 on the etch barrier layer 5.
  • a resin layer 7 is formed over the source/drain electrode pattern, and a pixel electrode pattern 8 formed over the resin layer 7, which is disposed at a position corresponding to the source and drain of the source/drain electrode 6a.
  • via holes are provided at positions corresponding to the source/drain electrodes 6b (not indicated by reference numerals in FIG. 1), and the pixel electrode patterns 8 pass through the via holes A22 and via holes.
  • B2 connects the drain of the source/drain electrode 6a to the source/drain electrode 6b, and the via hole A21 is used to connect the data line.
  • the pixel electrode pattern 8 is transferred to the driving TFT, the driving TFT is turned on, the current flows from the source to the drain, and the driving TFT is connected to a storage capacitor (not shown) to charge the capacitor, and when the scanning line is turned off, the storage is performed.
  • the voltage in the capacitor can still keep the driving TFT in the on state, so the fixed current of the OLED can be maintained in one screen.
  • An object of the present invention is to form a via of a switching TFT and a via hole for driving a TFT by a single patterning process, and to reduce the degree of damage of a channel of a via region of the switching TFT.
  • a method of fabricating an array substrate includes a first region corresponding to a via of a switching transistor, a second region corresponding to a via of a driving transistor, and a first region and a third region outside the second region, the method comprising: forming a gate pattern, a gate insulating layer, an active layer pattern, and an etch barrier layer on the substrate; forming a photoresist layer on the etch barrier layer; The engraved layer is subjected to a patterning process, so that the photoresist in the first region is partially etched, and the second The photoresist in the region is completely etched, and the photoresist in the third region is completely retained; the remaining photoresist and the etch barrier in the first region are etched by the same etching process while etching The etch stop layer and the gate insulating layer in the second region are removed.
  • the step of performing a patterning process on the photoresist layer includes: performing incomplete exposure of the photoresist layer in the first region by using the same mask to make the photoresist in the first region Partially removed, the photoresist in the second region is completely exposed to completely remove the photoresist in the second region.
  • the step of exposing using the same mask comprises: exposing the photoresist layer using a slit mask, the slit mask having in the first region The slit has an opening in the second region.
  • the step of exposing using the same mask comprises: exposing the photoresist layer using a gray tone mask or a halftone mask, the gray mask or halftone mask
  • the plate is translucent in the first region and completely transparent in the second region.
  • the step of forming a photoresist layer on the etch barrier layer includes: forming a photoresist layer on the etch barrier layer such that the photoresist in the second region has a first thickness, The photoresist in the first region has a second thickness, and the second thickness is greater than the first thickness; and the second thickness is set to be when the photoresist layer in the first region is completely etched, The etch stop layer and the gate insulating layer of the second region are not completely etched.
  • the etching step includes: ashing the photoresist in the first region after the etch barrier layer and the gate insulating layer of the second region are etched to a certain thickness Processing, removing the remaining photoresist in the first region; continuing to etch the etch stop layer of the first region and the etch stop layer and the gate insulating layer of the second region are completely etched.
  • the step of ashing the photoresist in the first region comprises: ashing the remaining photoresist in the first region using an oxygen plasma gas.
  • the gate insulating layer and the etch stop layer are made of the same material; and the step of ashing the photoresist in the first region includes: at the second Area When the thickness of the remaining material to be etched in the domain is the same as the original thickness of the etch barrier layer in the first region, the photoresist layer of the first region is subjected to ashing treatment to remove the first region. The remaining photoresist.
  • the gate insulating layer and the etch barrier layer are made of silicon oxide.
  • the method further includes forming a source-drain electrode pattern on the etch barrier layer and forming a pixel electrode pattern over the source-drain electrode pattern after the etching process;
  • the pixel electrode pattern connects a drain of the switching transistor and a gate of the driving transistor.
  • an array substrate fabricated by the method of fabricating an array substrate according to any of the above-described exemplary embodiments.
  • the method for fabricating the array substrate provided by the invention has a photoresist layer remaining above the via region of the switching transistor, thereby increasing the thickness of the material to be etched over the active layer of the switching transistor, thereby avoiding active
  • the time the layer is etched reduces the extent to which the active layer is damaged.
  • only one patterning process is used, which simplifies the fabrication process.
  • FIG. 1 is a schematic structural view of an AMOLED array substrate at one pixel
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • step S12 is a schematic structural view of a substrate obtained after step S12 at one pixel;
  • step S13 is a schematic structural view of a substrate obtained after step S13 at one pixel;
  • step S14 is a schematic structural view of a substrate obtained after step S14 at one pixel;
  • FIG. 6 is a schematic structural view of a substrate obtained after step S15 at one pixel;
  • step S3 is a schematic structural view of a substrate obtained after step S3 at one pixel;
  • step S4 is a schematic structural view of a substrate obtained after step S4 at one pixel;
  • step S5 is a schematic structural view of a substrate obtained after step S5 at one pixel;
  • FIG. 10 is a schematic structural view of a substrate obtained after step S6 at one pixel.
  • An embodiment of the present invention provides a method of fabricating an array substrate, wherein the array substrate includes a first region corresponding to a via of a switching transistor, a second region corresponding to a via of a driving transistor, and a first region And a third area outside the second area, as shown in FIG. 2, the method includes the following steps:
  • step S1 a gate pattern, a gate insulating layer, an active layer pattern, and an etch barrier layer are formed on the substrate.
  • Step S2 forming a photoresist layer on the etch barrier layer.
  • Step S3 performing a patterning process on the photoresist layer, so that the photoresist in the first region is partially etched, the photoresist in the second region is completely etched, and in the third region. The photoresist inside is completely retained.
  • step S4 in the same etching process, the remaining photoresist and the etch barrier layer in the first region are etched away, and the etch barrier layer and the gate insulating layer in the second region are etched and etched away.
  • the thickness of the material to be etched over the active layer of the switching transistor is increased, thereby avoiding the active layer being etched. Time reduces the extent to which the active layer is damaged.
  • only one patterning process is used, which simplifies the fabrication process.
  • step S1 may specifically include the following steps (not shown in the figure):
  • step S11 a transparent substrate is provided, and the transparent substrate is cleaned.
  • the transparent substrate here may specifically be a glass substrate.
  • step S12 a gate material layer of 50 to 400 nm is deposited on the transparent substrate by a sputtering process or an evaporation process, and a gate pattern is formed by patterning and etching.
  • the gate material layer herein may be formed of a metal material.
  • the patterning and etching process for forming the gate pattern may specifically include: coating a photoresist on the gate material layer, and then exposing and developing the photoresist by using a mask, leaving only the lithography of the gate pattern region. After the glue is used, the remaining photoresist is used as a protective layer, and the gate material layer is etched by an etching solution to form a gate pattern.
  • FIG 3 is a schematic structural view of a substrate obtained after step S12 at one pixel, including a substrate 1, a gate 2a and a gate 2b formed on the substrate.
  • step S13 SiOx having a thickness of 100 to 500 nm is prepared as a gate insulating layer by chemical vapor deposition.
  • step S13 is a schematic structural view of a substrate obtained after step S13 at one pixel, and different from FIG. 3, further including a gate insulating layer 3 over the gate 2a and the gate 2b, the gate insulating layer 3 covering the All areas within the pixel.
  • Step S14 depositing an active material layer on the gate insulating layer by a sputtering process, and performing a patterning and etching process to obtain an active layer pattern.
  • step S14 For the specific manner of step S14, reference may be made to the process of forming the gate pattern in the above step S12, which will not be described in detail herein.
  • the above active material layer can be made of IGZO (indium gallium zinc oxide).
  • 5 is a schematic structural view of a substrate obtained after step S14 at one pixel. Different from FIG. 4, an active layer pattern 4 is also disposed over the gate insulating layer 3, and the active layer pattern 4 is located at the gate 2a. Above. There is no active layer pattern above the gate 2b.
  • step S15 silicon oxide having a thickness of 50 to 500 nm is prepared as an etch barrier layer by chemical vapor deposition on the substrate obtained in step S14.
  • FIG. 6 is a schematic structural view of a substrate obtained after step S15 at one pixel. Unlike FIG. 5, an etch stop layer 5 is formed over the active layer pattern 4 and the gate insulating layer 3, and an etch stop is formed.
  • the barrier layer 5 covers all areas within the pixel.
  • silicon nitride can also be used as an etch barrier.
  • step S1 is completed.
  • a photoresist layer may be formed over the etch barrier layer by coating.
  • the photoresist layer herein may be a light-sensitive mixed liquid composed of three main components of a photosensitive resin, a sensitizer, and a solvent. After the photosensitive resin is irradiated, a photocuring reaction can be quickly performed in the exposed region, and the cured photosensitive resin can be washed away by a specific solution.
  • step S3 can also be implemented in various ways.
  • One of the methods may be: using the same mask to incompletely expose the photoresist in the first region to partially remove the photoresist in the first region, and photolithography in the second region.
  • the glue is fully exposed to completely remove the photoresist in the second region.
  • full exposure to a region is the complete transmission of light in that region, and full exposure to a region refers to the transmission of light portions in that region.
  • the mask here may be a slit mask having a slit in the first region and an opening in the second region.
  • the slit here refers to a slit having a width corresponding to the wavelength of the light used, and the light is diffracted as it passes through the respective slits, and the photoresist under the region is uniformly incompletely exposed due to the interference under the region.
  • the opening here refers to a slit whose width is much larger than the wavelength of light. When the light passes through the opening, the diffraction phenomenon is not obvious, and the photoresist under the opening is completely exposed.
  • the mask plate here may expose the photoresist layer by a gray tone mask or a halftone mask, the gray mask or halftone mask being translucent in the first region, in the first The second area is completely transparent.
  • FIG. 7 is a schematic view showing the structure of the substrate obtained after the step S3 at one pixel, on which the photoresist 9 is coated on the etch barrier layer 5, in the region a11 for forming the A11 hole in the photoresist and for The region a12 where the A12 hole is formed, the photoresist 9 is partially retained, and the photoresist 9 is completely removed in the region b1 corresponding to the hole for forming the B1, and the photoresist 9 is completely retained in other regions.
  • a schematic view of a slit mask 10 is also shown, which has a plurality of slits in the region for forming the a11 region and the a12 region, for forming b1.
  • the area of the aperture area has an opening.
  • the photoresist layer of the first region is formed by the same etching process (for example, a dry etching process).
  • etching process for example, a dry etching process.
  • a photoresist layer may be formed on the etch barrier layer such that the photoresist in the second region has a first thickness, and the photoresist in the first region has a second thickness. And the second thickness is greater than the first thickness;
  • the second thickness needs to be set such that when the photoresist layer of the first region is completely etched, the etch barrier layer and the gate insulating layer of the second region are not completely etched;
  • step S4 may include:
  • the photoresist of the first region is ashed to remove the photoresist remaining in the first region; and the etching is continued until The etch stop layer of the first region and the gate insulating layer and the etch stop layer of the second region are completely etched.
  • the thickness of the applied photoresist is 1500 nm.
  • the thickness of the photoresist in the first region may be 2000 nm.
  • the gate insulating layer and the etch stop layer are made of the same material, such as silicon oxide, in practical applications, in the above step S4, the remaining oxidation in the second region
  • the thickness of the silicon ie, the sum of the thicknesses of the gate insulating layer and the etch stop layer (how else remains)
  • the photoresist is ashed to remove the remaining photoresist in the first region.
  • the same dry etching process can be used to make the etch barrier material of the first region completely etched, and the gate insulating material of the second region is also completely etched. Avoid over-etching the gate of the active layer pattern or the via region of the driving TFT.
  • the first layer may be etched when the etch barrier layer is completely etched.
  • the remaining photoresist in the area is ashed.
  • the ashing treatment herein may specifically be: ashing the remaining photoresist layer in the first region using an oxygen plasma gas.
  • an oxygen plasma gas may also be used to ash the remaining photoresist in the first region.
  • FIG. 8 is a schematic structural view of the substrate obtained after the step S4 at one pixel, compared with FIG.
  • the barrier layer 5 has a source via hole A11 and a drain via hole A12 formed above the gate electrode 2a, and a via hole B1 is formed above the gate electrode 2b.
  • the foregoing method may further include: not shown in the figure:
  • Step S5 depositing a source/drain metal layer on the substrate obtained in step S4, and forming a source/drain electrode pattern by a patterning process.
  • the source/drain electrode layer includes a source/drain electrode of the switching TFT and a source/drain electrode of the driving TFT.
  • FIG. 9 is a schematic view showing the structure of the substrate obtained after the step S5 at one pixel.
  • an active drain electrode pattern is further formed over the etch barrier layer 5.
  • the source-drain electrode pattern includes a source-drain electrode 6a of the switching TFT and a source-drain electrode 6b of the driving TFT.
  • the source and drain electrodes 6a of the switching TFT are respectively connected to the active layer pattern 4 through the source via A11 and the drain A12 on the etch barrier layer 5, and the source and drain electrodes 6b of the driving TFT pass through the etch barrier layer 5 and the gate insulating layer.
  • the via B1 on 3 is connected to the gate 2b.
  • the above method may further include: a step S6, forming a resin layer on the source/drain electrode pattern, and then switching the TFT in the resin layer by a patterning process.
  • Two via holes are formed above the source and drain electrodes, and a via hole is formed above the source and drain electrodes of the driving TFT.
  • 10 is a schematic structural view of a substrate obtained after step S6 at one pixel. Unlike FIG. 9, a resin layer 7 is further formed over the source/drain electrode pattern, and the resin layer 7 is formed.
  • the hole A21 is provided at a position corresponding to the source via A11, the via A22 is formed at a position corresponding to the drain via A12, and the via B2 is formed above the source/drain electrode 6b.
  • the method may further include a step (not shown): step S7, forming a pixel electrode pattern on the resin layer, the pixel electrode pattern connecting the drain and the driving of the switching transistor The gate of the transistor.
  • a pixel electrode material may be deposited on the substrate obtained in step S5, because in step S6, the formed pixel electrode material connects the drain of the switching transistor and the gate of the driving transistor, further passing The patterning process forms a corresponding pixel electrode pattern.
  • a schematic diagram of the substrate obtained after forming the pixel electrode pattern at one pixel can be as shown in FIG.
  • the above method when the above method is also used to fabricate AMOLED+COA (Color On Array), the above method should also include the process of fabricating a color filter.
  • the above method can be used to fabricate a WOLED (White OLED, white OLED), and can also be used to fabricate an array substrate such as a PLED.
  • the present invention also provides an array substrate which is an array substrate produced by the method described in any of the above.

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Abstract

提供了一种阵列基板及其制作方法，其中阵列基板包括与开关晶体管的过孔对应的第一区域、与驱动晶体管的过孔对应的第二区域、以及除第一区域和第二区域之外的第三区域，该方法包括：在基底上形成栅极图形、栅绝缘层、有源层图形和刻蚀阻挡层；在刻蚀阻挡层上形成光刻胶层；对光刻胶层进行一次图案化工艺，使得第一区域内的光刻胶被部分刻蚀，第二区域内的光刻胶被完全刻蚀，并且第三区域内的光刻胶被完全保留；通过同一刻蚀工艺蚀掉第一区域内的剩余光刻胶和刻蚀阻挡层，以及第二区域内的刻蚀阻挡层和栅绝缘层。该方法能够通过一次图案化工艺形成开关TFT的过孔和驱动TFT的过孔，并能降低开关TFT的过孔区域的沟道被损坏的程度。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
背景技术
AMOLED(Active Matrix Driving Organic Light Emitting Diode，有源矩阵驱动有机发光二极管)显示面板的像素驱动电路一般包含至少两个TFT(Thin Film Transistor，薄膜晶体管)和一个存储电容，其中一个为开关TFT(Switching TFT)，另一个为驱动TFT(Driving TFT)。如图1所示，为包含像素驱动电路的AMOLED阵列基板在一个像素处的结构示意图，该阵列基板包括基底1、形成在基底1上的栅极图形，该栅极图形由图中的开关TFT的栅极2a和驱动TFT的栅极2b组成，在栅极图形的上方形成有栅绝缘层3，在栅极2a上方的区域内，在栅绝缘层3的上方形成有有源层图形4，在栅极2b上方的区域内，在栅极绝缘层3的上方不具有有源层图形4，在有源层图形4和栅绝缘层3之上形成有刻蚀阻挡层5，在刻蚀阻挡层5的上方形成有源漏电极图形，漏电极图形包括开关TFT的源漏电极6a和驱动TFT的源漏电极6b。开关TFT的源漏电极6a的通过刻蚀阻挡层5上的源极过孔A11和漏极过孔A12与有源层图形4连接，漏极通过刻蚀阻挡层5上的过孔A12与有源层图形4连接，驱动TFT的源漏电极6b通过栅绝缘层3和刻蚀阻挡层5上的过孔B1与栅极2b连接。在源漏电极图形之上还形成有树脂层7，以及形成在树脂层7之上的像素电极图形8，该树脂层7上在对应于源漏电极6a的源极和漏极位置处对应设置有过孔(图1中未用附图标记指出)，在对应于源漏电极6b位置设置有过孔(图1中未用附图标记指出)，像素电极图形8通过过孔A22和过孔B2将源漏电极6a的漏极与源漏电极6b连接，过孔A21用于连接数据线。在扫描线开启时，开关TFT的栅极2a上施加一定电压，电流从开关TFT的源极流向漏极，并通 过像素电极图形8传输到驱动TFT，使驱动TFT导通，电流从源极流向漏极，驱动TFT与存储电容(图中未示出)连接，从而为电容充电，当扫描线关闭时，存储于电容中的电压仍能保持驱动TFT在导通状态，故能在一个画面内维持OLED的固定电流。
现有技术中，制作上述的过孔A11、A12和B1的方式主要有两种，一种是在沉积栅绝缘层3、形成有源层图形4、沉积刻蚀阻挡层5之后，在刻蚀阻挡层5上涂覆光刻胶，并采用一次图案化工艺在过孔A11、A12和B1的上方形成光刻胶去除区域，之后采用干刻工艺进行刻蚀，直至B1区域内的栅绝缘层和刻蚀阻挡层被完全刻蚀。这种方式虽然节省了一道图案化工艺，但是由于对B1区域需要刻蚀的厚度大于A11和A12区域需要刻蚀的厚度，这样在同等刻蚀条件下，会导致A11和A12区域的刻蚀阻挡层5材料被完全时，B1区域内的栅绝缘层3未被完全刻蚀，在对B1区域内的栅绝缘层3继续刻蚀时，A11和A12区域上方的有源层图形4遭到损坏。另一种方式是，首先在形成栅绝缘层3之后，通过一次图案化工艺形成B1区域栅绝缘层3中的过孔，之后在形成刻蚀阻挡层5之后，通过另一次图案化工艺形成A11、A12和B1区域的刻蚀阻挡层5中的过孔，这样能够有效避免有源层图形4被破坏，但是由于多了一次图案化工艺，增加了阵列基板的制作难度。
发明内容
本发明的一个目的在于通过一次图案化工艺形成开关TFT的过孔和驱动TFT的过孔，并降低开关TFT的过孔区域的沟道被损坏的程度。
根据本发明的一个方面，提供了一种阵列基板的制作方法，阵列基板包括与开关晶体管的过孔对应的第一区域、与驱动晶体管的过孔对应的第二区域、以及除第一区域和第二区域之外的第三区域，该方法包括：在基底上形成栅极图形、栅绝缘层、有源层图形和刻蚀阻挡层；在刻蚀阻挡层上形成光刻胶层；对光刻胶层进行一次图案化工艺，使得第一区域内的光刻胶被部分刻蚀，第二 区域内的光刻胶被完全刻蚀，并且第三区域内的光刻胶被完全保留；通过同一刻蚀工艺，蚀掉第一区域内的剩余光刻胶和刻蚀阻挡层，同时刻蚀掉第二区域内的刻蚀阻挡层和栅绝缘层。
根据示例性的实施例，对光刻胶层进行一次图案化工艺的步骤包括：采用同一掩膜板对第一区域内的光刻胶层进行不完全曝光以使第一区域内的光刻胶被部分地去除，对第二区域内的光刻胶进行完全曝光以使该第二区域内的光刻胶被完全去除。
根据示例性的实施例，所述采用同一掩膜板进行曝光的步骤包括：使用狭缝掩膜板对所述光刻胶层进行曝光，所述狭缝掩膜板在所述第一区域具有狭缝，在所述第二区域具有开口。
根据示例性的实施例，采用同一掩膜板进行曝光的步骤包括：采用灰色调掩膜板或者半色调掩膜板对光刻胶层进行曝光，所述灰色调掩膜板或者半色调掩膜板在所述第一区域半透明，在所述第二区域完全透明。
根据示例性的实施例，在刻蚀阻挡层上形成光刻胶层的步骤包括：在所述刻蚀阻挡层上形成光刻胶层，使得第二区域内的光刻胶具有第一厚度，第一区域内的光刻胶具有第二厚度，并且第二厚度大于第一厚度；并且所述第二厚度被设定为当所述第一区域内的光刻胶层被完全刻蚀时，所述第二区域的刻蚀阻挡层和栅绝缘层未被完全刻蚀。
根据示例性的实施例，所述刻蚀步骤包括：在所述第二区域的刻蚀阻挡层和栅绝缘层刻蚀了一定厚度之后，对所述第一区域内的光刻胶进行灰化处理，去除所述第一区域内剩余的光刻胶；继续刻蚀至所述第一区域的刻蚀阻挡层以及所述第二区域的刻蚀阻挡层和栅绝缘层被完全刻蚀。
根据示例性的实施例，对所述第一区域内的光刻胶进行灰化处理的步骤包括：使用氧等离子气体对所述第一区域内剩余的光刻胶进行灰化。
根据示例性的实施例，所述栅绝缘层和所述刻蚀阻挡层采用相同的材料制作；并且对所述第一区域内的光刻胶进行灰化处理的步骤包括：在所述第二区 域内剩余的需要被刻蚀材料的厚度与所述第一区域内的刻蚀阻挡层的原始厚度相同时，对所述第一区域的光刻胶层进行灰化处理，去除所述第一区域内剩余的光刻胶。
根据示例性的实施例，所述栅绝缘层和所述刻蚀阻挡层采用氧化硅制作。
根据示例性的实施例，所述方法还包括：在所述蚀刻工艺之后，在所述刻蚀阻挡层上形成源漏电极图形以及在所述源漏电极图形的上方形成像素电极图形；其中，所述像素电极图形连接所述开关晶体管的漏极和所述驱动晶体管的栅极。
根据本发明的另一方面，还提供一种利用上述任一示例性实施例所述的阵列基板制作方法制作的阵列基板。
本发明提供的阵列基板的制作方法，由于在开关晶体管的过孔区域的上方保留有光刻胶层，增大了开关晶体管的有源层上方需要刻蚀的材料的厚度，从而避免了有源层被刻蚀的时间，降低了有源层被损害的程度。另外，在刻蚀开关晶体管的过孔和驱动晶体管的过孔的过程中，仅使用一次图案化工艺，简化了制作工艺。
附图说明
图1为AMOLED阵列基板在一个像素处的结构示意图；
图2为本发明一实施例提供的阵列基板的制作方法的流程示意图；
图3为经步骤S12之后得到的基板在一个像素处的结构示意图；
图4为经步骤S13之后得到的基板在一个像素处的结构示意图；
图5为经步骤S14之后得到的基板在一个像素处的结构示意图；
图6为经步骤S15之后得到的基板在一个像素处的结构示意图；
图7为经步骤S3之后得到的基板在一个像素处的结构示意图；
图8为经步骤S4之后得到的基板在一个像素处的结构示意图；
图9为经步骤S5之后得到的基板在一个像素处的结构示意图；
图10为经步骤S6之后得到的基板在一个像素处的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他的实施例，都属于本发明保护的范围。
本发明一实施例提供了一种阵列基板的制作方法，其中所述阵列基板包括与开关晶体管的过孔对应的第一区域、与驱动晶体管的过孔对应的第二区域、以及除第一区域和第二区域之外的第三区域，如图2所示，该方法包括以下步骤：
步骤S1，在基底上形成栅极图形、栅绝缘层、有源层图形和刻蚀阻挡层。
步骤S2，在所述刻蚀阻挡层上形成光刻胶层。
步骤S3，对所述光刻胶层进行一次图案化工艺，使得在第一区域内的光刻胶被部分刻蚀，在第二区域内的光刻胶被完全刻蚀，并且在第三区域内的光刻胶被完全保留。
步骤S4，在同一刻蚀工艺中，刻蚀掉第一区域内的剩余光刻胶和刻蚀阻挡层，同时刻蚀刻蚀掉第二区域内的刻蚀阻挡层和栅绝缘层。
本发明实施例中，由于在开关晶体管的过孔的上方保留有光刻胶层，增大了开关晶体管的有源层上方需要刻蚀的材料的厚度，从而避免了有源层被刻蚀的时间，降低了有源层被损害的程度。另外，在刻蚀开关晶体管的过孔和驱动晶体管的过孔的过程中，仅使用一次图案化工艺，简化了制作工艺。
在具体实施时，上述的各个步骤可以通过多种方式实现。比如在一种可能的实施方式中，上述的步骤S1可以具体包括如下步骤(图中未示出)：
步骤S11，提供透明基底，并对透明基底进行清洗。
这里的透明基底具体可以为玻璃基底。
步骤S12，采用溅射工艺或蒸镀工艺在透明基底上沉积50～400nm的栅极材料层，并进行图案化及刻蚀工艺形成栅极图形。
在具体实施时，这里的栅极材料层可以由金属材料形成。进行图案化及刻蚀工艺形成栅极图形可以具体包括：在栅极材料层上覆涂光刻胶，之后采用掩膜板对该光刻胶进行曝光显影，仅保留栅极图形区域的光刻胶，之后使用剩余的光刻胶作为保护层，采用刻蚀液对栅极材料层进行刻蚀，形成栅极图形。
图3为经步骤S12之后得到的基板在一个像素处的结构示意图，包括基底1、形成在基底上的栅极2a和栅极2b。
步骤S13，利用化学气相沉淀的方法制备厚度为100～500nm的SiOx作为栅极绝缘层。
步骤S13的具体实施方式可以参考现有技术，在此不再详细说明。图4为经步骤S13之后得到的基板在一个像素处的结构示意图，与图3不同的是，还包括在栅极2a和栅极2b的上方还包括栅绝缘层3，栅绝缘层3覆盖该像素内的所有区域。
步骤S14，采用溅射工艺在栅绝缘层上沉积有源材料层，并进行图案化及刻蚀工艺，得到有源层图形。
步骤S14的具体方式可以参考上述步骤S12中形成栅极图形的过程，在此不再详细说明。上述的有源材料层可以采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)制作。图5为经步骤S14之后得到的基板在一个像素处的结构示意图，与图4不同的是，还包括在栅绝缘层3之上有源层图形4、有源层图形4位于栅极2a的上方。在栅极2b的上方不存在有源层图形。
步骤S15，在步骤S14得到的基板上利用化学气相沉淀法制备厚度50～500nm的氧化硅作为刻蚀阻挡层。
图6为经步骤S15之后得到的基板在一个像素处的结构示意图，与图5不同的是，在有源层图形4和栅绝缘层3的上方还形成有刻蚀阻挡层5，刻蚀阻 挡层5覆盖该像素内的所有区域。当然在实际应用中，也可以采用氮化硅作为刻蚀阻挡层。
至此，完成了步骤S1。在步骤S1之后的步骤S2中，可以通过涂覆的方式在刻蚀阻挡层之上形成光刻胶层。这里的光刻胶层可以为由感光树脂、增感剂和溶剂三种主要成分组成的对光敏感的混合液体。感光树脂经光照后，在曝光区能很快地发生光固化反应，后续通过特定的溶液可以将固化的感光树脂清洗掉。
在具体实施时，上述的步骤S3也可以通过多种方式实现。其中一种方式可以具体为：采用同一掩膜板对第一区域内的光刻胶进行不完全曝光以使该第一区域内的光刻胶被部分地去除，对第二区域内的光刻胶进行完全曝光以使该第二区域内的光刻胶被完全去除。具体来说，对一个区域完全曝光是在该区域光线完全透过，而对一个区域完全曝光是指在该区域光线部分的透过。
这里的掩膜板可以为狭缝掩膜板，狭缝掩膜板在第一区域具有狭缝，在第二区域具有开口。这里的狭缝是指宽度与所采用的光的波长相当的缝隙，光在通过各个狭缝时发生衍射，在该区域下方由于干涉作用，对该区域下方的光刻胶进行均匀的不完全曝光。这里的开口则是指宽度远大于光的波长的缝隙，光在通过开口时，衍射现象不明显，对该开口下方的光刻胶进行完全曝光。
另外，这里的掩膜板可以为灰色调掩膜板或者半色调掩膜板对光刻胶层进行曝光，所述灰色调掩膜板或者半色调掩膜板在第一区域半透明，在第二区域完全透明。
图7为经步骤S3之后得到的基板在一个像素处的结构示意图，在刻蚀阻挡层5之上涂覆有光刻胶9，光刻胶中在用于形成A11孔的区域a11和用于形成A12孔的区域a12，光刻胶9部分保留，在对应于用于形成B1孔的区域b1，光刻胶9完全去除，在其他区域，光刻胶9完全保留。在图6中，还示出了所采用的狭缝掩膜板10的示意图，该狭缝掩膜板10在用于形成a11区域和a12区域的区域具有多个狭缝，在用于形成b1孔区域的区域具有开口。
在实际应用中，在上述的步骤S4中，在第一区域中的光刻胶材料的厚度适中的情况下，采用同一刻蚀工艺(例如，干刻工艺)将第一区域的光刻胶层和刻蚀阻挡层刻蚀完毕时，同时第二区域的刻蚀阻挡层和栅绝缘层基本也完全被刻蚀，这样就可以避免过刻蚀对有源层图形或者区域的栅极的损坏。
但是在实际应用中，第一区域的光刻胶材料的厚度很难严格控制，为了进一步降低第一区域的有源层图形或者光刻胶去除区域的栅极被损坏的程度。本发明实施例中，可以在步骤S2中，在刻蚀阻挡层上形成光刻胶层，使得第二区域内的光刻胶具有第一厚度，第一区域内的光刻胶具有第二厚度，并且第二厚度大于第一厚度；
此外，所述第二厚度需要被设定成当所述第一区域的光刻胶层被完全刻蚀时，所述第二区域的刻蚀阻挡层和栅绝缘层未被完全刻蚀；
此时步骤S4可以包括：
在所述第二区域的刻蚀阻挡层和栅绝缘层刻蚀了一定厚度之后，对第一区域的光刻胶进行灰化处理，去除第一区域内剩余的光刻胶；继续刻蚀至所述第一区域的刻蚀阻挡层以及所述第二区域的栅绝缘层和刻蚀阻挡层被完全刻蚀。
比如一般在进行曝光显影时，所涂覆的光刻胶的厚度在1500nm。在本发明实施例中，为了使所述第一区域内的光刻胶具有足够的厚度，第一区域的光刻胶的厚度可以为2000nm。
进一步的，如果所述栅绝缘层和所述刻蚀阻挡层采用相同的材料制作，比如均为氧化硅，则在实际应用中，在上述的步骤S4中，在所述第二区域剩余的氧化硅的厚度(即栅绝缘层与刻蚀阻挡层(如何还有剩余的话)的厚度之和)与所述第一区域内的刻蚀阻挡层的原始厚度相同时，对所述第一区域的光刻胶进行灰化处理，去除该第一区域中剩余的光刻胶。这样，在进行灰化处理之后，采用相同的干刻工艺可以使得第一区域的刻蚀阻挡层材料被完全刻蚀时，第二区域的栅绝缘层材料也被完全刻蚀。避免过刻蚀损害有源层图形或者驱动TFT的过孔区域的栅极。
更进一步的，如果栅绝缘层的材料与刻蚀阻挡层的厚度相同且材料相同(例如，均为氧化硅)，则可以在第二区域的刻蚀阻挡层被完全刻蚀时，对第一区域剩余的光刻胶进行灰化处理。
这里的灰化处理可以具体为：使用氧等离子气体对所述第一区域内剩余的光刻胶层进行灰化。当然在实际应用中，也可以使用其他的气体比如氦气对第一区域剩余的光刻胶进行灰化。
在步骤S4之后，完成了对开关TFT的过孔和驱动TFT的过孔的刻蚀过程，图8为经步骤S4之后得到的基板在一个像素处的结构示意图，与图7相比，刻蚀阻挡层5在栅极2a的上方形成有源极过孔A11和漏极过孔A12，在栅极2b的上方形成有过孔B1。
在具体实施时，在上述的步骤S4之后，上述的方法还可以包括图中未示出的：
步骤S5，在步骤S4得到的基板上沉积源漏金属层，并通过图案化工艺形成源漏电极图形。该源漏电极层包括开关TFT的源漏电极和驱动TFT的源漏电极。
图9为经步骤S5之后得到的基板在一个像素处的结构示意图，与图8不同的是，在刻蚀阻挡层5的上方还形成有源漏电极图形。源漏电极图形包括开关TFT的源漏电极6a和驱动TFT的源漏电极6b。开关TFT的源漏电极6a分别通过刻蚀阻挡层5上的源极过孔A11和漏极A12与有源层图形4连接，驱动TFT的源漏电极6b通过刻蚀阻挡层5以及栅绝缘层3上的过孔B1与栅极2b连接。
在具体实施时，在上述的步骤S5之后，上述的方法还可以包括图中未示出的：步骤S6，在源漏电极图形之上形成树脂层，之后通过图形化工艺在树脂层中开关TFT源漏两个电极的上方形成两个过孔，在驱动TFT的源漏电极的上方形成一个过孔。图10为经步骤S6之后得到的基板在一个像素处的结构示意图，与图9不同的是，在源漏电极图形的上方还形成有树脂层7，树脂层7 中在对应于源极过孔A11的位置具有过孔A21，在对应于漏极过孔A12的位置处具有过孔A22，在源漏电极6b的上方形成有过孔B2。
在具体实施时，在上述的步骤S4之后，上述的方法还可以包括图中未示出的：步骤S7，在树脂层之上形成像素电极图形，该像素电极图形连接开关晶体管的漏极和驱动晶体管的栅极。在具体实施时，可以在步骤S5得到的基板上沉积一层像素电极材料，由于在步骤S6中，所形成的像素电极材料会将开关晶体管的漏极和驱动晶体管的栅极相连，进一步的通过图形化工艺形成对应的像素电极图形。在形成像素电极图形之后得到的基板在一个像素处的示意图可以如图1所示。
在实际应用中，当上述的方法还用于制作AMOLED+COA(Color On Array，彩膜制作在基板上)时，上述的方法还应包括制作彩色滤光片的过程。上述的方法可以用于制作WOLED(White OLED，白光OLED)，也可以用于制作PLED等阵列基板。
本发明还提供了一种阵列基板，该阵列基板为利用上述任一项所述的方法所制作的阵列基板。
以上所述，仅为本发明的具体实施方式，但是，本发明的保护范围不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替代，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种阵列基板的制作方法，所述阵列基板包括与开关晶体管的过孔对应的第一区域、与驱动晶体管的过孔对应的第二区域、以及除第一区域和第二区域之外的第三区域，所述制作方法的特征在于包括以下步骤：
    在基底上形成栅极图形、栅绝缘层、有源层图形和刻蚀阻挡层；
    在所述刻蚀阻挡层上形成光刻胶层；
    对所述光刻胶层进行一次图案化工艺，使得第一区域内的光刻胶被部分刻蚀，第二区域内的光刻胶被完全刻蚀，并且第三区域内的光刻胶被完全保留；
    通过同一刻蚀工艺，蚀掉所述第一区域内的剩余光刻胶和刻蚀阻挡层，同时刻蚀掉所述第二区域内的刻蚀阻挡层和栅绝缘层。
  2. 如权利要求1所述的方法，其特征在于，
    对所述光刻胶层进行一次图案化工艺的步骤包括：
    采用同一掩膜板对第一区域内的光刻胶层进行不完全曝光以使第一区域内的光刻胶被部分地去除，对第二区域内的光刻胶进行完全曝光以使该第二区域内的光刻胶被完全去除。
  3. 如权利要求2所述的方法，其特征在于，
    所述采用同一掩膜板进行曝光的步骤包括：
    使用狭缝掩膜板对所述光刻胶层进行曝光，所述狭缝掩膜板在所述第一区域具有狭缝，在所述第二区域具有开口。
  4. 如权利要求2所述的方法，其特征在于，
    采用同一掩膜板进行曝光的步骤包括：
    采用灰色调掩膜板或者半色调掩膜板对光刻胶层进行曝光，所述灰色调掩膜板或者半色调掩膜板在所述第一区域半透明，在所述第二区域完全透明。
  5. 如权利要求1所述的方法，其特征在于，在刻蚀阻挡层上形成光刻胶层的步骤包括：
    在所述刻蚀阻挡层上形成光刻胶层，使得第二区域内的光刻胶具有第一厚度，第一区域内的光刻胶具有第二厚度，并且第二厚度大于第一厚度；并且
    所述第二厚度被设定为当所述第一区域内的光刻胶层被完全刻蚀时，所述第二区域的刻蚀阻挡层和栅绝缘层未被完全刻蚀。
  6. 如权利要求5所述的方法，其特征在于，
    所述刻蚀步骤包括：
    在所述第二区域的刻蚀阻挡层和栅绝缘层刻蚀了一定厚度之后，对所述第一区域内的光刻胶进行灰化处理，去除所述第一区域内剩余的光刻胶；
    继续刻蚀至所述第一区域的刻蚀阻挡层以及所述第二区域的刻蚀阻挡层和栅绝缘层被完全刻蚀。
  7. 如权利要求6所述的方法，其特征在于，对所述第一区域内的光刻胶进行灰化处理的步骤包括：
    使用氧等离子气体对所述第一区域内剩余的光刻胶进行灰化。
  8. 如权利要求6或7所述的方法，其特征在于，所述栅绝缘层和所述刻蚀阻挡层采用相同的材料制作；并且
    对所述第一区域内的光刻胶进行灰化处理的步骤包括：
    在所述第二区域内剩余的需要被刻蚀材料的厚度与所述第一区域内的刻蚀阻挡层的原始厚度相同时，对所述第一区域的光刻胶层进行灰化处理，去除所述第一区域内剩余的光刻胶。
  9. 如权利要求8所述的方法，其特征在于，所述栅绝缘层和所述刻蚀阻挡层采用氧化硅制作。
  10. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述蚀刻工艺之后，在所述刻蚀阻挡层上形成源漏电极图形以及在所述源漏电极图形的上方形成像素电极图形；
    其中，所述像素电极图形连接所述开关晶体管的漏极和所述驱动晶体管的栅极。
  11. 一种利用权利要求1-10任一项所述的阵列基板制作方法制作的阵列基板。
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