WO2018129932A1 - Circuit d'unité registre à décalage, son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage - Google Patents

Circuit d'unité registre à décalage, son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage Download PDF

Info

Publication number
WO2018129932A1
WO2018129932A1 PCT/CN2017/099871 CN2017099871W WO2018129932A1 WO 2018129932 A1 WO2018129932 A1 WO 2018129932A1 CN 2017099871 W CN2017099871 W CN 2017099871W WO 2018129932 A1 WO2018129932 A1 WO 2018129932A1
Authority
WO
WIPO (PCT)
Prior art keywords
potential
node
terminal
transistor
circuit
Prior art date
Application number
PCT/CN2017/099871
Other languages
English (en)
Chinese (zh)
Inventor
樊君
李伟
李付强
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/756,975 priority Critical patent/US10706767B2/en
Publication of WO2018129932A1 publication Critical patent/WO2018129932A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to generation of a gate drive signal, and more particularly to a shift register unit circuit, a driving method for the shift register unit circuit, a gate driving circuit, and a display device.
  • a shift register including a plurality of cascaded shift register unit circuits can operate as a gate drive circuit of the display panel.
  • high temperature conditions eg, 70-85 ° C
  • the leakage current of certain transistors in the shift register cell circuit may increase significantly, for example, relative to an increase of 2 to 3 orders of magnitude at room temperature. This can result in a large change in the potential of some internal nodes, and thus a deterioration in the output gate drive signal.
  • the display panel has poor high temperature reliability.
  • a shift register unit circuit comprising: an input circuit configured to supply an effective potential from a first scan level terminal to a first node in response to an input pulse from an input being active, And supplying an inactive potential from the second scan level terminal to the first node in response to the reset pulse from the reset terminal being active; the output circuit being configured to be from the first clock in response to the second node being at the active potential a first clock signal of the terminal is supplied to the output terminal, and a potential of the second node is changed from the effective potential to further away from the potential of the output terminal to jump to the effective potential An invalid potential; and a potential control circuit configured to limit a change in a potential of the first node caused by the transition of the potential of the output terminal from an inactive potential to an active potential.
  • the potential control circuit is configured to cause the first node to be non-conducting with the second node in response to a change in potential of the second node exceeding a threshold.
  • the potential control circuit includes a first control transistor having a gate coupled to the potential control terminal, a first electrode coupled to the first node, and a connection To the second electrode of the second node.
  • the first control transistor is configured to be turned on in response to a control signal from the potential control terminal being active, and turned off in response to the change in potential of the second node exceeding the threshold.
  • the first node is directly connected to the second node
  • the potential control circuit includes a second capacitor coupled to the second node and a first one for supplying the reactive potential Between the reference levels.
  • the potential control circuit is further configured to supply an effective potential from the second reference level terminal to the second scan level terminal in response to the output being at the active potential.
  • the potential control circuit further includes a second control transistor having a gate connected to the output, a first electrode connected to the second reference level terminal, and a second to Scan the second electrode at the level end.
  • the input circuit includes: a first transistor having a gate connected to the input, a first electrode connected to the first node, and a first connected to the first scan level end a second electrode; and a second transistor having a gate connected to the reset terminal, a first electrode connected to the second scan level terminal, and a second electrode connected to the first node.
  • the output circuit includes: a third transistor having a gate connected to the second node, a first electrode connected to the output, and a second electrode connected to the first clock terminal And a first capacitor connected between the second node and the output.
  • the output circuit is further configured to supply the inactive potential from the first reference level terminal to the output terminal in response to the third node being at the active potential.
  • the output circuit further includes a fourth transistor having a gate connected to the third node, a first electrode connected to the first reference level terminal, and a connection to the output terminal Second electrode.
  • the shift register unit circuit further includes a node control circuit configured to set the third node at the inactive potential in response to the second node being at the active potential, And setting the third node at the effective potential in response to the second node being at the inactive potential.
  • the node control circuit includes: a sixth transistor having a connection a gate connected to the second node, a first electrode connected to the first reference level terminal, and a second electrode connected to the third node; a seventh transistor having a connection to supply for a gate of a second clock end of the second clock signal of the opposite phase of the first clock signal, a first electrode connected to the third node, and a second electrode connected to the second clock terminal; and a third capacitor Connected between the third node and the first reference level terminal.
  • the node control circuit is further configured to set the second node at the inactive potential in response to the third node being at the active potential.
  • the node control circuit further includes a fifth transistor having a gate connected to the third node, a first electrode connected to the second node, and connected to the first reference The second electrode at the level end.
  • a method of driving a shift register unit circuit as described above includes supplying an effective potential from the first scan level terminal to the first node in response to an input pulse from the input being active; responsive to the second node being at the active potential a first clock signal from the first clock terminal is supplied to the output terminal; causing a potential of the second node to be from the effective potential in response to the output terminal transitioning from the inactive potential to being at the active potential Changing to further away from the inactive potential; limiting a change in potential of the first node caused by the transition of the potential of the output from an inactive potential to an active potential; and in response to a reset pulse from the reset terminal
  • the effective potential from the second scan level terminal is supplied to the first node.
  • a gate driving circuit including a plurality of cascaded shift register unit circuits as described above is provided.
  • a display device comprising the gate drive circuit as described above.
  • 1 is a circuit diagram of a portion of a typical shift register unit circuit
  • FIG. 2 is a block diagram of a shift register unit circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of an example circuit of the shift register unit circuit shown in FIG. 2;
  • FIG. 4 is an example timing diagram for an example circuit as shown in FIG. 3;
  • Figure 5 is a circuit diagram of another example circuit of the shift register unit circuit shown in Figure 2;
  • FIG. 6 is an example timing diagram for an example circuit as shown in FIG. 5;
  • FIGS. 7A and 7B are block diagrams of gate drive circuits in different scan modes, in accordance with an embodiment of the present disclosure.
  • FIG. 8 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of a portion of a typical shift register unit circuit. How the performance of the shift register unit circuit is affected by high temperature conditions will be described below with reference to FIG.
  • the circuit portion includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C1.
  • a high level voltage from the first scan level terminal CN is supplied to the pull-up node PU through the first transistor T1, and the third transistor T3 is turned on.
  • the turned-on third transistor T3 transmits a clock signal from the clock terminal CLK to the output terminal OUT such that the potential of the output terminal OUT changes as the clock signal changes.
  • the potential of the output terminal OUT transitions from a low level to a high level, the potential at the pull-up node PU is further raised due to the bootstrap effect of the capacitor C1.
  • Vgs the gate-source voltage
  • Vds the drain-source voltage
  • the shift register unit circuit 200 includes an input circuit 210, an output circuit 220, a potential control circuit 230, and a node control circuit 240.
  • the input circuit 210 is configured to supply an effective potential from the first scan level terminal CN to the first node N1 in response to the input pulse from the input terminal IN being active.
  • the input circuit 210 is also configured to supply an inactive potential from the second scan level terminal CNB to the first node N1 in response to the reset pulse from the reset terminal RST being active.
  • the output circuit 220 is configured to supply a first clock signal from the first clock terminal CLK to the output terminal OUT in response to the second node N2 being at an active potential.
  • the output circuit 220 is also configured to cause the potential of the second node N2 to be changed from the effective potential to further away from the inactive potential in response to the potential of the output terminal OUT transitioning from the inactive potential to the active potential.
  • the potential control circuit 230 is configured to limit a change in the potential of the first node N1 caused by the jump of the potential of the output terminal OUT from the inactive potential to the effective potential. As will be discussed later, this can suppress leakage current flowing from the first node N1 in the circuit, and thus improve the performance of the shift register unit circuit 200 under high temperature conditions.
  • the node control circuit 240 as indicated by the dashed box is less closely related to the inventive concept of the present disclosure and will be described later.
  • the term "effective potential” as used herein refers to the potential at which the circuit component (eg, transistor) involved is enabled.
  • the term “invalid potential” refers to the potential at which the circuit components involved are disabled.
  • the effective potential is high and the inactive potential is low.
  • the effective potential is low and the inactive potential is high.
  • FIG. 3 is a circuit diagram of an example circuit 200A of shift register unit circuit 200 as shown in FIG. 2. An example configuration of the shift register unit circuit 200 will be described below with reference to FIG.
  • the input circuit 210 includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 has a gate connected to the input terminal IN, a first electrode connected to the first node N1, and a second electrode connected to the first scan level terminal CN.
  • the second transistor T2 has a gate connected to the reset terminal RST, a first electrode connected to the second scan level terminal CNB, and a second electrode connected to the first node N1.
  • the output circuit 220 includes a third transistor T3 and a first capacitor C1.
  • the third transistor T3 has a gate connected to the second node N2, a first electrode connected to the output terminal OUT, and a second electrode connected to the first clock terminal CLK.
  • the first capacitor C1 is connected between the second node N2 and the output terminal OUT.
  • the output circuit 220 is further configured to supply an inactive potential from the first reference level terminal VGL to the output terminal OUT in response to the third node N3 being at an active potential.
  • the output circuit 220 further includes a fourth transistor T4 having a gate connected to the third node N3, a first electrode connected to the first reference level terminal VGL, and being connected to the output terminal OUT.
  • the second electrode is a fourth transistor T4 having a gate connected to the third node N3, a first electrode connected to the first reference level terminal VGL, and being connected to the output terminal OUT.
  • the potential control circuit 230 is configured to cause the first node N1 and the second node N2 to bring out of conduction in response to the change in the potential of the second node N2 exceeding a threshold.
  • the potential control circuit 230 includes a first control transistor TK1 having a gate connected to the potential control terminal PCN, a first electrode connected to the first node N1, and a second electrode connected to the second node N2.
  • the first control transistor TK1 is configured to be turned on in response to the control signal from the potential control terminal PCN being active.
  • the first control transistor TK1 is also configured to be turned off in response to the change in the potential of the second node N2 exceeding the threshold.
  • the node control circuit 240 is configured to set the third node N3 to be in an inactive potential in response to the second node N2 being at an active potential, and to be inactive in response to the second node N2
  • the third node N3 is set to be at an effective potential.
  • the node control circuit 240 includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3.
  • the sixth transistor T6 has a gate connected to the second node N2, a first electrode connected to the first reference level terminal VGL, and a second electrode connected to the third node N3.
  • the seventh transistor T7 has a gate connected to a second clock terminal CLKB for supplying a second clock signal having an opposite phase to the first clock signal, a first electrode connected to the third node N3, and a second clock connected thereto The second electrode of terminal CLKB.
  • the third capacitor C3 is connected between the third node N3 and the first reference level terminal VGL.
  • node control circuit 240 is further configured to set second node N2 to an inactive potential in response to third node N3 being at an active potential.
  • the node control circuit 240 further includes a fifth transistor T5 having a gate connected to the third node N3, a first electrode connected to the second node N2, and being connected to the first reference The second electrode of the flat end VGL.
  • FIG. 4 is an example timing diagram for an example circuit 200A as shown in FIG. The operation of the example circuit 200A of FIG. 3 is described below with reference to FIG. Hereinafter, a high level is indicated by 1 and a low level is indicated by 0. It is also assumed that the first scan level terminal CN supplies a high level voltage, and the second scan level terminal CNB and the first reference level terminal VGL supply a low level voltage.
  • the sixth transistor T6 and the seventh transistor T7 are designed such that the equivalent resistance of the sixth transistor T6 is much smaller than the equivalent resistance of the seventh transistor T7.
  • the third node N3 is set to be at an inactive potential. Since the first node N1 is at the effective potential, the third transistor T3 is turned on, and the invalid clock signal from the first clock terminal CLK is transmitted to the output terminal OUT.
  • Vds is reduced by approximately one time, greatly reducing the leakage current flowing through the second transistor T2. Therefore, the potential of the second node N2 is less affected by the leakage current, so that the output terminal OUT can output a normal pulse signal.
  • the third node N3 is set to the effective potential, and the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, so that the output terminal OUT outputs an inactive level signal.
  • the first capacitor C1 keeps the first node PU at an inactive potential
  • the third capacitor C3 keeps the third node N3 at an effective potential. Since the third node N3 is at an effective potential, the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fifth transistor T5 transmits a low level voltage from the first reference level terminal VGL to the first node N1, ensuring that the first node N1 is at an inactive potential.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, ensuring that the output terminal OUT outputs an inactive level signal.
  • FIG. 5 is a circuit diagram of another example circuit 200B of shift register unit circuit 200 as shown in FIG. 2.
  • Input circuit 210, output circuit 220, and node control circuit 240 The configuration is the same as those described above with respect to FIG. 3 and will not be repeated here.
  • the first node N1 is directly connected to the second node N2 without the first control transistor TK1 being connected therebetween.
  • the potential control circuit 240 includes a second capacitor C2 connected between the second node N2 and the first reference level terminal VGL for supplying an ineffective potential.
  • the second capacitor C2 is operable to maintain the potential of the first node N1 stable when the potential of the second node N2 jumps due to the bootstrap effect of the first capacitor C1. This is because the second capacitor C2 is connected in series with the first capacitor C1, and thus the voltage jump across the first capacitor C1 can be shared.
  • the variation of the potential of the first node N1 is limited such that the drain-source voltage Vds of the second transistor T2 is reduced compared to the second capacitor C2 otherwise, thereby reducing the leakage flowing through the second transistor T2.
  • the current and in turn, contributes to the stabilization of the potential of the first node N1. This can improve the reliability of the example circuit 200B under high temperature conditions.
  • the potential control circuit 240 can also be configured to supply an effective potential from the second reference level terminal VGH to the second scan level terminal CNB in response to the output terminal OUT being at an active potential.
  • the potential control circuit 240 further includes a second control transistor TK2 having a gate connected to the output terminal OUT, a first electrode connected to the second reference level terminal VGH, and connected to the second Scanning the second electrode CNB at the level end.
  • FIG. 6 is an example timing diagram for an example circuit as shown in FIG. 5.
  • the operation of the example circuit 200B of FIG. 5 is described below with reference to FIG.
  • a high level is indicated by 1
  • a low level is indicated by 0.
  • the first scan level terminal CN and the second reference level terminal VGH supply a high level voltage
  • the second scan level terminal CNB and the first reference level terminal VGL supply a low level voltage.
  • the potential of the second node N2 (equivalently, the first node N1) is further pulled high. Due to the presence of the second capacitor C2, the rise in the potential of the first node N1 is limited, thereby reducing the leakage current flowing through the second transistor T2.
  • the first capacitor C1 keeps the first node PU at an inactive potential
  • the third capacitor C3 keeps the third node N3 at an effective potential. Since the third node N3 is at an effective potential, the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fifth transistor T5 transmits a low level voltage from the first reference level terminal VGL to the first node N1, ensuring that the first node N1 is at an inactive potential.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, ensuring that the output terminal OUT outputs an inactive level signal.
  • the gate driving circuits 700A, 700B each include n The cascaded shift register unit circuits, each of which may be the shift register unit circuit 200 as described above.
  • the n shift register unit circuits are respectively connected to n gate lines G[1], G[2], G[3], ..., G[n-1], and G[n] to supply gates thereto.
  • Pole drive signal. n may be an integer greater than or equal to two.
  • each of the shift register unit circuits is connected to the output terminal OUT of the adjacent previous shift register unit circuit, and except for the nth shift register
  • the reset terminal RST of each of the shift register unit circuits is connected to the output terminal OUT of the adjacent next shift register unit circuit.
  • the input terminal IN of the first shift register unit circuit receives the start signal STV as the input pulse.
  • the reset terminal RST of the nth shift register unit circuit receives the start signal STV as the input pulse.
  • the input terminal IN and the reset terminal RST of the shift register unit circuit are used interchangeably, and the first scan level terminal CN and the second scan level terminal CNB are used interchangeably.
  • the first scan level terminal CN supplies the active level voltage
  • the second scan level terminal CNB supplies the inactive level voltage
  • the input terminal IN and the reset terminal RST are normally used.
  • the reverse scan mode the first scan level terminal CN supplies an inactive level voltage
  • the second scan level terminal CNB supplies an active level voltage.
  • the input terminal IN serves as a "reset terminal”
  • the reset terminal RST serves as an "input terminal".
  • FIG. 8 is a block diagram of a display device 800 in accordance with an embodiment of the present disclosure.
  • the display device 800 includes a display panel 810, a timing controller 820, a gate driving circuit 830, and a data driving circuit 840.
  • Gate drive circuit 830 can be gate drive circuit 700A or 700B as described above with respect to Figures 7A and 7B.
  • the display panel 810 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 810 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 810 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • the display panel 810 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 820 controls the operations of the display panel 810, the gate drive circuit 830, and the data drive circuit 840.
  • the timing controller 820 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 720 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the gate drive circuit 830 receives the first control signal CONT1 from the timing controller 820.
  • the gate driving circuit 830 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driving circuit 830 can sequentially apply a plurality of gate signals to the gate lines GL.
  • the data driving circuit 840 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 820.
  • the data driving circuit 840 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driving circuit 840 can apply a plurality of data voltages to the data lines DL.
  • gate drive circuit 830 and/or data drive circuit 840 may be disposed (eg, directly mounted) on display panel 810, or may be by, for example, a Tape Carrier Package (TCP). Connected to display panel 810. In some embodiments, gate drive circuit 830 and/or data drive circuit 840 can be integrated in display panel 810.
  • TCP Tape Carrier Package
  • Examples of display device 800 include, but are not limited to, cell phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators.
  • each transistor is illustrated and described as an n-type transistor, a p-type transistor is possible.
  • the gate-on voltage has a low level
  • the gate-off voltage has a high level.
  • each transistor can be, for example, a thin film transistor that is typically fabricated such that their first and second electrodes are used interchangeably. Other embodiments are also contemplated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

L'invention concerne un circuit d'unité registre à décalage (200, 200A, 200B) comprenant : un circuit d'entrée (210) configuré pour fournir un potentiel valide à un premier nœud (N1) en réponse à une impulsion d'entrée valide d'une extrémité d'entrée (ENTRÉE), et pour fournir un potentiel invalide au premier nœud (N1) en réponse à une impulsion de réinitialisation valide d'une extrémité de réinitialisation (RST) ; un circuit de sortie (220) configuré pour fournir un premier signal d'horloge à une extrémité de sortie (SORTIE) en réponse au cas où un second nœud (N2) a un potentiel valide, et pour changer le potentiel du second nœud (N2) ayant un potentiel valide afin de l'éloigner davantage du potentiel invalide en réponse au cas où le potentiel de l'extrémité de sortie (SORTIE) saute du potentiel invalide au potentiel valide ; et un circuit de commande de potentiel (230) configuré pour limiter le changement du potentiel du premier nœud (N1) provoqué par le saut du potentiel de l'extrémité de sortie (SORTIE) du potentiel invalide au potentiel valide.
PCT/CN2017/099871 2017-01-16 2017-08-31 Circuit d'unité registre à décalage, son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage WO2018129932A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/756,975 US10706767B2 (en) 2017-01-16 2017-08-31 Shift register unit circuit, driving method thereof, gate drive circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710028509.0A CN106601176A (zh) 2017-01-16 2017-01-16 移位寄存器单元电路、驱动方法、移位寄存器和显示装置
CN201710028509.0 2017-01-16

Publications (1)

Publication Number Publication Date
WO2018129932A1 true WO2018129932A1 (fr) 2018-07-19

Family

ID=58585888

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/099871 WO2018129932A1 (fr) 2017-01-16 2017-08-31 Circuit d'unité registre à décalage, son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage

Country Status (3)

Country Link
US (1) US10706767B2 (fr)
CN (1) CN106601176A (fr)
WO (1) WO2018129932A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10706767B2 (en) 2017-01-16 2020-07-07 Boe Technology Group Co., Ltd. Shift register unit circuit, driving method thereof, gate drive circuit and display device
CN112802422A (zh) * 2021-01-29 2021-05-14 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452425B (zh) 2017-08-16 2021-02-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
TWI638348B (zh) * 2017-08-25 2018-10-11 友達光電股份有限公司 移位暫存器及其觸控顯示裝置
CN107731170B (zh) * 2017-10-31 2020-03-17 京东方科技集团股份有限公司 补偿模块、栅极驱动单元、电路及其驱动方法和显示装置
CN108172163B (zh) * 2018-01-02 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路及其显示面板
CN108257567A (zh) * 2018-01-31 2018-07-06 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、触控显示装置
CN108564910A (zh) * 2018-03-12 2018-09-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108447438B (zh) * 2018-04-10 2020-12-08 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存器及其控制方法
CN108538238A (zh) * 2018-05-24 2018-09-14 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN108717844B (zh) * 2018-06-29 2020-08-04 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN109147638A (zh) * 2018-07-16 2019-01-04 厦门天马微电子有限公司 驱动电路、显示面板及显示装置
CN108711401B (zh) * 2018-08-10 2021-08-03 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109686292B (zh) 2019-01-25 2022-05-27 鄂尔多斯市源盛光电有限责任公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
JP7351855B2 (ja) 2019-03-22 2023-09-27 京東方科技集團股▲ふん▼有限公司 シフトレジスタユニット、駆動回路、表示装置及び駆動方法
CN110136669B (zh) * 2019-05-17 2022-01-11 武汉京东方光电科技有限公司 移位寄存器单元及其驱动方法和栅极驱动电路
CN112133254B (zh) * 2019-06-25 2021-12-17 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置和控制方法
WO2021226870A1 (fr) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 Substrat d'affichage, procédé de fabrication et appareil d'affichage
CN111462675B (zh) * 2020-05-13 2023-06-27 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
US11848064B2 (en) * 2020-12-26 2023-12-19 Hefei Boe Joint Technology Co., Ltd. Shift register and method for driving the same, gate driving circuit, and display device
CN114067719A (zh) * 2021-11-30 2022-02-18 上海中航光电子有限公司 一种显示面板及其驱动方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100177023A1 (en) * 2009-01-12 2010-07-15 Samsung Mobile Display Co., Ltd. Shift register and organic light emitting display device using the same
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN103761992A (zh) * 2013-12-20 2014-04-30 友达光电股份有限公司 移位寄存器
CN104021769A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示屏
CN104425033A (zh) * 2013-08-20 2015-03-18 友达光电股份有限公司 移位寄存器及包含其的移位寄存器组
CN104700805A (zh) * 2015-03-26 2015-06-10 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN106297697A (zh) * 2016-08-29 2017-01-04 京东方科技集团股份有限公司 移位寄存器及其操作方法
CN106601176A (zh) * 2017-01-16 2017-04-26 京东方科技集团股份有限公司 移位寄存器单元电路、驱动方法、移位寄存器和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101192760B1 (ko) * 2005-06-28 2012-10-18 엘지디스플레이 주식회사 쉬프트 레지스터 및 이의 구동방법
CN102800289B (zh) * 2012-08-10 2015-02-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN103050106B (zh) * 2012-12-26 2015-02-11 京东方科技集团股份有限公司 栅极驱动电路、显示模组和显示器
CN103474038B (zh) * 2013-08-09 2016-11-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器与显示装置
US9437324B2 (en) 2013-08-09 2016-09-06 Boe Technology Group Co., Ltd. Shift register unit, driving method thereof, shift register and display device
CN203760057U (zh) * 2014-03-27 2014-08-06 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103996367B (zh) * 2014-04-18 2017-01-25 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路和显示装置
CN203882580U (zh) * 2014-06-16 2014-10-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN104282285B (zh) * 2014-10-29 2016-06-22 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN105185290B (zh) * 2015-09-06 2017-10-10 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100177023A1 (en) * 2009-01-12 2010-07-15 Samsung Mobile Display Co., Ltd. Shift register and organic light emitting display device using the same
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN104425033A (zh) * 2013-08-20 2015-03-18 友达光电股份有限公司 移位寄存器及包含其的移位寄存器组
CN103761992A (zh) * 2013-12-20 2014-04-30 友达光电股份有限公司 移位寄存器
CN104021769A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示屏
CN104700805A (zh) * 2015-03-26 2015-06-10 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN106297697A (zh) * 2016-08-29 2017-01-04 京东方科技集团股份有限公司 移位寄存器及其操作方法
CN106601176A (zh) * 2017-01-16 2017-04-26 京东方科技集团股份有限公司 移位寄存器单元电路、驱动方法、移位寄存器和显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10706767B2 (en) 2017-01-16 2020-07-07 Boe Technology Group Co., Ltd. Shift register unit circuit, driving method thereof, gate drive circuit and display device
CN112802422A (zh) * 2021-01-29 2021-05-14 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板
CN112802422B (zh) * 2021-01-29 2022-06-10 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板
US11893922B2 (en) 2021-01-29 2024-02-06 Yungu (Gu'an) Technology Co., Ltd. Shift register, gate drive circuit and display panel

Also Published As

Publication number Publication date
CN106601176A (zh) 2017-04-26
US20190057637A1 (en) 2019-02-21
US10706767B2 (en) 2020-07-07

Similar Documents

Publication Publication Date Title
WO2018129932A1 (fr) Circuit d'unité registre à décalage, son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage
US8964932B2 (en) Shift register, gate driving circuit and display
CN107464526B (zh) 一种像素补偿电路、其驱动方法及显示装置
US11094245B2 (en) Shift register, driving method thereof, gate driving circuit and display device
KR102015396B1 (ko) 쉬프트 레지스터와 이의 구동방법
US20190006018A1 (en) Shift register unit circuit, method of driving the same, gate drive circuit, and display apparatus
WO2020191511A1 (fr) Unité d'enregistrement de décalage, circuit de commande, appareil d'affichage et procédé de commande
CN107369413B (zh) 一种像素补偿电路、其驱动方法、显示面板及显示装置
US11257418B2 (en) Driving unit and driving method thereof, gate driving circuit and display substrate
WO2018129928A1 (fr) Circuit de registre à décalage et son procédé d'attaque, circuit d'attaque de grille, et dispositif d'affichage
KR20130107528A (ko) 게이트 구동 회로 및 이를 이용한 표시 장치
WO2018126687A1 (fr) Circuit de registre à décalage, procédé de pilotage de celui-ci, circuit de pilotage de grille et dispositif d'affichage
WO2018126741A1 (fr) Circuit de registre à décalage, son procédé d'attaque, circuit d'attaque d'électrode grille, panneau d'affichage et dispositif d'affichage
WO2019015267A1 (fr) Unité de registre à décalage et son procédé d'attaque et circuit d'attaque de grille
US10192474B2 (en) Controllable voltage source, shift register and unit thereof, and display
US11308859B2 (en) Shift register circuit and method of driving the same, gate driver circuit, array substrate and display device
CN110992871A (zh) 移位寄存器和显示面板
US11373576B2 (en) Shift register and method of driving the same, gate driving circuit
CN114882831A (zh) 一种显示面板的显示控制方法、显示模组及显示装置
CN103489393A (zh) 显示器
US20230298530A1 (en) Gate Driver and Electroluminescent Display Apparatus Including the Same
TW201340065A (zh) 閘極驅動器
JP6539637B2 (ja) 有機発光ディスプレイ装置のエミッション信号制御回路及びエミッション信号制御方法、並びに有機発光ディスプレイ装置
US20230162685A1 (en) Shift Register Unit, Method for Driving Shift Register Unit, Gate Driving Circuit, and Display Device
JP2021504757A (ja) 液晶表示パネル及びそのｅｏａモジュール

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17891777

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17891777

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/02/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17891777

Country of ref document: EP

Kind code of ref document: A1