WO2018126688A1 - 阵列基板的制作方法、阵列基板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板及显示装置 Download PDF

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Publication number
WO2018126688A1
WO2018126688A1 PCT/CN2017/096837 CN2017096837W WO2018126688A1 WO 2018126688 A1 WO2018126688 A1 WO 2018126688A1 CN 2017096837 W CN2017096837 W CN 2017096837W WO 2018126688 A1 WO2018126688 A1 WO 2018126688A1
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Prior art keywords
layer
transparent electrode
forming
pattern
photoresist
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PCT/CN2017/096837
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English (en)
French (fr)
Inventor
卢彦春
周纪登
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/764,028 priority Critical patent/US10429698B2/en
Publication of WO2018126688A1 publication Critical patent/WO2018126688A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
    • G02F1/133723—Polyimide, polyamide-imide
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/038—Macromolecular compounds which are rendered insoluble or differentially wettable
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device.
  • the polyimide resin (Polyimide, PI for short) film thickening for preparing the oriented film has a significant improvement effect on the friction anchoring ability, and the frictional ability is enhanced to significantly improve the light leakage afterimage of the large-sized product.
  • the thickening of the PI film can also cause problems such as panel stains, mainly due to the large difference in the via hole, and the PI diffusion is easily affected and adsorbed into the via hole, resulting in obvious color cloud (mura), serious Affect the quality of the picture.
  • the present invention aims to solve one of the technical problems existing in the prior art, and provides a method for fabricating an array substrate, an array substrate, and a display device.
  • a basic method for fabricating an array comprising:
  • the substrate comprising a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulating layer covering the data electrode pattern layer, the data electrode pattern layer including at least one data electrode;
  • the transparent electrode layer including a transparent electrode and a connection portion connected to the transparent electrode, the connection portion being located in the via hole to electrically connect the transparent electrode to the corresponding data electrode
  • a filler is disposed above the connecting portion for filling the via hole covered by the connecting portion.
  • the step of forming a transparent electrode layer comprises:
  • a photoresist layer is coated on the transparent electrode material layer.
  • the photoresist layer is formed of a positive photoresist material
  • the step of forming a transparent electrode layer further includes:
  • Exposing the photoresist layer with a halftone mask comprising a light transmissive region, a semi-transmissive region, and a light-shielding region, wherein the light-shielding region corresponds to the transparent electrode material layer a region for forming the connecting portion, wherein the semi-transmissive region corresponds to a region on the transparent electrode material layer for forming the transparent electrode, and the light transmitting region corresponds to the transparent electrode material layer a light shielding area and an area other than the semi-light transmitting area;
  • the protective pattern is ashed to remove material on the protective pattern other than the area used to form the filler disposed over the joint.
  • the photoresist layer is formed of a negative photoresist material
  • the step of forming a transparent electrode layer further includes:
  • Exposing the photoresist layer with a halftone mask wherein the halftone mask comprises a light transmissive region, a semi-transmissive region, and a light shielding region, wherein the light transmissive region corresponds to the transparent electrode material layer a region for forming the connecting portion, wherein the semi-transmissive region corresponds to a region on the transparent electrode material layer for forming the transparent electrode, and the light shielding region corresponds to the transparent electrode material layer a light transmissive area and an area other than the semi-transmissive area;
  • the protective pattern is ashed to remove material on the protective pattern other than the area used to form the filler disposed over the joint.
  • the step of forming a transparent electrode layer further comprises: after the step of ashing the protection pattern:
  • the patterned transparent electrode material layer is annealed to obtain the transparent electrode layer.
  • the data electrode includes a source and a drain in the step of forming a via extending through the insulating layer to expose a portion of the drain.
  • the manufacturing method further comprises: after the step of forming a transparent electrode layer:
  • An alignment film is formed on the transparent electrode layer.
  • the material of the alignment film includes a polyimide resin.
  • the material of the transparent electrode material layer comprises indium tin oxide.
  • the step of providing a substrate comprises:
  • the gate pattern layer comprising a gate
  • the material of the active layer pattern layer comprises amorphous silicon.
  • an array substrate is provided, wherein the array substrate is fabricated by the manufacturing method described above, wherein a filler is disposed above the connecting portion of the transparent electrode layer for Fill the vias covered by the connection.
  • the filler is composed of a photoresist.
  • the array substrate further includes an alignment film formed over the transparent electrode layer.
  • the material of the alignment film includes a polyimide resin.
  • a display device wherein the display device comprises the array substrate as described above.
  • the method for fabricating the array substrate of the present invention by providing a filler over the connection portion to fill the via hole covered by the connection portion, when the alignment film is coated on the transparent electrode layer, the corresponding hole is reduced.
  • the adsorption of the position of the connecting portion on the alignment film, the array substrate produced by the method is applied to the display device to avoid color moiré, and the quality of the display screen is improved.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate provided by the present invention
  • FIG. 2 is a flow chart of an embodiment of forming a transparent electrode layer in a method for fabricating an array substrate according to the present invention, wherein the photoresist layer is made of a positive photoresist material;
  • FIG. 3 is a flow chart of another embodiment of forming a transparent electrode layer in a method for fabricating an array substrate according to the present invention, wherein the photoresist layer is made of a negative photoresist material;
  • FIG. 4 is a flow chart showing steps of providing a substrate in a method for fabricating an array substrate according to the present invention
  • FIG. 5 is a schematic structural view of the array substrate after exposure according to the present invention.
  • FIG. 6 is a schematic structural view of the array substrate after the development and etching in the manufacturing process of the present invention.
  • FIG. 7 is a schematic structural view of the array substrate after ashing in the manufacturing process of the present invention.
  • a method for fabricating an array substrate is provided, wherein, as shown in FIG. 1, the manufacturing method includes:
  • the substrate comprises a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulating layer covering the data electrode pattern layer, the data electrode pattern layer comprising at least one data electrode;
  • the substrate includes a transparent substrate on which data is deposited And forming, by the patterning process, the data electrode pattern layer, and forming the insulating layer covering the data electrode pattern layer on the transparent substrate forming the data electrode pattern layer.
  • the data electrode material layer is usually a metal layer film, and the metal layer film is usually deposited by magnetron sputtering; wherein the patterning process generally includes photoresist coating, exposure, development, engraving a process such as etching and photoresist stripping, that is, coating a photoresist on the deposited metal layer film to cover the metal layer film, and then exposing with a mask to form an exposed region and a non-exposed region, and removing by development a photoresist in the exposed region (for example, a positive photoresist), the non-exposed region retains the photoresist; the metal layer film is etched, and the metal layer film in the non-exposed region is not protected by the photoresist The photoresist is etched and finally stripped to obtain the data electrode pattern layer.
  • etching and photoresist stripping that is, coating a photoresist on the deposited metal layer film to cover the metal layer film, and then exposing with a mask to form an exposed region and a
  • the substrate may refer to either a substrate without any film layer, such as a transparent substrate, or a substrate formed with other film layers or patterns.
  • a via hole penetrating the insulating layer is formed by an etching process.
  • the transparent electrode material layer is formed on the transparent substrate on which step S102 is completed.
  • the transparent electrode layer includes a transparent electrode and a connecting portion connected to the transparent electrode, wherein the connecting portion is located in the via hole to connect the transparent electrode and the corresponding data electrode Electrically connected, a filler is disposed above the connecting portion for filling the via hole covered by the connecting portion.
  • the transparent electrode layer is formed by a patterning process on the transparent substrate of step S103, the transparent electrode layer includes the transparent electrode and the connecting portion, and the transparent electrode is connected to the connecting portion, as shown in FIG. 5.
  • the connecting portion is located in the via hole formed in step S102.
  • the via hole exposes a portion of the data electrode, and the connection is connected to the transparent electrode. a portion in the via hole that is in contact with the exposed portion of the data electrode, so the via hole is capable of the transparent electrode and The data electrodes are connected.
  • the shape of the upper portion of the connecting portion is the same as the shape of the through hole, and a filler is disposed above the connecting portion. It can be understood that The filler fills at least a portion of the connecting portion above.
  • a via is provided above the connection portion to fill the via hole, that is, to fill the via hole covered by the connection portion of the transparent electrode. Since the via hole formed in the insulating layer is filled with the filler, when the alignment film is coated on the transparent electrode layer, the adsorption of the alignment film by the connection portion in the via hole is alleviated, and thus the array substrate application produced by the method is applied. When the display device is used, color cloud moiré can be avoided, and the quality of the display screen is improved.
  • the data electrode includes a source and a drain in a step of forming a via hole penetrating the insulating layer to expose a portion of the drain.
  • the data electrode includes the source and the drain, and the via connects the transparent electrode and a portion of the drain.
  • a source-drain metal film is deposited by magnetron sputtering, and the source and the drain pattern layer are formed by a patterning process.
  • the material of the source and the drain may be formed of one or more materials of molybdenum, aluminum, aluminum-bismuth alloy, titanium and copper.
  • the step of forming the transparent electrode layer in the step S104 may specifically include:
  • the transparent electrode material layer is deposited on the transparent substrate completed in the foregoing step S102.
  • the transparent electrode material is an indium tin oxide material.
  • a photoresist layer is coated on the transparent substrate completed in step S201, and the light is A layer of a capping layer covers the layer of transparent electrode material.
  • the step of forming a transparent electrode layer further includes:
  • S2031 exposing the photoresist layer by using a halftone mask, wherein the halftone mask comprises a light transmissive region, a semi-transmissive region, and a light shielding region, wherein the light shielding region corresponds to the transparent electrode material a region on the layer for forming the connecting portion, wherein the semi-transmissive region corresponds to a region on the transparent electrode material layer for forming the transparent electrode, and the light transmitting region corresponds to the transparent electrode material layer An area outside the above area;
  • the photoresist layer 19 coated in step S202 may be exposed as shown in FIG. 5, where the exposure is performed using a halftone mask, and the halftone mask shown in FIG.
  • the light-transmissive region 20, the semi-transmissive region 21 and the light-shielding region 22 are formed.
  • the photoresist layer 19 is exemplified by the positive photoresist material.
  • the light shielding region 22 of the halftone mask corresponds to the region of the transparent electrode material layer where the connection portion 17 corresponding to the via hole corresponds, that is, the position corresponding to the light shielding region 22 shown in FIG. .
  • the photoresist layer exposed by the halftone mask is developed in step S2031, wherein the photoresist layer of the transparent region is completely removed after being developed, the semi-transparent The photoresist layer of the light region is thinned after development, and the photoresist layer of the light-shielding region is completely retained, and finally the protective pattern is obtained.
  • the transparent electrode material layer from which the photoresist is removed is etched to obtain the transparent electrode layer. It can be understood that the photoresist layer of the semi-transmissive region passes through the engraving. After the etching process is completely removed, the photoresist layer of the light-shielding region can be filled above the connecting portion although it is thinned after the etching process.
  • FIG. 6 a schematic structural view of the array substrate after development and etching, as can be seen from FIG. 6 and FIG. 5 , the light transmissive area on the array substrate and the halftone mask in FIG. 6 .
  • the corresponding photoresist layer 19 has been removed, and the thickness of the photoresist layer 19 corresponding to the semi-transmissive region 21 is also thinned, and the thickness of the photoresist layer 19 corresponding to the light-shielding region 22 is also There is a thinning, but as can be seen from Fig. 6, the upper position of the connecting portion 17 can still be filled.
  • the photoresist layer on the protection pattern is ashed to obtain the transparent electrode, but the photoresist layer disposed on the connection portion remains to fill the connection portion.
  • the via after the covering It will be understood that the photoresist described herein is filled over the joint as a filler as described above.
  • the structure of the array substrate after ashing is as shown in FIG. 7 and FIG. 6 .
  • the photoresist layer 19 on the transparent electrode 16 is completely removed to obtain transparency.
  • the electrode 16, the photoresist layer 19 above the connection portion 17 is partially removed, and the remaining photoresist fills the via hole covered by the connection portion 17.
  • the step of forming the transparent electrode layer in the step S104 described above may specifically include:
  • step S201 and step S202 are the same as the steps described above.
  • the step of forming a transparent electrode layer further includes:
  • exposing the photoresist layer by using a halftone mask wherein the halftone mask comprises a light transmissive region, a semi-transmissive region, and a light shielding region, wherein the light transmissive region corresponds to the transparent electrode a region on the material layer for forming the connection portion, wherein the semi-transmissive region corresponds to a region on the transparent electrode material layer for forming the transparent electrode, and the light shielding region corresponds to the transparent electrode material layer An area outside the above area.
  • the photoresist layer 19 is formed of the negative photoresist material, since the characteristics of the negative photoresist material are opposite to those of the positive photoresist material, the halftone mask is exposed to the photoresist layer 19, the light transmissive regions 20 and the light shielding regions 22 on the halftone mask are opposite to the corresponding positions on the transparent electrode material layer, that is, the halftone
  • the light transmitting region 20 of the mask corresponds to a region of the transparent electrode material layer where the connecting portion 17 corresponding to the via hole corresponds (not shown).
  • the photoresist layer 19 is a positive photoresist material
  • the photoresist layer after being exposed through the halftone mask in step S2032 is developed, wherein the light shielding is performed.
  • the photoresist layer of the region is completely removed after development, and the photoresist layer of the semi-transmissive region is thinned after development, and the photoresist layer of the transparent region is completely retained. Down, the protection pattern is finally obtained.
  • the transparent electrode material layer from which the photoresist is removed is etched to obtain the transparent electrode layer. It can be understood that the photoresist layer of the semi-transmissive region passes through the engraving. After the etching process is completely removed, the photoresist layer of the light-transmissive region can be filled with the via hole covered by the connecting portion although it is thinned after the etching process.
  • step S2062 is the same as step S2061.
  • the filling in the connecting portion is formed at the same time as the step of forming the transparent electrode layer, and the use of the mask is not increased, and the complexity of the process is not increased.
  • the step of forming a transparent electrode layer further comprises: after the step of ashing the protection pattern:
  • the patterned transparent electrode material layer is annealed to obtain the transparent electrode layer.
  • the patterned photoresist layer on the electrode material layer is completely thermally cured after being annealed to obtain the transparent electrode layer.
  • the fabrication method further includes: after the step of forming the transparent electrode layer:
  • An alignment film is formed on the transparent electrode layer.
  • the array substrate produced by the method described above is provided with a filler in the connection portion corresponding to the via hole on the transparent electrode layer, for example, the light described above.
  • the glue is formed, and therefore, the alignment film formed on the transparent electrode on which the filler is formed can avoid the problem of uneven coating.
  • the material of the alignment film includes a polyimide resin.
  • the material of the transparent electrode material layer described above includes indium tin oxide.
  • the step of providing a substrate includes:
  • a gate metal layer film is deposited by magnetron sputtering on the transparent substrate described above, and the gate pattern layer including the gate electrode is formed by a patterning process.
  • the patterning process may specifically include processes such as photoresist coating, exposure, development, etching, and photoresist stripping.
  • a photoresist is coated on the deposited gate metal layer film and covers the gate metal layer film; then exposed by a mask to form an exposed region and a non-exposed region; and the exposed region is removed by development Gluing (in the case of a positive photoresist), the photoresist in the non-exposed area is retained; the gate metal film is etched, and the gate metal film in the non-exposed area is not etched due to the protection of the photoresist Finally, the photoresist is stripped to form the gate pattern layer including the gate.
  • the material of the gate electrode may be a single layer or a multilayer composite laminate formed of one or more materials of molybdenum, aluminum, aluminum bismuth alloy, titanium and copper.
  • the gate insulating layer is formed by a method of thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like.
  • the active layer pattern layer includes an active layer corresponding to the gate, and the active layer is electrically connected to the data electrode .
  • an active layer film is deposited, and the active layer pattern layer is formed by a patterning process, and the active layer pattern layer includes the active layer a layer, the active layer is electrically connected to the data electrode described above, and when the data electrode includes the source and the drain, the source and the drain respectively and the active layer connection.
  • the material of the active layer pattern layer comprises amorphous silicon.
  • the array substrate is divided into a plurality of pixel units, each of which includes a gate, an active layer, a source and a drain, and the structural diagrams shown in FIG. 5 to FIG. 7 are only illustrated.
  • a schematic diagram of a structure in a pixel unit wherein a gate electrode 11 is formed over the transparent substrate 10, a gate insulating layer 12 is formed over the gate electrode 11, and an active layer 13 is formed over the gate insulating layer 12, and is gated
  • the data electrodes 14 (specifically, the source and the drain) are located on two layers above the active layer 13 and are respectively connected to the active layer 13 , and the insulating layer 15 is formed above the data electrode 14 .
  • the via hole penetrates through the insulating layer 15, and the transparent electrode layer is formed above the insulating layer 15, wherein the connecting portion 17 is located in the via hole, and the transparent electrode 16 is located above the insulating layer 15 and connected to the connecting portion 17.
  • the method for fabricating an array substrate provided by the present invention ensures that the flatness of the transparent electrode layer is provided on the transparent electrode layer by providing a filler on the transparent electrode layer above the connection portion corresponding to the via hole passing through the insulating layer.
  • the alignment film can be uniformly diffused over the transparent electrode layer, which solves the problem of uneven distribution of the alignment film due to adsorption of via holes in the prior art.
  • the manufacturing method does not increase the use of the mask while solving the above problems, and the process difficulty is not increased.
  • an array substrate is provided, wherein the array substrate is produced by the above-described fabrication method.
  • the array substrate includes a transparent substrate 10, a data electrode pattern layer disposed on the transparent substrate 10, an insulating layer 15 covering the data electrode pattern layer, and a transparent electrode above the insulating layer 15.
  • the data electrode layer includes at least one data electrode 14, and the insulating layer 15 is provided with a through hole penetrating the insulating layer 15.
  • the via hole connects the transparent electrode 16 and the partial data electrode 14, and the connection portion 17 is located in the via hole, and a filler 18 is disposed above the connection portion 17.
  • the at least one data electrode comprises a source and a drain, and the via is connected The transparent electrode and a portion of the drain are connected.
  • the filler comprises a photoresist.
  • the array substrate further includes an alignment film disposed above the transparent electrode layer.
  • the substrate in order to perfect the structure of the array substrate, is provided with a gate pattern layer on the transparent substrate, a gate insulating layer above the gate pattern layer, and An active layer pattern layer over the gate insulating layer, wherein the gate pattern layer includes a gate, the active layer pattern layer includes an active layer, and the gate corresponds to the active layer
  • the active layer is connected to the at least one data electrode, and when the at least one data electrode comprises a source and a drain, the source and the drain are respectively connected to the active layer.
  • the array substrate provided by the present invention is produced by the method described above.
  • the array substrate is applied to a liquid crystal display panel, there is no problem that the display panel is stained due to thickening of the alignment film, and
  • the liquid crystal display panel of the array substrate is applied to a display device, the color moiré problem does not occur, and the quality of the display screen can be improved.
  • a display device wherein the display device comprises the array substrate as described above.
  • the display device includes a product or component having a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a display, a notebook computer, or the like.
  • a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a display, a notebook computer, or the like.
  • the display device provided by the present invention improves the quality of the display screen by using the array substrate described above.

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Abstract

提供一种阵列基板的制作方法，包括：提供衬底，衬底包括透明基板、形成在透明基板上的数据电极图形层以及覆盖数据电极图形层的绝缘层，数据电极图形层包括至少一个数据电极（S101）；形成贯穿绝缘层的过孔，以至少暴露出至少一个数据电极中的一个数据电极的一部分（S102）；形成透明电极材料层（S103）；形成透明电极层，透明电极层包括透明电极和与透明电极相连的连接部，连接部位于过孔中，以将透明电极与相应的数据电极电连接，连接部上方设置有填充物（S104）。还提供一种阵列基板及显示装置。该阵列基板的制作方法减轻了与过孔对应的连接部位置对取向膜的吸附作用。

Description

阵列基板的制作方法、阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
随着薄膜晶体管液晶显示面板的技术发展，对画面品质的要求越来越高。用于制备取向膜的聚酰亚胺树脂(Polyimide，简称PI)膜增厚对提高摩擦锚定能力有显著的改善作用，且摩擦能力增强对大尺寸产品的漏光残像都有显著的改善作用。但是PI膜增厚也会带来面板污渍等问题，主要是由于过孔处段差较大，PI扩散很容易受到影响而被吸附进过孔，从而导致明显的色云纹(mura)出现，严重影响画面的品质。
发明内容
本发明旨在解决现有技术中存在的技术问题之一，提供一种阵列基板的制作方法、阵列基板及显示装置。
作为本发明的第一个方面，提供一种阵列基本的制作方法，包括：
提供衬底，所述衬底包括透明基板、形成在所述透明基板上的数据电极图形层以及覆盖所述数据电极图形层的绝缘层，所述数据电极图形层包括至少一个数据电极；
形成贯穿所述绝缘层的过孔，以至少暴露出所述至少一个数据电极中的一个数据电极的一部分；
形成透明电极材料层；
形成透明电极层，所述透明电极层包括透明电极和与所述透明电极相连的连接部，所述连接部位于所述过孔中，以将所述透明电极与相应的所述数据电极电连接，所述连接部上方设置有填充物，用以填充被所述连接部覆盖后的过孔。
可选地，形成透明电极层的步骤包括：
在形成有所述过孔的所述绝缘层的透明基板上沉积所述透明电极材料层；
在所述透明电极材料层上涂覆光刻胶层。
可选地，所述光刻胶层由正性光刻胶材料形成，所述形成透明电极层的步骤还包括：
利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述遮光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述透光区对应所述透明电极材料层上除所述遮光区和所述半透光区之外的区域；
对曝光后的所述光刻胶层进行显影，以获得保护图形；
对设置有所述保护图形的所述透明电极材料层进行刻蚀以获得所述透明电极层；
对所述保护图形进行灰化，以去除所述保护图形上除用于形成所述连接部上方设置的填充物的区域之外的材料。
可选地，所述光刻胶层由负性光刻胶材料形成，所述形成透明电极层的步骤还包括：
利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述透光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述遮光区对应所述透明电极材料层上除所述透光区和所述半透光区之外的区域；
对曝光后的所述光刻胶层进行显影，以获得保护图形；
对设置有所述保护图形的所述透明电极材料层进行刻蚀以获得所述透明电极层；
对所述保护图形进行灰化，以去除所述保护图形上除用于形成所述连接部上方设置的填充物的区域之外的材料。
可选地，所述形成透明电极层的步骤还包括在对所述保护图形进行灰化的步骤之后进行的：
对图形化的所述透明电极材料层进行退火，以获得所述透明电极层。
可选地，所述数据电极包括源极和漏极，在形成贯穿所述绝缘层的过孔的步骤中，以暴露出部分所述漏极。
可选地，所述制作方法还包括在形成透明电极层的步骤之后进行的：
在所述透明电极层上形成取向膜。
可选地，所述取向膜的材料包括聚酰亚胺树脂。
可选地，所述透明电极材料层的材料包括氧化铟锡。
可选地，所述提供衬底的步骤包括：
在所述透明基板上形成栅极图形层，所述栅极图形层包括栅极；
形成栅极绝缘层，以覆盖所述栅极图形层；
形成有源层图形层，以覆盖所述栅极图形层，所述有源层图形层包括与所述栅极对应的有源层，且所述有源层与所述至少一个数据电极电连接。
优选地，所述有源层图形层的材料包括非晶硅。
作为本发明的第二个方面，提供一种阵列基板，其中，所述阵列基板由前文所述的制作方法制作得到，其中所述透明电极层的所述连接部上方设置有填充物，用以填充被连接部覆盖后的过孔。
可选地，所述填充物由光刻胶构成。
可选地，所述阵列基板还包括在所述透明电极层上方形成的取向膜。
可选地，所述取向膜的材料包括聚酰亚胺树脂。
作为本发明的第三个方面，提供一种显示装置，其中，所述显示装置包括前文所述的阵列基板。
本发明提供的阵列基板的制作方法，通过在连接部的上方设置填充物，以填充被连接部覆盖后的过孔，当在透明电极层上涂覆取向膜时，减轻了与过孔对应的连接部位置对取向膜的吸附作用，通过该方法制作得到的阵列基板应用于显示装置中时避免出现色云纹，提高了显示画面的品质。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1为本发明提供的阵列基板的制作方法流程图；
图2为本发明提供的阵列基板的制作方法中形成透明电极层的一种实施方式流程图，其中，所述光刻胶层由正性光刻胶材料制成；
图3为本发明提供的阵列基板的制作方法中形成透明电极层的另一种实施方式流程图，其中，所述光刻胶层由负性光刻胶材料制成；
图4为本发明提供的阵列基板的制作方法中提供衬底的步骤流程图；
图5为本发明提供的阵列基板制作过程中曝光后的结构示意图；
图6为本发明提供的阵列基板制作过程中显影刻蚀后的结构示意图；
图7为本发明提供的阵列基板制作过程中灰化后的结构示意图。
其中，10、透明基板；11、栅极；12、栅极绝缘层；13、有源层；14、数据电极；15、绝缘层；16、透明电极；17、连接部；18、填充物；19、光刻胶层；20、透光区；21、半透光区；22、遮光区。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的第一个方面，提供一种阵列基板的制作方法，其中，如图1所示，所述制作方法包括：
S101、提供衬底，所述衬底包括透明基板、形成在所述透明基板上的数据电极图形层以及覆盖所述数据电极图形层的绝缘层，所述数据电极图形层包括至少一个数据电极；
具体地，所述衬底包括透明基板，在所述透明基板上沉积数据 电极材料层，并通过构图工艺获得所述数据电极图形层，在形成数据电极图形层的透明基板上形成覆盖所述数据电极图形层的所述绝缘层。
需要说明的是，所述数据电极材料层通常为金属层薄膜，通常采用磁控溅射的方法沉积所述金属层薄膜；其中所述构图工艺通常包括光刻胶涂覆、曝光、显影、刻蚀以及光刻胶剥离等工艺，即在沉积的所述金属层薄膜上涂覆光刻胶以覆盖所述金属层薄膜，然后利用掩膜板曝光，形成曝光区和非曝光区，通过显影去除曝光区的光刻胶(以正性光刻胶为例)，非曝光区保留光刻胶；刻蚀所述金属层薄膜，非曝光区的所述金属层薄膜由于光刻胶的保护而未被刻蚀，最后剥离光刻胶，得到所述数据电极图形层。
应当理解的是，所述衬底既可以指没有任何膜层的衬底，如透明基板，也可以指形成有其它膜层或者图案的衬底。
S102、形成贯穿所述绝缘层的过孔，以至少暴露出所述至少一个数据电极中的一个数据电极的一部分；
具体地，在完成S101步骤的透明基板上，通过刻蚀工艺形成贯穿所述绝缘层的过孔。
S103、形成透明电极材料层；
具体地，在完成步骤S102的透明基板上形成所述透明电极材料层。
S104、形成透明电极层，所述透明电极层包括透明电极和与所述透明电极相连的连接部，所述连接部位于所述过孔中，以将所述透明电极与相应的所述数据电极电连接，所述连接部上方设置有填充物，用以填充被所述连接部覆盖后的过孔。
具体地，在步骤S103的透明基板上通过构图工艺形成所述透明电极层，所述透明电极层包括所述透明电极和所述连接部，所述透明电极与所述连接部连接，由图5至图7可以看出，所述连接部位于步骤S102形成的所述过孔中，由前文所述可知，所述过孔暴露部分所述数据电极，而与所述透明电极连接的所述连接部位于所述过孔中与暴露的部分所述数据电极接触，所以所述过孔能够将所述透明电极和 所述数据电极连接，由图5至图7还可以看出所述连接部的上方的形状与所述过孔的形状相同，在所述连接部的上方设置有填充物，可以理解的是，所述填充物至少填充部分所述连接部的上方。
本发明提供的阵列基板的制作方法，通过在连接部的上方设置填充物，以填充过孔，即，填充被透明电极的连接部覆盖后的过孔。由于在绝缘层中形成的过孔被填充物填充，当在透明电极层上涂覆取向膜时，减轻了过孔中的连接部对取向膜的吸附，因此通过该方法制作得到的阵列基板应用于显示装置中时能够避免出现色云纹，提高了显示画面的品质。
可以理解的是，当被所述连接部覆盖后的过孔完全被所述填充物填充时，所述透明电极层的表面保持平整，当在所述透明电极层的上方涂覆取向膜时，不会影响取向膜的均匀扩散，能够保证涂覆的取向膜的均匀性，即使增厚取向膜也不会出现显示面板污渍等问题。
作为所述数据电极的一种具体地实施方式，所述数据电极包括源极和漏极，在形成贯穿所述绝缘层的过孔的步骤中，以暴露出部分所述漏极。
具体地，所述数据电极包括所述源极和漏极，所述过孔连接所述透明电极和部分所述漏极。在前文所述步骤S101中，采用磁控溅射的方法沉积源漏金属薄膜，通过构图工艺形成所述源极和所述漏极图形层。其中，所述源极和所述漏极的材料可以由钼、铝、铝钕合金、钛和铜中的一种或多种材料形成。
为了更加清楚地了解所述透明电极层的形成，作为一种具体地实施方式，如图2所示，前文所述步骤S104形成透明电极层的步骤具体可以包括：
S201、在形成有所述过孔的所述绝缘层的透明基板上沉积所述透明电极材料层；
具体地，在前述步骤S102完成的透明基板上，沉积所述透明电极材料层，优选地，所述透明电极材料为氧化铟锡材料。
S202、在所述透明电极材料层上涂覆光刻胶层；
具体地，在步骤S201完成的透明基板上涂覆光刻胶层，所述光 刻胶层覆盖所述透明电极材料层。
当所述光刻胶层由正性光刻胶材料形成时，所述形成透明电极层的步骤还包括：
S2031、利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述遮光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述透光区对应所述透明电极材料层上除上述区域之外的区域；
具体地，可以结合附图5所示，对步骤S202涂覆的光刻胶层19进行曝光，此处曝光采用的是半色调掩膜板，图5中所示的所述半色调掩膜板包括透光区20、半透光区21和遮光区22，光刻胶层19以所述正性光刻胶材料为例，为了实现连接部17上方形成填充物18，可以理解的是，在进行曝光时，所述半色调掩膜板的遮光区22与所述透明电极材料层上与所述过孔对应的连接部17所在区域对应，即图5中所示的遮光区22对应的位置。
S2041、对曝光后的所述光刻胶层进行显影，以获得保护图形；
具体地，对步骤S2031通过所述半色调掩膜板曝光后的所述光刻胶层进行显影，其中所述透光区的所述光刻胶层经过显影后完全去除了，所述半透光区的所述光刻胶层经过显影后变薄了，而所述遮光区的所述光刻胶层全部保留下来，最终获得了所述保护图形。
S2051、对设置有所述保护图形的所述透明电极材料层进行刻蚀；
具体地，对去除所述光刻胶的所述透明电极材料层进行刻蚀，获得所述透明电极层，可以理解的是，所述半透光区的所述光刻胶层经过所述刻蚀工艺后完全去除，所述遮光区的所述光刻胶层经过所述刻蚀工艺后虽然有所减薄，但还是能够填充所述连接部的上方。
如图6所示，为所述阵列基板显影刻蚀后的结构示意图，由图6和图5对比可以看出，图6中所述阵列基板上与所述半色调掩膜板的透光区20对应的光刻胶层19已经被去除，与半透光区21对应的光刻胶层19的厚度也变薄，与遮光区22对应的光刻胶层19的厚度也 有所减薄，但由图6可以看出，仍能够填充连接部17的上方位置。
S2061、对所述保护图形进行灰化，以去除所述保护图形上除用于形成所述连接部的区域之外的材料。
具体地，对所述保护图形上的所述光刻胶层进行灰化，获得所述透明电极，但是所述连接部上设置的所述光刻胶层保留，以填平被所述连接部覆盖后的所述过孔。可以理解的是，此处所述光刻胶作为前文所述的填充物填充在所述连接部上方。
如图7所示，为所述阵列基板灰化后的结构示意图，由图7与图6对比可以看出，经过灰化后，位于透明电极16上的光刻胶层19全部去除，获得透明电极16，连接部17上方的光刻胶层19部分去除，剩余的光刻胶填平被连接部17覆盖后的过孔。
作为另一种具体地实施方式，如图3所示，前文所述步骤S104形成透明电极层的步骤具体可以包括：
S201、在形成有所述过孔的所述绝缘层的透明基板上沉积所述透明电极材料层；
S202、在所述透明电极材料层上涂覆光刻胶层；
可以理解的是，步骤S201和步骤S202与前文描述的步骤相同。
当所述光刻胶层由负性光刻胶材料形成时，所述形成透明电极层的步骤还包括：
S2032、利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述透光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述遮光区对应所述透明电极材料层上除上述区域之外的区域。
可以理解的是，光刻胶层19由所述负性光刻胶材料形成时，由于所述负性光刻胶材料的特性与所述正性光刻胶材料的特性相反，所以在通过所述半色调掩膜板对光刻胶层19曝光时，所述半色调掩膜板上的透光区20与遮光区22与所述透明电极材料层上的对应位置相反，即所述半色调掩膜板的透光区20与所述透明电极材料层上与所述过孔对应的连接部17所在区域对应(图中未示出)。
S2042、对曝光后的所述光刻胶层进行显影，以获得保护图形；
可以理解的是，与光刻胶层19为正性光刻胶材料相反的是，在对步骤S2032通过所述半色调掩膜板曝光后的所述光刻胶层进行显影，其中所述遮光区的所述光刻胶层经过显影后被完全去除，所述半透光区的所述光刻胶层经过显影后变薄了，而所述透光区的所述光刻胶层全部保留下来，最终获得了所述保护图形。
S2052、对设置有所述保护图形的所述透明电极材料层进行刻蚀；
具体地，对去除所述光刻胶的所述透明电极材料层进行刻蚀，获得所述透明电极层，可以理解的是，所述半透光区的所述光刻胶层经过所述刻蚀工艺后被完全去除，所述透光区的所述光刻胶层经过所述刻蚀工艺后虽然有所减薄，但还是能够填充被所述连接部覆盖后的过孔。
S2062、对所述保护图形进行灰化，以去除所述保护图形上除用于形成所述连接部上方设置的填充物的区域之外的材料。
可以理解的是，步骤S2062与步骤S2061相同。
本发明提供的阵列基板的制作方法，在形成透明电极层的步骤的同时形成了连接部内的填充物，没有增加掩膜板的使用，未增加工艺的复杂度。
为了获得所述透明电极层，作为一种优选的实施方式，所述形成透明电极层的步骤还包括在对所述保护图形进行灰化的步骤之后进行的：
对图形化的所述透明电极材料层进行退火，以获得所述透明电极层。
可以理解的是，所述电极材料层上图形化的所述光刻胶层经过退火工艺后完全热固化下来，得到所述透明电极层。
当通过上述方法制作得到的所述阵列基板应用于液晶显示面板中时，为了控制液晶分子的扭曲状态，所述制作方法还包括在形成透明电极层的步骤之后进行的：
在所述透明电极层上形成取向膜。
由前文所述可知，通过前文所述的方法制作得到的所述阵列基板，其所述透明电极层上与所述过孔对应的所述连接部内设置有填充物，例如，前文所述的光刻胶，因此，在形成有填充物的透明电极上形成的取向膜能够避免涂覆不均的问题出现。
优选地，所述取向膜的材料包括聚酰亚胺树脂。
另外，优选地，前文所述透明电极材料层的材料包括氧化铟锡。
为了完善所述阵列基板的制作方法，如图4所示，所述提供衬底的步骤包括：
S301、在所述透明基板上形成栅极图形层，所述栅极图形层包括栅极；
具体地，在前文所述的透明基板上采用磁控溅射的方法沉积一层栅极金属层薄膜，并通过构图工艺形成包括所述栅极的所述栅极图形层。其中所述构图工艺具体可以包括光刻胶涂覆、曝光、显影、刻蚀以及光刻胶剥离等工艺。即在沉积的所述栅极金属层薄膜上涂覆光刻胶并覆盖所述栅极金属层薄膜；然后利用掩膜板进行曝光，形成曝光区和非曝光区；通过显影去除曝光区的光刻胶(以正性光刻胶为例)，非曝光区的光刻胶保留；刻蚀栅极金属层薄膜，非曝光区的栅极金属层薄膜由于光刻胶的保护而未被刻蚀，最后剥离光刻胶，形成了包括所述栅极的所述栅极图形层。
优选地，所述栅极的材料可以为钼、铝、铝钕合金、钛和铜中的一种或多种材料形成的单层或多层复合叠层。
S302、形成栅极绝缘层，以覆盖所述栅极图形层；
具体地，在完成步骤S301的透明基板上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相沉积、溅射等制备方法，形成所述栅极绝缘层。
S303、形成有源层图形层，以覆盖所述栅极图形层，所述有源层图形层包括与所述栅极对应的有源层，且所述有源层与所述数据电极电连接。
具体地，在完成步骤S302的透明基板上，沉积有源层薄膜，通过构图工艺形成所述有源层图形层，所述有源层图形层包括所述有源 层，所述有源层与前文所述的数据电极电连接，当所述数据电极包括所述源极和所述漏极时，所述源极和所述漏极分别与所述有源层连接。
优选地，所述有源层图形层的材料包括非晶硅。
可以理解的是，所述阵列基板被划分为多个像素单元，每个像素单元均包括栅极、有源层、源极和漏极，如图5至图7所示的结构示意图仅示例出一个像素单元中的结构示意图，其中，栅极11形成于透明基板10上方，栅极绝缘层12形成于栅极11的上方，有源层13形成于栅极绝缘层12的上方，并与栅极11位置对应，数据电极14(具体可以是源极和漏极)位于有源层13上方的两层，并分别与有源层13连接，绝缘层15形成于数据电极14的上方，所述过孔贯穿绝缘层15，所述透明电极层形成于绝缘层15的上方，其中连接部17位于所述过孔中，透明电极16位于绝缘层15上方并与连接部17连接。
本发明提供的阵列基板的制作方法，通过将透明电极层上与贯穿绝缘层的过孔位置对应的连接部的上方设置填充物，保证了透明电极层的平整度，当在该透明电极层上涂覆取向膜时，能够使得取向膜在透明电极层的上方均匀扩散，解决了现有技术中由于过孔的吸附作用导致取向膜分布不均的问题。另外，该制作方法在解决上述问题的同时不会增加掩膜板的使用，工艺制作难度也未增加。
作为本发明的第二个方面，提供一种阵列基板，其中，所述阵列基板由前文所述的制作方法制作得到。
具体地，如图7所示，所述阵列基板包括透明基板10、设置在透明基板10上的数据电极图形层、覆盖所述数据电极图形层的绝缘层15，位于绝缘层15上方的透明电极层，其中，所述透明电极层包括透明电极16和与透明电极16连接的连接部17，所述数据电极层包括至少一个数据电极14，绝缘层15上设置有贯穿绝缘层15的过孔，所述过孔连接透明电极16和部分数据电极14，连接部17位于所述过孔中，连接部17的上方设置有填充物18。
优选地，所述至少一个数据电极包括源极和漏极，所述过孔连 接所述透明电极和部分所述漏极。
优选地，所述填充物包括光刻胶。
优选地，所述阵列基板还包括取向膜，所述取向膜设置在所述透明电极层的上方。
另外，可以理解的是，为了完善所述阵列基板的结构，所述衬底上设置有位于所述透明基板上的栅极图形层、位于所述栅极图形层上方的栅极绝缘层，以及位于所述栅极绝缘层上方的有源层图形层，其中，所述栅极图形层包括栅极，所述有源层图形层包括有源层，所述栅极与所述有源层对应设置，所述有源层与所述至少一个数据电极连接，当所述至少一个数据电极包括源极和漏极时，所述源极和所述漏极分别与所述有源层连接。
关于阵列基板中使用的材料描述可以参照前文阵列基板的制作方法中的内容，此处不再赘述。
本发明提供的阵列基板，通过采用前文所述的方法制作得到，当该阵列基板应用于液晶显示面板中时，不会产生由于取向膜的增厚而导致显示面板出现污渍的问题，且当具有该阵列基板的液晶显示面板应用于显示装置中时不会出现色云纹问题，能够提高显示画面的品质。
作为本发明的第三个方面，提供一种显示装置，其中，所述显示装置包括前文所述的阵列基板。
具体地，所述显示装置包括液晶面板、手机、平板电脑、显示器、笔记本电脑等具有显示功能的产品或部件。
本发明提供的显示装置由于采用前文所述的阵列基板，提高了显示画面的品质。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

  1. 一种阵列基板的制作方法，包括：
    提供衬底，所述衬底包括透明基板、形成在所述透明基板上的数据电极图形层以及覆盖所述数据电极图形层的绝缘层，所述数据电极图形层包括至少一个数据电极；
    形成贯穿所述绝缘层的过孔，以至少暴露出所述至少一个数据电极中的一个数据电极的一部分；
    形成透明电极材料层；
    形成透明电极层，所述透明电极层包括透明电极和与所述透明电极相连的连接部，所述连接部位于所述过孔中，以将所述透明电极与相应的所述数据电极电连接，所述连接部上方设置有填充物，用以填充被所述连接部覆盖后的过孔。
  2. 根据权利要求1所述的制作方法，其中，形成透明电极层的步骤包括：
    在形成有所述过孔的所述绝缘层的透明基板上沉积所述透明电极材料层；
    在所述透明电极材料层上涂覆光刻胶层。
  3. 根据权利要求2所述的制作方法，其中，所述光刻胶层由正性光刻胶材料形成，以及所述形成透明电极层的步骤包括：
    利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述遮光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述透光区对应所述透明电极材料层上除所述遮光区和所述半透光区之外的区域；
    对曝光后的所述光刻胶层进行显影，以获得保护图形；
    对设置有所述保护图形的所述透明电极材料层进行刻蚀以获得所述透明电极层；
    对所述保护图形进行灰化，以去除所述保护图形上除用于形成 所述连接部上方设置的填充物的区域之外的材料。
  4. 根据权利要求2所述的制作方法，其中，所述光刻胶层由负性光刻胶材料形成，以及所述形成透明电极层的步骤包括：
    利用半色调掩膜板对所述光刻胶层进行曝光，其中，所述半色调掩膜板包括透光区、半透光区和遮光区，所述透光区对应所述透明电极材料层上用于形成所述连接部的区域，所述半透光区对应所述透明电极材料层上用于形成所述透明电极的区域，所述遮光区对应所述透明电极材料层上除所述透光区和所述半透光区之外的区域；
    对曝光后的所述光刻胶层进行显影，以获得保护图形；
    对设置有所述保护图形的所述透明电极材料层进行刻蚀以获得所述透明电极层；
    对所述保护图形进行灰化，以去除所述保护图形上除用于形成所述连接部上方设置的填充物的区域之外的材料。
  5. 根据权利要求3或4所述的制作方法，其中，所述形成透明电极层的步骤还包括在对所述保护图形进行灰化的步骤之后进行的：
    对图形化的所述透明电极材料层进行退火，以获得所述透明电极层。
  6. 根据权利要求1至4中任意一项所述的制作方法，其中，所述至少一个数据电极包括源极和漏极，在形成贯穿所述绝缘层的过孔的步骤中，以暴露出部分所述漏极。
  7. 根据权利要求1至4中任意一项所述的制作方法，还包括在形成透明电极层的步骤之后进行的：
    在所述透明电极层上形成取向膜。
  8. 根据权利要求7所述的制作方法，其中，所述取向膜的材料包括聚酰亚胺树脂。
  9. 根据权利要求1至4中任意一项所述的制作方法，其中，所述透明电极材料层的材料包括氧化铟锡。
  10. 根据权利要求1至4中任意一项所述的制作方法，其中，所述提供衬底的步骤包括：
    在所述透明基板上形成栅极图形层，所述栅极图形层包括栅极；
    形成栅极绝缘层，以覆盖所述栅极图形层；
    形成有源层图形层，以覆盖所述栅极图形层，所述有源层图形层包括与所述栅极对应的有源层，且所述有源层与所述至少一个数据电极电连接。
  11. 根据权利要求10所述的制作方法，其中，所述有源层图形层的材料包括非晶硅。
  12. 一种阵列基板，其中，所述阵列基板由权利要求1至11中任意一项所述的制作方法制作得到，其中所述透明电极层的所述连接部上方设置有填充物，用以填充被连接部覆盖后的过孔。
  13. 根据权利要求12所述的阵列基板，其中所述填充物由光刻胶构成。
  14. 根据权利要求12或13所述的阵列基板，还包括在所述透明电极层上方形成的取向膜。
  15. 根据权利要求14所述的阵列基板，其中，所述取向膜的材料包括聚酰亚胺树脂。
  16. 一种显示装置，包括权利要求12至15中任一项所述的阵列基板。
PCT/CN2017/096837 2017-01-03 2017-08-10 阵列基板的制作方法、阵列基板及显示装置 WO2018126688A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN106783747A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080003723A1 (en) * 2006-06-28 2008-01-03 Lg.Philips Lcd Co., Ltd. Method for fabricating thin film transistor substrate
CN105304649A (zh) * 2015-10-28 2016-02-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN105607365A (zh) * 2015-12-31 2016-05-25 深圳市华星光电技术有限公司 一种coa基板及其制作方法
CN106783747A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3429440B2 (ja) * 1997-10-24 2003-07-22 シャープ株式会社 半導体装置およびその製造方法
US6060714A (en) * 1998-01-23 2000-05-09 Ois Optical Imaging Systems, Inc. Large area imager with photo-imageable interface barrier layer
KR101192750B1 (ko) * 2005-12-30 2012-10-18 엘지디스플레이 주식회사 Ｔｆｔ 어레이 기판 및 그 제조방법
CN102707523A (zh) * 2012-04-20 2012-10-03 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
US9046722B2 (en) * 2012-09-20 2015-06-02 Shanghai Avic Optoelectronics Co., Ltd. Method of fabricating In-Plane Switching (IPS) screen electrode
CN103021939B (zh) * 2012-11-30 2015-01-07 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN103855087B (zh) * 2014-02-24 2016-04-27 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN105867038A (zh) * 2016-06-17 2016-08-17 深圳市华星光电技术有限公司 阵列基板及其制作方法、液晶显示器
CN106206432A (zh) * 2016-08-16 2016-12-07 京东方科技集团股份有限公司 阵列基板、阵列基板的制造方法及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080003723A1 (en) * 2006-06-28 2008-01-03 Lg.Philips Lcd Co., Ltd. Method for fabricating thin film transistor substrate
CN105304649A (zh) * 2015-10-28 2016-02-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN105607365A (zh) * 2015-12-31 2016-05-25 深圳市华星光电技术有限公司 一种coa基板及其制作方法
CN106783747A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置

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