WO2018121109A1 - 闪存存储结构及其制造方法 - Google Patents

闪存存储结构及其制造方法 Download PDF

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WO2018121109A1
WO2018121109A1 PCT/CN2017/110888 CN2017110888W WO2018121109A1 WO 2018121109 A1 WO2018121109 A1 WO 2018121109A1 CN 2017110888 W CN2017110888 W CN 2017110888W WO 2018121109 A1 WO2018121109 A1 WO 2018121109A1
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floating gate
layer
forming
substrate
field oxide
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梁志彬
刘涛
张松
金炎
王德进
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs

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  • the present invention relates to the field of semiconductor memory technologies, and in particular, to a flash memory storage structure and a method of fabricating the same.
  • the basic unit of the semiconductor memory device is a semiconductor structure which can represent two states of 0 and 1, and generally, a MOS structure which is common to semiconductor devices is employed.
  • the basic structure of the conventional flash memory (FLASH memory) is mostly to add floating gate memory or release charge in the MOS structure to realize the states of 0 and 1.
  • the outer edge of the floating gate is a tip structure, and when the data needs to be erased, the floating gate tip can be discharged by applying a high voltage to the gate to cause electrons to penetrate from the tunneling oxide layer.
  • the control gate releases the charge stored in the floating gate and changes the storage state of the basic storage unit to achieve the purpose of erasing. It can be understood that the thinner the tunneling oxide layer, the more easily electrons tunnel.
  • an intermediate structure covered with a tunneling oxide layer is further formed after the floating gate is formed. Thereafter the intermediate structure undergoes multiple wet etching processes. Due to the instability of the wet etching, more corrosion occurs at the corners of the bottom of the tunneling oxide layer relative to other places, so that the control gate forms a sharp corner there during the subsequent formation of the control gate. Electrons are easily tunneled from the control gate into the floating gate (this process is called anti-tunneling), resulting in erase instability.
  • a method of manufacturing a flash memory storage structure comprising:
  • a control gate is formed on the tunnel oxide layer.
  • the step of forming a protective sidewall at a corner of the bottom of the floating gate includes:
  • the isolation layer covers the field oxide structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate;
  • Part of the isolation layer is removed and only the protective sidewalls at the corners of the bottom of the floating gate are retained.
  • a flash storage structure comprising:
  • a control gate is formed on the tunnel oxide layer.
  • the flash memory storage structure of the above embodiment and the manufacturing method thereof by forming a protective sidewall at the bottom corner of the floating gate, and subsequently forming the tunnel oxide layer, even after undergoing multiple wet etching, the bottom corner of the tunnel oxide layer Corroded, it will also be protected from further corrosion by the protective sidewall.
  • the control gate does not form sharp corners. It can effectively prevent electron anti-tunneling.
  • the protective sidewalls are made of materials that are not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.
  • FIG. 1 is a schematic diagram of a memory formed using a basic structure having a floating gate
  • FIG. 2a is a schematic structural view of the basic storage unit of FIG. 1;
  • FIG. 2b is a schematic structural view of the basic memory cell of FIG. 1 in the presence of a wet etch defect
  • FIG. 3 is a flow chart showing a method of manufacturing a flash memory storage structure according to an embodiment
  • FIG. 4a to 4e are schematic diagrams showing intermediate structures after processing in the steps shown in FIG. 3;
  • Figure 5 is a flow chart for forming a floating gate
  • 6a to 6c and 4b are schematic diagrams showing the intermediate structure after the steps in the flow shown in FIG. 5;
  • Figure 7 is a schematic view showing the structure formed after depositing an isolation layer on the intermediate structure.
  • FIG. 1 is a schematic diagram of a memory formed using a basic structure having a floating gate. As shown in FIG. 2a, it is a schematic structural diagram of such a basic storage unit.
  • the basic memory cell 10 includes a substrate structure 15, a polysilicon floating gate 11 disposed on the substrate 15, a field oxide structure 12 formed on the floating gate 11, and tunneling oxidation overlying the floating gate 11 and the field oxide structure 12.
  • Layer 13, and polysilicon control gate 14 overlying tunneling oxide layer 13.
  • the floating gate 11 has a tip end 111.
  • control gate 14 forms a sharp corner 141 at the bottom of the tunnel oxide layer 13, as shown in Figure 2b. Electrons are easily tunneled from the control gate 14 into the floating gate 11, resulting in an unstable erase.
  • the method of the following embodiments can be used to better fabricate flash memory storage structures and avoid the formation of sharp corners at the bottom of the tunnel oxide layer.
  • FIG. 3 is a flow chart of a method of fabricating a flash memory storage structure in accordance with an embodiment. The method includes the following steps S110 to S150. 4a to 4e are schematic views of intermediate structures after processing in each step.
  • Step S110 depositing a polysilicon layer 200 on the substrate structure 100.
  • the substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and a gate oxide layer above the channel region. For the sake of simplicity, these details are not shown in FIGS. 4a to 4e. It is expressly shown that it is represented only by the entire substrate structure 100.
  • This step is a process after the substrate structure 100 is completed. The structure formed after the treatment in this step is as shown in Fig. 4a.
  • Step S120 forming a floating gate 210 and a field oxide structure 220 overlying the floating gate by using the polysilicon layer 200.
  • the polysilicon layer 200 is processed to form a floating gate 210 and a field oxide structure 220.
  • the structure formed after the treatment in this step is as shown in Fig. 4b. Since the subsequent wet cleaning is performed by a plurality of steps of the wet process, resulting in the recess at the bottom corner of the subsequent tunnel oxide layer 220, or even the corner of the bottom of the floating gate 210, it is necessary to perform the following step S130.
  • Step S130 forming a protective sidewall 610 at a corner of the bottom of the floating gate 210.
  • the structure formed after the treatment in this step is as shown in Fig. 4c.
  • Step S140 forming a tunneling oxide layer on the field oxide structure 220 and the floating gate 210.
  • the tunnel oxide layer 300 is a silicon dioxide layer and can be formed by deposition.
  • the structure formed after the treatment in this step is as shown in Fig. 4d.
  • Step S150 forming a control gate 400 on the tunnel oxide layer 300.
  • the structure formed after the treatment in this step is as shown in Fig. 4e.
  • the protective sidewall 610 is formed at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 220, even after a plurality of wet etching, the bottom corner of the tunnel oxide layer 220 is Corrosion will also be prevented by the protective sidewall 610 from further corrosion.
  • the control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling.
  • the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.
  • the above step S120 may include the following sub-steps S121-S124.
  • 6a to 6c and 4b are schematic views of intermediate structures after processing in each step.
  • Sub-step S121 forming a mask layer 500 on the polysilicon layer 200.
  • the mask layer 500 may be a silicon nitride (SiN) layer.
  • the structure formed after the treatment in this step is as shown in Fig. 6a.
  • Sub-step S122 patterning the mask layer 500 to form a floating gate window 510 to expose a portion of polysilicon Floor.
  • the structure formed after the treatment in this step is as shown in Fig. 6b.
  • Sub-step S123 oxidative growth is performed in the floating gate window to form a field oxide structure. This step can form the tip of the floating gate while growing the oxygen structure of the field. The structure formed after the treatment in this step is as shown in Fig. 6c.
  • Sub-step S124 removing the mask layer and etching a polysilicon layer outside the field oxide structure coverage region to form a floating gate.
  • the structure formed after the treatment in this step is as shown in Fig. 4b.
  • step S130 may include the following sub-steps S131-S132. Description will be made below with reference to Figs. 4b, 7 and 4c.
  • Step S131 depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxide structure.
  • This intermediate structure is shown in Figure 4b.
  • the isolation layer 600 covers the field oxide structure 220, the sidewall of the floating gate 210, and the substrate structure 100 that does not cover the floating gate 210.
  • the isolation layer 500 can be made of a silicon nitride material. It can be understood that, by depositing the isolation layer, there will also be a portion of the isolation layer at the corners of the floating gate 210.
  • Step S132 removing a part of the isolation layer and leaving only the isolation layer located at the corner of the floating gate to form a protective sidewall.
  • the removed portion of the isolation layer includes a portion overlying the surface of the field oxide structure, a portion overlying the sidewall of the floating gate, and a portion overlying the substrate structure.
  • This step can be performed by dry etching. Self-aligned etching is used when etching a portion of the floating gate sidewall. After the processing in this step, the formed structure is as shown in Fig. 4c.
  • the protective sidewalls can be formed at the corners of the floating gate in other ways, and are not limited to the above manner.
  • the flash memory structure includes a substrate structure 100, a floating gate 210, a field oxide structure 220, a tunnel oxide layer 300, and a control gate 400 which are sequentially stacked.
  • the substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and has a gate oxide layer above the channel region, and the floating gate 210 is located on the gate oxide layer.
  • a floating gate 210 is formed on the substrate structure 100 and over the channel between the source and drain regions.
  • the floating gate 210 is a polysilicon material.
  • the floating gate 210 has a discharge tip 211.
  • Field oxide structure 220 overlies floating gate 210, and field oxide structure 220 is a silicon dioxide material.
  • a tunnel oxide layer 300 is formed on the floating gate 210 and the field oxide structure 220, and the tunnel oxide layer 300 is a silicon dioxide material.
  • a protective sidewall 610 is provided, and the protective sidewall 610 may be made of a material that attenuates electron tunneling, such as a silicon nitride material.
  • the tunnel oxide layer 300 covers the sidewalls of the floating gate 210 and the protective sidewall 610.
  • a control gate 400 is formed on the tunnel oxide layer 300, and the control gate 400 is a polysilicon material.
  • the height of the protective side wall 610 is 1/5 to 1/2 of the height of the floating gate side wall.
  • the flash memory structure of the above embodiment by forming the protective sidewall 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 300, even if subjected to multiple wet etching, the bottom corner of the tunnel oxide layer 220 The area is corroded and will also be protected from further corrosion by the protective side wall 610.
  • the control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling.
  • the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. The formed semiconductor device erase is more stable.

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Abstract

一种闪存存储结构及其制造方法。该方法包括：在衬底结构上淀积多晶硅层（S110）；利用所述多晶硅层形成浮栅和覆盖在浮栅上的场氧结构（S120）；在所述浮栅底部的边角处形成保护侧墙（S130）；在场氧结构及浮栅上形成隧穿氧化层（S140）；在所述隧穿氧化层上形成控制栅（S150）。

Description

闪存存储结构及其制造方法 技术领域
本发明涉及半导体存储技术领域，特别是涉及一种闪存存储结构及其制造方法。
背景技术
半导体存储器件的基本单位为可以表示0和1两种状态的半导体结构，一般地，都采用半导体器件常见的MOS结构。传统的闪存(FLASH存储)的基本结构大都是在MOS结构中加入浮栅存储或释放电荷以实现表示0和1两种状态。
传统的用作基本存储单元的MOS结构中，浮栅外缘为尖端结构，在需要擦除数据时，可通过在栅极施加高压驱使浮栅尖端放电，使电子从隧穿氧化层穿透到控制栅，释放浮栅中存储的电荷，改变基本存储单元的存储状态，达到擦除的目的。可以理解的是，隧穿氧化层越薄，电子越容易发生隧穿。
然而在该基本存储单元的制程中，形成浮栅后会进一步形成覆盖有隧穿氧化层的中间结构。此后该中间结构会经历多次湿法腐蚀工艺。由于湿法腐蚀的不稳定性，在隧穿氧化层的底部的边角处会相对其他地方腐蚀得更多，因此在后续形成控制栅的过程中，控制栅在该处形成尖角。电子很容易从控制栅隧穿进入浮栅(该过程称为反隧穿)，导致擦除不稳定。
发明内容
基于此，有必要提供一种闪存存储结构的制造方法，其可以消除浮栅底部边角处的过刻蚀，提高擦除的稳定性。
一种闪存存储结构的制造方法，包括：
在衬底结构上淀积多晶硅层；
利用所述多晶硅层形成浮栅和覆盖在浮栅上的场氧结构；
对所述浮栅底部的边角处形成保护侧墙；
在场氧结构及浮栅上形成隧穿氧化层；
在所述隧穿氧化层上形成控制栅。
在其中一个实施例中，所述对所述浮栅底部的边角处形成保护侧墙的步骤包括：
在形成浮栅和场氧结构后的中间结构上沉积隔离层；所述隔离层覆盖场氧结构、浮栅的侧墙以及未覆盖浮栅的衬底结构上；
去除部分隔离层并仅保留位于浮栅底部的边角处的保护侧墙。
一种闪存存储结构，包括：
衬底结构；
浮栅，形成在所述衬底结构上；
场氧结构，覆盖在所述浮栅上；
保护侧墙，位于所述浮栅底部的边角处；
隧穿氧化层，形成在所述浮栅和场氧结构上；
控制栅，形成在所述隧穿氧化层上。
上述实施例的闪存存储结构及其制造方法，通过在浮栅底部边角处形成保护侧墙，后续形成隧穿氧化层后，即使经历多次湿法腐蚀，隧穿氧化层的底部边角处被腐蚀，也会被保护侧墙阻止进一步腐蚀。控制栅不会形成尖角， 可以有效地防止电子反隧穿。进一步地，保护侧墙采用不易被电子隧穿的材料，也可以有效防止电子反隧穿。因此所形成的半导体器件擦除更加稳定。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为采用具有浮栅的基本结构形成的存储器的原理图；
图2a为图1中的基本存储单元的结构示意图；
图2b为图1中的基本存储单元在出现湿法刻蚀缺陷时的结构示意图；
图3为一实施例的闪存存储结构的制造方法流程图；
图4a～图4e为图3所示流程中各步骤处理后的中间结构示意图；
图5为形成浮栅的流程图；
图6a～图6c及图4b为图5所示流程中各步骤处理后的中间结构示意图；
图7为在中间结构上沉积隔离层后所形成的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术 领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1为采用具有浮栅的基本结构形成的存储器的原理图。如图2a所示，是这种基本存储单元的结构示意图。该基本存储单元10包括衬底结构15、设于衬底15上的多晶硅浮栅11、形成在浮栅11上的场氧结构12、覆盖在浮栅11和场氧结构12上的隧穿氧化层13、以及覆盖在隧穿氧化层13上的多晶硅控制栅14。其中，浮栅11具有尖端111。
在对该基本存储单元10进行擦除时，是在控制栅14上加高压，使浮栅11尖端放电。浮栅11中存储的电子从隧穿氧化层13穿透到控制栅14，改变基本存储单元10的存储状态，达到擦除的目的。
在该基本存储单元10的制程中，控制栅14在隧穿氧化层13的底部形成尖角141，如图2b所示。电子很容易从控制栅14隧穿进入浮栅11，导致擦除不稳定。
以下实施例的方法可以用于更好地制造闪存存储结构，且可以避免在隧穿氧化层的底部形成尖角。
图3为一实施例的闪存存储结构的制造方法流程图。该方法包括以下步骤S110～S150。图4a～图4e为各步骤处理后的中间结构示意图。
步骤S110：在衬底结构100上淀积多晶硅层200。衬底结构100包括衬底、在衬底上形成的源极区、漏极区和沟道区，且沟道区上方具有栅氧层，为简单起见，这些细节结构在图4a～4e中未明确示出，仅以整个衬底结构100来表示。本步骤是在完成衬底结构100之后的工序。本步骤处理后形成的结构如图4a所示。
步骤S120：利用所述多晶硅层200形成浮栅210和覆盖在浮栅上的场氧结构220。多晶硅层200经过处理，形成浮栅210和场氧结构220。本步骤处理后形成的结构如图4b所示。由于后续湿法清洗由经过很多步湿法工艺，导致后续的隧穿氧化层220底部边角处内凹、甚至浮栅210的底部的边角处内凹，因此需要执行以下步骤S130。
步骤S130：对所述浮栅210底部的边角处形成保护侧墙610。本步骤处理后形成的结构如图4c所示。
步骤S140：在场氧结构220及浮栅210上形成隧穿氧化层。隧穿氧化层300为二氧化硅层，可以采用淀积的方式形成。本步骤处理后形成的结构如图4d所示。
步骤S150：在所述隧穿氧化层300上形成控制栅400。本步骤处理后形成的结构如图4e所示。
上述实施例的方法，通过在浮栅210底部边角处形成保护侧墙610，在后续形成隧穿氧化层220后，即使经历多次湿法腐蚀，隧穿氧化层220的底部边角处被腐蚀，也会被保护侧墙610阻止进一步腐蚀。控制栅400不会形成尖角，可以有效地防止电子反隧穿。进一步地，保护侧墙610采用不易被电子隧穿的氮化硅材料，也可以有效防止电子反隧穿。因此所形成的半导体器件擦除更加稳定。
在一个实施例中，如图5所示，上述步骤S120可以包括以下子步骤S121～S124。图6a～图6c及图4b为各步骤处理后的中间结构示意图。
子步骤S121：在所述多晶硅层200上形成掩膜层500。所述掩膜层500可以为氮化硅(SiN)层。本步骤处理后形成的结构如图6a所示。
子步骤S122：图形化所述掩膜层500形成浮栅窗口510露出部分多晶硅 层。本步骤处理后形成的结构如图6b所示。
子步骤S123：在所述浮栅窗口内进行氧化生长形成场氧结构。本步骤在生长场氧结构的同时，可以形成浮栅的尖端。本步骤处理后形成的结构如图6c所示。
子步骤S124：去除所述掩膜层并刻蚀场氧结构覆盖区域之外的多晶硅层以形成浮栅。本步骤处理后形成的结构如图4b所示。
在一个实施例中，上述步骤S130可以包括以下子步骤S131～S132。以下结合图4b、图7和图4c进行说明。
步骤S131：在形成浮栅和场氧结构后的中间结构上沉积隔离层。该中间结构如图4b所示。经过本步骤处理后，如图7所示，该隔离层600覆盖场氧结构220、浮栅210的侧墙以及未覆盖浮栅210的衬底结构100上。该隔离层500可以采用氮化硅材料。可以理解，经过沉积隔离层，浮栅210的边角处也会有部分隔离层。
步骤S132：去除部分隔离层并仅保留位于浮栅边角处的隔离层形成保护侧墙。去除的部分隔离层包括覆盖在场氧结构表面的部分、覆盖在浮栅侧墙的部分以及覆盖在衬底结构上的部分。本步骤可以采用干法刻蚀。在刻蚀位于浮栅侧墙的部分时，采用自对准刻蚀。经过本步骤处理后，形成的结构如图4c所示。
可以理解，还可以采用其他方式在所述浮栅边角处形成保护侧墙，不限于上述方式。
基于相同发明构思，提供一种闪存存储结构。如图4e所示，该闪存存储结构包括依次层叠的衬底结构100、浮栅210、场氧结构220、隧穿氧化层300以及控制栅400。
衬底结构100包括衬底、在衬底上形成的源极区、漏极区和沟道区，且沟道区上方具有栅氧层，浮栅210位于栅氧层上。为简单起见，这些细节结构在图4e中未明确示出，仅以整个衬底结构100来表示。浮栅210形成在所述衬底结构100上，且位于所述源极区和漏极区之间的沟道之上。浮栅210为多晶硅材料。所述浮栅210具有放电尖端211。场氧结构220覆盖在所述浮栅210上，场氧结构220为二氧化硅材料。隧穿氧化层300形成在所述浮栅210和场氧结构220上，隧穿氧化层300为二氧化硅材料。其中，浮栅210底部的边角处的设有保护侧墙610，所述保护侧墙610可以采用减弱电子隧穿的材料，例如氮化硅材料。隧穿氧化层300覆盖在浮栅210的侧墙以及保护侧墙610上。控制栅400形成在所述隧穿氧化层300上，控制栅400为多晶硅材料。保护侧墙610的高度为浮栅侧墙高度的1/5～1/2。
上述实施例的闪存存储结构，通过在浮栅210底部边角处形成保护侧墙610，在后续形成隧穿氧化层300后，即使经历多次湿法腐蚀，隧穿氧化层220的底部边角处被腐蚀，也会被保护侧墙610阻止进一步腐蚀。控制栅400不会形成尖角，可以有效地防止电子反隧穿。进一步地，保护侧墙610采用不易被电子隧穿的氮化硅材料，也可以有效防止电子反隧穿。所形成的半导体器件擦除更加稳定。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种闪存存储结构的制造方法，包括：
    在衬底结构上淀积多晶硅层；
    利用所述多晶硅层形成浮栅和覆盖在浮栅上的场氧结构；
    对所述浮栅底部的边角处形成保护侧墙；
    在场氧结构及浮栅上形成隧穿氧化层；
    在所述隧穿氧化层上形成控制栅。
  2. 根据权利要求1所述的方法，其中，所述对所述浮栅底部的边角处形成保护侧墙的步骤包括：
    在形成浮栅和场氧结构后的中间结构上沉积隔离层；所述隔离层覆盖场氧结构、浮栅的侧墙以及未覆盖浮栅的衬底结构上；
    去除部分隔离层并仅保留位于浮栅底部的边角处的保护侧墙。
  3. 根据权利要求2所述的方法，其中，去除部分所述隔离层时采用干法刻蚀和自对准。
  4. 根据权利要求2所述的方法，其中，所述隔离层采用氮化硅材料。
  5. 根据权利要求1所述的方法，其中，所述利用所述多晶硅层形成浮栅和覆盖在浮栅上的场氧结构的步骤包括：
    在所述多晶硅层上形成掩膜层；
    图形化所述掩膜层形成浮栅窗口露出部分多晶硅层；
    在所述浮栅窗口内进行氧化生长形成场氧结构；
    去除所述掩膜层并刻蚀场氧结构覆盖区域之外的多晶硅层以形成浮栅。
  6. 根据权利要求5所述的方法，其中，去除所述掩膜层并干法蚀刻多晶 硅层以形成浮栅。
  7. 根据权利要求5所述的方法，其中，所述掩膜层为氮化硅层。
  8. 根据权利要求1所述的方法，其中，在所述场氧结构及浮栅上形成隧穿氧化层的步骤中，采用淀积法形成所述隧穿氧化层。
  9. 根据权利要求1所述的方法，其中，所述隧穿氧化层为二氧化硅层。
  10. 根据权利要求1所述的方法，其中，在所述在衬底结构上淀积多晶硅层的步骤之前，形成衬底结构，包括：
    形成衬底；
    在衬底上形成源极区、漏极区和沟道区；
    在沟道区上方形成栅氧层。
  11. 一种闪存存储结构，包括：
    衬底结构；
    浮栅，形成在所述衬底结构上；
    场氧结构，覆盖在所述浮栅上；
    保护侧墙，位于所述浮栅底部的边角处；
    隧穿氧化层，形成在所述浮栅和场氧结构上；
    控制栅，形成在所述隧穿氧化层上。
  12. 根据权利要求11所述的闪存存储结构，其中，所述保护侧墙为减弱电子隧穿的材料。
  13. 根据权利要求11所述的闪存存储结构，其中，所述保护侧墙为氮化硅材料。
  14. 根据权利要求11所述的闪存存储结构，其中，所述保护侧墙覆盖在浮栅侧墙上的部分的高度为浮栅侧墙高度的1/5～1/2。
  15. 根据权利要求11所述的闪存存储结构，其中，所述衬底结构包括衬底和形成在衬底上的源极区和漏极区，所述浮栅位于源极区和漏极区的沟道之上。
  16. 根据权利要求11所述的闪存存储结构，其中，所述隧穿氧化层为二氧化硅材料。
  17. 根据权利要求11所述的闪存存储结构，其中，所述控制栅为多晶硅材料。
PCT/CN2017/110888 2016-12-29 2017-11-14 闪存存储结构及其制造方法 Ceased WO2018121109A1 (zh)

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