WO2018110556A1 - 炭化珪素半導体装置およびその製造方法 - Google Patents

炭化珪素半導体装置およびその製造方法 Download PDF

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Publication number
WO2018110556A1
WO2018110556A1 PCT/JP2017/044580 JP2017044580W WO2018110556A1 WO 2018110556 A1 WO2018110556 A1 WO 2018110556A1 JP 2017044580 W JP2017044580 W JP 2017044580W WO 2018110556 A1 WO2018110556 A1 WO 2018110556A1
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Prior art keywords
layer
guard ring
conductivity type
type
electrode
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English (en)
French (fr)
Japanese (ja)
Inventor
竹内　有一
龍太 鈴木
永岡　達司
佐智子 青井
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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Priority to CN201780075779.5A priority Critical patent/CN110050349B/zh
Publication of WO2018110556A1 publication Critical patent/WO2018110556A1/ja
Priority to US16/427,413 priority patent/US11177353B2/en
Anticipated expiration legal-status Critical
Priority to US17/477,168 priority patent/US11769801B2/en
Ceased legal-status Critical Current

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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
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Definitions

  • the present disclosure relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a deep layer and a guard ring layer and a method for manufacturing the same.
  • SiC silicon carbide
  • SiC has been attracting attention as a power device material that can provide high electric field breakdown strength.
  • MOSFETs and Schottky diodes have been proposed as SiC power devices (see, for example, Patent Document 1).
  • the SiC power device includes a cell part in which a power element such as a MOSFET or a Schottky diode is formed, and a guard ring part surrounding the cell part. Between the cell part and the guard ring part, a connecting part for connecting them is provided, and an electrode pad, for example, is provided on the surface side of the semiconductor substrate in the connecting part. Then, in the outer peripheral region including the guard ring portion, by forming a concave portion in which the surface of the semiconductor substrate is recessed, in the thickness direction of the substrate, the cell portion and the connecting portion become a mesa portion protruding in an island shape. .
  • n-type current spreading layer when such an n-type current spreading layer is formed, since the n-type current spreading layer has a relatively high concentration, an electric field easily enters between the p-type guard rings, resulting in a decrease in breakdown voltage due to electric field concentration. . In order to cope with this, it is conceivable to narrow the interval between the p-type guard rings to suppress the entry of the electric field. However, due to the resolution of photolithography and the like, there is a limit to reducing the interval between the p-type guard rings, and it is difficult to reduce the interval to, for example, 0.5 ⁇ m or less. For this reason, there is a concern that it will not be possible to cope with further miniaturization in the future.
  • An object of the present disclosure is to provide a SiC semiconductor device having a structure capable of suppressing a decrease in breakdown voltage due to electric field concentration and a manufacturing method thereof when forming a current spreading layer.
  • An SiC semiconductor device includes a first or second conductivity type substrate on a cell portion and an outer peripheral portion, and a first conductivity having a lower impurity concentration than that of the substrate. And a first conductivity type current spreading layer formed on the drift layer and having a higher impurity concentration than the drift layer.
  • a second conductive type layer formed in a stripe shape on the current spreading layer, a first electrode electrically connected to the second conductive type layer, and electrically connected to the back side of the substrate
  • a vertical semiconductor element that has a second electrode and allows a current to flow between the first electrode and the second electrode.
  • the guard ring portion is provided with a line-shaped second conductivity type guard ring that is formed from the surface of the current spreading layer and has a plurality of frame shapes surrounding the cell portion.
  • a recess in which the current spreading layer is recessed from the cell portion in the guard ring portion, an island-like mesa portion is formed in which the cell portion protrudes from the guard ring portion in the thickness direction of the substrate.
  • a second conductivity type electric field relaxation layer having a lower impurity concentration than the guard ring is provided on the surface layer portion of the drift layer from the boundary position between the portion and the concave portion toward the outer peripheral side of the mesa portion.
  • the electric field relaxation layer for electric field relaxation is formed on the surface layer portion of the drift layer from the boundary position between the mesa portion and the concave portion toward the outer peripheral side of the mesa portion. For this reason, the electric field can be prevented from entering between the guard rings. Thereby, the electric field concentration is relaxed, the breakdown of the interlayer insulating film due to the electric field concentration is suppressed, and it is possible to suppress the breakdown voltage reduction. Therefore, a SiC semiconductor device capable of obtaining a desired breakdown voltage can be obtained.
  • the carrier concentration is higher in the current distribution layer than the current distribution layer and the guard ring in the current distribution layer from the boundary position between the mesa portion and the recess toward the outer periphery side of the mesa portion.
  • a lowered electric field relaxation layer of the first conductivity type or the second conductivity type is provided.
  • the electric field relaxation layer is formed in the current spreading layer in the guard ring portion. Even if such an electric field relaxation layer is formed, the electric field can be prevented from entering between the guard rings. Therefore, the same effect as that of the SiC semiconductor device according to one aspect of the present disclosure described above can be obtained.
  • FIG. 2 is a cross-sectional view taken along the line II-II in FIG. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device concerning 1st Embodiment.
  • FIG. 3B is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3A.
  • FIG. 3B is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3B.
  • FIG. 3D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3C.
  • FIG. 3D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3D.
  • FIG. 3D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3F.
  • FIG. 3D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3G. It is the figure which showed typically the upper surface layout of the SiC semiconductor device concerning 2nd Embodiment. It is sectional drawing of the SiC semiconductor device concerning 3rd Embodiment. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device concerning 3rd Embodiment.
  • FIG. 6B is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 6A.
  • FIG. 6D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 6B.
  • FIG. 6D is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 6C. It is sectional drawing of the SiC semiconductor device demonstrated in the modification of 3rd Embodiment.
  • the SiC semiconductor device shown in FIG. 1 is configured to have a cell part in which a MOSFET having a trench gate structure is formed and an outer peripheral part surrounding the cell part.
  • the outer peripheral portion is configured to include a guard ring portion and a connecting portion disposed inside the guard ring portion, that is, between the cell portion and the guard ring portion.
  • FIG. 1 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing.
  • SiC semiconductor device is formed using the n + -type substrate 1 made of SiC, made of SiC on the main surface of the n + -type substrate 1 n - -type drift layer 2 and the n-type current spreading
  • the layer 2a, the p-type base region 3, and the n + -type source region 4 are epitaxially grown in this order.
  • the n + type substrate 1 has an n-type impurity concentration of 1.0 ⁇ 10 19 / cm 3 and a surface of a (0001) Si surface.
  • the n ⁇ type drift layer 2 has an n type impurity concentration of 0.5 to 2.0 ⁇ 10 16 / cm 3 , for example.
  • the n-type current distribution layer 2a has an n-type impurity concentration higher than that of the n ⁇ -type drift layer 2, that is, a low resistance, and serves to reduce the JFET resistance by distributing the current over a wider range. Fulfill.
  • the n-type current spreading layer 2a is, for example, 8 ⁇ 10 16 / cm 3 and has a thickness of 0.5 ⁇ m.
  • the p-type base region 3 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, about 2.0 ⁇ 10 17 / cm 3 and a thickness of 300 nm.
  • the n + -type source region 4 has a higher impurity concentration than the n ⁇ -type drift layer 2, and the n-type impurity concentration in the surface layer portion is, for example, 2.5 ⁇ 10 18 to 1.0 ⁇ 10 19 / cm 3 and has a thickness. It is composed of about 0.5 ⁇ m.
  • the p type base region 3 and the n + type source region 4 are left on the surface side of the n + type substrate 1, and in the guard ring portion, the n + type source region 4 and the p type base region 3 are stored.
  • a recess 20 is formed so as to penetrate and reach n-type current spreading layer 2a. With this structure, a mesa structure is configured.
  • a p-type deep layer 5 is formed so as to penetrate the n + -type source region 4 and the p-type base region 3 and reach the n-type current spreading layer 2a.
  • the p-type deep layer 5 has a higher p-type impurity concentration than the p-type base region 3.
  • the p-type deep layer 5 is provided in stripe-shaped trenches 5a that are arranged in the n-type current distribution layer 2a at equal intervals and spaced apart from each other, and are formed by p-type epitaxial growth. It is comprised by the epitaxial film.
  • the trench 5a corresponds to a deep trench, for example, having a width of 1 ⁇ m or less and an aspect ratio of 2 or more.
  • each p-type deep layer 5 has a p-type impurity concentration of, for example, 1.0 ⁇ 10 17 to 1.0 ⁇ 10 19 / cm 3 , a width of 0.7 ⁇ m, and a depth of about 2.0 ⁇ m.
  • Each p-type deep layer 5 is located at the deepest bottom portion at the same position as the boundary position between the n-type current distribution layer 2a and the n ⁇ -type drift layer 2 or closer to the p-type base region 3 side. . That is, the p-type deep layer 5 and the n-type current distribution layer 2 a are formed to the same depth, or the n-type current distribution layer 2 a is formed deeper than the p-type deep layer 5. As shown in FIG.
  • the p-type deep layer 5 is formed from one end of the cell portion to the other end.
  • the p-type deep layer 5 extends in the same direction as a trench gate structure described later as a longitudinal direction, and further extends to the outside of the cell portion from both ends of the trench gate structure. linked.
  • the extending direction of the p-type deep layer 5 is arbitrary, but it extends in the ⁇ 11-20> direction, and both opposing wall surfaces constituting the long side of the trench 5a are the same (1-100) surface As a result, the growth during the buried epitaxy becomes equal on both wall surfaces. For this reason, it is possible to obtain a uniform film quality and to obtain an effect of suppressing embedding defects.
  • a gate trench 6 having, for example, a width of 0.8 ⁇ m and a depth of 1.0 ⁇ m is formed so as to penetrate the p-type base region 3 and the n + -type source region 4 and reach the n ⁇ -type drift layer 2. Yes.
  • the p-type base region 3 and the n + -type source region 4 described above are arranged so as to be in contact with the side surface of the gate trench 6.
  • the gate trench 6 is formed in a line-shaped layout in which the horizontal direction in FIG. 2 is the width direction, the vertical direction is the longitudinal direction, and the vertical direction is the depth direction. Also, as shown in FIG. 1, the gate trenches 6 are arranged so that a plurality of gate trenches 6 are sandwiched between the p-type deep layers 5 and are arranged in parallel at equal intervals to form a stripe shape. .
  • a portion of the p-type base region 3 located on the side surface of the gate trench 6 is used as a channel region that connects the n + -type source region 4 and the n ⁇ -type drift layer 2 when the vertical MOSFET is operated.
  • a gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region.
  • a gate electrode 8 made of doped Poly-Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is completely filled with the gate insulating film 7 and the gate electrode 8.
  • the gate disposed on the source electrode 9 corresponding to the first electrode and the electrode pad portion via the interlayer insulating film 10.
  • a pad 31 is formed.
  • the source electrode 9 and the gate pad 31 are made of a plurality of metals, such as Ni / Al. Of the plurality of metals, at least the n-type SiC, specifically, the n + -type source region 4 and the portion in contact with the gate electrode 8 in the case of n-type doping are made of a metal capable of ohmic contact with the n-type SiC. Yes.
  • At least a portion of the plurality of metals that contacts the p-type SiC, specifically, the p-type deep layer 5, is made of a metal that can make ohmic contact with the p-type SiC.
  • the source electrode 9 and the gate pad 31 are electrically insulated by being formed on the interlayer insulating film 10.
  • the source electrode 9 is in electrical contact with the n + -type source region 4 and the p-type deep layer 5 through the contact hole formed in the interlayer insulating film 10, and the gate pad 31 is in electrical contact with the gate electrode 8. It has been made.
  • the drain electrode 11 corresponding to the second electrode electrically connected to the n + -type substrate 1 is formed on the back side of the n + -type substrate 1 .
  • an n-channel inversion type MOSFET having a trench gate structure is formed on the back side of the n + -type substrate 1 .
  • a cell portion is configured by arranging a plurality of such MOSFETs.
  • the recess 20 is formed so as to penetrate the n + -type source region 4 and the p-type base region 3 and reach the n-type current spreading layer 2a. Therefore, the n + -type source region 4 and the p-type base region 3 are removed at a position away from the cell portion, and the n-type current distribution layer 2a is exposed.
  • cell portions and connecting portions located inside the recesses 20 are mesa portions protruding in an island shape.
  • a plurality of p-type guard rings 21 are provided in the surface layer portion of the n-type current spreading layer 2a located below the recess 20, although seven are shown in FIG. 1 so as to surround the cell portion. It has been.
  • the p-type guard ring 21 has a quadrangular shape with rounded corners, but may be configured in other frame shapes such as a circular shape.
  • the p-type guard ring 21 is disposed in a trench 21a formed in the n-type current distribution layer 2a, and is constituted by a p-type epitaxial film formed by epitaxial growth.
  • the trench 21a corresponds to a guard ring trench, and has a width of 1 ⁇ m or less and an aspect ratio of 2 or more, for example.
  • Each part constituting the p-type guard ring 21 has the same configuration as the p-type deep layer 5 described above.
  • the p-type guard ring 21 is different from the linearly formed p-type deep layer 5 in that the upper surface shape is a frame-like line shape surrounding the cell portion and the connecting portion, but the other is the same. is there. That is, the p-type guard ring 21 has the same width and the same thickness as the p-type deep layer 5, that is, the same depth.
  • the intervals between the p-type guard rings 21 may be equal intervals, but the electric field concentration is reduced on the inner peripheral side, that is, the cell part side, so that the equipotential lines are directed toward the outer peripheral side.
  • the interval between the p-type guard rings 21 is narrower toward the outer peripheral side and narrower at the cell side.
  • an EQR structure is provided on the outer periphery of the p-type guard ring 21 as necessary, thereby forming a guard ring portion having an outer peripheral pressure resistant structure surrounding the cell portion.
  • a plurality of p-type connecting layers 30 are formed in the surface layer portion of the n ⁇ -type drift layer 2 in the connecting portion, with a portion extending from the cell portion to the guard ring portion as a connecting portion.
  • a connecting portion is formed so as to surround the cell portion, and further, a rectangular p having four rounded corners so as to surround the outside of the connecting portion.
  • a plurality of mold guard rings 21 are formed.
  • a plurality of p-type connecting layers 30 are arranged in parallel with the p-type deep layer 5 formed in the cell portion. In the present embodiment, the p-type connecting layer 30 is equally spaced from the adjacent p-type deep layers 5. Has been placed.
  • the p-type connecting layer 30 extends from the p-type deep layer 5, and the p-type guard ring extends from the tip of the p-type connecting layer 30.
  • the distance to 21 is made shorter.
  • Each p-type connection layer 30 is disposed in a trench 30a that reaches the n-type drift layer 2 through the n + -type source region 4 and the p-type base region 3, and is constituted by a p-type epitaxial film formed by epitaxial growth. .
  • the p-type tie layer 30 is formed to be connected to the tip of the p-type deep layer 5.
  • the trench 30a corresponds to a connecting trench, and has a width of 1 ⁇ m or less and an aspect ratio of 2 or more, for example. Since the p-type connecting layer 30 is in contact with the p-type base region 3, it is fixed at the source potential.
  • Each part constituting the p-type tie layer 30 has the same configuration as the p-type deep layer 5 and the p-type guard ring 21 described above, and the upper surface shape of the p-type tie layer 30 is linear.
  • the p-type guard ring 21 is different from the p-type guard ring 21 formed in a frame shape, but the others are the same. That is, the p-type connecting layer 30 has the same width, the same thickness, that is, the same depth as the p-type deep layer 5 and the p-type guard ring 21. Further, in the present embodiment, the interval between the p-type connecting layers 30 is equal to the interval between the p-type deep layers 5 in the cell portion, but may be different.
  • the upper surface of the p-type connecting layer 30 is semicircular at both ends in the longitudinal direction of each p-type connecting layer 30, that is, at both ends of the trench 30a.
  • the shape of the upper surface of both ends of the trench 30a may be a square shape.
  • an n-type layer may be formed by forming an n-type layer in the corner first. For this reason, it becomes possible to eliminate the part in which an n-type layer is formed by making the upper surface shape of the both ends of the p-type connection layer 30 into a semicircle.
  • an interlayer insulating film 10 is formed on the surface of the n + type source region 4 also at the connecting portion.
  • the gate pad 31 described above is formed on the interlayer insulating film 10 at the connecting portion.
  • the connecting portion is provided between the cell portion and the guard ring portion, and the connecting portion is constituted by a plurality of p-type connecting layers 30 embedded in the narrow trench 30a. If the trench 30a is formed with a wide width, the trench 30a cannot be embedded, so that the thickness of the p-type tie layer 30 is reduced, or when the p-type tie layer 30 is etched back and planarized. In some cases, the p-type tie layer 30 may be partially lost. However, since the trench 30a is configured with a narrow width as described above, the trench 30a is accurately embedded, and the thickness of the p-type connecting layer 30 is reduced, or the p-type connecting layer 30 is partially lost. It becomes possible to suppress that.
  • equipotential lines may rise between the p-type connecting layers 30.
  • a predetermined interval for example, equal to or less than that of the p-type deep layer 5
  • the electric field relaxation layer 40 is formed in the surface layer portion of the n ⁇ type drift layer 2 so as to reach the guard ring portion from the connecting portion.
  • the electric field relaxation layer 40 may be formed in the outer peripheral direction of the mesa portion from the position near the cell portion or the connecting portion of the guard ring portion, that is, the boundary position between the mesa portion and the recessed portion 20. Then, it is also formed at a position near the guard ring portion in the connecting portion. More specifically, the electric field relaxation layer 40 is formed in the entire region from a position near the cell portion or the connecting portion of the guard ring portion to a position near the guard ring portion of the connecting portion, and at least a band-like shape surrounding the mesa portion.
  • the p-type impurity concentration of the electric field relaxation layer 40 is, for example, 0.5 ⁇ 10 17 / cm 3 , which is lower than the p-type deep layer 5 and the p-type guard ring 21.
  • the thickness of the electric field relaxation layer 40 is arbitrary, for example, about 0.5 ⁇ m.
  • the interval between the p-type guard rings 21 is reduced.
  • the JFET resistance can be reduced.
  • An electric field easily enters between the rings 21. For this reason, it is desired to suppress the entry of the electric field between the p-type guard rings 21 by narrowing the interval between the p-type guard rings 21, but when forming the trench 21a in which the p-type guard ring 21 is disposed.
  • the electric field relaxation layer 40 by forming the electric field relaxation layer 40, the electric field can be prevented from entering between the p-type guard rings 21.
  • the formation range of the electric field relaxation layer 40 in the guard ring portion is basically determined based on the arrangement interval of the p-type guard ring 21 and the respective impurity concentrations of the p-type guard ring 21 and the n-type current spreading layer 2a. That is, the p-type guard ring 21 is formed so that the electric field concentration is relaxed on the cell side and the equipotential lines are directed toward the outer peripheral side.
  • the p-type guard ring 21 and the p-type guard ring 21 and the n-type current distribution layer are formed. The entry of the electric field varies depending on the impurity concentration of 2a.
  • the electric field relaxation layer 40 includes a position that is assumed to reach the interlayer insulating film 10 formed thereon when an electric field enters between the p-type guard rings 21. Thus, the electric field relaxation layer 40 is formed.
  • the SiC semiconductor device concerning this embodiment is comprised by the above structures.
  • the channel region is formed in the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. To do.
  • a current flows between the source electrode 9 and the drain electrode 11 via the n + -type source region 4 and the n ⁇ -type drift layer 2.
  • the p-type deep layer 5 formed to a position deeper than the trench gate structure prevents the electric field from entering the bottom of the gate trench, The electric field concentration is relaxed. Thereby, destruction of the gate insulating film 7 is prevented.
  • the rising of the equipotential line is suppressed, and is directed toward the guard ring portion.
  • the p-type guard ring 21 terminates the equipotential lines while spreading toward the outer peripheral direction, and a desired breakdown voltage can be obtained also in the guard ring portion.
  • the electric field relaxation layer 40 is provided at least on the connecting portion side in the guard ring portion, the entry of the electric field between the p-type guard rings 21 is suppressed. Thereby, the electric field concentration is relaxed, the breakdown of the interlayer insulating film 10 due to the electric field concentration is suppressed, and it is possible to suppress the breakdown voltage reduction. Therefore, a SiC semiconductor device capable of obtaining a desired breakdown voltage can be obtained.
  • n + type substrate 1 is prepared as a semiconductor substrate. Then, after n - type drift layer 2 made of SiC is epitaxially grown on the main surface of n + -type substrate 1, p-type impurities are ionized into the surface layer portion of n ⁇ -type drift layer 2 using a mask (not shown).
  • the electric field relaxation layer 40 is formed by implanting and performing activation annealing.
  • the electric field relaxation layer 40 may be formed at least near the planned formation position of the joint portion of the planned formation positions of the guard ring portion, but here it is formed so as to enter the planned formation position of the joint portion. Like to do.
  • the n-type current distribution layer 2 a, the p-type base region 3, and the n + -type source region 4 are epitaxially grown in order on the n ⁇ -type drift layer 2 and the electric field relaxation layer 40.
  • a mask (not shown) is arranged on the surface of the n + -type source region 4, and regions where the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30 are to be formed are opened. Then, by performing anisotropic etching such as RIE (Reactive Ion Etching) using the mask, the trenches 5a, 21a, and 30a are formed.
  • anisotropic etching such as RIE (Reactive Ion Etching)
  • the electric field relaxation layer 40 is added to the cell ring and the connection portion near the formation position of the guard ring portion, and the guard ring portion of the connection portion formation position. It is also formed near the planned position. For this reason, even if the formation positions of the trenches 5a, 21a, and 30a are shifted due to the mask shift, the electric field relaxation layer 40 is accurately disposed at least at a position where the electric field relaxation layer 40 is to be formed in the guard ring portion. You can make it. Moreover, since the electric field relaxation layer 40 can be formed in a strip-like frame shape, it can be easily formed without the need for fine processing.
  • Step shown in FIG. 3D After removing the mask, a p-type layer is formed, and then etched back so that a portion of the p-type layer formed above the surface of the n + -type source region 4 is removed, and the p-type deep layer 5, A p-type guard ring 21 and a p-type tie layer 30 are formed.
  • the p-type layer is buried in the trenches 5a, 21a, and 30a by buried epi, but since the trenches 5a, 21a, and 30a are formed with the same width, the p-type layer is formed on the surface of the p-type layer. It is possible to suppress occurrence of shape abnormality and unevenness. Therefore, the p-type layer can be surely embedded in each of the trenches 5a, 21a and 30a, and the surface of the p-type layer has a flat shape with few irregularities.
  • the surface of the p-type layer has a flat shape with few irregularities, so that the surfaces of the p-type deep layer 5, the p-type guard ring 21, and the p-type tie layer 30 are flat. . Therefore, a desired gate shape can be obtained when various processes for forming the trench gate structure are performed thereafter. Further, since the p-type layer is securely embedded in each of the trenches 5a, 21a, and 30a, there is no problem that the thickness of the p-type connecting layer 30 is reduced.
  • Step shown in FIG. 3E After forming a mask (not shown) on the n + -type source region 4 and the like, a region where the gate trench 6 is to be formed in the mask is opened. Then, the gate trench 6 is formed by performing anisotropic etching such as RIE using a mask.
  • a mask (not shown) is formed again, and a region where the recess 20 is to be formed in the mask is opened.
  • the recessed part 20 is formed by performing anisotropic etching, such as RIE, using a mask.
  • anisotropic etching such as RIE
  • the n-type current distribution layer 2a is exposed through the n + -type source region 4 and the p-type base region 3, and a plurality of n-type current distribution layers 2a are exposed from the surface of the n-type current distribution layer 2a.
  • the p-type guard ring 21 is arranged.
  • the gate trench 6 and the recessed part 20 were formed as a separate process using a separate mask here, it can also be formed simultaneously using the same mask.
  • the gate insulating film 7 is formed by, for example, thermal oxidation, and the gate insulating film 7 covers the inner wall surface of the gate trench 6 and the surface of the n + -type source region 4. Then, after depositing Poly-Si doped with p-type impurities or n-type impurities, this is etched back to leave the Poly-Si at least in the gate trench 6 to form the gate electrode 8.
  • An interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, a portion of the mask located between the gate electrodes 8, that is, a portion corresponding to the p-type deep layer 5 and its vicinity are opened. Thereafter, the interlayer insulating film 10 is patterned using a mask to form a contact hole exposing the p-type deep layer 5 and the n + -type source region 4.
  • Step shown in FIG. 3H On the surface of the interlayer insulating film 10, for example, an electrode material composed of a laminated structure of a plurality of metals is formed. Then, the source electrode 9 and the gate pad 31 are formed by patterning the electrode material. Note that a gate lead-out portion connected to the gate electrode 8 of each cell is provided in a cross section different from that of FIG. A contact hole is opened in the interlayer insulating film 10 at the lead-out portion, so that the gate pad 31 and the gate electrode 8 are electrically connected.
  • the SiC semiconductor device according to the present embodiment is completed by performing steps such as forming the drain electrode 11 on the back surface side of the n + type substrate 1.
  • the electric field relaxation layer 40 for electric field relaxation is formed in the surface layer portion of the n ⁇ type drift layer 2 so as to reach the guard ring portion from the connecting portion. For this reason, entry of an electric field between the p-type guard rings 21 can be suppressed. Thereby, the electric field concentration is relaxed, the breakdown of the interlayer insulating film 10 due to the electric field concentration is suppressed, and it is possible to suppress the breakdown voltage reduction. Therefore, a SiC semiconductor device capable of obtaining a desired breakdown voltage can be obtained.
  • the electric field relaxation layer 40 has a plurality of lines. More specifically, the electric field relaxation layer 40 is extended in the normal direction with respect to each side at equal intervals at a position corresponding to each side of the quadrangular p-type guard ring 21 with four rounded corners. In the positions corresponding to the four corners, the p-type guard ring 21 extends in the radial direction from the center. That is, the electric field relaxation layer 40 is disposed orthogonally to the p-type guard ring 21.
  • the formation area of the electric field relaxation layer 40 is smaller than that in the first embodiment, the electric field can be effectively relaxed with a minimum p-type impurity dose, and leakage during application of a high voltage due to ion implantation defects can be prevented. It can be minimized.
  • a third embodiment will be described.
  • an impurity layer serving as a substitute for the electric field relaxation layer 40 described in the first and second embodiments is provided, and the others are the same as those in the first and second embodiments. Only parts different from the first and second embodiments will be described.
  • an electric field relaxation layer 50 is formed in the n-type current distribution layer 2a in the guard ring portion.
  • the electric field relaxation layer 50 is formed over the entire area of the guard ring portion. More specifically, the electric field relaxation layer 50 is formed in a frame shape at the guard ring portion.
  • the electric field relaxation layer 50 is configured by an n-type layer whose carrier concentration is lower than that of the n-type current distribution layer 2 a or a p-type layer whose carrier concentration is lower than that of the p-type guard ring 21. That is, the absolute value of the difference between the donor concentration Nd and the acceptor concentration Na in the electric field relaxation layer 50 is made lower than the carrier concentration of the n-type current distribution layer 2a or the p-type guard ring 21, for example,
  • the thickness of the electric field relaxation layer 50 is arbitrary, for example, about 0.5 ⁇ m.
  • the electric field relaxation layer 50 is formed within the thickness of the p-type guard ring 21, that is, from the surface of the p-type guard ring 21 on the interlayer insulating film 10 side to the bottom surface on the n ⁇ -type drift layer 2 side. It is formed between.
  • the formation depth of the electric field relaxation layer 50 is such that the upper surface side of the electric field relaxation layer 50 on the interlayer insulating film 10 side is deeper than the surface of the p-type guard ring 21 and shallower than the bottom surface. Just do it. That is, the lower surface side that is the n ⁇ -type drift layer 2 side of the electric field relaxation layer 50 may be deeper than the bottom surface of the p-type guard ring 21.
  • the electric field relaxation layer 50 is formed in the n-type current distribution layer 2a in the guard ring portion. Even if such an electric field relaxation layer 50 is formed, the electric field can be prevented from entering between the p-type guard rings 21. Therefore, the same effects as those of the first and second embodiments can be obtained.
  • the manufacturing method of the SiC semiconductor device of the present embodiment is substantially the same as the manufacturing method of the SiC semiconductor device shown in FIGS. 3A to 3H described in the first embodiment, and therefore, different portions will be mainly described.
  • an n ⁇ type drift layer 2 made of SiC, an n type current distribution layer 2a, a p type base region 3 and an n + type source region 4 are epitaxially grown on the main surface of the n + type substrate 1 in this order.
  • Step shown in FIG. 6B Next, by performing the same process as shown in FIGS. 3C and 3D, trenches 5a, 21a, 30a are formed, and p-type deep layer 5, p-type guard ring 21 is formed in trenches 5a, 21a, 30a. And the p-type connecting layer 30 is formed.
  • Step shown in FIG. 6C A mask (not shown) is formed, and a region where the recess 20 is to be formed in the mask is opened. And the recessed part 20 is formed by performing anisotropic etching, such as RIE, using a mask. Thereby, at the position where the recess 20 is formed, the n-type current distribution layer 2a is exposed through the n + -type source region 4 and the p-type base region 3, and a plurality of layers are formed on the surface layer portion of the n-type current distribution layer 2a. A structure in which two p-type guard rings 21 are arranged is configured.
  • the n-type impurity is ion-implanted using the mask used for forming the recess 20 as it is, and then activation annealing is performed to form the electric field relaxation layer 50 in the recess 20.
  • the absolute value of the difference between the donor concentration Nd and the acceptor concentration Na of the electric field relaxation layer 50 is
  • the step of forming the gate trench 6 in the step shown in FIG. 3D is performed.
  • the electric field relaxation layer 50 is formed only at a position near the cell portion or the joint portion of the guard ring portion. You may do it. Furthermore, the electric field relaxation layer 50 may be formed up to a position near the guard ring portion in the connecting portion.
  • the arrangement range of the p-type guard ring 21 and the p-type guard ring are determined for the ruled line range of the electric field relaxation layer 50.
  • 21 and the n-type current distribution layer 2a are determined based on the respective impurity concentrations.
  • the p-type guard ring 21 is formed such that the electric field concentration is reduced on the cell side and the equipotential lines are directed toward the outer peripheral side.
  • the arrangement interval, the p-type guard ring 21 and the n-type guard ring 21 are formed. The method of entering the electric field varies depending on the impurity concentration of the current spreading layer 2a.
  • the electric field relaxation layer 50 includes a position assumed to reach the interlayer insulating film 10 formed thereon when an electric field enters between the p-type guard rings 21. As described above, the electric field relaxation layer 50 is formed.
  • the n + -type source region 4 is continuously epitaxially grown on the p-type base region 3, but n-type impurities are ion-implanted at a desired position in the p-type base region 3.
  • the n + -type source region 4 may be formed.
  • each of the above embodiments only shows an example of a vertical semiconductor element, and a vertical type in which a current flows between a first electrode provided on the front surface side and a second electrode provided on the back surface side of the semiconductor substrate.
  • a semiconductor element it may be of another structure or conductivity type.
  • an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example.
  • the conductivity type of each component is reversed.
  • it may be a p-channel type MOSFET.
  • the MOSFET has been described as an example of the semiconductor element.
  • the present disclosure can be applied to an IGBT having a similar structure. The IGBT only changes the conductivity type of the n + type substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those in the above-described embodiments.
  • the vertical MOSFET having the trench gate structure has been described as an example.
  • the vertical MOSFET is not limited to the trench gate structure but may be a planar type.
  • a MOS structure power element not only a MOS structure power element but also a Schottky diode can be applied.
  • n on the main surface of the n + -type substrate - with -type drift layer is formed, the Schottky electrode corresponding to the first electrode formed thereon, further back surface side of the n + -type substrate
  • a Schottky diode is formed by forming an ohmic electrode corresponding to the second electrode.
  • a junction barrier Schottky diode hereinafter referred to as JBS
  • JBS junction barrier Schottky diode
  • the SiC semiconductor device provided with such JBS also includes the electric field relaxation layer 40 described in the first and second embodiments and the electric field relaxation layer 50 described in the third embodiment, so that the same as in each of the above embodiments. The effect of can be obtained.
  • the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30 are formed by buried epi growth, but may be formed by ion implantation.
  • the p-type deep layer 5 and the p-type connecting layer 30 are formed so as to penetrate the n + -type source region 4 and the p-type base region 3.
  • the p-type deep layer 5 and the p-type connecting layer 30 may be formed only below.

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