WO2018100844A1 - 駆動装置 - Google Patents

駆動装置 Download PDF

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Publication number
WO2018100844A1
WO2018100844A1 PCT/JP2017/033281 JP2017033281W WO2018100844A1 WO 2018100844 A1 WO2018100844 A1 WO 2018100844A1 JP 2017033281 W JP2017033281 W JP 2017033281W WO 2018100844 A1 WO2018100844 A1 WO 2018100844A1
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WO
WIPO (PCT)
Prior art keywords
potential
power supply
transistor
relationship
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/033281
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English (en)
French (fr)
Japanese (ja)
Inventor
川本　輝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to CN201780074087.9A priority Critical patent/CN110024291A/zh
Publication of WO2018100844A1 publication Critical patent/WO2018100844A1/ja
Priority to US16/424,646 priority patent/US20190296729A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/03—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
    • H02P7/04—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors by means of a H-bridge circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0054—Gating switches, e.g. pass gates

Definitions

  • the present disclosure relates to a driving device that controls driving of an open / close MOS transistor and a protective MOS transistor that are interposed in series in a power supply path from a DC power supply to a load.
  • a state occurs in which the positive side terminal and negative side terminal of a battery that is a power source are reversely connected (hereinafter referred to as reverse connection), an excessive reverse current is generated.
  • the flow may cause a failure of a circuit element such as a transistor.
  • a protective MOS transistor connected so that the direction of a parasitic diode is opposite to that of the originally provided power-off MOS transistor The structure which provides is disclosed. In this case, the reverse current can be cut off by the parasitic diode of the protective MOS transistor.
  • An object of the present disclosure is to provide a drive device that can reliably cut off a current that flows during reverse connection.
  • the driving device is a switching MOS transistor that is interposed in series in a power supply path from a DC power source to a load and that is connected so that the parasitic diodes are opposite to each other.
  • the driving of the protection MOS transistor is controlled.
  • the drive device includes a drive unit that drives the open / close MOS transistor and the protection MOS transistor. The drive unit operates by receiving power supply from the DC power source via the high potential side power line connected to the high potential side terminal of the DC power source and the low potential side power line connected to the low potential side terminal of the DC power source. .
  • the power supplied to the load and the power supplied to the drive unit are the same. For this reason, when the DC power supply is reversely connected, the drive unit cannot normally supply power, and thus cannot control the protection MOS transistor. Then, the protection MOS transistor is not controlled by the driving unit, the protection MOS transistor is kept on, and the reverse current cannot be cut off.
  • the drive device further includes a reverse connection protection control unit.
  • the reverse connection protection control unit When the potential relationship between the high potential side power supply line and the low potential side power supply line is reversed from the normal relationship, the reverse connection protection control unit forcibly drives the protection MOS transistor off regardless of the drive by the drive unit. The protection operation that cuts off the current flowing through the power supply path is executed.
  • FIG. 1 is a diagram schematically illustrating a configuration of a driving device and a driving target according to the first embodiment.
  • FIG. 2 is a diagram illustrating a specific configuration example of the drive device and the drive target according to the first embodiment.
  • FIG. 3 is a diagram schematically showing the gate voltage of each transistor in the normal state according to the first embodiment.
  • FIG. 4 is a diagram schematically showing the gate voltage of each transistor during reverse connection according to the first embodiment.
  • FIG. 5 is a diagram illustrating a specific configuration example of the drive device and the drive target according to the second embodiment.
  • FIG. 6 is a diagram illustrating a specific configuration example of the drive device and the drive target according to the third embodiment.
  • a driving device 1 shown in FIG. 1 controls driving of transistors Q1 and Q2 that are interposed in series in a power supply path from a DC power supply 2 to a load 3, and is configured as a semiconductor integrated circuit (IC).
  • IC semiconductor integrated circuit
  • the DC power source 2 is, for example, an in-vehicle battery, and a high potential side power line L1 (hereinafter, abbreviated as a power line L1) is connected to a high potential side terminal, and a low potential side power source is connected to the low potential side terminal.
  • a line L2 (hereinafter abbreviated as power supply line L2) is connected.
  • the transistors Q1 and Q2 are both N-channel MOS transistors and include a parasitic diode (body diode) connected between the drain and source with the source side as an anode.
  • the drain of the transistor Q1 is connected to the power supply line L1, and the source thereof is connected to the source of the transistor Q2.
  • the drain of the transistor Q2 is connected to the power supply line L2 via the load 3.
  • the transistors Q1 and Q2 are connected such that the parasitic diodes are opposite to each other.
  • the transistor Q1 corresponds to an open / close MOS transistor
  • the transistor Q2 corresponds to a protection MOS transistor.
  • the terminal P1 of the driving device 1 is connected to the power supply line L1 through the diode D1 in the reverse direction.
  • Terminals P2 and P3 of the driving device 1 are connected to power supply lines L1 and L2, respectively.
  • the drive device 1 includes a control unit 4, a drive unit 5, and a reverse connection protection control unit 6. The control unit 4 and the drive unit 5 operate by receiving power supply from the DC power supply 2 via the terminals P1 and P3.
  • the drive unit 5 generates a gate drive signal for driving the transistors Q1 and Q2 in accordance with the control signal given from the control unit 4. These gate drive signals are applied to the gates of the transistors Q1 and Q2 via terminals P4 and P5, respectively.
  • the control unit 4 controls the operation of the drive unit 5 as follows. In other words, the control unit 4 controls the operation of the drive unit 5 so that both the transistors Q1 and Q2 are turned on when the load 3 is energized.
  • the reverse connection protection control unit 6 When the potential relationship between the power supply lines L1 and L2 is reversed from the normal relationship, the reverse connection protection control unit 6 forcibly drives the transistor Q2 off regardless of the drive by the drive unit 5 and loads the load from the DC power supply 2. A protection operation for cutting off the current flowing in the power supply path leading to 3 is executed.
  • the reverse connection protection control unit 6 includes a potential relationship detection unit 7 and a potential fixing unit 8 as a configuration for realizing such a protection operation.
  • Each voltage of the power supply lines L1 and L2 is applied to the potential relationship detection unit 7 via terminals P2 and P3.
  • the potential relationship detection unit 7 divides each voltage and detects the potential relationship between the power supply lines L1 and L2 based on the divided voltage.
  • the potential relationship detection unit 7 detects whether the potential relationship between the power supply lines L1 and L2 is “normal relationship” or “reversed relationship”, and gives a signal representing the detection result to the potential fixing unit 8.
  • the potential fixing unit 8 fixes the gate potential of the transistor Q2 to the potential of the power supply line L1 when a signal indicating that the potential relationship of the power supply lines L1 and L2 is reversed from the potential relationship detection unit 7 is given. Although details will be described later, the above-described protection operation is realized by doing so.
  • the drive device 1 having such a function
  • a configuration as shown in FIG. 2 can be adopted.
  • the load 3 is comprised by the drive circuit which drives the motor M and the motor M is illustrated.
  • the drive circuit is configured as an H bridge circuit including four transistors Q3 to Q6.
  • the transistors Q3 to Q6 are all N-channel MOS transistors, and include a parasitic diode connected between the drain and source with the source side as the anode.
  • the interconnection node N1 of the transistors Q3 and Q4 is connected to one terminal of the motor M
  • the interconnection node N2 of the transistors Q5 and Q6 is connected to the other terminal of the motor M.
  • the interconnection node N3 of the transistors Q3 and Q5 is connected to the drain of the transistor Q2, and the interconnection node N4 of the transistors Q4 and Q6 is connected to the power supply line L2.
  • the driving device 1 includes a load driving unit 10 that drives the load 3 having such a configuration. Similar to the drive unit 5, the load drive unit 10 receives power supply from the DC power supply 2 via the terminals P 1 and P 3 and operates. The load driver 10 generates a gate drive signal for driving the transistors Q3 to Q6. These gate drive signals are applied to the gates of the transistors Q3 to Q6 via terminals P6 to P9, respectively.
  • the output stage for outputting each gate drive signal is composed of a half bridge circuit composed of two N-channel MOS transistors.
  • the drive unit 5 includes a charge pump circuit 11, transistors Q7 to Q10, and gate resistors Rg1 and Rg2.
  • the charge pump circuit 11 generates and outputs a boosted voltage obtained by boosting the voltage supplied via the terminal P1.
  • Each of the transistors Q7 to Q10 is an N-channel MOS transistor, and includes a parasitic diode connected between the drain and source with the source side as an anode.
  • the drain of the transistor Q7 is connected to the output terminal of the charge pump circuit 11, and its source is connected to the drain of the transistor Q8.
  • the source of the transistor Q8 is connected to the terminal P3.
  • the drain of the transistor Q9 is connected to the output terminal of the charge pump circuit 11, and its source is connected to the drain of the transistor Q10.
  • the source of the transistor Q10 is connected to the terminal P3.
  • the interconnection node N5 of the transistors Q7 and Q8 serves as an output terminal for the gate drive signal corresponding to the transistor Q1, and is connected to the terminal P4 via the gate resistor Rg1.
  • the interconnection node N6 of the transistors Q9 and Q10 serves as an output terminal for a gate drive signal corresponding to the transistor Q2, and is connected to the terminal P5 via the gate resistor Rg2.
  • the control unit 4 controls driving of the transistors Q7 to Q10 of the driving unit 5.
  • the reverse connection protection control unit 6 includes resistors R1 to R4 and transistors Q11 to Q13.
  • a series circuit of resistors R1 and R2 is connected between the terminals P2 and P3.
  • Each of the transistors Q11 to Q13 is an N-channel MOS transistor, and includes a parasitic diode connected between the drain and source with the source side as an anode.
  • the drain of the transistor Q11 is connected to the terminal P2, and the source thereof is connected to the source of the transistor Q12.
  • the drain of the transistor Q12 is connected to the terminal P3 through a series circuit of resistors R3 and R4.
  • the gates of the transistors Q11 and Q12 are connected to the interconnection node N7 of the resistors R1 and R2.
  • the drain of the transistor Q13 is connected to the terminal P5, and its source is connected to the drain of the transistor Q12.
  • Transistor Q13 has its gate connected to interconnection node N8 of resistors R3 and R4.
  • each resistance value is set so that the resistance value of the resistor R1 is much higher than the resistance value of the resistor R2.
  • each of these resistance values is set to such a value that the voltage at the interconnection node N7 is substantially equal to the voltage level of the DC power supply 2 (for example, 12V) at the time of reverse connection and is approximately 0V at the normal time.
  • the resistance values of the resistors R3 and R4 are set to values at which the gate-source voltage of the transistor Q13 is equal to or higher than a threshold voltage for driving the transistor Q13 on during reverse connection.
  • the potential relation detection unit 7 is configured by the resistors R1 and R2 and the transistors Q11 and Q12
  • the potential fixing unit 8 is configured by the resistors R3 and R4 and the transistor Q13.
  • the transistor Q13 constituting the potential fixing unit 8 corresponds to a switch that opens and closes between the gate of the transistor Q2 and the power supply line L1.
  • the resistors R3 and R4 constituting the potential fixing unit 8 may turn off the transistor Q13 when the potential relationship detecting unit 7 detects that the potential relationship is normal, and the potential relationship may be reversed. When detected, it corresponds to the switch controller 12 which turns on the transistor Q13.
  • the voltage value of the DC power supply 2 is, for example, 12V.
  • the potential of the power supply line L1 is 12 V and the potential of the power supply line L2 is 0V. That is, the potential relationship between the power supply lines L1 and L2 is a normal relationship. Therefore, power is normally supplied to the control unit 4, the drive unit 5, and the load drive unit 10. Accordingly, the control unit 4, the drive unit 5, and the load drive unit 10 are all in a normal operation state.
  • the drive unit 5 outputs a gate drive signal for turning on the transistors Q1 and Q2.
  • the gate voltages of the transistors Q1 and Q2 are turned on, and the transistors Q1 and Q2 are turned on.
  • the load driving unit 10 drives the transistors Q3 to Q6 according to the desired energization state of the motor M.
  • the gate voltages of the transistors Q4 and Q5 are ON level, the gate voltages of the transistors Q4 and Q5 are OFF level, and the gate voltages of the transistors Q3 and Q6 are OFF level.
  • the gate voltages of the transistors Q4 and Q5 are turned on. That is, the transistors Q3 and Q6 and the transistors Q4 and Q5 are turned on and off in a complementary manner.
  • the voltage at the node N7 is almost 0 V, and the transistors Q11 and Q12 are turned off.
  • the source voltage of the transistor Q13 becomes 0 V, which is the voltage of the power supply line L2.
  • the gate voltage of the transistor Q13 is also 0 V (OFF level) which is the voltage of the power supply line L2, and the transistor Q13 is turned off.
  • the reverse connection protection control unit 6 does not prevent the driving unit 5 from turning on the transistor Q2.
  • the drive unit 5 cannot drive the transistor Q2 off. This is because the source of the transistor Q2 is connected to the source of the transistor Q1. Therefore, in this case, the source voltage of the transistor Q2 is a voltage (for example, 0.7 V) that is higher than 0 V that is the potential of the power supply line L1 by the forward voltage of the parasitic diode of the transistor Q1.
  • the gate voltage of the transistor Q2 is a voltage (for example, 11.3V) lower than the 12V which is the potential of the power supply line L2 by the forward voltage of the parasitic diode of the transistor Q10. For this reason, the gate-source voltage of the transistor Q2 becomes equal to or higher than the threshold voltage Vt, and the transistor Q2 is turned on.
  • the load driving unit 10 cannot turn off the transistors Q3 to Q6.
  • the reason is the same as the reason why the driving unit 5 cannot drive the transistor Q2 off. Therefore, as shown in FIG. 4, the gate voltages of the transistors Q3 to Q6 are all turned on, and the transistors Q3 to Q6 are turned on.
  • the excessive current is prevented from flowing by the following operation of the reverse connection protection control unit 6. That is, in this case, the voltage at the node N7 is approximately 12V, and the transistors Q11 and Q12 are turned on.
  • the gate voltage of the transistor Q2 becomes a voltage (for example, 0.7V) higher than the 0V that is the voltage of the power supply line L1 by the forward voltage of the parasitic diode of the transistor Q11. That is, as shown in FIG. 4, the gate voltage of the transistor Q2 becomes OFF level, and the transistor Q2 is driven off.
  • the reverse connection protection control unit 6 forcibly drives the transistor Q2 off regardless of the driving of the transistor Q2 by the drive unit 5. Therefore, all the above-described paths are blocked, and an excessive current is prevented from flowing.
  • the parasitic diode of the transistor Q2 is connected so that the power supply line L2 side becomes a cathode. For this reason, the above-described operation also prevents the generation of reverse current via the parasitic diode of the transistor Q2.
  • the reverse connection protection control unit 6 performs a protection operation for forcibly driving off the transistor Q2 regardless of the drive by the drive unit 5 and cutting off the current flowing through the power supply path. Thereby, even if the drive unit 5 is not operating normally, the transistor Q2 is turned off, and a path through which a reverse current caused by reverse connection flows is cut off. As described above, according to the present embodiment, since the current flowing during the reverse connection can be surely cut off, the circuit elements such as the transistors Q1 to Q6 can be used even when the DC power supply 2 is reversely connected. Can be prevented.
  • the reverse connection protection control unit 6 is configured to limit the current flowing at the time of reverse connection by the resistors R3 and R4, and only needs to allow a relatively small current to flow. For this reason, the transistors Q11 to Q13 constituting the reverse connection protection control unit 6 can be of a relatively small size capable of flowing such a small current. Therefore, according to the present embodiment, it is possible to reliably cut off the current flowing during the reverse connection while suppressing increase in circuit area and cost increase.
  • the potential relation detection unit 7 is configured to divide the voltages of the power supply lines L1 and L2 by the resistors R1 and R2 and detect the potential relation of the power supply lines L1 and L2 based on the divided voltage. In this way, since the potential relationship can be detected with a simple circuit configuration, the effects of suppressing the increase in the circuit area and the cost increase described above are further enhanced.
  • the potential fixing unit 8 detects that the potential relationship between the power supply lines L1 and L2 is reversed by the potential relationship detecting unit 7, the gate potential of the transistor Q2 that is an N-channel MOS transistor is set to the potential of the power supply line L1. Fix to potential. In this way, at the time of reverse connection, the gate voltage of the transistor Q2 can be reliably set to the OFF level (0 V) and the transistor Q2 can be driven off.
  • the drive device 21 of the present embodiment is different from the drive device 1 of the first embodiment in that a reverse connection protection control unit 22 is provided instead of the reverse connection protection control unit 6.
  • the reverse connection protection control unit 22 is different from the reverse connection protection control unit 6 in the configuration of the potential fixing unit.
  • the potential fixing unit 23 includes resistors R21 to R24 and a comparator CP21.
  • a series circuit of resistors R21 and R22 and a series circuit of resistors R23 and R24 are respectively connected.
  • the interconnection node N21 of the resistors R21 and R22 is connected to the inverting input terminal of the comparator CP21, and the interconnection node N22 of the resistors R23 and R24 is connected to the non-inverting input terminal of the comparator CP21.
  • the output terminal of the comparator CP21 is connected to the terminal P5.
  • the comparator CP21 includes a power supply terminal P21 and a ground terminal P22 for receiving supply of operating power.
  • the power supply terminal P21 is connected to the terminal P3, and the ground terminal P22 is connected to the drain of the transistor Q12.
  • the comparator CP21 is operable by receiving the operation power supply when the transistors Q11 and Q12 are turned on and the potential relationship between the power supply lines L1 and L2 is reversed. It becomes a state.
  • the comparator CP21 operates when the potential relation detection unit 7 detects that the potential relation of the power supply lines L1 and L2 is reversed and the transistors Q11 and Q12 are turned on when the reverse connection occurs. It becomes a state.
  • the comparator CP21 when the transistors Q11 and Q12 are off, the comparator CP21 is in an inoperable non-operating state because the supply of operating power is stopped. That is, the comparator CP21 does not operate when the potential relationship between the power supply lines L1 and L2 is detected to be normal by the potential relationship detection unit 7 and the transistors Q11 and Q12 are turned off when the reverse connection is normal. It becomes a state.
  • the resistance values of the resistors R21 to R24 are set to values at which the voltage of the interconnection node N21 is higher than the voltage of the interconnection node N22 during reverse connection. Therefore, at the time of reverse connection, the comparator CP21 is in an operating state, and the voltage level of the output signal is 0V.
  • the reverse connection protection control unit 22 of the present embodiment forcibly turns off the transistor Q2 regardless of the drive by the drive unit 5 at the time of reverse connection, similarly to the reverse connection protection control unit 6 of the first embodiment. Then, a protection operation for cutting off the current flowing in the power supply path is executed. Therefore, also according to this embodiment, the current flowing during reverse connection can be reliably interrupted, so that the same effect as in the first embodiment can be obtained.
  • the driving device 31 of this embodiment controls driving of the transistors Q ⁇ b> 1 and Q ⁇ b> 31 that are interposed in series in the power supply path from the DC power supply 2 to the load 3.
  • the transistor Q31 is a P-channel MOS transistor and includes a parasitic diode connected between the drain and source with the drain side as an anode.
  • the drain of the transistor Q1 is connected to the power supply line L1, and the source thereof is connected to the drain of the transistor Q31.
  • the source of the transistor Q31 is connected to the power supply line L2 through the load 3.
  • the transistors Q1 and Q31 are connected such that the parasitic diodes are opposite to each other.
  • the transistor Q31 corresponds to a protection MOS transistor.
  • the drive device 31 is different from the drive device 1 of the first embodiment in that a reverse connection protection control unit 32 is provided instead of the reverse connection protection control unit 6.
  • the reverse connection protection control unit 32 differs from the reverse connection protection control unit 6 in the configuration of the potential fixing unit.
  • the potential fixing unit 33 includes resistors R31 and R32, a transistor Q32, and a diode D31.
  • the drain of the transistor Q12 is connected to the terminal P3 through a series circuit of resistors R31 and R32.
  • the transistor Q32 is a P-channel MOS transistor and includes a parasitic diode connected between the drain and source with the drain side as an anode.
  • Transistor Q31 has its gate connected to interconnection node N31 of resistors R31 and R32.
  • the drain of the transistor Q32 is connected to the terminal P5 through the diode D31 in the forward direction.
  • the source of the transistor Q32 is connected to the terminal P3.
  • the resistance values of the resistors R31 and R34 are set to values at which the source-gate voltage of the transistor Q32 is equal to or higher than a threshold voltage for driving the transistor Q31 on during reverse connection.
  • the transistor Q32 corresponds to a switch that opens and closes between the gate of the transistor Q2 and the power supply line L1.
  • the resistors R31 and R32 turn off the transistor Q32 when the potential relationship detection unit 7 detects that the potential relationship is normal, and the transistors R32 and R32 turn off the transistor Q32 when the potential relationship is reversed. This corresponds to the switch control unit 34 that turns on Q32.
  • the control unit 4, the drive unit 5, and the load drive unit 10 are all in a normal operation state as in the first embodiment.
  • the voltage at the node N7 is almost 0 V, and the transistors Q11 and Q12 are turned off.
  • the source voltage and the gate voltage of the transistor Q32 both become 0 V, which is the voltage of the power supply line L2. Therefore, transistor Q32 is turned off.
  • the reverse connection protection control unit 32 does not prevent the driving unit 5 from turning on the transistor Q31.
  • the reverse connection protection control unit 32 forcibly turns off the transistor Q31 regardless of the drive of the transistor Q31 by the drive unit 5. For this reason, the current path from the power supply line L2 to the power supply line L1 is blocked, and an excessive current is prevented from flowing.
  • the reverse connection protection control unit 32 of the present embodiment forcibly drives the transistor Q31 off regardless of the drive by the drive unit 5 during reverse connection, similar to the reverse connection protection control unit 6 of the first embodiment. Then, a protection operation for cutting off the current flowing in the power supply path is executed. Therefore, also according to this embodiment, the current flowing during reverse connection can be reliably interrupted, so that the same effect as in the first embodiment can be obtained.
  • the potential fixing unit 33 of the reverse connection protection control unit 32 includes a diode D31.
  • the reason for providing the diode D31 is as follows. That is, when the drain of the transistor Q32 is directly connected to the terminal P5 without providing the diode D31, a current path is formed from the terminal P5, that is, the gate of the transistor Q31 to the power supply line L2 via the parasitic diode of the transistor Q32. End up. Then, when normal, the reverse connection protection control unit 32 may prevent the driving unit 5 from turning on the transistor Q31.
  • the reverse connection protection control unit 32 causes the transistor by the drive unit 5 to operate normally.
  • the on-drive of Q31 is not hindered.
  • the potential fixing unit 33 uses the gate potential of the transistor Q31, which is a P-channel MOS transistor, of the power supply line L2. Fix to potential. In this way, at the time of reverse connection, the gate voltage of the transistor Q31 can be reliably set to the OFF level (about 12V), and the transistor Q31 can be driven off.
  • the specific configuration of the reverse connection protection control unit is not limited to the configuration illustrated in each of the above embodiments.
  • the drive by the drive unit 5 is performed. Any configuration can be used as long as the transistor Q2 can be forcibly driven off to perform a protection operation for cutting off the current flowing in the power supply path from the DC power supply 2 to the load 3.
  • the load 3 is not limited to the configuration shown in FIG. 2 or the like, and may be, for example, a resistance load, an inductive load, or the like, or a three-phase motor and a drive circuit that drives the three-phase motor. .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Electronic Switches (AREA)
  • Protection Of Static Devices (AREA)
PCT/JP2017/033281 2016-12-01 2017-09-14 駆動装置 Ceased WO2018100844A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201780074087.9A CN110024291A (zh) 2016-12-01 2017-09-14 驱动装置
US16/424,646 US20190296729A1 (en) 2016-12-01 2019-05-29 Drive device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016234094A JP6711251B2 (ja) 2016-12-01 2016-12-01 駆動装置
JP2016-234094 2016-12-01

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/424,646 Continuation US20190296729A1 (en) 2016-12-01 2019-05-29 Drive device

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WO2018100844A1 true WO2018100844A1 (ja) 2018-06-07

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JP (1) JP6711251B2 (https=)
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