WO2018094596A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2018094596A1
WO2018094596A1 PCT/CN2016/106887 CN2016106887W WO2018094596A1 WO 2018094596 A1 WO2018094596 A1 WO 2018094596A1 CN 2016106887 W CN2016106887 W CN 2016106887W WO 2018094596 A1 WO2018094596 A1 WO 2018094596A1
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Prior art keywords
layer
buffer layer
array substrate
conductor
metal layer
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PCT/CN2016/106887
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English (en)
French (fr)
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李文辉
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深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2016/106887 priority Critical patent/WO2018094596A1/zh
Priority to KR1020197015549A priority patent/KR20190065458A/ko
Priority to CN201680036580.7A priority patent/CN107820640A/zh
Priority to EP16922321.1A priority patent/EP3547351A1/en
Priority to US16/349,490 priority patent/US20200194572A1/en
Priority to JP2019526296A priority patent/JP2019536284A/ja
Publication of WO2018094596A1 publication Critical patent/WO2018094596A1/zh

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

提供一种阵列基板的制造方法，所述方法包括：在基板（10）上依次形成栅极（20）、栅极绝缘层（30）、缓冲层（40）和金属层（50）。对所述金属层（50）及所述缓冲层（40）进行图案化处理，以在所述金属层（50）上形成源极（51）、漏极（52）及介于二者之间的沟道（53），所述缓冲层（40）部分露出于所述沟道（53）。对露出所述沟道（53）部分的缓冲层（40）进行半导体化处理，以在沟道（53）内形成半导体区域（41）。上述制造方法省去了传统阵列基板结构中的金属氧化物半导体层，降低了制作成本。此外，在形成沟道过程中无需蚀刻缓冲层，简化了蚀刻流程，从而减小了蚀刻难度，进一步降了低阵列基板的制造成本。

Description

阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)阵列基板被广泛应用于不同类型的显示装置中。现有技术的阵列基板中，将源漏极层形成于半导体层之上。源漏极层包括金属层和导体缓冲层，金属层与半导体层之间通过导体缓冲层隔开。这样设置的目的在于防止源极漏极层中的金属层扩散至半导体层中，减少金属层与半导体层之间的接触阻抗，避免造成金属穿刺等不良。
在阵列基板上形成沟道过程中，就需要依次对金属层和导体缓冲层进行蚀刻，以露出所述金属半导体层。因此，现有技术中的蚀刻过程复杂、难度较大，造成阵列基板的制造成本居高不下。
发明内容
本申请的目的在于提供一种阵列基板的制造方法，可以简化蚀刻流程，降低阵列基板的制作成本。
本申请的另一目的在于提供一种上述制造方法制造的阵列基板。
为实现上述目的，本申请提供如下技术方案：
本申请提供一种阵列基板的制造方法，所述方法包括：
在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层；
对所述金属层及所述导体缓冲层进行图案化处理，以在所述金属层上形成源极、漏极及介于二者之间的沟道，所述导体缓冲层部分露出于所述沟道；
对露出所述沟道部分的导体缓冲层进行半导体化处理，以在沟道内形成半导体区域。
其中，所述对所述金属层及所述导体缓冲层进行图案化处理，以在所述金属层上形成源极、漏极及介于二者之间的沟道，所述导体缓冲层部分露出于所述沟道步骤中包括：
在所述金属层上涂覆光刻胶；
提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域；
以所述光刻胶为遮蔽层，对所述金属层及导体缓冲层进行蚀刻，使得蚀刻后的金属层及导体缓冲层具有源极和漏极图案；
将所述光刻胶的所述半曝光区域转化为全曝光区域；
蚀刻所述蚀刻后的金属层之露出于所述全曝光区域的部分，以形成沟道并露出所述导体缓冲层。
其中，对所述导体缓冲层进行半导体化处理，以在所述导体缓冲层之露出于所述沟道部分形成半导体区域步骤中包括：
以所述光刻胶为遮蔽层，对所述导体缓冲层之露出于所述沟道部分进行等离子处理或高温氧化气氛处理，以使得所述导体缓冲层之露出于所述沟道部分形成所述半导体区域。
其中，所述方法还包括在所述半导体区域形成后，通过灰化处理或剥离法去除所述光刻胶。
其中，所述将所述光刻胶的所述半曝光区域转化为全曝光区域步骤中，包括对所述光刻胶进行灰化处理，使得所述半曝光区域转化为所述全曝光区域。
其中，所述以所述光刻胶为遮蔽层，对所述金属层及导体缓冲层进行蚀刻，使得蚀刻后的金属层及导体缓冲层具有源极和漏极图案步骤中，包括蚀刻液对所述金属层及导体缓冲层进行蚀刻。
其中，所述蚀刻液可以选用H2O2、金属螯合剂或有机酸。
其中，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。
其中，所述在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层步骤中，包括在栅绝缘层上通过溅射或热蒸发的方法沉积导体缓冲层。
其中，所述在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层步骤中，包括通过PECVD方法沉积所述栅极绝缘层。
本申请还提供一种阵列基板，其中，包括依次层叠设置于基板的栅极、栅极绝缘层、导体缓冲层和金属层，其中，所述导体缓冲层包括半导体区域和导体区域，所述金属层包括源极和漏极，所述源极和漏极之间设有沟道，所述源极及所述漏极正对所述导体区域，所述半导体区域露出于所述沟道。
其中，所述导体缓冲层材料为金属氧化物。
其中，所述金属氧化物为IGZO。
其中，所述金属层采用铜或铜合金材料制成。
本申请实施例具有如下优点或有益效果：
本申请的阵列基板的制造方法中，在所述金属层上形成源极、漏极及介于二者之间的沟道，导体缓冲层部分露出于所述沟道，对所述导体缓冲层进行半导体化处理，以在所述导体缓冲层之露出于所述沟道部分形成半导体区域，所述源极和所述漏极之间依次经过导体区域和半导体区域电性连接，从而省去了传统阵列基板结构中的金属氧化物半导体层，降低了制作成本。此外，在形成沟道过程中无需蚀刻导体缓冲层，简化了蚀刻流程，从而减小了蚀刻难度，进一步降了低阵列基板的制造成本。本申请的阵列基板能够降低制造成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的制造方法流程图。
图2～图8为图1的所示制造方法的过程示意图。
图9为本申请实施例提供的阵列基板。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请以下实施例中所采用的序数限定词，第一、第二等仅是为了清楚地说明本申请中相似的特征的区别性的用语，不代表相应的特征的排列顺序或者使用顺序。
本申请的制造方法生产出的阵列基板可以应用于液晶显示屏或者有机显示屏中。本申请实施例涉及的柔性显示屏用于但不限于手机、平板电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)或电子阅读器等，本 申请实施例对此不作具体限定。
请参阅图1，图1为本申请实施例提供的一种阵列基板的制造方法流程图。本申请提供的制造方法主要包括如下步骤：
步骤S001：在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层。
具体的，请结合参阅图2。所述基板10为透明玻璃基板，在所述基板10上沉积第一金属薄膜。所述第一金属薄膜可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。通过构图工艺利用普通光阻层形成栅线(图未示出)、公共电极线(图未示出)和栅极20的图形。然后在此基础上通过PECVD(等离子体增强化学气相沉积法)方法沉积栅极绝缘层30，栅极绝缘层30可以选用氧化物、氮化物或者氧氮化合物等。
然后，在栅绝缘层上通过溅射或热蒸发的方法沉积导体缓冲层40，导体缓冲层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。
接着，在所述导体缓冲层40上采用溅射或热蒸发的方法形成金属层50。所述导体缓冲层40的作用在于防止金属层50与半导体区域(如图5中标号41)直接接触，造成金属层50中的金属扩散到半导体区域中，避免造成金属穿刺等不良，从而提升阵列基板性能。
步骤S002：对所述金属层及所述导体缓冲层进行图案化处理，以在所述金属层上形成源极、漏极及介于二者之间的沟道，所述导体缓冲层部分露出于所述沟道。
具体的，步骤S002具体包括步骤S0021～S0025：
步骤S0021：在所述金属层50上涂覆光刻胶60；
步骤S0022：提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域。
具体的，请结合参阅图3。将多灰阶掩膜版70遮盖在所述光刻胶60上方。可选的，所述多灰阶掩膜版70可以为半色调掩膜版(Half tone mask)或灰色调掩膜版(Gray tone mask)。对所述光刻胶60进行曝光、显影(即图案化)。所述多灰阶掩膜版70上设有全透光区域71、半透光区域72和不透光区域73。 曝光光线经所述多灰阶掩膜版70后对所述光刻胶60进行光刻。请结合参阅图4，全透光区域71下方光刻胶60被完全光刻形成全曝光区域61，全曝光区域61下方的金属层50露出于所述光刻胶60。半透光区域72下方的光刻胶60被部分光刻从而形成半曝光区域62。不透光区域71下方光刻胶60被保留。也就是说，光刻胶60经过图案化后在其上形成半曝光区域71。
步骤S0023：以所述光刻胶为遮蔽层，对所述金属层及导体缓冲层进行蚀刻，使得蚀刻后的金属层及导体缓冲层具有源极和漏极图案。
请参阅图5。进一步具体的，可以在所述光刻胶60上喷淋蚀刻液，蚀刻液经由光刻胶60上的全曝光区域61对金属层50和导体缓冲层40进行依次蚀刻，直至将所述金属层50和所述导体缓冲层40形成具有源极和漏极图案，最后去除所述蚀刻液完成所述金属层50的图案化过程。可以理解的是，该步骤中所述金属层50和所述导体缓冲层40形成的图案相同。可以理解的是，对所述金属层50及导体缓冲层40蚀刻过程还可以通过干法蚀刻完成，此处不加以限定。
步骤S0024：将所述光刻胶的所述半曝光区域转化为全曝光区域。
请结合参阅图6。具体的，可以对所述光刻胶60进行灰化处理，使得所述半曝光区域62转化为所述全曝光区域。可以理解的是，所述“灰化处理”即将氧气激发成电浆，通过氧气与光刻胶反应，从而将所述光刻胶60整体打薄，光刻胶60整体打薄后，半曝光区域62处的光刻胶会首先被完全去除，即所述半曝光区域将会转化为全曝光区域62。此时，所述金属层50部分暴露于所述全曝光区域62。
步骤S0025：蚀刻所述蚀刻后的金属层之露出于所述全曝光区域的部分，以形成沟道并露出所述导体缓冲层。
请结合参阅图7，在本步骤中，需要在所述金属层50上形成源极51、漏极52及介于源极51和漏极52之间的沟道53。具体的，可以在所述光刻胶60上喷淋蚀刻液，蚀刻液经由光刻胶60上的全曝光区域62对金属层50进行蚀刻，直至将所述金属层50之位于全曝光区域62正下方的部分完全蚀刻，形成沟道53，所述导体缓冲层40且露出于所述沟道53。可以理解的是，此时沟道53的底部即为导体缓冲层40。可以理解的是，所述沟道53为梯形。这是由于蚀刻液经全曝光区域62进入金属层50表面后会向两侧扩散。并且越往上其接 触蚀刻液的时间也就越长，蚀刻液往两侧蚀刻的量就越大，因此在金属层50上会形成梯形沟道53。
优选的，所述蚀刻液可以选用H2O2、金属螯合剂或有机酸等。
步骤S003：对露出所述沟道部分的所述导体缓冲层进行半导体化处理，以在所述沟道内形成半导体区域。
具体的，请结合参阅图8。以所述光刻胶60为遮蔽层，对所述导体缓冲层40之露出于所述沟道部分41进行等离子处理或高温氧化气氛处理，所述导体缓冲层之露出于所述沟道部分经过等离子处理或高温氧化气氛处理后，形成所述半导体区域41。可以理解的是，导体缓冲层40之被光刻胶60覆盖区域的导电性能保持不变，因此仍为导体区域42。换而言之，经过半导体化处理后的导体缓冲层40包括半导体区域41和导体区域42。
导体缓冲层40的导体区域42分别与源极51和漏极52连接，所述源极51和所述漏极52之间依次经过导体区域42和半导体区域41电性连接，从而省去了传统阵列基板结构中的金属氧化物半导体层，降低了制作成本。此外，在形成沟道过程中无需蚀刻导体缓冲层，从而减小了蚀刻难度，进一步降了低阵列基板的制造成本。
请参阅图9，当半导体区域41形成后，可以去除所述光刻胶60，并继续后续步骤，完成阵列基板的制作。后续步骤不是本申请保护的重点，此处不再赘述。
去除光刻胶60可以采用湿法蚀刻工艺的剥离法去除所述光刻胶。该过程可以采用现有技术的光刻胶剥离方法，在此不再赘述。或者，还可以采用上述的灰化工艺去除所述光刻胶。
本申请的阵列基板的制造方法中在所述金属层上形成源极、漏极及介于二者之间的沟道，导体缓冲层部分露出于所述沟道，对所述导体缓冲层进行半导体化处理，以在所述导体缓冲层之露出于所述沟道部分形成半导体区域，所述源极和所述漏极之间依次经过导体区域和半导体区域电性连接，从而省去了传统阵列基板结构中的金属氧化物半导体层，降低了制作成本。此外，在形成沟道过程中无需蚀刻导体缓冲层，简化了蚀刻流程，从而减小了蚀刻难度，进一步降了低阵列基板的制造成本。
请参阅图9，本申请还提供一种阵列基板100。阵列基板100包括依次层叠设置于基板10的栅极20、栅极绝缘层30、导体缓冲层40和金属层50。金属层50包括源极51和漏极52，所述源极51和所述漏极52之间设置有沟道53。所述导体缓冲层40包括半导体区域41和导体区域42，所述半导体区域41露出于所述沟道53，所述源极51及所述漏极52正对所述导体区域42。
本申请的阵列基板中，导体缓冲层的半导体区露出于源极和漏极之间的沟道，所述源极和所述漏极之间依次经过导体缓冲层上的导体区域和半导体区域电性连接，从而省去了传统阵列基板结构中的金属氧化物半导体层，降低了制作成本。此外，在形成沟道过程中无需蚀刻导体缓冲层，从而减小了蚀刻难度，进一步降了低阵列基板的制造成本。
具体的，所述沟道53为梯形沟道。这是由于湿法蚀刻所述沟道53时，蚀刻液经全曝光区域62进入金属层50表面后会向两侧扩散。并且越往上其接触蚀刻液的时间也就越长，蚀刻液往两侧蚀刻的量就越大，因此在金属层50上会形成梯形沟道53。
可选的，所述金属层50可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。
导体缓冲层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (14)

  1. 一种阵列基板的制造方法，其特征在于，所述方法包括：
    在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层；
    对所述金属层及所述导体缓冲层进行图案化处理，以在所述金属层上形成源极、漏极及介于二者之间的沟道，所述导体缓冲层部分露出于所述沟道；
    对露出所述沟道部分的导体缓冲层进行半导体化处理，以在沟道内形成半导体区域。
  2. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述对所述金属层及所述导体缓冲层进行图案化处理，以在所述金属层上形成源极、漏极及介于二者之间的沟道，所述导体缓冲层部分露出于所述沟道步骤中包括：
    在所述金属层上涂覆光刻胶；
    提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域；
    以所述光刻胶为遮蔽层，对所述金属层及导体缓冲层进行蚀刻，使得蚀刻后的金属层及导体缓冲层具有源极和漏极图案；
    将所述光刻胶的所述半曝光区域转化为全曝光区域；
    蚀刻所述蚀刻后的金属层之露出于所述全曝光区域的部分，以形成沟道并露出所述导体缓冲层。
  3. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述对所述导体缓冲层进行半导体化处理，以在所述导体缓冲层之露出于所述沟道部分形成半导体区域步骤中包括：
    以所述光刻胶为遮蔽层，对所述导体缓冲层之露出于所述沟道部分进行等离子处理或高温氧化气氛处理，以使得所述导体缓冲层之露出于所述沟道部分形成所述半导体区域。
  4. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述方法还 包括在所述半导体区域形成后，通过灰化处理或剥离法去除所述光刻胶。
  5. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述将所述光刻胶的所述半曝光区域转化为全曝光区域步骤中，包括对所述光刻胶进行灰化处理，使得所述半曝光区域转化为所述全曝光区域。
  6. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述以所述光刻胶为遮蔽层，对所述金属层及导体缓冲层进行蚀刻，使得蚀刻后的金属层及导体缓冲层具有源极和漏极图案步骤中，包括采用蚀刻液对所述金属层及导体缓冲层进行蚀刻。
  7. 如权利要求6所述的阵列基板的制造方法，其特征在于，所述蚀刻液可以选用H2O2、金属螯合剂或有机酸。
  8. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。
  9. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层步骤中，包括在栅绝缘层上通过溅射或热蒸发的方法沉积导体缓冲层。
  10. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在基板上依次形成栅极、栅极绝缘层、导体缓冲层和金属层步骤中，包括通过PECVD方法沉积所述栅极绝缘层。
  11. 一种阵列基板，其特征在于，包括依次层叠设置于基板的栅极、栅极绝缘层、导体缓冲层和金属层，其中，所述导体缓冲层包括半导体区域和导体区域，所述金属层包括源极和漏极，所述源极和漏极之间设有沟道，所述源极及所述漏极正对所述导体区域，所述半导体区域露出于所述沟道。
  12. 如权利要求11所述的阵列基板，其特征在于，所述导体缓冲层材料为金属氧化物。
  13. 如权利要求12所述的阵列基板，其特征在于，所述金属氧化物为 IGZO。
  14. 如权利要求11所述的阵列基板，其特征在于，所述金属层采用铜或铜合金材料制成。
PCT/CN2016/106887 2016-11-23 2016-11-23 阵列基板及其制造方法 WO2018094596A1 (zh)

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