WO2018076285A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2018076285A1
WO2018076285A1 PCT/CN2016/103795 CN2016103795W WO2018076285A1 WO 2018076285 A1 WO2018076285 A1 WO 2018076285A1 CN 2016103795 W CN2016103795 W CN 2016103795W WO 2018076285 A1 WO2018076285 A1 WO 2018076285A1
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protective layer
layer
source
array substrate
exposed
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PCT/CN2016/103795
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English (en)
French (fr)
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叶江波
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深圳市柔宇科技有限公司
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Priority to CN201680034308.5A priority Critical patent/CN107810556B/zh
Priority to PCT/CN2016/103795 priority patent/WO2018076285A1/zh
Publication of WO2018076285A1 publication Critical patent/WO2018076285A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • Array substrates are widely used in different types of display devices. With the rapid development of display technology, people have higher and higher requirements on the resolution and response time of the display. In this case, the mobility requirements set on the display array substrate are getting higher and higher.
  • the purpose of the application is to provide a method for manufacturing an array substrate, which can avoid corrosion of the active layer during the manufacturing process and improve the performance of the array substrate.
  • Another object of the present application is to provide an array substrate manufactured by the above manufacturing method.
  • the present application provides a method of fabricating an array substrate, the method comprising:
  • a gate electrode Forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, a first protective layer, and a source/drain layer on the substrate;
  • the portion of the first protective layer exposed to the hollow region is dry etched such that a portion of the first protective layer exposed to the hollow region and the first protective layer
  • the remaining portion of the step of separating includes bombarding the first protective layer with an etching gas to cause the a slit is formed between a portion of the first protective layer exposed to the hollow region and a remaining portion of the first protective layer, the slit blocking a portion of the first protective layer exposed to the hollow region and The remainder of the first protective layer.
  • the etching gas is a mixture of one or any of SF6, O2, Cl2, He, Ar.
  • the step of removing the source and drain layers exposed to the hollow region to expose the first protective layer includes spraying an etchant on the source and drain layers to perform etching.
  • the etchant is removed after the first protective layer is completely exposed.
  • the step of removing the source and drain layers exposed to the hollow region to expose the first protective layer includes spraying an etchant on the source and drain layers to perform etching.
  • a trapezoidal channel is formed on the source drain layer, and the etching liquid is removed after the first protective layer is exposed to the trapezoidal channel.
  • the removing the portion of the source/drain layer exposed to the hollow region to expose the first protective layer by controlling the concentration of the etchant and the etchant at the source drain
  • the etching time of the pole layer is such that the first protective layer is completely exposed to the trapezoidal channel, wherein the concentration of the etching liquid and the etching time are preset values.
  • the etching solution comprises H2O2, a metal chelating agent or an organic acid.
  • the step of sequentially forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, a first protective layer, and a source/drain layer on the substrate includes sequentially performing on the metal oxide semiconductor layer by a sputtering method.
  • the first protective layer and the source and drain layers are formed.
  • the metal oxide is made of IGZO material
  • the first protective layer is made of GZO material.
  • the source and drain layers comprise a metal layer and a second protective layer which are disposed in a stack
  • the step of forming the source and drain layers comprises sequentially forming a metal layer and a second layer on the first protective layer by a sputtering method.
  • the protective layer comprises sequentially forming a metal layer and a second layer on the first protective layer by a sputtering method.
  • the second protective layer is made of GZO material.
  • the present application provides an array substrate including a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, a first protective layer, and a source/drain layer, which are sequentially stacked on a substrate, and the source and drain layers are provided with a turn-on a channel of the first protective layer, a portion of the first protective layer exposed to the channel being separated from a remaining portion of the first protective layer.
  • a slit is formed between a portion of the first protective layer exposed to the hollow region and a remaining portion of the first protective layer, and the slit blocks the first protective layer from being exposed Department of hollowing out Divided into the remainder of the first protective layer.
  • the channel is a trapezoidal channel.
  • the source and drain layers comprise a metal layer and a second protective layer which are disposed in a stack, and the metal layer is interposed between the first protective layer and the second protective layer.
  • the second protective layer is made of GZO material.
  • the metal oxide is made of IGZO material
  • the first protective layer is made of GZO material.
  • the source and drain layers are made of copper or copper alloy materials.
  • the source and drain layers and the first protective layer are etched twice, the first time the source and drain layers are completely etched, and then the second time by the dry etching method
  • the protective layer is etched such that the metal oxide semiconductor layer is partially exposed to the first protective layer, and the first protective layer can protect the metal oxide semiconductor layer from being etched during the dry etching process, avoiding metal
  • the surface of the oxide semiconductor layer is destroyed (forming sharp corners and pits), ensuring electron mobility and improving the performance of the array substrate.
  • FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 2 to 5 are schematic views of processes of the manufacturing method shown in Fig. 1.
  • FIG. 6 is an array substrate provided by an embodiment of the present application.
  • the array substrate produced by the manufacturing method of the present application can be applied to a liquid crystal display or an organic display.
  • the flexible display screen according to the embodiment of the present invention is used for, but not limited to, a mobile phone, a tablet computer, a palmtop computer, a personal digital assistant (PDA), or an e-reader.
  • PDA personal digital assistant
  • FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • the manufacturing method provided by the present application mainly includes the following steps:
  • S001 sequentially forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, a first protective layer, and a source/drain layer on the substrate.
  • the substrate 10 is a transparent glass substrate on which a first metal thin film is deposited.
  • the first metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • a pattern of a gate line (not shown), a common electrode line (not shown), and a gate electrode 20 is formed by a patterning process using a common photoresist layer.
  • the gate insulating layer 30 is deposited by a PECVD (plasma enhanced chemical vapor deposition) method, and the gate insulating layer 30 may be an oxide, a nitride or an oxynitride.
  • the metal oxide semiconductor layer 40 is deposited on the gate insulating layer by sputtering or thermal evaporation, and the metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxide.
  • IGZO indium gallium zinc oxide
  • HIZO IZO
  • a-InZnO a-InZnO
  • ZnO:F In2O3:Sn
  • In2O3:Mo In2SnO4
  • Cd2SnO4 ZnO:Al
  • TiO2:Nb Cd-Sn-O or other metal oxide.
  • it can be made of IGZO material.
  • the first protective layer 50 and the source and drain layers 60 are sequentially formed on the substrate 10 by sputtering or thermal evaporation.
  • the function of the first protective layer 50 is to prevent metal in the source and drain layers 60 from diffusing into the metal oxide semiconductor layer 40 so as not to degrade the performance of the array substrate.
  • the first protective layer 50 may be made of a different material of the metal oxide semiconductor layer 50, such as a GZO material.
  • the source and drain layer 60 includes a metal layer 61 and a second protective layer 62 which are disposed in a stacked manner.
  • the metal layer 61 and the second protective layer 62 may be sequentially formed on the first protective layer 50 by a sputtering method or a thermal evaporation method.
  • the second protective layer 62 material may be the same material as the first protective layer 50.
  • the second protective layer 62 serves to prevent the metal layer 61 from being oxidized.
  • the metal layer 61 can be selected from Cr, Metals or alloys such as W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal can also satisfy the needs.
  • it may be made of a copper or copper alloy material.
  • the first protective layer 50 and the second protective layer each have a thickness of 300A.
  • the metal layer 61 may have a thickness of 2000A.
  • the metal oxide semiconductor layer 40 has a thickness of 300A.
  • S002 covering the source and drain layers with a photoresist layer, and the photoresist layer is provided with a hollow region.
  • the photoresist layer 70 is thus formed by a photolithography process.
  • a cutout 71 is formed on the cover photoresist layer 70.
  • the photoresist layer 70 covers the second protective layer 62.
  • the second protective layer 62 has a hollow region 71 partially exposed on the photoresist layer 70. This is followed by etching to form the channel 65.
  • a channel 65 needs to be formed, and a source 63 and a drain 64 are formed on the source and drain layer 60.
  • the channel 65 may be formed on the source and drain layers by a wet etching method while the source 63 and the drain 64 are formed by the channel.
  • an etchant may be sprayed on the photoresist layer 70, and the etchant sequentially etches the second protective layer 62 and the metal layer 61 via the hollow region 71 on the photoresist layer 70 until the metal layer is The portion of the 61 located directly below the hollowed out region 71 is completely etched to expose the first protective layer 50.
  • the depth of the etching can be controlled by controlling the etching liquid concentration and the etching time, wherein the etching liquid concentration and the etching time can be set in advance.
  • the etching solution may be etched in the first protective layer 50 for a period of time to completely etch the metal layer 61, and then the etching is removed. liquid.
  • a source 63, a drain 64, and a channel 65 interposed therebetween are formed on the source/drain layer 60.
  • the bottom of the channel 65 is the first protective layer 50 at this time.
  • the channel 65 is trapezoidal. This is because the etching liquid diffuses to both sides after entering the second protective layer 62 and the surface of the metal layer 61 through the hollow region 71. Further, the longer the time for contacting the etching liquid, the larger the etching liquid is etched to both sides, and thus the trapezoidal channel 65 is formed on the source/drain layer 60.
  • the etching solution may be selected from H 2 O 2 , a metal chelating agent or an organic acid.
  • S004 dry etching a portion of the first protective layer exposed in the hollow region, such that a portion of the first protective layer exposed to the hollow region and a remaining portion of the first protective layer cut off.
  • the etching gas may be placed in a low pressure environment, and a voltage is applied to excite the etching gas into a plasma, and the first protective layer 50 is bombarded.
  • the first protective layer 50 is etched.
  • a reflective bounce occurs on the sidewall 651 of the channel 65. Therefore, a slit 66 is formed at the junction of the bottom of the trench 65 (the first protective layer 50) and the sidewall 651, and the etching speed is faster toward the intermediate position near the junction. Therefore, the metal oxide semiconductor layer 40 under the interface is first exposed to the slit 66 on the first protective layer 50.
  • a slit 66 is formed between the portion 51 of the first protective layer 50 exposed to the hollow region 71 and the remaining portion 52 of the first protective layer 50, and the slit 66 blocks the The portion 51 of the first protective layer 50 exposed to the hollowed out region 71 and the remaining portion 52 of the first protective layer.
  • the metal oxide semiconductor layer 40 is partially exposed to the slit 66.
  • a channel through which electrons migrate can be formed. That is, the first protective layer 50 does not need to be completely etched, and the first protective layer 50 can function to protect the metal oxide semiconductor layer 40 during the dry etching process, thereby preventing the metal oxide semiconductor layer 40 from being etched.
  • the resulting surface quality is degraded, affecting the rate of electron migration, etc., thereby improving the basic performance of the array.
  • the dry etching may be stopped, and the photoresist layer 70 may be removed, and the subsequent steps may be continued to complete the fabrication of the array substrate.
  • the subsequent steps are not the focus of the protection of the present invention and will not be described here.
  • the etching gas may be appropriately selected, for example, one or a mixture of any one of SF 6 , O 2 , Cl 2 , He, Ar (argon), or the like is selected.
  • the source and drain layers and the first protective layer are etched twice, the first time the source and drain layers are completely etched, and then the second time by the dry etching method
  • the protective layer is etched such that the metal oxide semiconductor layer is partially exposed to the first protective layer, and the first protective layer can protect the metal oxide semiconductor layer from being etched during the dry etching process, avoiding metal
  • the surface of the oxide semiconductor layer is destroyed (forming sharp corners and pits), ensuring the surface quality of the metal oxide semiconductor layer, ensuring electron mobility and improving the performance of the array substrate.
  • the present application further provides an array substrate 100 .
  • the array substrate 100 includes sequential layers The gate electrode 20 of the substrate 10, the gate insulating layer 30, the metal oxide semiconductor layer 40, the first protective layer 50, and the source/drain layer 60 are stacked.
  • a channel 65 leading to the first protective layer 50 is disposed on the source and drain layer 60.
  • the source drain layer 60 includes a source 63 and a drain 64 disposed between the source 63 and the drain 64.
  • a portion 51 of the first protective layer 50 exposed to the channel is isolated from the remaining portion 52 of the first protective layer 50.
  • the first protective layer is covered on the metal oxide semiconductor layer and the gate insulating layer, and the portion of the first protective layer located in the channel is separated from other portions of the protective layer such that the first protective layer is located in the trench.
  • the portion of the track protects the metal oxide semiconductor layer from damage during channel formation, ensures surface quality of the metal oxide semiconductor layer, ensures electron mobility, and improves the performance of the array substrate.
  • a slit 66 is formed between the portion 51 of the first protective layer 50 exposed to the hollow region and the remaining portion 52 of the first protective layer, and the slit blocks the first protective layer The portion 51 exposed to the hollow region and the remaining portion 52 of the first protective layer.
  • the channel 65 is a trapezoidal channel.
  • the etching liquid diffuses to both sides after entering the second protective layer 62 and the surface of the metal layer 61 through the hollow region 71. Further, the longer the time for contacting the etching liquid, the larger the etching liquid is etched to both sides, and thus the trapezoidal channel 65 is formed on the source/drain layer 60.
  • the first protective layer 50 may be made of a material different from the metal oxide semiconductor layer 50, and may be, for example, a GZO material.
  • the source and drain layer 60 includes a metal layer 61 and a second protective layer 62 which are disposed in a stacked manner. The metal layer 61 and the second protective layer 62 may be sequentially formed on the first protective layer 50 by a sputtering method or a thermal evaporation method.
  • the second protective layer 62 material may be the same material as the first protective layer 50.
  • the second protective layer 62 serves to prevent the metal layer 61 from being oxidized.
  • the metal layer 61 may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • it may be made of a copper or copper alloy material.

Abstract

一种阵列基板的制造方法，包括：在基板（10）上依次形成栅极（20）、栅极绝缘层（30）、金属氧化物半导体层（40）、第一保护层（50）和源漏极层（60）；在源漏极层（60）上形成光阻层（70），光阻层（70）上设置有镂空区（71）；去除源漏极层（60）之露出于镂空区（71）的部分，以露出第一保护层（50）；对第一保护层（50）之露出于镂空区（71）的部分进行干法蚀刻，以使得第一保护层（50）之露出于镂空区（71）的部分与第一保护层（50）之其余部分隔断。第一保护层（50）可以保护金属氧化物半导体层（40）不被蚀刻，避免金属氧化物半导体层（40）表面被损毁，保证了电子迁移率，提升阵列基板的性能。

Description

阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法。
背景技术
阵列基板被广泛应用于不同类型的显示装置中。随着显示技术的飞速发展，人们对显示器的分辨率，响应时间等特性要求也越来越高。在这种情况下，对设置在显示器阵列基板上的迁移率要求越来越高。
目前，用非晶硅制作有源层已经不能满足对迁移率的要求，人们已经将目光投向了具有较高迁移率的金属氧化物材料。现有技术中制造将金属氧化物作为有源层材料的过程中，主要有如下问题：传统工艺进行源漏极的构图工艺时，由于有源层上方没有遮挡，因此会对有源层造成损伤，从而影响到阵列基板的性能。
发明内容
本申请的目的在于提供一种阵列基板的制造方法，可以避免制造过程中造成有源层的腐蚀，提升阵列基板的性能。
本申请的另一目的在于提供一种上述制造方法制造的阵列基板。
为实现上述目的，本申请提供如下技术方案：
本申请提供一种阵列基板的制造方法，所述方法包括：
在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层；
在所述源漏极层上形成光阻层，所述光阻层上设置有镂空区；
去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层；
对所述第一保护层之露出于所述镂空区的部分进行干法蚀刻，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分隔断。
其中，所述对所述第一保护层之露出于所述镂空区的部分进行干法蚀刻，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分隔断步骤中，包括使用蚀刻气体对所述第一保护层进行轰击，以使得所述 第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分之间形成狭缝，所述狭缝隔断所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分。
其中，所述蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。
其中，所述去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，包括在所述源漏极层喷淋蚀刻液进行蚀刻，在所述第一保护层完全露出后去除所述蚀刻液。
其中，所述去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，包括在所述源漏极层喷淋蚀刻液进行蚀刻，以在所述源漏极层上形成梯形沟道，在所述第一保护层露出于所述梯形沟道后去除所述蚀刻液。
其中，所述去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，通过控制所述蚀刻液的浓度及所述蚀刻液在所述源漏极层的蚀刻时间，使得所述第一保护层完全露出于所述梯形沟道，其中，所述蚀刻液的浓度和所述蚀刻时间为预设值。
其中，所述蚀刻液包括H2O2、金属螯合剂或有机酸。
其中，所述在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层步骤中，包括通过溅射法在所述金属氧化物半导体层上依次形成所述第一保护层和所述源漏极层。
其中，所述金属氧化物采用IGZO材料，所述第一保护层采用GZO材料。
其中，所述源漏极层包括层叠设置的金属层和第二保护层，形成所述源漏极层步骤中，包括通过溅射法在所述第一保护层上依次形成金属层和第二保护层。
其中，所述第二保护层采用GZO材料。
本申请提供一种阵列基板，包括依次层叠设置于基板的栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层，所述源漏极层上设有通向所述第一保护层的沟道，所述第一保护层之露出于所述沟道的部分与所述第一保护层之其余部分隔断。
其中，所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分之间设有狭缝，所述狭缝隔断所述第一保护层之露出于所述镂空区的部 分与所述第一保护层之其余部分。
其中，所述沟道为梯形沟道。
其中，所述源漏极层包括层叠设置的金属层和第二保护层，所述金属层介于所述第一保护层和所述第二保护层之间。
其中，所述第二保护层采用GZO材料。
其中，所述金属氧化物采用IGZO材料，所述第一保护层采用GZO材料。
其中，所述源漏极层采用铜或铜合金材料制成。
本申请实施例具有如下优点或有益效果：
本申请的阵列基板的制造方法中，对源漏极层和第一保护层进行两次蚀刻，第一次先将源漏极层完全蚀刻，然后第二次通过干法蚀刻的方法对第一保护层进行蚀刻，以使得所述金属氧化物半导体层部分露出于所述第一保护层，干法蚀刻过程中所述第一保护层可以保护所述金属氧化物半导体层不被蚀刻，避免金属氧化物半导体层表面被损毁(形成尖角和凹坑)，保证了电子迁移率，提升阵列基板的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的制造方法流程图。
图2～图5为图1的所示制造方法的过程示意图。
图6为本申请实施例提供的阵列基板。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请以下实施例中所采用的序数限定词，第一、第二等仅是为了清楚地 说明本申请中相似的特征的区别性的用语，不代表相应的特征的排列顺序或者使用顺序。
本申请的制造方法生产出的阵列基板可以应用于液晶显示屏或者有机显示屏中。本发明实施例涉及的柔性显示屏用于但不限于手机、平板电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)或电子阅读器等，本发明实施例对此不作具体限定。
请参阅图1，图1为本申请实施例提供的一种阵列基板的制造方法流程图。本申请提供的制造方法主要包括如下步骤：
S001：在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层。
具体的，请结合参阅图2。所述基板10为透明玻璃基板，在所述基板10上沉积第一金属薄膜。所述第一金属薄膜可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。通过构图工艺利用普通光阻层形成栅线(图未示出)、公共电极线(图未示出)和栅极20的图形。然后在此基础上通过PECVD(等离子体增强化学气相沉积法)方法沉积栅极绝缘层30，栅极绝缘层30可以选用氧化物、氮化物或者氧氮化合物等。
然后，在栅绝缘层上通过溅射或热蒸发的方法沉积金属氧化物半导体层40，金属氧化物半导体层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO：F、In2O3：Sn、In2O3：Mo、Cd2SnO4、ZnO：Al、TiO2：Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。
接着，在基板10上采用溅射或热蒸发的方法依次形成第一保护层50和源漏极层60。所述第一保护层50的作用在于防止源漏极层60中的金属扩散到金属氧化物半导体层40中，以免降低阵列基板的性能。
优选的，所述第一保护层50可以采用金属氧化物半导体层50不同的材料制成，例如可以为GZO材料。优选的，所述源漏极层60包括层叠设置的金属层61和第二保护层62。可以通过溅射法或热蒸发的方法在所述第一保护层50上依次形成金属层61和第二保护层62。
可选的，所述第二保护层62材料可以与所述第一保护层50材料相同。所述第二保护层62用于防止所述金属层61被氧化。所述金属层61可以选用Cr、 W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。
可选的，所述第一保护层50和所述第二保护层的厚度皆为300A。所述金属层61的厚度可以为2000A。
可选的，所述金属氧化物半导体层40的厚度为300A。
S002：在所述源漏极层上覆盖光阻层，所述光阻层上设置有镂空区。
具体的，请结合参阅图3。在所述第二保护层上涂覆光刻胶；提供一掩膜版遮盖在所述光刻胶上方。从而通过光刻工艺形成光阻层70。盖光阻层70上形成有镂空区71。所述光阻层70覆盖于所述第二保护层62上方。所述第二保护层62有部分区域露出于所述光阻层70上的镂空区71。以便接下来进行蚀刻形成沟道65。
S003：去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层。
请结合参阅图4，在本步骤中，需要形成沟道65，以及在所述源漏极层60上形成了源极63和漏极64。具体的，可以通过湿法蚀刻的方法在所述源漏极层上形成沟道65，同时藉由所述沟道形成源极63和漏极64。
进一步具体的，可以在所述光阻层70上喷淋蚀刻液，蚀刻液经由光阻层70上的镂空区71依次对第二保护层62和金属层61进行蚀刻，直至将所述金属层61之位于镂空区71正下方的部分完全蚀刻，露出第一保护层50。在此步骤中，可以通过控制蚀刻液浓度和蚀刻时间来控制蚀刻的深度，其中，所述蚀刻液浓度和所述蚀刻时间可以预先设定。但实际生产过程中很难正好蚀刻到所述第一保护层50处。鉴于第一保护层50的厚度对阵列基板的性能没有影响，为保证将金属层61完全蚀刻，可以使得蚀刻液在第一保护层50蚀刻一段时间，以便将金属层61完全蚀刻后，清除蚀刻液。此时，在所述源漏极层60上形成了源极63、漏极64及介于二者之间的沟道65。可以理解的是，此时沟道65的底部即为第一保护层50。可以理解的是，所述沟道65为梯形。这是由于蚀刻液经镂空区71进入第二保护层62和金属层61表面后会向两侧扩散。并且越往上其接触蚀刻液的时间也就越长，蚀刻液往两侧蚀刻的量就越大，因此在源漏极层60上会形成梯形沟道65。
优选的，所述蚀刻液可以选用H2O2、金属螯合剂或有机酸等。
S004：对所述第一保护层之露出于所述镂空区的部分进行干法蚀刻，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分隔断。
具体的，请结合参阅图5。可以将蚀刻气体置于低压环境，并施以电压，将蚀刻气体激发成电浆，再对所述第一保护层50进行轰击。以蚀刻第一保护层50。在电浆对第一保护层50进行轰击过程中，电浆进入沟道65后，会在在沟道65的侧壁651上产生反射反弹。因此，在沟道65底部(第一保护层50)与侧壁651交界处会先形成狭缝66，临近交界处相对中间位置的蚀刻速度更快。因此交界处下方的金属氧化物半导体层40先露出于所述第一保护层50上的狭缝66。换而言之，所述第一保护层50之露出于所述镂空区71的部分51与所述第一保护层50之其余部分52之间形成狭缝66，所述狭缝66隔断所述第一保护层50之露出于所述镂空区71的部分51与所述第一保护层之其余部分52。所述金属氧化物半导体层40部分露出于所述狭缝66。对于金属氧化物半导体层40只要有一部分露出于所述第一保护层50，则电子迁移的通道就可以形成。也就是说，无需将第一保护层50完全刻蚀，在进行干法蚀刻过程中，第一保护层50可以起到保护金属氧化物半导体层40的作用，避免金属氧化物半导体层40由于蚀刻造成的表面质量下降、影响电子迁移速率等，从而提升阵列基本的性能。
请参阅图6，当狭缝66形成后，可以停止干法蚀刻，并去除所述光阻层70，并继续后续步骤，完成阵列基板的制作。后续步骤不是本发明保护的重点，此处不再赘述。
优选的，所述蚀刻气体可以适当的选用，例如选择SF6、O2、Cl2、He、Ar(氩气)中一种或任意几种的混合等。
本申请的阵列基板的制造方法中，对源漏极层和第一保护层进行两次蚀刻，第一次先将源漏极层完全蚀刻，然后第二次通过干法蚀刻的方法对第一保护层进行蚀刻，以使得所述金属氧化物半导体层部分露出于所述第一保护层，干法蚀刻过程中所述第一保护层可以保护所述金属氧化物半导体层不被蚀刻，避免金属氧化物半导体层表面被损毁(形成尖角和凹坑)，保证了金属氧化物半导体层的表面质量，保证了电子迁移率，提升阵列基板的性能。
请参阅图6，本申请还提供一种阵列基板100。阵列基板100包括依次层 叠设置于基板10的栅极20、栅极绝缘层30、金属氧化物半导体层40、第一保护层50和源漏极层60。所述源漏极层60上设有通向所述第一保护层50的沟道65。进一步的，源漏极层60包括源极63和漏极64，所述沟道65设置于所述源极63和所述漏极64之间。所述第一保护层50之露出于所述沟道的部分51与所述第一保护层50之其余部分52隔断。
本申请的阵列基板中，在金属氧化物半导体层和栅极绝缘层上覆盖有第一保护层，并且第一保护层位于沟道中的部分与其保护层其他部分隔断，使得第一保护层位于沟道中的部分可以保护金属氧化物半导体层在形成沟道过程中不受损伤，保证了金属氧化物半导体层的表面质量，保证了电子迁移率，提升阵列基板的性能。
进一步的，所述第一保护层50之露出于所述镂空区的部分51与所述第一保护层之其余部分52之间设有狭缝66，所述狭缝隔断所述第一保护层之露出于所述镂空区的部分51与所述第一保护层之其余部分52。
具体的，所述沟道65为梯形沟道。湿法蚀刻所述沟道65时，由于蚀刻液经镂空区71进入第二保护层62和金属层61表面后会向两侧扩散。并且越往上其接触蚀刻液的时间也就越长，蚀刻液往两侧蚀刻的量就越大，因此在源漏极层60上会形成梯形沟道65。
优选的，所述第一保护层50可以采用与金属氧化物半导体层50不同的材料制成，例如可以为GZO材料。优选的，所述源漏极层60包括层叠设置的金属层61和第二保护层62。可以通过溅射法或热蒸发的方法在所述第一保护层50上依次形成金属层61和第二保护层62。
可选的，所述第二保护层62材料可以与所述第一保护层50材料相同。所述第二保护层62用于防止所述金属层61被氧化。所述金属层61可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种阵列基扳的制造方法，其特征在于，所述方法包括：
    在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层；
    在所述源漏极层上形成光阻层，所述光阻层上设置有镂空区；
    去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层；
    对所述第一保护层之露出于所述镂空区的部分进行干法蚀刻，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分隔断。
  2. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述对所述第一保护层之露出于所述镂空区的部分进行干法蚀刻，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分隔断步骤中，包括使用蚀刻气体对所述第一保护层进行轰击，以使得所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分之间形成狭缝，所述狭缝隔断所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分。
  3. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。
  4. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，包括在所述源漏极层喷淋蚀刻液进行蚀刻，在所述第一保护层完全露出后去除所述蚀刻液。
  5. 如权利要求4所述的阵列基板的制造方法，其特征在于，所述去除所述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，包括在所述源漏极层喷淋蚀刻液进行蚀刻，以在所述源漏极层上形成梯形沟道，在所述第一保护层露出于所述梯形沟道后去除所述蚀刻液。
  6. 如权利要求5所述的阵列基板的制造方法，其特征在于，所述去除所 述源漏极层之露出于所述镂空区的部分，以露出所述第一保护层步骤中，通过控制所述蚀刻液的浓度及所述蚀刻液在所述源漏极层的蚀刻时间，使得所述第一保护层完全露出于所述梯形沟道，其中，所述蚀刻液的浓度和所述蚀刻时间为预设值。
  7. 如权利要求4所述的阵列基板的制造方法，其特征在于，所述蚀刻液包括H2O2、金属螯合剂或有机酸。
  8. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层步骤中，包括通过溅射法在所述金属氧化物半导体层上依次形成所述第一保护层和所述源漏极层。
  9. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述金属氧化物采用IGZO材料，所述第一保护层采用GZO材料。
  10. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述源漏极层包括层叠设置的金属层和第二保护层，形成所述源漏极层步骤中，包括通过溅射法在所述第一保护层上依次形成金属层和第二保护层。
  11. 如权利要求10所述的阵列基板的制造方法，其特征在于，所述第二保护层采用GZO材料。
  12. 一种阵列基板，其特征在于，包括依次层叠设置于基板的栅极、栅极绝缘层、金属氧化物半导体层、第一保护层和源漏极层，所述源漏极层上设有通向所述第一保护层的沟道，所述第一保护层之露出于所述沟道的部分与所述第一保护层之其余部分隔断。
  13. 如权利要求12所述的阵列基板，其特征在于，所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分之间设有狭缝，所述狭缝隔断所述第一保护层之露出于所述镂空区的部分与所述第一保护层之其余部分。
  14. 如权利要求12所述的阵列基板，其特征在于，所述沟道为梯形沟道。
  15. 如权利要求12所述的阵列基板，其特征在于，所述源漏极层包括层叠设置的金属层和第二保护层，所述金属层介于所述第一保护层和所述第二保护层之间。
  16. 如权利要求14所述的阵列基板，其特征在于，所述第二保护层采用GZO材料。
  17. 如权利要求12所述的阵列基板，其特征在于，所述金属氧化物采用IGZO材料，所述第一保护层采用GZO材料。
  18. 如权利要求12所述的阵列基板，其特征在于，所述源漏极层采用铜或铜合金材料制成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257879A (zh) * 2021-05-25 2021-08-13 厦门天马微电子有限公司 一种阵列基板及显示面板

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111740001B (zh) * 2020-01-20 2022-09-09 绍兴中芯集成电路制造股份有限公司 压电器件及其形成方法
CN114695529A (zh) * 2022-03-16 2022-07-01 Tcl华星光电技术有限公司 Tft基板及其制作方法、液晶显示面板和oled显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110263079A1 (en) * 2010-04-23 2011-10-27 Applies Materials, Inc. Interface protection layaer used in a thin film transistor structure
CN103855030A (zh) * 2012-11-29 2014-06-11 乐金显示有限公司 制造氧化物薄膜晶体管的方法
CN104134671A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 薄膜晶体管阵列基板及其制造方法
US20150102317A1 (en) * 2013-10-15 2015-04-16 Samsung Display Co., Ltd. Thin film transistor substrates, display devices and methods of manufacturing display devices
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101410926B1 (ko) * 2007-02-16 2014-06-24 삼성전자주식회사 박막 트랜지스터 및 그 제조방법
TWI513002B (zh) * 2012-06-05 2015-12-11 Innocom Tech Shenzhen Co Ltd 薄膜電晶體基板以及顯示器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110263079A1 (en) * 2010-04-23 2011-10-27 Applies Materials, Inc. Interface protection layaer used in a thin film transistor structure
CN103855030A (zh) * 2012-11-29 2014-06-11 乐金显示有限公司 制造氧化物薄膜晶体管的方法
CN104134671A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 薄膜晶体管阵列基板及其制造方法
US20150102317A1 (en) * 2013-10-15 2015-04-16 Samsung Display Co., Ltd. Thin film transistor substrates, display devices and methods of manufacturing display devices
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257879A (zh) * 2021-05-25 2021-08-13 厦门天马微电子有限公司 一种阵列基板及显示面板
CN113257879B (zh) * 2021-05-25 2022-07-15 厦门天马微电子有限公司 一种阵列基板及显示面板

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