WO2018090426A1 - 具有连续侧墙的半导体设置及其制造方法 - Google Patents

具有连续侧墙的半导体设置及其制造方法 Download PDF

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Publication number
WO2018090426A1
WO2018090426A1 PCT/CN2016/111274 CN2016111274W WO2018090426A1 WO 2018090426 A1 WO2018090426 A1 WO 2018090426A1 CN 2016111274 W CN2016111274 W CN 2016111274W WO 2018090426 A1 WO2018090426 A1 WO 2018090426A1
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dielectric
gate
substrate
gate stack
forming
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French (fr)
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朱慧珑
张严波
钟汇才
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US16/461,330 priority Critical patent/US10833086B2/en
Publication of WO2018090426A1 publication Critical patent/WO2018090426A1/zh
Anticipated expiration legal-status Critical
Priority to US17/039,770 priority patent/US11251184B2/en
Priority to US17/039,755 priority patent/US11251183B2/en
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular to semiconductor arrangements having continuous sidewall spacers and methods of fabricating the same, and electronic devices including such semiconductor arrangements.
  • FinFETs typically include vertical fins on the substrate and a gate stack that intersects the fins.
  • a channel may be formed on the sidewall of the fin.
  • ridges each extending continuously respectively may be formed on the substrate. Depending on the layout design, these continuously extending ridges can be patterned into different portions that subsequently form the fins of the device.
  • gate lines each extending continuously may be formed on the substrate. Depending on the layout design, these continuously extending gate lines can be patterned into separate portions that then form the gate of the device. On the sidewalls of the gate, sidewalls can be formed around the gate of the device.
  • FIG. 1 is a top view showing a conventional semiconductor arrangement including a FinFET.
  • the semiconductor arrangement includes a plurality of fins 101 extending in a first direction (eg, a horizontal direction in the drawing) on a substrate and a second direction (eg, perpendicular) that intersects the first direction (eg, a plurality of gate stacks 103-1 extending in the vertical direction in the figure.
  • the gate stack may include, for example, a gate dielectric layer and a gate electrode layer. Where the fins intersect the gate stack, a channel can be created; and on both sides of the channel region of the fin, source and drain regions can be formed separately (thereby obtaining a FinFET). Side walls 105 surrounding the respective gate stacks 103-1 are formed on the sidewalls of the respective gate stacks 103-1.
  • the dummy gate 103-2 may be formed for the purpose of patterning convenience and electrical isolation.
  • the dummy gate 103-2 and the gate stack 103-1 may include the same configuration so as to be formed together with the gate stack 103-1 (due Thus, a sidewall spacer around the dummy gate 103-2 may also be formed on the sidewall of the dummy gate 103-2.
  • the dummy gate 103-2 may not intersect the continuous fins and thus does not actually constitute the device. For example, in the example of FIG. 1, the dummy gate 103-2 is formed to intersect the gap between the fins 101 in the first direction.
  • a gap between the spacers 105 on the substrate may be filled with a dielectric such as an interlayer dielectric layer (ILD) (not shown in the drawings for clarity), such as an oxide, particularly in a back gate process.
  • ILD interlayer dielectric layer
  • the top surface of the ILD may be substantially flush with the top surface of the gate stack 103-1, the dummy gate 103-2, and the sidewall 105, for example, by a planarization process such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • contact holes can be etched in the ILD, which can extend between opposing sidewalls.
  • a contact material such as a metal such as tungsten (W) may be deposited on the substrate and planarized such as CMP.
  • the CMP can stop at the ILD or the side wall.
  • the contact material is filled in the contact hole to form the contact portion 107.
  • the contact portions on opposite sides (left and right sides in the drawing) of the dummy gate 103-2 may be electrically separated by the side walls 105 of the dummy gate 103-2.
  • this structure has the following disadvantages.
  • etching the ILD eg, isotropic etching
  • ILD isotropic etching
  • these gaps may then be filled with contact material, causing unnecessary electrical shorts between the contacts, as shown at 107X in FIG.
  • the edges of the dummy gates 103-2 are not aligned with the ends of the fins 101. This causes an increase in the spacing between the gate ends, thereby reducing the integration density.
  • an object of the present disclosure is at least in part to provide a semiconductor arrangement and a method of fabricating the same, and an electronic device including such a semiconductor arrangement, wherein the sidewall spacers may extend continuously in the extending direction of the gate.
  • a semiconductor arrangement comprising: a substrate; a plurality of fins formed on the substrate extending in a first direction; and a second formed on the substrate crossing the first direction a plurality of gate stacks extending in a direction and a dummy gate extending in a second direction and composed of a dielectric, wherein each gate stack intersects at least one fin; sidewalls formed on sidewalls of the gate stack and sidewalls of the dummy gate; Provided between the first gate stack and the second gate stack aligned in the second direction for stacking the first gate and the first The second gate stacks the electrically isolated dielectric, wherein the sidewalls of the first gate stack and the second gate stack extend integrally, and the dielectric is disposed in a space surrounded by the integrally extended sidewalls of the first gate stack and the second gate stack.
  • the at least a portion of the first gate stack and the second gate stack in the second direction are spaced apart by a line spacing that can be achieved by photolithography in the
  • a method of fabricating a semiconductor arrangement comprising: forming a plurality of ridges each extending continuously in a first direction on a substrate; forming respective ridges on the substrate a plurality of sacrificial gate lines extending continuously in a second direction intersecting to intersect the plurality of ridges; sidewalls surrounding each of the sacrificial gate lines are formed on sidewalls of each of the sacrificial gate lines; forming on the substrate a first dielectric, planarized to expose the sacrificial gate line; a sacrificial gate line removed to expose the underlying ridge; a second dielectric filled into the space within the sidewall; a portion of the second dielectric is masked by the mask and exposed a second portion of the second dielectric, wherein, at the at least one sacrificial gate line, the mask covers a second dielectric of a certain dimension in the second direction; removing the exposed second dielectric to expose the underlying ridge
  • a method of fabricating a semiconductor arrangement comprising: forming a plurality of ridges each extending continuously in a first direction on a substrate; forming respective ridges on the substrate a plurality of sacrificial gate lines extending continuously in a second direction intersecting to intersect the plurality of ridges; sidewalls surrounding each of the sacrificial gate lines are formed on sidewalls of each of the sacrificial gate lines; forming on the substrate a first dielectric flattening to expose the sacrificial gate line; removing the sacrificial gate line to expose the underlying ridge; filling a space in the sidewall with a second dielectric; masking a portion of the second portion with the first mask Dielectric and exposing the first portion of the second dielectric; removing the exposed first portion of the second dielectric to expose the underlying ridge; forming a first gate stack in the space left by the removal of the first portion of the second dielectric;
  • the second mask shield
  • an electronic device including the semiconductor arrangement described above.
  • the sidewall spacers may extend continuously between the opposing (pseudo) gates, even if the (pseudo) gates are not continuous with each other, which helps to avoid (self-alignment) electrical shorts between the contacts.
  • the spacing between the ends of the gate stack is defined by the use of mask lines (rather than the spacing between the mask lines), which may be smaller than the line spacing achievable by lithography in the fabrication process.
  • the isolation dielectric between the ends of the gate stack is defined by utilizing register overlaps between the masks (rather than mask lines) so that the dimensions of the isolation dielectric can be less than the key lithography process can achieve. Line width (CD).
  • the ends of the fins adjacent to the dummy grid can be self-aligned to the inner walls of the respective side walls, thereby contributing to an increase in integration density.
  • FIG. 1 is a top view showing a conventional arrangement including a FinFET
  • FIG. 2 is a top view showing a semiconductor arrangement in accordance with an embodiment of the present disclosure
  • 3(a)-23(b) are diagrams showing a flow of manufacturing a semiconductor arrangement in accordance with an embodiment of the present disclosure
  • 24(a)-26 are schematic diagrams showing partial stages in a process of fabricating a semiconductor arrangement in accordance with another embodiment of the present disclosure.
  • FIG. 27 illustrates stress enhancement that can be achieved by a stress retention mechanism in accordance with an embodiment of the present disclosure
  • 28(a)-33 show schematic diagrams of partial stages in a process of fabricating a semiconductor arrangement in accordance with another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • ridges each extending in the first direction may be formed on the substrate, and second, respectively, formed on the ridges respectively crossing (eg, substantially perpendicular) to the first direction A grid line that extends continuously to intersect the ridge.
  • sidewalls surrounding the respective gate lines may be formed on sidewalls of the respective gate lines.
  • the side walls can extend continuously over the length of the grid lines (in the second direction).
  • the ridges can be patterned in the design layout and then the grid lines are formed.
  • the gate lines can be formed directly on the continuously extending ridges, and the ridges can be patterned in a subsequent design in a subsequent step, as described below.
  • the latter case will be described as an example.
  • a first dielectric eg, an interlayer dielectric layer (ILD)
  • ILD interlayer dielectric layer
  • the first dielectric may be planarized to expose the gate lines (eg, planarization may stop at the gate lines).
  • the separation of the grid lines can be performed.
  • the gate lines can be removed (thus, such gate lines can be referred to as "sacrificial" gate lines). Due to the removal of the sacrificial gate lines, the underlying ridges are exposed. Depending on the layout design, the ridges can be separated at certain areas (if the ridges have been separated before the grid lines are formed, then no need to do this).
  • a portion of the exposed ridges may be selectively etched through the space surrounded by the side walls to separate the respective ridges into different portions (separated in electrical properties, possibly physically still partially continuous) These parts then form the fins of the different devices.
  • the ends of these portions or fins may be self-aligned to the inner wall of the side wall. Then, you can fill in the space inside the side wall
  • the dielectric is such that different portions of the ridges can be electrically isolated from one another.
  • the second dielectric within the sidewalls can be removed to expose the underlying ridges or fins.
  • the gate stack can then be formed in the space left due to the removal of the second dielectric.
  • the gate stack can intersect the underlying fins and thus form the corresponding device and FinFET.
  • the second medium remaining in the side walls may form a dummy grid.
  • the sidewalls on the sidewalls of the gate stack aligned in the second direction can extend continuously in one piece, even if the gate stacks are not between each other continuous.
  • the ends of the fins may be self-aligned to the inner walls of the respective side walls.
  • the gate-end spacing or the reduction in the dimension of the dielectric filled in the spacer can be achieved by appropriately utilizing the mask.
  • a mask can be utilized to shield the second dielectric.
  • the mask can mask a second dielectric of a certain dimension.
  • the spacing between the ends of the gate stack formed on opposite sides of the remaining second dielectric will be defined by the dimension and thus may be less than the line spacing achievable by lithography in the fabrication process.
  • different masks can be used in different portions to mask different portions of the second dielectric to effect selective etching of different regions of the second dielectric, respectively. There may be a registration overlap between these masks. Due to the registration overlap, a second dielectric of a certain size can be left, which can be smaller than the critical line width (CD) that can be achieved by lithography in the fabrication process.
  • CD critical line width
  • FIG. 2 is a top view showing a semiconductor arrangement in accordance with an embodiment of the present disclosure.
  • the semiconductor arrangement is made, for example, according to the above process.
  • the semiconductor arrangement may include a plurality of fins 201 extending in a first direction (eg, a horizontal direction in the drawing) on a substrate and intersecting (eg, perpendicular) with the first direction
  • the gate stacks 203-1, 203-1' may include a gate dielectric layer and a gate electrode layer.
  • the dummy gate 203-2 may include a dielectric (eg, the second dielectric described above).
  • Side walls 205 are formed on the sidewalls of the gate stack and the dummy gate.
  • the side wall 205 can be a ring structure.
  • the upper and lower ends of the side wall 205 are not shown (it can be considered that they are in the area shown in the drawing) Outside).
  • the respective gate stacks and/or dummy gates are aligned with each other along the extending direction of the side walls (ie, the second direction) (they together occupy the position of the sacrificial gate line originally surrounded by the side wall) .
  • the gate stacks 203-1, 203-1' intersect the fins 201 to form a corresponding device, a FinFET.
  • the ends of the fins 201 are aligned with the inner walls of the respective side walls 205 as indicated by the arrows in the figure, the dummy gates 203-2 do not actually intersect the fins, and their opposite sides (figure The opposite fins in the middle and left sides are electrically isolated from each other.
  • a spacer 203-2' may be provided between the opposing gate stacks 203-1 and 203-1'.
  • the isolation portion 203-2' may include the same dielectric as the dummy gate 203-2, for example, in the above process due to the retention of the second dielectric at the region of the isolation portion.
  • the semiconductor arrangement further includes a contact portion 207 formed in a self-aligned manner.
  • the contact portion 207 can extend between adjacent side walls 205. Since the side walls 205 extend continuously, the contact portions 207 on opposite sides of the same side wall 205 can be reliably electrically isolated by the continuously extending side walls 205.
  • 3(a)-23(b) are schematic diagrams showing a flow of fabricating a semiconductor arrangement in accordance with an embodiment of the present disclosure.
  • Fig. 3(a), 3(b) and 3(c) (Fig. 3(a) is a plan view, Fig. 3(b) is a cross-sectional view taken along line AA' in Fig. 3(a), Fig. 3(c)
  • the substrate 1001 is provided as shown in the cross-sectional view taken along line BB' in Fig. 3(a).
  • the substrate 1001 may be various forms of substrates including, but not limited to, bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. In the following description, a bulk Si substrate will be described as an example for convenience of explanation.
  • various well regions such as p-wells and n-wells as shown in the drawing, can be formed, for example, by ion implantation.
  • a p-well can be formed over the entire substrate region and an n-well can be embedded in a portion of the p-well.
  • an n-type device can be formed on the p-well, and a p-type device can be formed on the n-well.
  • a ridge extending in the first direction (for example, the horizontal direction in FIGS. 3(a) and 3(b), and the direction perpendicular to the paper surface in FIG. 3(c)) is formed.
  • 1001F a ridge extending in the first direction (for example, the horizontal direction in FIGS. 3(a) and 3(b), and the direction perpendicular to the paper surface in FIG. 3(c)) is formed.
  • 1001F a groove may be formed in the substrate 1001 by patterning the substrate 1001, and a portion between adjacent grooves protrudes with respect to the groove to form a ridge.
  • the ridge 1001F can extend in parallel and can Have the same or different spacing and / or width.
  • An isolation layer 1009 such as an oxide such as silicon oxide, may be formed over the substrate 1001 to fill the recesses to surround the bottom of the ridges 1001F.
  • the portion of the ridge 1001F above the top surface of the isolation layer 1009 can then form the fins of the device, referred to herein as "fin lines.”
  • the fin line is also indicated by "1001F”.
  • a buried oxide (BOX) layer in the SOI substrate can serve as an isolation layer.
  • the fin line may be separated into different portions to form a fin layout, and then an isolation layer is formed to define the active region.
  • the continuously extending fin lines may be retained to form the isolation layer directly.
  • the fin lines are separated again to form the final active area layout.
  • the latter case will be described as an example.
  • a punch-through blocking layer may be formed in a lower portion of the fin line in the ridge.
  • a p-type PTSL p-PTSL
  • an n-type PTSL can be formed (n -PTSL).
  • the p-type doping concentration in the p-PTSL may be higher than the p-type doping concentration in the p-well, and the n-type doping concentration in the n-PTSL may be higher than the n-type doping concentration in the n-well.
  • FIG. 4(a) is a plan view
  • Fig. 4(b) is a cross-sectional view taken along line AA' in Fig. 4(a)
  • Fig. 4 (c) is a cross-sectional view taken along line BB' in FIG. 4(a)) and may be formed on the substrate 1001 (more specifically, on the isolation layer 1009) to intersect with the first direction (for example, substantially The second direction of the vertical direction (for example, the vertical direction in FIG. 4(a), the direction perpendicular to the paper surface in FIG. 4(b), the horizontal direction in FIG. 4(c)) and thus the fin line 1001F Intersecting sacrificial gate lines 1003.
  • the etch stop layer 1011 may be formed first.
  • the etch stop layer 1011 of the oxide may be formed by deposition or thermal oxidation to a thickness of about 1-5 nm.
  • an etch stop layer 1011 is formed on the surface of the fin line 1001F, for example, by thermal oxidation; and in FIG. 4(a), for convenience, The etch stop layer 1011 is not shown.
  • Sacrificial gate line material can then be formed over substrate 1001, such as by deposition.
  • the sacrificial gate line material for example, including polysilicon or amorphous silicon, may have a thickness of about 150-300 nm.
  • the formed sacrificial gate line material may be planarized, such as chemical mechanical polishing (CMP), to flatten its top surface and remain on the fins.
  • CMP chemical mechanical polishing
  • the thickness above the top surface of line 1001F can be about 70-150 nm.
  • the sacrificial gate line material can then be patterned into a series of sacrificial gate lines 1003 by, for example, photolithography.
  • the sacrificial gate lines 1003 may extend in parallel and may have the same or different pitch and/or width.
  • the hard mask layer 1013 is utilized for etching of the sacrificial gate line material such as RIE (selective etching of the isolation layer 1009 and/or the etch stop layer 1011 with respect to the oxide).
  • the hard mask layer 1013 may include, for example, a nitride (eg, silicon nitride) having a thickness of about 50-150 nm. The process of etching using a hard mask will not be described herein.
  • the spacer 1005 may be formed by a spacer forming process.
  • the spacer 1005 may, for example, comprise a nitride having a thickness of about 3-10 nm. As described above, the spacer 1005 surrounds each of the sacrificial gate lines 1003 to form a ring shape. In the plan view of Fig. 4 (a), the upper and lower ends of the side wall 1005 are not shown.
  • a first dielectric such as an oxide may be filled at a space between each of the sacrificial gate lines 1003 and their respective spacers 1005 to shield portions of the fin lines 1001F exposed by the respective sacrificial gate lines 1003 and their respective spacers 1005.
  • an oxide may be deposited on the structures shown in FIGS. 4(a), 4(b), and 4(c) and planarized, such as CMP.
  • the CMP may stop at the sacrificial gate line 1003, thereby exposing the sacrificial gate line 1003.
  • the first dielectric 1015 thus filled may also help to maintain stress or prevent stress release in subsequent processing.
  • the definition of the active region can be performed, that is, the fin line 1001F is separated according to the layout design.
  • the side wall 1005 may be utilized to define the end of the fin obtained by separating the fin line 1001F.
  • FIG. 6(a) is a plan view
  • Fig. 6(b) is a cross-sectional view taken along line AA' in Fig. 6(a)
  • Etching with respect to the oxide isolation layer 1009, the etch stop layer 1011 and the first dielectric 1015, and the nitride spacers 1005 such as wet etching or vapor phase etching
  • the sacrificial gate line 1003 is removed, thereby being in the sidewall 1005
  • a groove T is formed inside.
  • the etching is preferably isotropic etching to expose the inner wall of the side wall 1005 well.
  • the fin line 1001F currently covered by the etch stop layer 1011) is exposed.
  • the exposed fin line 1001F a portion of it may be separated according to the layout design to form a separate active region or fin. For example, this can mask the fins that do not need to be separated by photoresist and expose The fin lines that need to be separated are then selectively etched.
  • Figs. 7(a) and 7(b) are plan views
  • Fig. 7(b) is a cross-sectional view taken along line AA' in Fig. 7(a)
  • the photoresist 1017 is formed on the structures shown in a) and 6(b) and patterned (for example, by exposure and development) to expose the first and third sacrificial gate lines when counting from left to right.
  • the trench T shields the trench T corresponding to the second and fourth sacrificial gate lines.
  • the present disclosure Not limited to this.
  • a portion of the trench T can be shielded while another portion can be exposed.
  • the trench T to be exposed or a part thereof is determined according to the layout design.
  • the fin line 1001F can be separated via the trench T.
  • the etch stop layer 1011 and the ridges 1001F may be selectively etched by reactive ion etching (RIE). Etching of the ridges 1001F may sever the fin lines (ie, the portions of the ridges above the top surface of the isolation layer 1009). Thus, the fin line 1001F is separated into different portions which can then constitute the fins of the device. Hereinafter, the fin is still indicated by "1001F".
  • the etch of the ridge 1001F can pass through the PTSL and stop in the n-well or p-well. This helps to ensure electrical isolation between the separate fins. Thereafter, the photoresist 1017 can be removed.
  • the side wall 1005 is similar to the mask when the fin line 1001F is separated, the ends of the separated rear fins are self-aligned to the inner wall of the side wall 1005. This helps to save area on the substrate and thus reduce manufacturing costs.
  • FIGS. 9(a) and 9(b) are plan views
  • FIG. 9(b) is a cross-sectional view taken along line AA' in FIG. 9(a)
  • the side wall 1005 may be A second dielectric 1019 is filled in the inner space, in particular between the opposite ends of the separated fins 1001F.
  • an oxynitride e.g., silicon oxynitride
  • CMP planarized, such as CMP, which may stop at the first dielectric 1015.
  • the second dielectric 1019 is surrounded by the sidewall 1005 to form a dummy gate.
  • the dummy gate is formed by filling the recess with a second dielectric.
  • the second dielectric may be deposited first on the sidewalls and the bottom wall of the recess to form a U-shaped structure with the two opposing inner sidewalls gradually coming together as the deposition progresses. Since the opening of the groove is small, the opposite inner side walls of the final U-shaped structure may not completely close, but there is a certain gap. That is, in the final dummy gate, such a gap may exist such that the dummy gate still exhibits a U-shaped structure. This structure can be seen in transmission electron microscopy (TEM) photographs.
  • TEM transmission electron microscopy
  • a stressed dielectric material can be used for the dummy gate to create stress in the fins to enhance device performance. For example, for a p-type device, the dummy gate can be stressed; for an n-type device, the dummy gate can be tensile stressed.
  • a true gate stack can be formed in the space inside the side wall 1005 in accordance with the layout design. For example, this can be done by removing a portion of the second dielectric 1019 to expose the underlying fins 1001F and forming a gate stack in the space left by the removal of the second dielectric 1019. The formed gate stack intersects the underlying fin 1001F to define a FinFET.
  • Figures 10(a) and 10(b) are a top view
  • Figure 10(b) is a cross-sectional view along line AA' in Figure 10(a)
  • the photoresist 1021 is formed on the structure shown in FIG. 9(b) and patterned to shield the n-type device region (for example, the upper left portion and the right portion in FIG. 10(a)) to expose the p-type device region (for example, , in the lower left part of Figure 10 (a).
  • the second dielectric 1019 inside the sidewall 1005 may be removed by selective etching of the second dielectric 1019, and a gate may be formed in a space left inside the sidewall 1005 due to the removal of the second dielectric 1019.
  • Stack to make a FinFET may be made by selective etching of the second dielectric 1019, and a gate may be formed in a space left inside the sidewall 1005 due to the removal of the second dielectric 1019.
  • a strain source leak technique may also be employed herein.
  • the photoresist 1021 shown in FIGS. 10(a) and 10(b) can be used as a mask to selectively etch the first dielectric 1015 of the oxide and the etch stop layer 1011 such as RIE to expose the underlying layer. Fin 1001F. Thus, a portion (corresponding to the source/drain regions) in which the fins 1001F extend between the adjacent spacers 1005 in the p-type device region is exposed. Thereafter, the photoresist 1021 can be removed.
  • FIGS. 11(a) and 11(b) are plan views
  • FIG. 11(b) is a cross-sectional view taken along line AA' in FIG. 11(a)
  • the fin 1001F can be performed.
  • a selective etching such as RIE is performed to remove at least a portion thereof to make it concave.
  • the fin 1001F may be recessed into the n-PTSL, ie, the portion of the fin 1001F above the n-PTSL is removed.
  • an additional semiconductor material 1023 serving as a source/drain region may be epitaxially grown with the remainder of the fin 1001F as a seed.
  • the source/drain regions 1023 may include SiGe (atom percentage of Ge is about 30-75%) to apply compressive stress to the fins 1001F of Si serving as a channel region, thereby improving device performance.
  • the semiconductor material 1023 when the semiconductor material 1023 is grown, it may be doped in situ, such as p-type doping, with a doping concentration of about 1E19-1E21 cm -3 .
  • the top surface of the grown semiconductor material 1023 may be higher than the top surface of the fin 1001F to better stress the fin 1001F; on the other hand, may be lower than the top surface of the sidewall 1005 or the dummy gate 1019 so that A stress holding layer is formed thereon.
  • the grown semiconductor material 1023 can assume a ridge shape such as fin 1001F.
  • a third dielectric 1025 such as an oxide may be formed on, for example, by deposition in FIGS. 11(a) and 11(b), and It performs a planarization process such as CMP, and the CMP can be stopped at the sidewall 1005.
  • CMP planarization process
  • the formed third dielectric 1025 fills the space between adjacent sidewalls and helps prevent stress relief in the underlying semiconductor material 1023.
  • the n-type device region can be processed in the same manner.
  • FIG. 13(a) is a plan view
  • Fig. 13(b) is a cross-sectional view taken along line AA' in Fig. 13(a))
  • a photoresist 1027 is formed on the structure shown and patterned to shield the p-type device region (e.g., the lower left portion in Fig. 13(a)) to expose the n-type device region (e.g., upper left in Fig. 13(a) Department and right part).
  • the second dielectric 1019 inside the sidewall 1005 may be removed by selective etching of the second dielectric 1019, and a gate may be formed in a space left inside the sidewall 1005 due to the removal of the second dielectric 1019.
  • Stack to make a FinFET may be made by selective etching of the second dielectric 1019, and a gate may be formed in a space left inside the sidewall 1005 due to the removal of the second dielectric 1019.
  • strain source and drain techniques can also be applied to the n-type device region.
  • the first dielectric 1015 of the oxide and the etch stop layer 1011 may be selectively etched, such as RIE, by using the photoresist 1027 shown in FIGS. 13(a) and 13(b) as a mask to expose the underlying layer. Fin 1001F.
  • the photoresist 1027 shown in FIGS. 13(a) and 13(b) as a mask to expose the underlying layer. Fin 1001F.
  • the portion of the fin 1001F that extends between adjacent sidewalls 1005 in the n-type device region (pair) Should be exposed in the source/drain area). Thereafter, the photoresist 1027 can be removed.
  • the fin 1001F may be selectively etched such as RIE to remove at least a portion thereof to be recessed.
  • the fin 1001F can be recessed into the p-PTSL, ie, the portion of the fin 1001F that is above the p-PTSL is removed.
  • stress in the semiconductor layer 1023 may be released, but the third dielectric 1025 and the dummy gate 1019 between the p-type device region and the n-type device region help to reduce such release.
  • additional semiconductor material 1029 used as a source/drain region may be epitaxially grown with the remainder of the fin 1001F as a seed.
  • the source/drain regions 1029 may include Si:C (approximately 0.1-3% atomic percentage of C) to apply tensile stress to the fin 1001F of Si used as a channel region, thereby improving device performance.
  • the semiconductor material 1029 when the semiconductor material 1029 is grown, it may be doped in situ, such as n-type doping, with a doping concentration of about 1E19-1E21 cm -3 .
  • the top surface of the grown semiconductor material 1029 can be higher than the top surface of the fin 1001F to better stress the fin 1001F; on the other hand, can be lower than the top surface of the sidewall 1005 or the dummy gate 1019 so that A stress holding layer is formed thereon.
  • the grown semiconductor material 1029 can assume a ridge shape such as fin 1001F.
  • the stress in the grown semiconductor material 1029 can be prevented from being released due to the third dielectric 1025 present on the p-type device region and the dummy gate between the p-type device region and the n-type device region.
  • the p-type device area helps to improve the performance of p-type devices.
  • Figs. 15(a) and 15(b) are plan views
  • Fig. 15(b) is a cross-sectional view taken along line AA' in Fig. 15(a)
  • a fourth dielectric 1031 such as an oxide (which may be the same as the third dielectric 1025) is formed by deposition, and planarization treatment such as CMP is performed, and CMP may be stopped at the spacer 1005.
  • planarization treatment such as CMP is performed, and CMP may be stopped at the spacer 1005.
  • the formed fourth dielectric 1031 fills the space between adjacent sidewalls and helps prevent stress relief in the underlying semiconductor material 1029.
  • FIG. 27 illustrates stress enhancement that can be achieved by a stress retention mechanism in accordance with an embodiment of the present disclosure. As shown in Fig. 27, by using these stress retention mechanisms, stress enhancement of the channel region can be achieved for both the n-type device and the p-type device.
  • the current active region has been formed in such a form that the active region as a whole still has a ridge extending in the first direction, the ridge being in the dummy gate
  • the portion directly below 1019 and the side wall 1005 is the original fin 1001F, and the portion extending between the adjacent side walls 1005 is the strain source/drain region 1023, 1029.
  • the strain source/drain regions 1023, 1029 may be thicker than the original fins 1001F.
  • dummy gate 1019 can isolate different portions of the active region.
  • the desired portion of the dummy gate 1019 can be replaced with a true gate stack.
  • the portion of the dummy gate 1019 that needs to be replaced can first be removed and replaced with a true gate stack.
  • a replacement of the gate stack can be performed separately.
  • FIG. 16(a) is a plan view
  • Fig. 16(b) is a cross-sectional view taken along line AA' in Fig. 16(a))
  • Fig. 16(a) is a plan view
  • Fig. 16(b) is a cross-sectional view taken along line AA' in Fig. 16(a)
  • a photoresist 1033 is formed on the structures shown in a) and 15 (b), and the photoresist 1033 is patterned to shield the dummy gate portions to be retained (first, third, and fourth from left to right in the figure)
  • the dummy gate, and a portion of the second dummy gate exposes a dummy gate portion (a portion for a p-type device, a portion of the second dummy gate from left to right in the figure) that needs to be replaced.
  • the dummy gate 1019 is selectively etched such as RIE (dielectric 1025/1031 with respect to oxide and spacer 1005 of nitride) using photoresist 1033 as a mask. The etching may stop at the etch stop layer 1011.
  • the etch stop layer 1011 can be removed, for example, by cleaning or selective etching. Thereafter, the photoresist 1033 can be removed.
  • FIGS. 17(a) and 17(b) are plan views, and FIG. 17(b) is a cross-sectional view taken along line AA' in FIG. 17(a)), it may be as described above.
  • a gate stack is formed in the space left inside the side wall 1005.
  • a gate stack for a p-type device can be formed.
  • the gate dielectric layer 1035 may be first formed in the space by deposition such as atomic layer deposition (ALD).
  • the gate dielectric layer 1035 may comprise a high-k gate dielectric such as HfO 2 having a thickness of about 1-3 nm.
  • An oxide interface layer (not shown) may be formed on the surface of the fin 1001F to a thickness of about 0.3-1.2 nm before the gate dielectric layer 1035 is formed.
  • a gate electrode layer 1037-1 for a p-type device, such as a metal gate electrode may be formed by deposition.
  • the formed gate electrode layer 1037-1 and the gate dielectric layer 1035 may be planarized, such as CMP, and the CMP may be stopped at the dielectric 1025/1031.
  • the gate electrode layer 1037-1 and the gate dielectric layer 1035 remain inside the spacer 1005 to form a gate stack.
  • FIG. 18(a) is a plan view
  • Fig. 18(b) is a section along the line AA' in Fig. 18(a)
  • Figure 18(c) is a cross-sectional view taken along line BB' of Figure 18(a)
  • Figure 18(d) is a cross-sectional view taken along line CC' of Figure 18(a), which can be seen in Figure 17
  • a photoresist 1033' is formed on the structures shown in a) and 17(b), and the photoresist 1033' is patterned to mask the dummy gate portion to be retained (first to third pseudo-numbers from left to right in the figure) a gate, a portion of the second dummy gate, and a portion of the fourth dummy gate), and exposing a dummy gate portion to be replaced (a portion for the n-type device, the second dummy gate and the fourth dummy from left to right in the
  • the dummy gate 1019 is selectively etched such as RIE (dielectric 1025/1031 with respect to oxide and spacer 1005 of nitride) using photoresist 1033' as a mask.
  • the etching may stop at the etch stop layer 1011.
  • RIE dielectric 1025/1031 with respect to oxide and spacer 1005 of nitride
  • the etch stop layer 1011 can be removed, for example, by cleaning or selective etching. Thereafter, the photoresist 1033' can be removed.
  • photoresist 1033' may be utilized to mask the respective locations, leaving a dummy gate there for use as isolation. For example, as shown in FIG. 18(a) (see the dotted elliptical circle on the right side) and 18(c), at the fourth dummy gate from left to right, the photoresist 1033' covers the second direction. A dummy gate of a certain width is applied, and the dummy gate 1019 of the width is subsequently retained.
  • the photoresist 1033' and the previous photolithography may be utilized.
  • the registration between the glues 1033 overlaps to obscure the corresponding locations, leaving a dummy gate there for use as an isolation.
  • FIG. 18(a) see the dotted elliptical circle on the left side
  • 18(d) at the second dummy gate from left to right, the photoresist 1033' and the previous photoresist A certain width overlaps in the second direction between 1033, and the dummy gate 1019 of the width is subsequently retained.
  • FIG. 19(a) is a plan view
  • Fig. 19(b) is a section along the line AA' in Fig. 19(a)
  • Fig. 19(c) is a cross-sectional view taken along line BB' of FIG. 19(a)
  • FIG. 19(d) is a cross-sectional view taken along line CC' of FIG. 19(a), which may be as described above.
  • a gate stack is formed in the space left inside the side wall 1005.
  • a gate stack for an n-type device can be formed.
  • the gate dielectric layer 1035 may be first formed in the space by deposition such as atomic layer deposition (ALD).
  • the gate dielectric layer 1035 may comprise a high-k gate dielectric such as HfO 2 having a thickness of about 1-3 nm.
  • An oxide interface layer (not shown) may be formed on the surface of the fin 1001F to a thickness of about 0.3-1.2 nm before the gate dielectric layer 1035 is formed.
  • a gate electrode layer 1037-2 such as a metal gate electrode, for the n-type device can be formed by deposition.
  • the formed gate electrode layer 1037-2 and the gate dielectric layer 1035 may be planarized such as CMP, and the CMP may be stopped at the dielectric 1025/1031.
  • the gate electrode layer 1037-2 and the gate dielectric layer 1035 remain inside the sidewall spacers 1005 to form a gate stack.
  • n-type and p-type FinFETs are obtained.
  • the gate electrode layer 1037-1 can control the channel region in the fin 1001F via the gate dielectric layer 1035, and the source/drain region 1023 can be electrically connected through the channel region.
  • gate electrode layer 1037-2 can control the channel region in fin 1001F via gate dielectric layer 1035, and source/drain regions 1029 can be in electrical communication through the channel region.
  • different gate stacks may be formed for the n-type device and the p-type device, respectively (in this example, the same gate dielectric layer is formed for the n-type device and the p-type device, and different gate electrode layers are formed; but the present disclosure Not limited to this, for example, different gate dielectric layers may also be formed).
  • the gap between some of the opposing gate stacks is where the photoresist 1033' is located.
  • the line width is determined. This gap can be made narrower than conventional techniques in which the gap between the gate stacks is determined by the spacing between the lines (since in general, the line width can be smaller than the line spacing in lithography). That is, the distance between the opposite ends of the gate stack can be made smaller, thereby saving area and reducing manufacturing costs.
  • the isolation between certain opposing gate stacks is made by photoresist 1033' and light.
  • the registration overlap between the glue 1033 is determined.
  • This isolation can be made narrower than conventional techniques where the feature size is determined by linewidth (because in general the registration overlap in lithography can be less than the critical line width (CD)). That is, the distance between the opposite ends of the gate stack can be made smaller, thereby saving area and reducing manufacturing costs.
  • the gate stack may be recessed, and a protective layer 1039 may be formed on the top thereof.
  • the protective layer 1039 can include nitride.
  • the contact portion is formed in accordance with a self-alignment technique.
  • FIGS. 21(a) and 21(b) FIGS. 21(a) and 21(b)
  • FIGS. 21(a) and 21(b) FIGS. 21(a) and 21(b)
  • the dielectric 1025/ can be applied.
  • 1031 in this example, oxide
  • 1031 is subjected to selective etching such as wet etching and vapor phase etching (relative to semiconductor material 1023/1029, dummy gate of oxynitride, nitride spacer 1005 and protective layer 1039)
  • selective etching such as wet etching and vapor phase etching (relative to semiconductor material 1023/1029, dummy gate of oxynitride, nitride spacer 1005 and protective layer 1039)
  • Such etching may be isotropic etching, and the etched trenches or holes may be at least partially substantially conformal or substantially aligned with the outer walls of portions of side walls 1005.
  • the isolation of the dielectric 1025/1031 to the underlying isolation layer 1009 is shown in FIG. 21(a), but the disclosure is not limited thereto.
  • the dielectric 1025/1031 may also have a portion left as long as the source/drain regions 1023, 1029 are exposed.
  • a groove is left between the adjacent side walls 1005. These channels can then contain a conductive material to form a contact. Since the source/drain regions 1023, 1029 are located in these trenches, the contacts can be self-aligned to the source/drain regions 1023, 1029.
  • Figs. 22(a) and 22(b) are plan views
  • Fig. 22(b) is a cross-sectional view taken along line AA' in Fig. 22(a)
  • Fig. 21 The structure shown in a) and 21(b), for example, by forming a contact material 1041, and which can be planarized, such as CMP, can be stopped at the spacer 1005 or the protective layer 1039.
  • the contact material 1041 is filled in each of the grooves.
  • Contact material 1041 can comprise a conductive material, such as a metal such as W.
  • the contact material 1041 in the different trenches is isolated from each other due to the spacers 1005 therebetween.
  • a barrier layer such as a Ti or Ti/TiN laminate may be formed prior to forming the contact material 1041.
  • FIGS. 23(a) and 23(b) are plan views, and FIG. 23(b) is a cross-sectional view taken along line AA' in FIG. 23(a)
  • the contact material 1041 is separated into different contacts.
  • a photoresist (not shown) may be formed on the structures shown in Figs. 22(a) and 22(b) and patterned to expose where isolation is required while shielding the rest.
  • the contact material 1041 is selectively etched, such as RIE, using the photoresist as a mask to cut the contact material 1041.
  • RIE reactive etching
  • the techniques of this disclosure may be applied locally or locally to a substrate.
  • the gate electrode layer 1037-1 of the p-type device and the gate electrode layer of the n-type device 1037-2 is electrically isolated from each other.
  • the present disclosure is not limited thereto.
  • the gate electrode layer 1037-1 of the p-type device and the gate electrode layer 1037-2 of the n-type device are electrically connected to each other according to the layout design.
  • a mask layer 1043 can be formed on the structure shown in FIG.
  • the mask layer 1043 can include a nitride having a thickness of about 10-50 nm.
  • the mask layer 1043 can be patterned (eg, by photolithography) to expose isolation between the gate electrode layer 1037-1 and the gate electrode layer 1037-2 that are required to be electrically connected (ie, the dummy gate 1019).
  • the protective layer 1039 in this example, nitride
  • the dummy gate 1019 may be selectively etched using the mask layer 1043 (In this example, nitrogen oxides).
  • the gate dielectric layer 1035 can also be selectively etched, for example. Thus, a gap is left between the gate electrode layer 1037-1 and the gate electrode layer 1037-2.
  • a conductive material 1045 such as tungsten (W) may be filled in the void so as to be the gate electrode layer 1037-1 and the gate electrode layer 1037- 2 are electrically connected to each other.
  • the top surface of the filled conductive material 1045 is not higher than the top surface of the gate electrode layers 1037-1, 1037-2.
  • Dielectric 1039' such as nitride, can then be filled into the remaining space in the void.
  • the nitride may be planarized such as CMP.
  • the manufacture of the contact portion can be performed as in the above embodiment.
  • the processing is performed separately for the p-type device region and the n-type device region when the strain source/drain technique is applied.
  • the present disclosure is not limited thereto.
  • a ridge corresponding to a source/drain region can be replaced with a first strain source/drain for one type of device (eg, a p-type device) on all device regions, and then another type of device ( For example, the first strain source/drain on the n-type device region is replaced by a second strain source/drain for such devices.
  • Fig. 28(a) is a plan view
  • Fig. 28(b) is a cross-sectional view taken along line AA' in Fig. 28(a))
  • the first dielectric 1015 of the oxide and the etch stop layer 1011 may be selectively etched, such as RIE, over the entire substrate to expose the underlying fin 1001F.
  • RIE reactive ion etching
  • Figs. 29(a) and 29(b) are a plan view
  • Fig. 29(b) is AA' along Fig. 29(a).
  • the fin 1001F may be selectively etched such as RIE to remove at least a portion thereof to make it concave.
  • the additional semiconductor material 1023 serving as the source/drain regions of the p-type device can be epitaxially grown with the remainder of the fin 1001F as a seed.
  • FIGS. 11(a) and 11(b) reference can be made to the description above in connection with FIGS. 11(a) and 11(b).
  • a third dielectric 1025 such as an oxide may be formed on, for example, by deposition in FIGS. 29(a) and 29(b), and It performs a planarization process such as CMP, and the CMP can be stopped at the sidewall 1005.
  • the semiconductor material 1023 in the n-type device region can be replaced.
  • FIGS. 31(a) and 31(b) are plan views
  • FIG. 31(b) is a cross-sectional view taken along line AA' in FIG. 31(a)
  • FIG. 30 A photoresist 1027 is formed on the structure shown and patterned to shield the p-type device region (e.g., the lower left portion in Fig. 31(a)) to expose the n-type device region (e.g., upper left in Fig. 31(a) Department and right part).
  • the third dielectric 1025 of oxide is selectively etched, such as RIE, using photoresist 1027 as a mask to expose the underlying fins 1001F.
  • RIE reactive etching
  • the fin 1001F may be selectively etched such as RIE to remove at least a portion thereof to be recessed.
  • the additional semiconductor material 1029 serving as the source/drain region of the n-type device can be epitaxially grown with the remaining portion of the fin 1001F as a seed.
  • the semiconductor arrangement according to an embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating such semiconductor arrangements and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed and electronic devices can be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor arrangement.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, robots, smart chips, and the like.

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Abstract

一种具有连续侧墙的半导体设置及其制造方法以及包括这种半导体设置的电子设备。该半导体设置包括：衬底（1001）；在衬底上形成的沿第一方向延伸的多个鳍（201）；在衬底上形成的沿与第一方向交叉的第二方向延伸的多个栅堆叠（203-1、203-1'）以及沿第二方向延伸且由电介质构成的伪栅203-2，其中各栅堆叠与至少一个鳍相交；在栅堆叠和伪栅的侧壁上形成的侧墙（205）；以及设于在第二方向上在第一栅堆叠（203-1）和第二栅堆叠（203-1'）之间用以将它们电隔离的电介质（1019），其中，第一栅堆叠和第二栅堆叠的侧墙一体延伸，且该电介质设于第一栅堆叠和第二栅堆叠的一体延伸的侧墙所围绕的空间内，第一栅堆叠和第二栅堆叠在第二方向上的至少一部分间隔小于该半导体设置的制造工艺中光刻所能实现的线间隔。

Description

具有连续侧墙的半导体设置及其制造方法
相关申请的引用
本申请要求于2016年11月15日递交的题为“具有连续侧墙的半导体设置及其制造方法”的中国专利申请201611033447.4的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及具有连续侧墙的半导体设置及其制造方法以及包括这种半导体设置的电子设备。
背景技术
随着半导体器件的不断小型化，短沟道效应越来越明显。对此，提出了立体型器件——鳍式场效应晶体管(FinFET)。FinFET通常包括在衬底上的竖直鳍以及与鳍相交的栅堆叠。可以在鳍的侧壁上形成沟道。
为了形成FinFET，可以在衬底上形成各自分别连续延伸的脊状物。根据布局设计，可以将这些连续延伸的脊状物构图为不同的部分，这些部分随后形成器件的鳍。另外，可以在衬底上形成各自分别连续延伸的栅线。根据布局设计，可以将这些连续延伸的栅线构图为分离的部分，这些部分随后形成器件的栅。在栅的侧壁上，可以形成绕器件栅的侧墙。
图1是示出了包括FinFET的常规半导体设置的顶视图。
如图1所示，该半导体设置包括在衬底上沿第一方向(例如，图中水平方向)延伸的多个鳍101以及沿与第一方向相交(例如，垂直)的第二方向(例如，图中竖直方向)延伸的多个栅堆叠103-1。栅堆叠例如可以包括栅介质层和栅电极层。在鳍中与栅堆叠相交之处，可以产生沟道；而在鳍中沟道区的两侧，可以分别形成源区和漏区(由此得到FinFET)。在各个栅堆叠103-1的侧壁上形成了围绕相应栅堆叠103-1的侧墙105。
另外，为了构图方便以及电隔离等目的，还可以形成伪栅103-2。伪栅103-2与栅堆叠103-1可以包括相同的构造，从而可以与栅堆叠103-1一同形成(因 此，也可以在伪栅103-2的侧壁上形成绕伪栅103-2的侧墙)。但是，伪栅103-2可以不与连续的鳍相交，从而并不真正构成器件。例如，在图1的示例中，伪栅103-2形成为与第一方向上鳍101之间的间隙相交。
在衬底上各侧墙105之间的空隙中，可以填充有电介质如层间电介质层(ILD)(图中为清楚起见，并未示出)，例如氧化物，特别是在后栅工艺的情况下。ILD的顶面例如通过平坦化工艺如化学机械抛光(CMP)而可以与栅堆叠103-1、伪栅103-2、侧墙105的顶面保持大致齐平。
为应对器件小型化的趋势，可以采用自对准接触部技术。例如，可以在ILD中刻蚀接触孔，这种接触孔可以在相对的侧墙之间延伸。然后，可以在衬底上淀积接触材料，例如金属如钨(W)，并对其进行平坦化如CMP。CMP可以停止于ILD或侧墙。CMP后接触材料填充于接触孔中，形成接触部107。位于伪栅103-2相对两侧(图中左右两侧)的接触部可以通过该伪栅103-2的侧墙105而被电分离。
但是，这种结构存在以下缺点。在对ILD进行刻蚀(例如，各向同性刻蚀)时，有可能在相对的栅堆叠103-1的相对端部之间的ILD中形成缝隙。这些缝隙中随后可能被填充接触材料，从而造成接触部之间不必要的电短路，如图1中的107X所示。另外，如图1中的箭头所示，伪栅103-2的边缘与鳍101的端部并不是对准的。这会导致栅端部之间的间隔增加，从而降低了集成密度。
需要提供一种新的结构和工艺来至少部分地解决上述问题。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种半导体设置及其制造方法以及包括这种半导体设置的电子设备，其中在栅的延伸方向上，侧墙可以连续延伸。
根据本公开的一个方面，提供了一种半导体设置，包括：衬底；在衬底上形成的沿第一方向延伸的多个鳍；在衬底上形成的沿与第一方向交叉的第二方向延伸的多个栅堆叠以及沿第二方向延伸且由电介质构成的伪栅，其中各栅堆叠与至少一个鳍相交；在栅堆叠的侧壁以及伪栅的侧壁上形成的侧墙；以及设于在第二方向上对准的第一栅堆叠和第二栅堆叠之间用以将第一栅堆叠和第 二栅堆叠电隔离的电介质，其中，第一栅堆叠和第二栅堆叠的侧墙一体延伸，且所述电介质设于第一栅堆叠和第二栅堆叠的一体延伸的侧墙所围绕的空间内，其中，第一栅堆叠和第二栅堆叠在第二方向上的至少一部分间隔小于该半导体设置的制造工艺中光刻所能实现的线间隔。
根据本公开的另一方面，提供了一种制造半导体设置的方法，包括：在衬底上形成各自分别沿第一方向连续延伸的多个脊状物；在衬底上形成各自分别沿与第一方向交叉的第二方向连续延伸从而与所述多个脊状物相交的多条牺牲栅线；在各牺牲栅线的侧壁上形成绕各牺牲栅线的侧墙；在衬底上形成第一电介质，对其进行平坦化以露出牺牲栅线；去除牺牲栅线，以露出下方的脊状物；向侧墙内的空间中填充第二电介质；利用掩模遮蔽一部分第二电介质并露出其余部分的第二电介质，其中，在至少一条牺牲栅线处，掩模覆盖在第二方向上一定尺度的第二电介质；去除露出部分的第二电介质，以露出下方的脊状物；以及在由于所述部分第二电介质的去除而留下的空间中形成栅堆叠，其中，在所述至少一条牺牲栅线处，留有所述尺度的第二电介质，且在留下的第二电介质两侧形成的栅堆叠彼此之间在第二方向上的间隔由所述尺度限定，且因此能够小于该半导体设置的制造工艺中光刻所能实现的线间隔。
根据本公开的另一方面，提供了一种制造半导体设置的方法，包括：在衬底上形成各自分别沿第一方向连续延伸的多个脊状物；在衬底上形成各自分别沿与第一方向交叉的第二方向连续延伸从而与所述多个脊状物相交的多条牺牲栅线；在各牺牲栅线的侧壁上形成绕各牺牲栅线的侧墙；在衬底上形成第一电介质，对其进行平坦化以露出牺牲栅线；去除牺牲栅线，以露出下方的脊状物；向侧墙内的空间中填充第二电介质；利用第一掩模遮蔽一部分的第二电介质并露出第一部分的第二电介质；去除露出的第一部分第二电介质，以露出下方的脊状物；在由于第一部分第二电介质的去除而留下的空间中形成第一栅堆叠；利用第二掩模遮蔽一部分的第二电介质并露出第二部分的第二电介质，其中，在至少一条牺牲栅线处，第一掩模和第二掩模在第二方向上有一定尺度的套准交迭；去除露出的第二部分第二电介质，以露出下方的脊状物；在由于第二部分第二电介质的去除而留下的空间中形成第二栅堆叠，其中，在所述至少一条牺牲栅线处，留有所述尺度的第二电介质，且在留下的第二电介质两侧形 成的第一栅堆叠和第二栅堆叠彼此之间的间隔由所述尺度限定，且因此能够小于该半导体设置的制造工艺中光刻所能实现的关键线宽(CD)。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体设置。
根据本公开的实施例，侧墙可以在相对的(伪)栅之间连续延伸，即便这些(伪)栅彼此并不连续，这有助于避免(自对准)接触部之间的电短路。通过利用掩模线条(而不是掩模线条之间的间隔)来限定栅堆叠端部之间的间隔，该间隔的尺度可以小于制造工艺中光刻所能实现的线间隔。另一方面，通过利用掩模之间的套准交迭(而不是掩模线条)来限定栅堆叠端部之间的隔离电介质，从而该隔离电介质的尺度可以小于光刻工艺所能实现的关键线宽(CD)。另外，与伪栅邻接的鳍的端部可以自对准于相应侧墙的内壁，从而有助于提高集成密度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1是示出了包括FinFET的常规设置的顶视图；
图2是示出了根据本公开实施例的半导体设置的顶视图；
图3(a)-23(b)示出了根据本公开实施例的制造半导体设置的流程的示意图；
图24(a)-26示出了根据本公开另一实施例的制造半导体设置的流程中部分阶段的示意图；
图27示出了根据本公开实施例的应力保持机制所能实现的应力增强；
图28(a)-33示出了根据本公开另一实施例的制造半导体设置的流程中部分阶段的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知 结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，可以在衬底上形成各自分别沿第一方向延伸的脊状物，并在脊状物之上形成各自分别沿与第一方向交叉(例如，大致垂直)的第二方向连续延伸从而与脊状物相交的栅线。之后，可以在各栅线的侧壁上形成围绕相应栅线的侧墙。这样，侧墙可以在栅线(沿第二方向)的长度上连续延伸。在此，可以先按设计布局对脊状物进行构图，然后再形成栅线。或者，可以直接在连续延伸的脊状物上形成栅线，在后继的步骤中再按设计布局对脊状物进行构图，如下所述。以下，将以后一种情况为例进行描述。
此外，由于为了形成连续延伸侧墙而事实上采用的后栅工艺，可以在衬底上形成第一电介质(例如，层间电介质层(ILD))。可以对第一电介质进行平坦化处理，以露出栅线(例如，平坦化可以停止于栅线)。
在形成连续延伸的侧墙之后，可以进行栅线的分离(以及脊状物的分离，如果之前并未分离的话)。例如，可以去除栅线(因此，这种栅线可以称作“牺牲”栅线)。由于牺牲栅线的去除，露出了下方的脊状物。根据布局设计，可以在某些区域处分离脊状物(如果脊状物在形成栅线之前就已经分离，则在此无需进行)。例如，可以经由侧墙所围绕的空间，对露出的一部分脊状物进行选择性刻蚀，从而将相应脊状物分离为不同的部分(在电特性上分离，可能在物理上仍然部分地连续)，这些部分随后形成不同器件的鳍。这些部分或者说鳍的端部可以自对准于侧墙的内壁。随后，可以向侧墙内侧的空间中填入第二 电介质，使得脊状物的不同部分之间可以彼此电隔离。
根据布局设计，在将要形成真正栅堆叠的位置处，可以去除侧墙内的第二电介质，以露出下方的脊状物或者说鳍。然后，可以在由于第二电介质的去除而留下的空间中形成栅堆叠。于是，栅堆叠可以与下方的鳍相交，并因此构成相应的器件及FinFET。留于侧墙内的第二介质可以形成伪栅。
这样，在第二方向上对准的栅堆叠(占据相同牺牲栅线的位置，且被相同的侧墙所围绕)侧壁上的侧墙可以一体连续延伸，即使这些栅堆叠彼此之间并不连续。这样，就可以避免产生如图1所示的穿过栅端部之间的短路107X。此外，如上所述，鳍的端部可以自对准于相应侧墙的内壁。于是，可以避免如图1所示的由于鳍端部与栅边缘之间的不对准而造成的集成密度降低。
根据本公开的实施例，在去除第二电介质时，通过适当地利用掩模，可以实现栅端部间间隔或者该间隔中所填充的电介质的尺度的减小。例如，可以利用掩模来遮蔽第二电介质。在某些栅端部之间的间隔处，掩模可以遮蔽一定尺度的第二电介质。这样，在利用该掩模对第二电介质进行选择性刻蚀之后，所述尺度的第二电介质可以留下。因此，在该留下的第二电介质相对两侧形成的栅堆叠的端部之间的间隔将由该尺度来限定，并因此可以小于制造工艺中光刻所能实现的线间隔。又如，可以分次使用不同掩模来遮蔽第二电介质的不同部分，以便实现对第二电介质的不同区域分别进行选择性刻蚀。这些掩模之间可以存在套准交迭(overlay)。由于该套准交迭，可以留下一定尺度的第二电介质，该尺度可以小于制造工艺中光刻所能实现的关键线宽(CD)。
图2是示出了根据本公开实施例的半导体设置的顶视图。该半导体设置例如是根据上述工艺制作的。
如图2所示，根据该实施例的半导体设置可以包括在衬底上沿第一方向(例如，图中水平方向)延伸的多个鳍201以及沿与第一方向相交(例如，垂直)的第二方向(例如，图中竖直方向)延伸的多个栅堆叠203-1、203-1′和多个伪栅203-2。栅堆叠203-1、203-1′可以包括栅介质层和栅电极层。另外，伪栅203-2可以包括电介质(例如，上述第二电介质)。在栅堆叠和伪栅的侧壁上，形成有侧墙205。在实际中，侧墙205可以是环形结构。在图2中，为了方便起见，并未示出侧墙205的上、下端部(可以认为它们处于图中所示区域 之外)。在相同侧墙205的内侧，各栅堆叠和/或伪栅彼此沿着侧墙的延伸方向(即，第二方向)彼此对准(它们一起占据该侧墙原本围绕的牺牲栅线的位置)。
栅堆叠203-1、203-1′与鳍201相交，从而构成相应的器件即FinFET。在该示例中，由于如图中箭头所示，各鳍201的端部对准于相应侧墙205的内壁，从而伪栅203-2事实上不与鳍相交，且将其相对两侧(图中左右两侧)相对的鳍彼此电隔离。
根据布局设计，相对的栅堆叠203-1和203-1′之间可以设有隔离部203-2′。隔离部203-2′可以与伪栅203-2包括相同的电介质，例如是在上述工艺中由于在该隔离部的区域处保留第二电介质而得到的。
另外，该半导体设置还包括按照自对准方式形成的接触部207。接触部207可以在相邻的侧墙205之间延伸。由于侧墙205连续延伸，同一侧墙205相对两侧的接触部207可以通过该连续延伸的侧墙205而可靠地电隔离。
本公开可以各种形式呈现，以下将描述其中一些示例。
图3(a)-23(b)示出了根据本公开实施例的制造半导体设置的流程的示意图。
如图3(a)、3(b)和3(c)(图3(a)是俯视图，图3(b)是沿图3(a)中AA′线的截面图，图3(c)是沿图3(a)中BB′线的截面图)所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001中，例如通过离子注入，可以形成各种阱区，如图中所示的p-阱和n-阱。在该示例中，可以在整个衬底区域上形成p-阱，并在一部分p-阱中嵌入n-阱。例如，可以在p-阱上形成n型器件，而可以在n-阱上形成p型器件。
另外，在衬底1001上，形成有沿第一方向(例如，图3(a)和3(b)中的水平方向，图3(c)中垂直于纸面的方向)延伸的脊状物1001F。例如，可以通过对衬底1001进行构图来在衬底1001中形成凹槽，相邻凹槽之间的部分相对于凹槽突出而形成脊状物。当然，也可以在衬底上外延生长其他半导体层，并通过对该半导体层进行构图来形成脊状物。脊状物1001F可以平行延伸，并可以 具有相同或者不同的间距和/或宽度。
在衬底1001上可以形成隔离层1009，例如氧化物(如氧化硅)，以填充在凹槽中从而围绕脊状物1001F的底部。脊状物1001F位于隔离层1009顶面上方的部分随后可以形成器件的鳍，在此称作“鳍线”。在以下描述中，也以“1001F”来指示鳍线。当然，在SOI衬底的情况下，SOI衬底中的埋入氧化物(BOX)层可以充当隔离层。
根据本公开的实施例，可以将鳍线分离为不同的部分以形成鳍布局，然后再形成隔离层，以便限定有源区。备选地，可以保留连续延伸的鳍线，直接形成隔离层。在后继处理中，再对鳍线进行分离，以形成最终的有源区布局。在此，以后一种情况为例进行描述。
为了抑制源漏之间经由鳍下部的泄漏，可以在脊状物中鳍线的下部形成穿通阻止层(PTSL)。例如，对于要在p-阱上形成的n型器件，可以形成片p型的PTSL(p-PTSL)；而对于要在n-阱上形成的p型器件，可以形成n型的PTSL(n-PTSL)。p-PTSL中的p型掺杂浓度可以高于p-阱中的p型掺杂浓度，n-PTSL中的n型掺杂浓度可以高于n-阱中的n型掺杂浓度。
存在多种方法来形成鳍线以及各种阱和PTSL配置，在此不赘述。
接下来，如图4(a)、4(b)和4(c)(图4(a)是俯视图，图4(b)是沿图4(a)中AA′线的截面图，图4(c)是沿图4(a)中BB′线的截面图)所示，可以在衬底1001上(更具体地，在隔离层1009上)，形成沿与第一方向交叉(例如，大致垂直)的第二方向(例如，图4(a)中的竖直方向，图4(b)中垂直于纸面的方向，图4(c)中的水平方向)延伸并因此与鳍线1001F相交的牺牲栅线1003。
为了在以下对牺牲栅线1003进行刻蚀的过程中能够更好地控制刻蚀过程，可以先形成刻蚀停止层1011。例如，可以通过淀积或者热氧化，形成氧化物的刻蚀停止层1011，厚度为约1-5nm。在图4(b)和4(c)中，示出了例如通过热氧化而在鳍线1001F的表面上形成的刻蚀停止层1011；而在图4(a)中，为方便起见，并未示出刻蚀停止层1011。
然后，可以在衬底1001上例如通过淀积形成牺牲栅线材料。牺牲栅线材料例如包括多晶硅或非晶硅，厚度可以为约150-300nm。可以对形成的牺牲栅线材料进行平坦化处理如化学机械抛光(CMP)，以使其顶面平坦，且留于鳍 线1001F顶面上方的厚度可以为约70-150nm。然后，可以通过例如光刻，将牺牲栅线材料构图为一系列牺牲栅线1003。例如，牺牲栅线1003可以平行延伸，并可以具有相同或者不同的间距和/或宽度。
在该示例中，对于牺牲栅线材料的刻蚀如RIE(相对于氧化物的隔离层1009和/或刻蚀停止层1011的选择性刻蚀)利用硬掩模层1013。硬掩模层1013例如可以包括氮化物(例如，氮化硅)，厚度为约50-150nm。利用硬掩模来进行刻蚀的过程在此不再赘述。
在牺牲栅线1003的侧壁上，可以通过侧墙(spacer)形成工艺，形成侧墙1005。侧墙1005例如可以包括氮化物，厚度为约3-10nm。如上所述，侧墙1005围绕各牺牲栅线1003，从而形成环状。在图4(a)的俯视图中，并未示出侧墙1005的上下端部。
接着，可以在各牺牲栅线1003及其相应侧墙1005之间的空隙处，填充第一电介质例如氧化物，以便遮挡鳍线1001F被各牺牲栅线1003及其相应侧墙1005露出的部分。例如，可以在图4(a)、4(b)和4(c)所示的结构上淀积氧化物，并对其进行平坦化处理如CMP。CMP可以停止于牺牲栅线1003，从而露出牺牲栅线1003。这样，得到了图5所示的结构(图5示出了AA′线截面处的情况)。如此填充的第一电介质1015在后继处理中还可以有助于保持应力或者防止应力释放。
在形成连续的侧墙1005之后，可以进行有源区的限定，即按照布局设计，对鳍线1001F进行分离。根据本公开的实施例，在对鳍线1001F进行分离时，可以利用侧墙1005来限定分离鳍线1001F所得到的鳍的端部。
为此，如图6(a)和6(b)(图6(a)是俯视图，图6(b)是沿图6(a)中AA′线的截面图)所示，可以通过选择性刻蚀(相对于氧化物的隔离层1009、刻蚀停止层1011和第一电介质1015以及氮化物的侧墙1005)如湿法腐蚀或气相刻蚀，去除牺牲栅线1003，从而在侧墙1005内侧形成沟槽T。在此，刻蚀优选地是各向同性刻蚀，以便很好地露出侧墙1005的内壁。在沟槽T中，露出了鳍线1001F(当前被刻蚀停止层1011覆盖)。
对于露出的鳍线1001F，可以根据布局设计，分离其中的一部分，以形成分离的有源区或者鳍。例如，这可以通过光刻胶遮蔽不需要分离的鳍线并露出 需要分离的鳍线，然后进行选择性刻蚀来进行。
例如，如图7(a)和7(b)(图7(a)是俯视图，图7(b)是沿图7(a)中AA′线的截面图)所示，可以在图6(a)和6(b)所示的结构上形成光刻胶1017，并将其构图(例如，通过曝光和显影)为露出从左向右数时第一和第三条牺牲栅线所对应的沟槽T，遮蔽第二和第四条牺牲栅线所对应的沟槽T。尽管在此示出了整个第一和第三条牺牲栅线所对应的沟槽T均被露出且第二和第四条牺牲栅线所对应的沟槽T均被遮蔽的情况，但是本公开不限于此。例如，沟槽T的一部分可以遮蔽而另一部分可以露出。这里需要指出的是，需要露出的沟槽T或者其一部分是根据布局设计而定的。
然后，如图8(图8示出了AA′线截面处的情况)所示，可以经由沟槽T，来分离鳍线1001F。例如，可以通过反应离子刻蚀(RIE)，依次选择性刻蚀刻蚀停止层1011和脊状物1001F。对脊状物1001F的刻蚀可以将鳍线(即，脊状物处于隔离层1009顶面上方的部分)切断。这样，鳍线1001F被分离为不同的部分，这些部分随后可以构成器件的鳍。以下，仍然以“1001F”来指示鳍。优选地，对脊状物1001F的刻蚀可以穿过PTSL，并停止于n-阱或p-阱中。这有助于确保各分离的鳍之间的电隔离。之后，可以去除光刻胶1017。
由于在分离鳍线1001F时侧墙1005类似于掩模，因此，分离后鳍的端部自对准于侧墙1005的内壁。这有助于节省衬底上的面积并因此降低制造成本。
接着，如图9(a)和9(b)(图9(a)是俯视图，图9(b)是沿图9(a)中AA′线的截面图)所示，可以向侧墙1005内侧的空间中特别是分离的鳍1001F的相对端部之间填充第二电介质1019。例如，可以在图8所示的结构上淀积氮氧化物(例如，氮氧化硅)，并对其进行平坦化处理如CMP，CMP可以停止于第一电介质1015。第二电介质1019被侧墙1005围绕，构成伪栅。
在此，通过向凹槽中填充第二电介质来形成伪栅。在填充时，第二电介质可能先淀积于凹槽的侧壁和底壁上，从而形成U型结构，该U型结构的两个相对内侧壁随着淀积进行而逐渐靠拢。由于沟槽的开口很小，因此最终U型结构的相对内侧壁可能并没有完全弥合，而是存在一定的缝隙。也即，在最终的伪栅中，可能存在这种缝隙，从而伪栅仍然呈现U型结构。这种结构可以在透射电镜(TEM)照片中看到。
由于电介质的伪栅留于鳍的相对端部之间，可以在后继的源/漏外延过程中降低应力弛豫。另外，可以将带应力的电介质材质用于伪栅，以便在鳍中产生应力，从而增强器件性能。例如，对于p型器件，伪栅可以带压应力；而对于n型器件，伪栅可以带拉应力。
之后，可以按照布局设计，在侧墙1005内侧的空间中需要之处形成真正的栅堆叠。例如，这可以通过去除一部分第二电介质1019，以露出下方的鳍1001F，并在由于第二电介质1019的去除而留下的空间中形成栅堆叠来进行。形成的栅堆叠与下方的鳍1001F相交，从而限定FinFET。
在该示例中，由于针对CMOS工艺，可以针对n型器件和p型器件分别形成不同的栅堆叠。为此，可以针对n型器件区域和p型器件区域分别进行处理。在以下，将描述先对p型器件区域进行处理然后再对n型器件进行处理的示例。但是，本公开不限于此，处理的顺序可以交换。
例如，参见图10(a)和10(b)(图10(a)是俯视图，图10(b)是沿图10(a)中AA′线的截面图)，可以在图9(a)和9(b)所示的结构上形成光刻胶1021，并将其构图为遮蔽n型器件区域(例如，图10(a)中左上部以及右部)，而露出p型器件区域(例如，图10(a)中左下部)。
此时，例如可以通过对第二电介质1019进行选择性刻蚀来去除侧墙1005内侧的第二电介质1019，并在由于第二电介质1019的去除而在侧墙1005内侧留下的空间中形成栅堆叠，来制作FinFET。
根据本公开的实施例，在此还可以采用应变源漏技术。
例如，可以图10(a)和10(b)所示的光刻胶1021为掩模，对氧化物的第一电介质1015以及刻蚀停止层1011进行选择性刻蚀如RIE，以便露出下方的鳍1001F。于是，p型器件区域中鳍1001F在相邻侧墙1005之间延伸的部分(对应于源/漏区)被露出。之后，可以去除光刻胶1021。
接着，如图11(a)和11(b)(图11(a)是俯视图，图11(b)是沿图11(a)中AA′线的截面图)所示，可以对鳍1001F进行选择性刻蚀如RIE，以至少去除其一部分从而使其下凹。例如，鳍1001F可以凹入至n-PTSL，即去除鳍1001F位于n-PTSL之上的部分。然后，可以以鳍1001F的剩余部分为种子，外延生长用作源/漏区的另外半导体材料1023。例如，对于p型器件，源/漏区1023可 以包括SiGe(Ge的原子百分比为约30-75％)，以便向用作沟道区的Si的鳍1001F施加压应力，从而改善器件性能。另外，在生长半导体材料1023时，可以对其进行原位掺杂，例如p型掺杂，掺杂浓度为约1E19-1E21cm-3。所生长的半导体材料1023的顶面可以高于鳍1001F的顶面，以便更好地向鳍1001F施加应力；另一方面，可以低于侧墙1005或伪栅1019的顶面，以便随后可以在此之上形成应力保持层。
在生长半导体材料1023时，由于在相对两侧(图11(a)和11(b)中左右两侧)以及底部均存在种子层，从而有助于高质量的生长。以这种方式进行生长，所生长的半导体材料1023可以呈现如鳍1001F的脊状。
另外，如图11(b)所示，由于n型器件区域上存在的第一电介质1015以及p型器件区域与n型器件区域之间的伪栅1019，可以防止所生长的半导体材料1023中的应力释放到n型器件区域，并有助于改善p型器件的性能。
然后，如图12(图12示出了AA′线截面处的情况)所示，可以在图11(a)和11(b)上例如通过淀积形成第三电介质1025如氧化物，并对其进行平坦化处理如CMP，CMP可以停止于侧墙1005。这样，所形成的第三电介质1025填充了相邻侧墙之间的空间，并且有助于防止下方的半导体材料1023中的应力释放。
接下来，可以对n型器件区域进行同样地处理。
为此，如图13(a)和13(b)(图13(a)是俯视图，图13(b)是沿图13(a)中AA′线的截面图)所示，可以在图12所示的结构上形成光刻胶1027，并将其构图为遮蔽p型器件区域(例如，图13(a)中左下部)，而露出n型器件区域(例如，图13(a)中左上部以及右部)。
此时，例如可以通过对第二电介质1019进行选择性刻蚀来去除侧墙1005内侧的第二电介质1019，并在由于第二电介质1019的去除而在侧墙1005内侧留下的空间中形成栅堆叠，来制作FinFET。
当然，也可以对n型器件区域应用应变源漏技术。
例如，可以图13(a)和13(b)所示的光刻胶1027为掩模，对氧化物的第一电介质1015以及刻蚀停止层1011进行选择性刻蚀如RIE，以便露出下方的鳍1001F。于是，n型器件区域中鳍1001F在相邻侧墙1005之间延伸的部分(对 应于源/漏区)被露出。之后，可以去除光刻胶1027。
接着，如图14(图14示出了AA′线截面处的情况)所示，可以对鳍1001F进行选择性刻蚀如RIE，以至少去除其一部分从而使其下凹。例如，鳍1001F可以凹入至p-PTSL，即去除鳍1001F位于p-PTSL之上的部分。在去除鳍1001F的该部分时，半导体层1023中的应力可能释放，但是第三电介质1025以及p型器件区域与n型器件区域之间的伪栅1019有助于减小这种释放。
然后，可以以鳍1001F的剩余部分为种子，外延生长用作源/漏区的另外半导体材料1029。例如，对于n型器件，源/漏区1029可以包括Si：C(C的原子百分比为约0.1-3％)，以便向用作沟道区的Si的鳍1001F施加拉应力，从而改善器件性能。另外，在生长半导体材料1029时，可以对其进行原位掺杂，例如n型掺杂，掺杂浓度为约1E19-1E21cm-3。所生长的半导体材料1029的顶面可以高于鳍1001F的顶面，以便更好地向鳍1001F施加应力；另一方面，可以低于侧墙1005或伪栅1019的顶面，以便随后可以在此之上形成应力保持层。
在生长半导体材料1029时，由于在相对两侧(图14中左右两侧)以及底部均存在种子层，从而有助于高质量的生长。以这种方式进行生长，所生长的半导体材料1029可以呈现如鳍1001F的脊状。
另外，如图14所示，由于在p型器件区域上存在的第三电介质1025以及p型器件区域与n型器件区域之间的伪栅，可以防止所生长的半导体材料1029中的应力释放到p型器件区域，并有助于改善p型器件的性能。
然后，如图15(a)和15(b)(图15(a)是俯视图，图15(b)是沿图15(a)中AA′线的截面图)所示，可以在图14上例如通过淀积形成第四电介质1031如氧化物(可以与第三电介质1025相同)，并对其进行平坦化处理如CMP，CMP可以停止于侧墙1005。这样，所形成的第四电介质1031填充了相邻侧墙之间的空间，并且有助于防止下方的半导体材料1029中的应力释放。
可以看出，由于存在多种应力保持机制，从而可以增加器件中的应力。图27示出了根据本公开实施例的应力保持机制所能实现的应力增强。如图27所示，采用这些应力保持机制，对n型器件和p型器件，均可以实现沟道区的应力增强。
如图15(a)和15(b)所示，当前的有源区已经形成为这样的形式：有源区总体上仍呈沿第一方向延伸的脊状物，该脊状物在伪栅1019和侧墙1005正下方的部分是原本的鳍1001F，而在相邻侧墙1005之间延伸的部分是应变源/漏区1023、1029。应变源/漏区1023、1029可以比原本的鳍1001F要粗。在该示例中，伪栅1019可以将有源区的不同部分相隔离。
在形成应变源/漏之后，可以将伪栅1019中需要之处替换为真正的栅堆叠。为此，首先可以去除伪栅1019中需要替换的部分，并在其中代之以真正的栅堆叠。对于n型器件和p型器件，可以分别进行栅堆叠的替代。
例如，如图16(a)和16(b)(图16(a)是俯视图，图16(b)是沿图16(a)中AA′线的截面图)所示，可以在图15(a)和15(b)所示的结构上形成光刻胶1033，并将该光刻胶1033构图为遮蔽需要保留的伪栅部分(图中从左至右数第一、第三和第四伪栅，以及第二伪栅的一部分)，并露出需要替换的伪栅部分(用于p型器件的部分，图中从左至右数第二伪栅的一部分)。以光刻胶1033为掩模，对伪栅1019进行选择性刻蚀如RIE(相对于氧化物的电介质1025/1031以及氮化物的侧墙1005)。刻蚀可以停止于刻蚀停止层1011。这样，由于这些部分的伪栅被去除，从而在侧墙1005内侧留下了空间(用于容纳栅堆叠)，且在该空间内露出了鳍1001F(鳍表面覆盖有刻蚀停止层1011，该刻蚀停止层1011例如可以通过清洗或者选择性刻蚀而被去除)。之后，可以去除光刻胶1033。
然后，如图17(a)和17(b)(图17(a)是俯视图，图17(b)是沿图17(a)中AA′线的截面图)所示，可以在如上所述在侧墙1005内侧留下的空间中形成栅堆叠。在此，可以形成针对p型器件的栅堆叠。
例如，可以首先在该空间中通过淀积如原子层淀积(ALD)形成栅介质层1035。栅介质层1035可以包括高K栅介质如HfO2，厚度为约1-3nm。在形成栅介质层1035之前，可以在鳍1001F的表面上形成氧化物的界面层(未示出)，厚度为约0.3-1.2nm。之后，可以通过淀积形成针对p型器件的栅电极层1037-1，例如金属栅电极。可以对所形成的栅电极层1037-1和栅介质层1035进行平坦化处理如CMP，CMP可以停止于电介质1025/1031。这样，栅电极层1037-1和栅介质层1035留于侧墙1005内侧，形成栅堆叠。
接下来，可以类似地对n型器件进行栅堆叠的替代。
例如，如图18(a)、18(b)、18(c)和18(d)(图18(a)是俯视图，图18(b)是沿图18(a)中AA′线的截面图，图18(c)是沿图18(a)中BB′线的截面图，图18(d)是沿图18(a)中CC′线的截面图)所示，可以在图17(a)和17(b)所示的结构上形成光刻胶1033′，并将该光刻胶1033′构图为遮蔽需要保留的伪栅部分(图中从左至右数第一和第三伪栅，第二伪栅的一部分，以及第四伪栅的一部分)，并露出需要替换的伪栅部分(用于n型器件的部分，图中从左至右数第二伪栅和第四伪栅的一部分)。以光刻胶1033′为掩模，对伪栅1019进行选择性刻蚀如RIE(相对于氧化物的电介质1025/1031以及氮化物的侧墙1005)。刻蚀可以停止于刻蚀停止层1011。这样，由于这些部分的伪栅被去除，从而在侧墙1005内侧留下了空间(用于容纳栅堆叠)，且在该空间内露出了鳍1001F(鳍表面覆盖有刻蚀停止层1011，该刻蚀停止层1011例如可以通过清洗或者选择性刻蚀而被去除)。之后，可以去除光刻胶1033′。
根据本公开的实施例，在栅堆叠的相对端部之间需要隔离的情况下，可以利用光刻胶1033′来遮蔽相应位置，从而在该处留下伪栅以便用作隔离。例如，如图18(a)(参见其中右侧的虚线椭圆圈)和18(c)所示，在从左至右数第四条伪栅处，光刻胶1033′覆盖了在第二方向上一定宽度的伪栅，该宽度的伪栅1019随后得以保留。
另外，根据本公开的实施例，在栅堆叠(特别是n型器件和p型器件的栅堆叠)的相对端部之间需要隔离的情况下，可以利用光刻胶1033′与前次光刻胶1033之间的套准交迭来遮蔽相应位置，从而在该处留下伪栅以便用作隔离。例如，如图18(a)(参见其中左侧的虚线椭圆圈)和18(d)所示，在从左至右数第二条伪栅处，光刻胶1033′与前次光刻胶1033之间在第二方向上交迭一定宽度，该宽度的伪栅1019随后得以保留。
然后，如图19(a)、19(b)、19(c)和19(d)(图19(a)是俯视图，图19(b)是沿图19(a)中AA′线的截面图，图19(c)是沿图19(a)中BB′线的截面图，图19(d)是沿图19(a)中CC′线的截面图)所示，可以在如上所述在侧墙1005内侧留下的空间中形成栅堆叠。在此，可以形成针对n型器件的栅堆叠。
例如，可以首先在该空间中通过淀积如原子层淀积(ALD)形成栅介质层1035。栅介质层1035可以包括高K栅介质如HfO2，厚度为约1-3nm。在形成 栅介质层1035之前，可以在鳍1001F的表面上形成氧化物的界面层(未示出)，厚度为约0.3-1.2nm。之后，可以通过淀积形成针对n型器件的栅电极层1037-2，例如金属栅电极。可以对所形成的栅电极层1037-2和栅介质层1035进行平坦化处理如CMP，CMP可以停止于电介质1025/1031。这样，栅电极层1037-2和栅介质层1035留于侧墙1005内侧，形成栅堆叠。
这样，就得到了n型和p型的FinFET。如图19(b)所示，在p型FinFET中，栅电极层1037-1可以介由栅介质层1035控制鳍1001F中的沟道区，且源/漏区1023可以通过沟道区电连通。类似地，在n型FinFET中，栅电极层1037-2可以介由栅介质层1035控制鳍1001F中的沟道区，且源/漏区1029可以通过沟道区电连通。
在此，可以对n型器件和p型器件分别形成不同的栅堆叠(在该示例中，对于n型器件和p型器件形成相同的栅介质层，并形成不同的栅电极层；但是本公开不限于此，例如也可以形成不同的栅介质层)。
参见图19(a)和19(c)，某些相对的栅堆叠之间的间隙(或者说，残留的伪栅1019在第二方向上的宽度)是由光刻胶1033′在该处的线宽决定的。相比于栅堆叠之间的间隙由线之间的间隔决定的常规技术，该间隙可以做得更窄(因为一般而言在光刻技术中线宽可以小于线间隔)。也即，栅堆叠的相对端部之间的距离可以更小，从而可以节省面积，并可以降低制造成本。
另外，参见图19(a)和19(d)，某些相对的栅堆叠之间的隔离(或者说，残留的伪栅1019在第二方向上的宽度)是由光刻胶1033′与光刻胶1033之间的套准交迭决定的。相比于特征尺寸由线宽决定的常规技术，该隔离可以做得更窄(因为一般而言在光刻技术中套准交迭可以小于关键线宽(CD))。也即，栅堆叠的相对端部之间的距离可以更小，从而可以节省面积，并可以降低制造成本。
在此，利用了两种不同方式来实现栅堆叠相对端部之间间隙的减小。可以根据布局设计，选择是否使用这些方式。
接下来，可以进行接触部的制作。
为了保护栅堆叠，如图20(图20示出了AA′线截面处的情况)所示，可以使栅堆叠凹入，并在其顶部形成保护层1039。例如，保护层1039可以包括 氮化物。
根据本公开的实施例，按照自对准技术来形成接触部。例如，如图21(a)和21(b)(图21(a)是俯视图，图21(b)是沿图21(a)中AA′线的截面图)所示，可以对电介质1025/1031(在该示例中，氧化物)进行选择性刻蚀如湿法腐蚀和气相刻蚀(相对于半导体材料1023/1029、氮氧化物的伪栅、氮化物的侧墙1005和保护层1039)，以至少部分地露出下方的源/漏区1023、1029。这种刻蚀可以是各向同性刻蚀，且刻蚀的沟槽或孔洞可以至少部分地与部分侧墙1005的外壁实质上共形或实质上对准。在图21(a)中示出了对电介质1025/1031的刻蚀露出下方的隔离层1009，但是本公开不限于此。例如，电介质1025/1031还可以留有一部分，只要源/漏区1023、1029被露出。
于是，如图21(a)和21(b)所示，在相邻的侧墙1005之间，留下了沟槽。这些沟道随后可以容纳导电材料以形成接触部。由于源/漏区1023、1029位于这些沟槽内，从而接触部可以自对准于源/漏区1023、1029。
然后，如图22(a)和22(b)(图22(a)是俯视图，图22(b)是沿图22(a)中AA′线的截面图)所示，可以在图21(a)和21(b)所示的结构上，例如通过淀积形成接触材料1041，并可以对其进行平坦化处理例如CMP，CMP可以停止于侧墙1005或保护层1039。于是，接触材料1041填充于各沟槽中。接触材料1041可以包括导电材料，例如金属如W。不同沟槽中的接触材料1041由于它们之间的侧墙1005而彼此隔离。
此外，在形成接触材料1041之前，可以先形成一层阻挡层(未示出)，例如Ti或者Ti/TiN叠层。
之后，如图23(a)和23(b)(图23(a)是俯视图，图23(b)是沿图23(a)中AA′线的截面图)所示，可以根据布局设计，将接触材料1041分离为不同的接触部。例如，可以在图22(a)和22(b)所示的结构上形成光刻胶(未示出)，并将其构图为露出需要隔离之处，而遮蔽其余之处。然后，以光刻胶为掩模，对接触材料1041进行选择性刻蚀如RIE，以切断接触材料1041。如图23(b)所示，形成了自对准于源/漏区1023、1029的接触部1041。
本公开的技术可以局部地或者全局地应用于衬底上。
在以上实施例中，p型器件的栅电极层1037-1和n型器件的栅电极层 1037-2彼此电隔离。但是，本公开不限于此。例如，在某些区域处，根据布局设计，p型器件的栅电极层1037-1和n型器件的栅电极层1037-2彼此电连接。
例如，在以上结合图3(a)-20描述的操作之后，如图24(a)和24(b)(图24(a)是俯视图，图24(b)是沿图24(a)中CC′线的截面图)所示，可以在图20所示的结构上形成掩模层1043。例如，掩模层1043可以包括氮化物，厚度为约10-50nm。可以将该掩模层1043构图(例如，通过光刻)为露出需要电连接的栅电极层1037-1和栅电极层1037-2之间的隔离(即，伪栅1019)。
然后，如图25(图25示出了CC′线截面处的情况)所示，可以利用掩模层1043，选择性刻蚀保护层1039(在该示例中，氮化物)和伪栅1019(在该示例中，氮氧化物)。在此，还可以对栅介质层1035进行选择性刻蚀如。于是，在栅电极层1037-1和栅电极层1037-2之间留下了空隙。
随后，如图26(图26示出了CC′线截面处的情况)所示，可以向空隙中填充导电材料1045如钨(W)，以便将栅电极层1037-1和栅电极层1037-2彼此电连接。优选地，填充的导电材料1045的顶面不高于栅电极层1037-1、1037-2的顶面。然后，可以向空隙中的剩余空间中填充电介质1039′如氮化物。可以对氮化物进行平坦化处理如CMP。
之后，可以同上述实施例中一样，进行接触部的制造。
在以上的实施例中，在应用应变源/漏技术时，针对p型器件区域和n型器件区域分别进行处理。但是，本公开不限于此。例如，可以在所有器件区域上将对应于源/漏区的脊状物替换为针对一种类型器件(例如，p型器件)的第一应变源/漏，然后再将另一种类型器件(例如，n型器件)区域上的第一应变源/漏替换为针对该类器件的第二应变源/漏。
如图28(a)和28(b)(图28(a)是俯视图，图28(b)是沿图28(a)中AA′线的截面图)所示，如在以上结合图9(a)和9(b)所述形成伪栅1019之后，可以在整个衬底上对氧化物的第一电介质1015以及刻蚀停止层1011进行选择性刻蚀如RIE，以便露出下方的鳍1001F。于是，p型器件区域和n型器件区域中鳍1001F在相邻侧墙1005之间延伸的部分(对应于源/漏区)被露出。该操作与以上结合图10(a)和10(b)描述的操作类似，但是并未形成光刻胶1021。
接着，如图29(a)和29(b)(图29(a)是俯视图，图29(b)是沿图29(a)中AA′ 线的截面图)所示，可以对鳍1001F进行选择性刻蚀如RIE，以至少去除其一部分从而使其下凹。然后，可以以鳍1001F的剩余部分为种子，外延生长用作p型器件的源/漏区的另外半导体材料1023。对此，例如可以参见以上结合图11(a)和11(b)的描述。
然后，如图30(图30示出了AA′线截面处的情况)所示，可以在图29(a)和29(b)上例如通过淀积形成第三电介质1025如氧化物，并对其进行平坦化处理如CMP，CMP可以停止于侧墙1005。
接下来，可以替换n型器件区域中的半导体材料1023。
为此，如图31(a)和31(b)(图31(a)是俯视图，图31(b)是沿图31(a)中AA′线的截面图)所示，可以在图30所示的结构上形成光刻胶1027，并将其构图为遮蔽p型器件区域(例如，图31(a)中左下部)，而露出n型器件区域(例如，图31(a)中左上部以及右部)。以光刻胶1027为掩模，对氧化物的第三电介质1025进行选择性刻蚀如RIE，以便露出下方的鳍1001F。于是，n型器件区域中鳍1001F在相邻侧墙1005之间延伸的部分(对应于源/漏区)被露出。之后，可以去除光刻胶1027。
接着，如图32(图32示出了AA′线截面处的情况)所示，可以对鳍1001F进行选择性刻蚀如RIE，以至少去除其一部分从而使其下凹。然后，如图33(图33示出了AA′线截面处的情况)所示，可以以鳍1001F的剩余部分为种子，外延生长用作n型器件的源/漏区的另外半导体材料1029。对此，例如可以参见以上结合图14的描述。接下来，可以如以上实施例中一样进行。
根据本公开实施例的半导体设置可以应用于各种电子设备。例如，通过集成这样的半导体设置以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体设置的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源、机器人、智能芯片等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (23)

  1. 一种半导体设置，包括：
    衬底；
    在衬底上形成的沿第一方向延伸的多个鳍；
    在衬底上形成的沿与第一方向交叉的第二方向延伸的多个栅堆叠以及沿第二方向延伸且由电介质构成的伪栅，其中各栅堆叠与至少一个鳍相交；
    在栅堆叠的侧壁以及伪栅的侧壁上形成的侧墙；以及
    设于在第二方向上对准的第一栅堆叠和第二栅堆叠之间用以将第一栅堆叠和第二栅堆叠电隔离的电介质，
    其中，第一栅堆叠和第二栅堆叠的侧墙一体延伸，且所述电介质设于第一栅堆叠和第二栅堆叠的一体延伸的侧墙所围绕的空间内，
    其中，第一栅堆叠和第二栅堆叠在第二方向上的至少一部分间隔小于该半导体设置的制造工艺中光刻所能实现的线间隔。
  2. 根据权利要求1所述的半导体设置，其中，所述电介质在第二方向上的尺度小于该半导体设置的制造工艺中光刻所能实现的关键线宽(CD)。
  3. 根据权利要求1所述的半导体设置，其中，至少一些鳍的端部邻接伪栅，且与相应的侧墙的内壁实质上对准。
  4. 根据权利要求1所述的半导体设置，其中，在第二方向上对准的至少一个栅堆叠和至少一个伪栅的侧墙一体延伸。
  5. 根据权利要求1-4中任一项所述的半导体设置，其中，在第二方向上跨及所述多个鳍的范围内，各侧墙均连续延伸。
  6. 根据权利要求1所述的半导体设置，其中，第一栅堆叠与第二栅堆叠之间的电介质与伪栅的电介质相同。
  7. 根据权利要求1所述的半导体设置，还包括：设于相邻的侧墙之间的电接触部。
  8. 根据权利要求7所述的半导体设置，其中，电接触部的侧壁同与之相对的侧墙的外壁实质上共形或实质上对准。
  9. 根据权利要求1所述的半导体设置，其中，至少一个鳍包括：
    第一半导体材料的第一部分，第一部分在栅堆叠以及侧墙的正下方延伸；以及
    第二半导体材料的第二部分，第二部分在侧墙之间延伸，且与第一部分相接，
    其中，第二半导体材料能够向第一半导体材料施加应力。
  10. 根据权利要求9所述的半导体设置，其中，第二部分的顶面高于第一部分的顶面，但是低于侧墙的顶面。
  11. 根据权利要求1所述的半导体设置，其中，伪栅的电介质形成U型结构。
  12. 一种制造半导体设置的方法，包括：
    在衬底上形成各自分别沿第一方向延伸的多个脊状物；
    在衬底上形成各自分别沿与第一方向交叉的第二方向连续延伸从而与所述多个脊状物相交的多条牺牲栅线；
    在各牺牲栅线的侧壁上形成绕各牺牲栅线的侧墙；
    在衬底上形成第一电介质，对其进行平坦化以露出牺牲栅线；
    去除牺牲栅线，以露出下方的脊状物；
    向侧墙内的空间中填充第二电介质；
    利用掩模遮蔽一部分第二电介质并露出其余部分的第二电介质，其中，在至少一条牺牲栅线处，掩模覆盖在第二方向上一定尺度的第二电介质；
    去除露出部分的第二电介质，以露出下方的脊状物；以及
    在由于所述部分第二电介质的去除而留下的空间中形成栅堆叠，
    其中，在所述至少一条牺牲栅线处，留有所述尺度的第二电介质，且在留下的第二电介质两侧形成的栅堆叠彼此之间在第二方向上的间隔由所述尺度限定，且因此能够小于该半导体设置的制造工艺中光刻所能实现的线间隔。
  13. 一种制造半导体设置的方法，包括：
    在衬底上形成各自分别沿第一方向延伸的多个脊状物；
    在衬底上形成各自分别沿与第一方向交叉的第二方向连续延伸从而与所述多个脊状物相交的多条牺牲栅线；
    在各牺牲栅线的侧壁上形成绕各牺牲栅线的侧墙；
    在衬底上形成第一电介质，对其进行平坦化以露出牺牲栅线；
    去除牺牲栅线，以露出下方的脊状物；
    向侧墙内的空间中填充第二电介质；
    利用第一掩模遮蔽一部分的第二电介质并露出第一部分的第二电介质；
    去除露出的第一部分第二电介质，以露出下方的脊状物；
    在由于第一部分第二电介质的去除而留下的空间中形成第一栅堆叠；
    利用第二掩模遮蔽一部分的第二电介质并露出第二部分的第二电介质，其中，在至少一条牺牲栅线处，第一掩模和第二掩模在第二方向上有一定尺度的套准交迭；
    去除露出的第二部分第二电介质，以露出下方的脊状物；
    在由于第二部分第二电介质的去除而留下的空间中形成第二栅堆叠，
    其中，在所述至少一条牺牲栅线处，留有所述尺度的第二电介质，且所述尺度能够小于该半导体设置的制造工艺中光刻所能实现的关键线宽(CD)。
  14. 根据权利要求12或13所述的方法，其中，在衬底上形成各自分别沿第一方向延伸的多个脊状物包括：
    在衬底上形成各自分别沿第一方向连续延伸的多个脊状物；以及
    对一部分脊状物进行选择性刻蚀。
  15. 根据权利要求12或13所述的的方法，其中，
    在衬底上形成各自分别沿第一方向延伸的多个脊状物包括在衬底上形成各自分别沿第一方向连续延伸的多个脊状物，以及
    在去除牺牲栅线之后且在向侧墙内的空间中填充第二电介质之前，该方法还包括：对露出的一部分脊状物进行选择性刻蚀。
  16. 根据权利要求12或13所述的方法，其中，在填充第二电介质之后且在去除露出部分的第二电介质之前，该方法还包括：
    选择性刻蚀第一电介质，以露出脊状物在侧墙之间延伸的部分；
    至少部分地去除所露出的脊状物在侧墙之间延伸的部分；
    在脊状物的剩余部分之间生长不同材料的另一脊状物；
    在衬底上形成第三电介质，并对其进行平坦化，平坦化停止于侧墙。
  17. 根据权利要求16所述的方法，其中，
    在衬底上的一部分区域上执行选择性刻蚀第一电介质到形成第三电介质的处理，并在衬底上的另一部分区域上另外执行去除第一电介质到形成第三电介质的处理，
    其中，在这两次处理中生长的另一脊状物的材料不同。
  18. 根据权利要求16所述的方法，其中，
    在衬底上的全部区域上执行选择性刻蚀第一电介质到形成第三电介质的处理，
    该方法还包括：
    在衬底的选定区域上选择性去除第三电介质和所述另一脊状物；
    在所述选定区域上脊状物的剩余部分之间生长又一脊状物；
    在衬底上形成第四电介质，并对其进行平坦化，平坦化停止于侧墙。
  19. 根据权利要求12或13所述的方法，其中，在形成栅堆叠之后，该方法还包括：
    选择性刻蚀第一电介质，至少部分地露出各脊状物在侧墙之间延伸的部分；
    在衬底上形成导电层，并对其进行平坦化，平坦化停止于侧墙；以及
    在导电层中的预定位置处形成电隔离。
  20. 根据权利要求19所述的方法，其中，对第一电介质的刻蚀是各向同性刻蚀，且刻蚀的沟槽或孔洞至少部分地与部分侧墙的外壁实质上共形或实质上对准。
  21. 根据权利要求12或13所述的方法，其中，形成栅堆叠包括：
    在同一侧墙围绕的空间内形成不同的栅堆叠。
  22. 一种电子设备，包括由如权利要求1-11中任一项所述的半导体设置。
  23. 根据权利要求22所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、可穿戴智能设备、移动电源、机器人、智能芯片。
PCT/CN2016/111274 2016-11-15 2016-12-21 具有连续侧墙的半导体设置及其制造方法 Ceased WO2018090426A1 (zh)

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