WO2018077065A1 - 薄膜晶体管及其制作方法、阵列基板、显示面板 - Google Patents

薄膜晶体管及其制作方法、阵列基板、显示面板 Download PDF

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Publication number
WO2018077065A1
WO2018077065A1 PCT/CN2017/106504 CN2017106504W WO2018077065A1 WO 2018077065 A1 WO2018077065 A1 WO 2018077065A1 CN 2017106504 W CN2017106504 W CN 2017106504W WO 2018077065 A1 WO2018077065 A1 WO 2018077065A1
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Prior art keywords
photoresist
source
drain
region
layer
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English (en)
French (fr)
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周强
朱超凡
任兴凤
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/778,719 priority Critical patent/US10504926B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a display panel.
  • Thin film transistors play an important role in display devices.
  • a thin film transistor is widely used in a large-sized LCD display and an AM-OLED display.
  • the active layer of the thin film transistor may be a semiconductor material containing a metal element, such as a metal oxide semiconductor material or a metal doped semiconductor material.
  • a metal element such as a metal oxide semiconductor material or a metal doped semiconductor material.
  • the present disclosure provides a method of fabricating a thin film transistor, including:
  • etch stop layer Forming a pattern including an active layer, an etch stop layer, and source and drain electrodes on the active layer using the same mask, wherein the etch stop layer is arranged to electrically connect the source and drain To the active layer.
  • a pattern including an active layer, an etch stop layer, and source and drain electrodes on the active layer is formed, including:
  • Exposing and developing the photoresist layer by using a gray scale mask forming a first photoresist completely reserved region in a region corresponding to the pattern of the source to be formed in the photoresist layer, and being formed with Forming a second photoresist completely reserved region in a region corresponding to the pattern of the drain, forming a photoresist partial retention region in a region corresponding to a pattern of the source to be formed and a pattern of the drain, and waiting for Forming a photoresist completely removed region around the region corresponding to the pattern of the formed active layer;
  • the source and drain films, the etch barrier film, and the semiconductor film containing the metal element are etched using the photoresist layer and an etching process to form a pattern including a source, a drain, and an active layer.
  • the source and drain films, the etch barrier film, and the semiconductor film containing the metal element are etched using the photoresist layer and an etching process to form a pattern including a source, a drain, and an active layer, including :
  • the source and drain films are first etched by a wet etching process, and remain in a region corresponding to the first photoresist completely remaining region, the second photoresist completely remaining region, and the photoresist portion remaining region.
  • the etch barrier film is first etched by a dry etching process, and remains in a region corresponding to the first photoresist completely reserved region, the second photoresist completely reserved region, and the photoresist portion reserved region.
  • the etch barrier film is first etched by a dry etching process, and remains in a region corresponding to the first photoresist completely reserved region, the second photoresist completely reserved region, and the photoresist portion reserved region.
  • the photoresist layer of the first photoresist completely reserved region, the second photoresist completely reserved region, and the photoresist portion remaining region is subjected to ashing treatment to completely remove the photoresist layer in the photoresist remaining region, and simultaneously Thinning the photoresist layer in the completely remaining region of the first photoresist and the completely remaining region of the second photoresist;
  • the source and drain films are etched a second time by a wet etching process to retain the source and drain films in a region corresponding to the first photoresist completely remaining region and the second photoresist completely remaining region. Forming a pattern including a source and a drain;
  • the metal element-containing semiconductor film is etched by a wet etching process, and remains in a region corresponding to the first photoresist completely remaining region, the second photoresist completely remaining region, and the photoresist portion remaining region.
  • the method before sequentially forming a semiconductor film containing a metal element, an etch barrier film, and a source/drain film on a base substrate, the method further includes: forming a pattern including a gate on the base substrate and covering the gate including a patterned gate insulating layer;
  • Forming a semiconductor film containing a metal element, an etch barrier film, and a source/drain film sequentially on the base substrate comprising: sequentially forming on the base substrate on which the pattern including the gate electrode and the gate insulating layer are formed A semiconductor film containing a metal element, an etch barrier film, and a source/drain film.
  • the material of the metal element-containing semiconductor film is a metal oxide semiconductor material or a metal doped semiconductor material.
  • the material of the etch barrier film is graphite, graphene or carbon nanomaterial.
  • the material of the etch barrier film is a mixture of at least one of graphite, graphene, and carbon nanomaterials and a non-metal oxide.
  • the material of the etch barrier film is a non-metallic dopant.
  • the thickness of the etch barrier film is approximately
  • the present disclosure provides a thin film transistor including a substrate substrate, a semiconductor active layer containing a metal element on the base substrate, a source and a drain on the active layer, And an etch barrier layer between the source and the active layer and between the drain and the active layer, wherein the etch stop layer is arranged to place the source and drain A pole is electrically connected to the active layer.
  • the present disclosure provides an array substrate comprising a thin film transistor as described above.
  • the present disclosure provides a display device comprising an array substrate as described above.
  • 1 is a schematic structural view of a thin film transistor
  • FIG. 2 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • 4a, 4b, 4c, 4d, 4e, 4f, 4g, and 4h are schematic structural diagrams during fabrication of a thin film transistor according to an embodiment of the present disclosure.
  • a thin film transistor, a method for fabricating the same, an array substrate, and a display panel provided by the embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings and embodiments.
  • a conventional bottom-gate thin film transistor is as shown in FIG. 1 and includes a substrate 1 , a gate 2 on the substrate 1 , an active layer 4 insulated from the gate 2 through the insulating layer 3 , and The source layer 4 is electrically connected to the source 5 and the drain 6.
  • the active layer 4 is a semiconductor material containing a metal element
  • the etching is performed on the source.
  • the active layer region between 5 and drain 6 causes damage. This results in failure to meet design requirements, reduced mobility, and affects the performance of thin film transistors.
  • Embodiments of the present disclosure provide a method of fabricating a thin film transistor. As shown in FIG. 2, the manufacturing method includes the following steps:
  • Step 210 sequentially forming a semiconductor film containing a metal element, an etch barrier film, and a source/drain film on the base substrate;
  • Step 220 forming a pattern including an active layer, an etch barrier layer, and a source and a drain on the active layer using the same mask, wherein the etch barrier layer is arranged to be the source and the drain A pole is electrically connected to the active layer.
  • the etch barrier film can protect the semiconductor film containing the metal element when etching the metal layer. Since the etching stopper film is formed on the semiconductor film containing the metal element, the etching stopper film protects the semiconductor film containing the metal element from being etched in the patterning process, thereby ensuring the performance of the formed active layer .
  • the etching method for etching the etching stopper film is different from the etching method for the semiconductor film containing a metal element, so that the semiconductor film containing the metal element is not damaged.
  • step 220 includes the following steps:
  • the photoresist layer is exposed and developed by using a gray scale mask, and a first photoresist completely reserved region is formed in a region corresponding to the pattern of the source to be formed in the photoresist layer, and the drain to be formed is formed.
  • Forming a second photoresist completely reserved area in the corresponding area of the pattern in Forming a photoresist portion remaining region in a corresponding region between the pattern of the source to be formed and the drain pattern, and forming a photoresist completely removed region around the region corresponding to the pattern of the active layer to be formed;
  • the source and drain films, the etch barrier film, and the semiconductor film containing the metal element are etched using a photoresist layer and an etching process to form a pattern including a source, a drain, and an active layer.
  • a mask is formed using a gray scale mask.
  • a mask can be formed by using a halftone mask.
  • a source and a drain film, an etch barrier film, and a semiconductor film containing a metal element are etched by using a photoresist layer and an etching process to form a pattern including a source, a drain, and an active layer, including :
  • the source and drain films are first etched by a wet etching process, and the source in a region corresponding to the first photoresist completely reserved region, the second photoresist completely reserved region, and the photoresist portion reserved region is retained. Drain film
  • the etching etch film is first etched by a dry etching process, and is left in the region corresponding to the completely remaining region of the first photoresist, the completely remaining region of the second photoresist, and the remaining portion of the photoresist portion.
  • Etch barrier film
  • the photoresist layer of the first photoresist completely reserved region, the second photoresist completely reserved region, and the photoresist portion remaining region is subjected to ashing treatment to completely remove the photoresist layer in the photoresist remaining region, and simultaneously Thinning the photoresist layer in the completely remaining region of the first photoresist and the completely remaining region of the second photoresist;
  • the source and drain films are etched a second time by a wet etching process, and the source and drain films in a region corresponding to the first photoresist completely remaining region and the second photoresist completely remaining region are retained, thereby forming the inclusion Source and drain patterns;
  • the semiconductor film containing the metal element is etched by a wet etching process to retain the metal contained in the region corresponding to the completely remaining region of the first photoresist, the completely remaining region of the second photoresist, and the remaining portion of the photoresist portion.
  • the photoresist layer of the first photoresist completely remaining region and the second photoresist completely remaining region is removed.
  • the barrier film is etched.
  • the semiconductor film containing the metal element can be protected from etching.
  • the etch barrier film is dry etched. Generally, dry etching does not cause damage to a semiconductor film containing a metal element. This further ensures the performance of the formed active layer.
  • the photoresist used may be a positive photoresist or a negative photoresist.
  • the method provided by the embodiment of the present disclosure further includes: forming on the substrate substrate a pattern of the gate and a gate insulating layer covering the pattern including the gate.
  • Forming a semiconductor film containing a metal element, an etch barrier film, and a source/drain film sequentially on the base substrate comprising: sequentially forming a metal element on the base substrate on which the pattern including the gate electrode and the gate insulating layer are formed The semiconductor film, the etch barrier film, and the source and drain films.
  • the material of the semiconductor film containing the metal element may be, but not limited to, a metal oxide semiconductor material or a metal doped semiconductor material.
  • the metal oxide semiconductor material may be, but not limited to, IGZO.
  • the metal-doped semiconductor material may be, but not limited to, zinc sulfide (ZnS), cadmium telluride (CdTe), copper gallium selenide (CuGaSe 2 ), silver indium telluride (AglnTe 2 ), silver telluride (AgTlTe 2 ). Or copper sulphide (Cu 2 FeSnS 4 ).
  • the material of the etch barrier film may be, but not limited to, graphite, graphene, carbon nanomaterial; a mixture of at least one of graphite, graphene, carbon nanomaterial and non-metal oxide; or Non-metallic dopants.
  • the etch barrier film may be listed, and other materials may be used as long as the semiconductor film containing the metal element is not etched, and the etching process of the etch barrier film is not It can damage the semiconductor film.
  • the material of the etch stop film is electrically conductive such that a subsequently formed etch stop layer electrically connects the source and drain to the active layer, respectively.
  • the non-metallic dopant may be a material in which one of silicon is doped with boron, nitrogen, phosphorus, and arsenic, or a material in which one of boron, nitrogen, phosphorus, and arsenic is doped, or other materials.
  • the material of the non-metal oxide may be, but not limited to, silicon oxide or silicon oxynitride.
  • the thickness of the etch barrier film is approximately For example, the thickness of the etch barrier film is
  • an embodiment of the present disclosure also provides a thin film transistor.
  • the thin film transistor is fabricated by the fabrication method as described in any of the above embodiments.
  • the thin film transistor includes a base substrate, a semiconductor active layer containing a metal element on the base substrate, a source and a drain on the active layer, and a source and an active layer between the source and the drain An etch stop layer with the active layer, wherein the etch stop layer is arranged to electrically connect the source and drain to the active layer.
  • a thin film transistor and a method for fabricating the same according to the structure of a specific thin film transistor are described in more detail below.
  • the structure of the thin film transistor is as shown in FIG. 3, and includes a base substrate 01, a gate electrode 02 on the base substrate 01, a gate insulating layer 03 covering the gate electrode 02, and a metal on the gate insulating layer 03.
  • the manufacturing method of the above thin film transistor structure includes, for example, the following steps 1 to 9.
  • Step 1 sequentially forming a gate electrode 02, a gate insulating layer 03, a metal oxide semiconductor film 04', an etch barrier film 07', a source/drain film 05', and a photoresist layer 08 on the base substrate 01. Shown in 4a.
  • the etch barrier film in this embodiment is graphite, and the material of the metal oxide semiconductor film is Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • Step 2 performing exposure development on the photoresist layer 08 to form a first photoresist completely remaining region A in the region corresponding to the pattern of the source to be formed in the photoresist layer 08, and the drain to be formed Forming a second photoresist completely remaining region B in a region corresponding to the pattern, forming a photoresist portion remaining region C in a region corresponding to a pattern of a source to be formed and a pattern of a drain, and being formed A complete photoresist removal region D is formed around the corresponding region of the pattern of the active layer, as shown in FIG. 4b.
  • Step 3 performing a first etching of the source/drain film 05' by a wet etching process, leaving the first photoresist completely reserved region A, the second photoresist completely remaining region B, and the photoresist partially retained.
  • the source/drain film 05' in the region corresponding to the region C is as shown in FIG. 4c.
  • Step 4 performing a first etching on the etch barrier film 07' by a dry etching process, leaving the first photoresist completely reserved region A, the second photoresist completely remaining region B, and the photoresist portion retained.
  • the etch barrier film 07' in the region corresponding to the region C is as shown in Fig. 4d.
  • Step 5 performing ashing treatment on the photoresist layer 08 in the first photoresist completely remaining region A, the second photoresist completely remaining region B, and the photoresist portion remaining region C, completely
  • the photoresist layer 08 in the photoresist portion retention region C is removed, and the photoresist layer 08 in the first photoresist completely remaining region A and the second photoresist completely remaining region B is thinned, as shown in FIG. 4e. Show.
  • Step 6 performing a second etching on the source/drain film 05' by a wet etching process to remove the source/drain film 05' in a region corresponding to the photoresist partially remaining region C, and retaining the first light
  • the engraving completely retains the source and drain film 05' in the region corresponding to the region A and the second photoresist completely remaining region B, thereby forming at least the pattern 05 of the source and the pattern 06 of the drain, as shown in FIG. 4f.
  • Step 7 etching the metal oxide semiconductor film 04' by a wet etching process, and retaining corresponding to the first photoresist completely remaining region A, the second photoresist completely remaining region B, and the photoresist partially reserved region The metal oxide semiconductor film 04' in the region C, thereby forming at least the pattern 04 of the active layer, as shown in Fig. 4g.
  • Step 8 The etching etch film 07' is etched a second time by a dry etching process to remove the etch barrier film 07' in the region corresponding to the photoresist portion remaining region C, as shown in Fig. 4h.
  • etching of the etch barrier film 07' is completed to obtain an etch stop layer 07 as shown in FIG.
  • Step 9 Removing the photoresist layer 08 in the first photoresist completely remaining region A and the second photoresist completely remaining region B.
  • an embodiment of the present disclosure further provides an array substrate including the thin film transistor according to any of the above embodiments.
  • an embodiment of the present disclosure further provides a display device including the array substrate as described in the above embodiments.
  • the display device may be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the etch barrier film is formed on the semiconductor film containing the metal element, the etch barrier film can be protected when the metal layer is etched The semiconductor film containing the metal element is not etched, and the performance of the formed active layer is ensured.

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  • Engineering & Computer Science (AREA)
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Abstract

公开了一种薄膜晶体管及其制作方法、阵列基板、显示面板。该制作方法包括：在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻膜以及源漏极膜；以及利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。由于在含有金属元素的半导体膜上形成有刻蚀阻挡膜，在构图工艺中，该刻蚀阻挡膜可以保护含有金属元素的半导体膜不被刻蚀，保证了形成的有源层的性能。 (图2)

Description

薄膜晶体管及其制作方法、阵列基板、显示面板
相关专利申请
本申请主张于2016年10月31日提交的中国专利申请No.201610943113.4的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板、显示面板。
背景技术
薄膜晶体管(Thin-film Transistor，TFT)在显示器件中具有十分重要的作用。作为非线性开关元件，薄膜晶体管被广泛地应用于大尺寸LCD显示器和AM-OLED显示器中。
薄膜晶体管的有源层可能为含有金属元素的半导体材料，例如金属氧化物半导体材料、掺杂金属的半导体材料。这种情况下，在刻蚀金属层以形成源极和漏极时，由于有源层中含有金属元素，该刻蚀会对源极和漏极之间的有源层区域造成损伤。这导致有源层不能满足设计需求，迁移率降低，进而影响薄膜晶体管的性能。
发明内容
本公开实施例的目的是提供一种薄膜晶体管及其制作方法、阵列基板、显示面板，用于减轻或克服一个或多个前文所述的缺点。
在第一方面，本公开提供了一种薄膜晶体管的制作方法，包括：
在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜；以及
利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
例如，利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，包括：
在源漏极膜上涂覆光刻胶层；
利用灰阶掩膜版对光刻胶层进行曝光显影，在所述光刻胶层中与待形成的源极的图形对应的区域中形成第一光刻胶完全保留区域，在与待形成的漏极的图形对应的区域中形成第二光刻胶完全保留区域，在与待形成的源极的图形和漏极的图形之间对应的区域中形成光刻胶部分保留区域，以及在与待形成的有源层的图形对应的区域周围形成光刻胶完全去除区域；以及
利用所述光刻胶层和刻蚀工艺，刻蚀所述源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形。
例如，利用所述光刻胶层和刻蚀工艺，刻蚀所述源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形，包括：
采用湿法刻蚀工艺对所述源漏极膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述源漏极膜；
采用干法刻蚀工艺对所述刻蚀阻挡膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述刻蚀阻挡膜；
对第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域的光刻胶层进行灰化处理，完全去除光刻胶部分保留区域的光刻胶层，同时减薄第一光刻胶完全保留区域以及第二光刻胶完全保留区域的光刻胶层；
采用湿法刻蚀工艺对所述源漏极膜进行第二次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域对应的区域中的所述源漏极膜，从而形成包括源极和漏极的图形；
采用湿法刻蚀工艺对所述含有金属元素的半导体膜进行刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述含有金属元素的半导体膜，从而形成包括有源层的图形；
采用干法刻蚀工艺对所述刻蚀阻挡膜进行第二次刻蚀，去除与光刻胶部分保留区域对应的区域中的所述刻蚀阻挡膜；以及
去除所述第一光刻胶完全保留区域以及第二光刻胶完全保留区域 的光刻胶层。
例如，在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜之前，该方法还包括：在衬底基板上形成包括栅极的图形以及覆盖所述包括栅极的图形的栅绝缘层；以及
其中在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜，包括：在形成有所述包括栅极的图形和所述栅绝缘层的衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜。
例如，所述含有金属元素的半导体膜的材料为金属氧化物半导体材料或掺杂金属的半导体材料。
例如，所述刻蚀阻挡膜的材料为石墨、石墨烯或者碳纳米材料。例如，所述刻蚀阻挡膜的材料为石墨、石墨烯、碳纳米材料中的至少一种与非金属氧化物的混合物。例如，所述刻蚀阻挡膜的材料为非金属掺杂物。
例如，所述刻蚀阻挡膜的厚度是大约
Figure PCTCN2017106504-appb-000001
在第二方面，本公开提供了一种薄膜晶体管，包括衬底基板、位于所述衬底基板上的含有金属元素的半导体有源层、位于所述有源层上的源极和漏极、以及位于所述源极与所述有源层之间并且位于所述漏极与所述有源层之间的刻蚀阻挡层，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
在第三方面，本公开提供了一种阵列基板，包括如以上所述的薄膜晶体管。
在第四方面，本公开提供了一种显示装置，包括如以上所述的阵列基板。
附图说明
图1为一种薄膜晶体管的结构示意图；
图2为本公开实施例提供的一种薄膜晶体管的制作方法流程图；
图3为本公开实施例提供的一种薄膜晶体管的结构示意图；以及
图4a、4b、4c、4d、4e、4f、4g和4h为本公开实施例提供的一种薄膜晶体管的制作过程中的结构示意图。
具体实施方式
下面结合附图和实施例对本公开实施例提供的一种薄膜晶体管、其制作方法、阵列基板及显示面板进行更详细地说明。
目前，比较常规的底栅型薄膜晶体管如图1所示，包括衬底基板1，位于衬底基板1上的栅极2、通过绝缘层3与栅极2绝缘的有源层4、与有源层4电连接的源极5和漏极6。对于有源层4为含有金属元素的半导体材料的薄膜晶体管，在刻蚀金属层以形成源极5和漏极6时，由于有源层4中也含有金属元素，该刻蚀会对源极5和漏极6之间的有源层区域造成损伤。这导致不能满足设计需求，迁移率降低，影响薄膜晶体管的性能。
本公开实施例提供一种薄膜晶体管的制作方法。如图2所示，该制作方法包括如下步骤：
步骤210、在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜；以及
步骤220、利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
该刻蚀阻挡膜可以在刻蚀金属层时对含有金属元素的半导体膜进行保护。由于在含有金属元素的半导体膜上形成有刻蚀阻挡膜，在构图工艺中，该刻蚀阻挡膜保护该含有金属元素的半导体膜不被刻蚀，由此保证了形成的有源层的性能。
此外，刻蚀该刻蚀阻挡膜所采用的刻蚀方法与含有金属元素的半导体膜的刻蚀方法不同，因此不会对含有金属元素的半导体膜造成损伤。
另外，本制作工艺中，只利用同一掩膜版，完成包括源极、漏极、刻蚀阻挡层以及有源层的图形的刻蚀，节省掩膜次数，简化工艺，降低了成本。
具体实施时，例如，上述步骤220包括下述步骤：
在所述源漏极膜上涂覆光刻胶层；
利用灰阶掩膜版对光刻胶层进行曝光显影，在光刻胶层中与待形成的源极的图形对应的区域中形成第一光刻胶完全保留区域，在与待形成的漏极的图形对应的区域中形成第二光刻胶完全保留区域，在与 待形成的源极的图形和漏极的图形之间对应的区域中形成光刻胶部分保留区域，以及在与待形成的有源层的图形对应的区域周围形成光刻胶完全去除区域；以及
利用光刻胶层和刻蚀工艺，刻蚀源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形。
本实施例中，利用灰阶掩膜版形成掩膜。实际实施时，具体可以利用半色调掩膜版形成掩膜。
具体实施时，例如，利用光刻胶层和刻蚀工艺，刻蚀源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形，包括：
采用湿法刻蚀工艺对源漏极膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的源漏极膜；
采用干法刻蚀工艺对刻蚀阻挡膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的刻蚀阻挡膜；
对第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域的光刻胶层进行灰化处理，完全去除光刻胶部分保留区域的光刻胶层，同时减薄第一光刻胶完全保留区域以及第二光刻胶完全保留区域的光刻胶层；
采用湿法刻蚀工艺对源漏极膜进行第二次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域对应的区域中的源漏极膜，从而形成包括源极和漏极的图形；
采用湿法刻蚀工艺对含有金属元素的半导体膜进行刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的含有金属元素的半导体膜，从而形成包括有源层的图形；
采用干法刻蚀工艺对刻蚀阻挡膜进行第二次刻蚀，去除与光刻胶部分保留区域对应的区域中的刻蚀阻挡膜；以及
去除第一光刻胶完全保留区域以及第二光刻胶完全保留区域的光刻胶层。
本实施例中，在采用湿法刻蚀工艺刻蚀源漏极膜时，刻蚀阻挡膜 可以保护含有金属元素的半导体膜不被刻蚀。该刻蚀阻挡膜是采用干法刻蚀。一般干法刻蚀不会对含有金属元素的半导体膜造成损伤。这进一步保证了形成的有源层的性能。
以上实施例中，所采用的光刻胶可以是正性光刻胶，也可以是负性光刻胶。
基于以上任意实施例，例如，在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜之前，本公开实施例提供的方法还包括：在衬底基板上形成包括栅极的图形以及覆盖所述包括栅极的图形的栅绝缘层。
在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜，包括：在形成有包括栅极的图形和所述栅绝缘层的衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜。
基于以上任意实施例，例如，含有金属元素的半导体膜的材料可以但不限于为金属氧化物半导体材料或掺杂金属的半导体材料。
金属氧化物半导体材料可以但不限于为IGZO。
掺杂金属的半导体材料可以但不限于是硫化锌(ZnS)、碲化镉(CdTe)、硒化铜镓(CuGaSe2)、碲化银铟(AglnTe2)、碲化银铊(AgTlTe2)或硫化铜铁锡(Cu2FeSnS4)。
基于以上任意实施例，例如，刻蚀阻挡膜的材料可以但不限于为石墨、石墨烯、碳纳米材料；石墨、石墨烯、碳纳米材料中的至少一种与非金属氧化物的混合物；或者非金属掺杂物。此处只是列举了几种可采用的刻蚀阻挡膜的材料，也可以采用其它的材料，只要能够保护含有金属元素的半导体膜不被刻蚀，且该刻蚀阻挡膜的刻蚀过程中不会对半导体膜造成损伤即可。该刻蚀阻挡膜的材料是导电的，使得后续形成的刻蚀阻挡层将源极和漏极分别电连接到有源层。
非金属掺杂物可以是硅掺杂硼、氮、磷和砷其中一种的材料，也可以是锗掺杂硼、氮、磷和砷其中一种的材料，或者其它材料。
非金属氧化物的材料可以但不限于为氧化硅或者氮氧化硅。
刻蚀阻挡膜的厚度是大约
Figure PCTCN2017106504-appb-000002
例如，刻蚀阻挡膜的厚度为
Figure PCTCN2017106504-appb-000003
基于同样的发明构思，本公开实施例还提供一种薄膜晶体管。该薄膜晶体管是采用如以上任意实施例所述的制作方法制作得到的。该 薄膜晶体管包括衬底基板、位于所述衬底基板上的含有金属元素的半导体有源层、位于有源层上的源极和漏极、以及位于源极与有源层之间并且位于漏极与有源层之间的刻蚀阻挡层，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
下面以具体的薄膜晶体管的结构为例，对本公开实施例提供的一种薄膜晶体管及其制作方法进行更加详细地描述。
本实施例中，薄膜晶体管的结构如图3所示，包括衬底基板01，位于衬底基板01上的栅极02，覆盖栅极02的栅绝缘层03，位于栅绝缘层03上的金属氧化物半导体材料的有源层的图形04，位于该有源层的图形04上的源极的图形05和漏极的图形06，以及位于源极的图形05与有源层的图形04之间并且位于漏极的图形06与有源层的图形04之间的刻蚀阻挡层07。以上薄膜晶体管结构的制作方法例如包括下述步骤一至步骤九。
步骤一、在衬底基板01上依次形成栅极02、栅绝缘层03、金属氧化物半导体膜04’、刻蚀阻挡膜07’、源漏极膜05’以及光刻胶层08，如图4a所示。
本实施例中的刻蚀阻挡膜为石墨，并且金属氧化物半导体膜的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
步骤二、对光刻胶层08进行曝光显影，在光刻胶层08中与待形成的源极的图形对应的区域中形成第一光刻胶完全保留区域A，与待形成的漏极的图形对应的区域中形成第二光刻胶完全保留区域B，在与待形成的源极的图形和漏极的图形之间对应的区域中形成光刻胶部分保留区域C，以及在与待形成的有源层的图形对应的区域周围形成光刻胶完全去除区域D，如图4b所示。
步骤三、采用湿法刻蚀工艺对源漏极膜05’进行第一次刻蚀，保留与第一光刻胶完全保留区域A、第二光刻胶完全保留区域B以及光刻胶部分保留区域C对应的区域中的源漏极膜05’，如图4c所示。
步骤四、采用干法刻蚀工艺对刻蚀阻挡膜07’进行第一次刻蚀，保留与第一光刻胶完全保留区域A、第二光刻胶完全保留区域B以及光刻胶部分保留区域C对应的区域中的刻蚀阻挡膜07’，如图4d所示。
步骤五、对第一光刻胶完全保留区域A、第二光刻胶完全保留区域B以及光刻胶部分保留区域C中的光刻胶层08进行灰化处理，完全 去除光刻胶部分保留区域C中的光刻胶层08，同时减薄第一光刻胶完全保留区域A以及第二光刻胶完全保留区域B中的光刻胶层08，如图4e所示。
步骤六、采用湿法刻蚀工艺对源漏极膜05’进行第二次刻蚀，去除与光刻胶部分保留区域C对应的区域中的源漏极膜05’，并且保留与第一光刻胶完全保留区域A以及第二光刻胶完全保留区域B对应的区域中的源漏极膜05’，从而至少形成源极的图形05和漏极的图形06，如图4f所示。
步骤七、采用湿法刻蚀工艺对金属氧化物半导体膜04’进行刻蚀，保留与第一光刻胶完全保留区域A、第二光刻胶完全保留区域B以及光刻胶部分保留区域对应的区域C中的金属氧化物半导体膜04’，从而至少形成有源层的图形04，如图4g所示。
步骤八、采用干法刻蚀工艺对刻蚀阻挡膜07’进行第二次刻蚀，去除与光刻胶部分保留区域C对应的区域中的刻蚀阻挡膜07’，如图4h所示。
该步骤中，完成对刻蚀阻挡膜07’的刻蚀，得到如图3所示的刻蚀阻挡层07。
步骤九、去除第一光刻胶完全保留区域A以及第二光刻胶完全保留区域B中的光刻胶层08。
该步骤结束之后就得到了具有如图3所示结构的薄膜晶体管。
基于同样的发明构思，本公开实施例还提供一种阵列基板，包括如以上任意实施例所述的薄膜晶体管。
基于同样的发明构思，本公开实施例还提供一种显示装置，包括如以上实施例所述的阵列基板。需要说明的是，所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的薄膜晶体管及其制作方法、阵列基板、显示面板中，由于在含有金属元素的半导体膜上形成有刻蚀阻挡膜，在刻蚀金属层时，该刻蚀阻挡膜可以保护含有金属元素的半导体膜不被刻蚀，保证了形成的有源层的性能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不 脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜；以及
    利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
  2. 根据权利要求1所述的制作方法，其中利用同一掩膜版，形成包括有源层、刻蚀阻挡层以及在有源层上的源极和漏极的图形，包括：
    在源漏极膜上涂覆光刻胶层；
    利用灰阶掩膜版对所述光刻胶层进行曝光显影，在所述光刻胶层中与待形成的源极的图形对应的区域中形成第一光刻胶完全保留区域，在与待形成的漏极的图形对应的区域中形成第二光刻胶完全保留区域，在与待形成的源极的图形和漏极的图形之间对应的区域中形成光刻胶部分保留区域，以及在与待形成的有源层的图形对应的区域周围形成光刻胶完全去除区域；以及
    利用所述光刻胶层和刻蚀工艺，刻蚀所述源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形。
  3. 根据权利要求2所述的制作方法，其中利用所述光刻胶层和刻蚀工艺，刻蚀所述源漏极膜、刻蚀阻挡膜以及含有金属元素的半导体膜以形成包括源极、漏极以及有源层的图形，包括：
    采用湿法刻蚀工艺对所述源漏极膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述源漏极膜；
    采用干法刻蚀工艺对所述刻蚀阻挡膜进行第一次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述刻蚀阻挡膜；
    对第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域的光刻胶层进行灰化处理，完全去除光刻胶部分保留区域的光刻胶层，同时减薄第一光刻胶完全保留区域以及第二光刻胶 完全保留区域的光刻胶层；
    采用湿法刻蚀工艺对所述源漏极膜进行第二次刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域对应的区域中的所述源漏极膜，从而形成包括源极和漏极的图形；
    采用湿法刻蚀工艺对所述含有金属元素的半导体膜进行刻蚀，保留与第一光刻胶完全保留区域、第二光刻胶完全保留区域以及光刻胶部分保留区域对应的区域中的所述含有金属元素的半导体膜，从而形成包括有源层的图形；
    采用干法刻蚀工艺对所述刻蚀阻挡膜进行第二次刻蚀，去除与光刻胶部分保留区域对应的区域中的所述刻蚀阻挡膜；以及
    去除所述第一光刻胶完全保留区域以及第二光刻胶完全保留区域的光刻胶层。
  4. 根据权利要求1～3中任意一项所述的制作方法，其中在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜之前，该方法还包括：在衬底基板上形成包括栅极的图形以及覆盖所述包括栅极的图形的栅绝缘层，以及
    其中在衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜，包括：在形成有所述包括栅极的图形和所述栅绝缘层的衬底基板上依次形成含有金属元素的半导体膜、刻蚀阻挡膜以及源漏极膜。
  5. 根据权利要求1～3中任意一项所述的制作方法，其中所述含有金属元素的半导体膜的材料为金属氧化物半导体材料或掺杂金属的半导体材料。
  6. 根据权利要求1所述的制作方法，其中所述刻蚀阻挡膜的材料为石墨、石墨烯或者碳纳米材料。
  7. 根据权利要求1所述的制作方法，其中所述刻蚀阻挡膜的材料为石墨、石墨烯、碳纳米材料中的至少一种与非金属氧化物的混合物。
  8. 根据权利要求1所述的制作方法，其中所述刻蚀阻挡膜的材料为非金属掺杂物。
  9. 根据权利要求8所述的制作方法，其中所述非金属掺杂物为硅掺杂硼、氮、磷和砷其中一种，或者锗掺杂硼、氮、磷和砷其中一种。
  10. 根据权利要求6-9中任意一项所述的制作方法，其中所述刻蚀 阻挡膜的厚度是大约
    Figure PCTCN2017106504-appb-100001
  11. 一种薄膜晶体管，包括衬底基板、位于所述衬底基板上的含有金属元素的半导体有源层、位于所述有源层上的源极和漏极、以及位于所述源极与所述有源层之间并且位于所述漏极与所述有源层之间的刻蚀阻挡层，其中所述刻蚀阻挡层布置成将所述源极和漏极电连接到所述有源层。
  12. 一种阵列基板，包括如权利要求11所述的薄膜晶体管。
  13. 一种显示装置，包括如权利要求12所述的阵列基板。
PCT/CN2017/106504 2016-10-31 2017-10-17 薄膜晶体管及其制作方法、阵列基板、显示面板 Ceased WO2018077065A1 (zh)

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