WO2018070417A1 - 構造物、その製造方法、半導体素子及び電子回路 - Google Patents
構造物、その製造方法、半導体素子及び電子回路 Download PDFInfo
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- WO2018070417A1 WO2018070417A1 PCT/JP2017/036802 JP2017036802W WO2018070417A1 WO 2018070417 A1 WO2018070417 A1 WO 2018070417A1 JP 2017036802 W JP2017036802 W JP 2017036802W WO 2018070417 A1 WO2018070417 A1 WO 2018070417A1
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- Prior art keywords
- metal oxide
- layer
- noble metal
- oxide semiconductor
- structure according
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
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- H01L31/108—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the Schottky type
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Definitions
- the present invention relates to a structure, a manufacturing method thereof, a semiconductor element, and an electronic circuit.
- a Schottky junction usually means a junction resulting from a metal-semiconductor interface that exhibits a rectifying action.
- the rectifying action is an action that easily allows current to flow in one direction from the metal to the semiconductor or from the semiconductor to the metal. This action is caused by a change in the depletion layer that spreads from the metal-semiconductor interface to the semiconductor side in the Schottky junction. Yes. Since metals and semiconductors are generally classified according to the presence or absence of the depletion layer spread, they are in contact with different materials, and if the change in the depletion layer spread is observed only on one side of the material, a Schottky junction is used.
- thin film semiconductors can be cited, and amorphous silicon, polycrystalline silicon, metal oxide semiconductors, and organic thin film semiconductors are attracting attention.
- TFTs thin film transistors
- Schottky junctions have few reports and are poorly understood.
- pinning levels generated at the Schottky interface hindered practical application. Pinning levels are also a problem for Schottky junctions in single crystal silicon, and are determined by the expected Schottky barrier height (the metal work function, the Fermi level difference of the semiconductor, and the energy level of the semiconductor band edge).
- the height of the barrier is reduced as compared to the above.
- organic semiconductors the practical use of TFTs is limited due to their stability and process adaptability, and it has been difficult to consider application to Schottky devices.
- Metal oxide semiconductors are recognized as semiconductors suitable as TFTs for display applications, and are expected to be expanded to further applications utilizing their process suitability, electrical characteristics, and stability.
- Patent Document 1 describes that a Schottky barrier can be formed by using a metal oxide Schottky electrode for single crystal ZnO.
- Non-Patent Document 1 for an InGaZnO thin film that is an amorphous metal oxide semiconductor, Pt deposited by electron beam is selected for a Schottky electrode, and SiO 2 , polyimide, and polyethylene terephthalate are selected for a substrate, and diode characteristics are evaluated. .
- Non-Patent Document 2 describes that Pt, Au, and Pd are Schottky electrodes, a semiconductor is an InGaZnO thin film, and a semiconductor film is formed after UV-ozone treatment is performed on the surface of the Schottky electrode on a glass substrate. .
- Non-Patent Document 3 it is possible to form a Schottky barrier for bulk single crystal ZnO, heteroepitaxial ZnO thin film, and amorphous GaInZnO thin film by using 10 nm silver oxide formed by reactive sputtering as a Schottky electrode.
- Non-Patent Document 4 Pt, which is a Schottky electrode, is formed on a SiO 2 substrate, and an InGaZnO semiconductor thin film and an Al ohmic electrode are stacked thereon.
- Patent Document 2 describes that a Si substrate is used as a support substrate and an ohmic junction, and a Schottky performance is obtained by using a noble metal electrode on top of a metal oxide semiconductor containing In regardless of whether it is polycrystalline or amorphous. Yes.
- An object of the present invention is to provide a structure having a Schottky barrier function, a method of manufacturing the same, a semiconductor, which is capable of forming a film at a low temperature, has excellent process adaptability, can freely select a substrate, and has a low reverse current characteristic It is to provide an element and an electronic circuit.
- a metal oxide semiconductor layer; A noble metal oxide layer, The metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, A structure in which the noble metal oxide layer has a thickness of more than 10 nm.
- 2. The structure according to 1, having a depletion region. 3.
- 3. The structure according to 1 or 2, wherein the noble metal oxide layer includes a polycrystalline structure. 4).
- 4. The structure according to any one of 1 to 3, further including a noble metal layer on the side opposite to the metal oxide semiconductor layer adjacent to the noble metal oxide layer. 5).
- the structure according to 4 further comprising a low-resistance base metal layer on the opposite side of the noble metal oxide layer adjacent to the noble metal layer. 6).
- the noble metal oxide of the noble metal oxide layer is one or more selected from the group consisting of palladium oxide, ruthenium oxide, platinum oxide, iridium oxide, silver oxide, rhenium oxide, osmium oxide, rhodium oxide, nickel oxide and gold oxide.
- the structure according to any one of 1 to 5. 7).
- Noble metal oxide of the noble metal oxide layer PdO of PdO structure, RuO 2 of rutile structure, ⁇ -PtO 2 PtO 2 structure, Ag 2 O of IrO 2, Cu 2 O structure of rutile structure, skutterudite structure of ReO 3, OsO 2 of rutile structure, either of Rh 2 O 3, NiO structure of corundum structure NiO, and Au 2 O 3 structure is one or more selected from the group consisting of Au 2 O 3 1-6
- the metal oxide of the metal oxide semiconductor layer is an oxide of one or more metal elements selected from the group consisting of In, Sn, Cd, Zn, Ga, and Ge. object.
- the metal oxide of the metal oxide semiconductor layer is an oxide of one or more metal elements selected from the group consisting of In, Sn, Cd, Zn, Ga, and Ge. object.
- a Ga or In content in the metal oxide semiconductor layer is 45 atomic% or more with respect to all metal elements in the metal oxide semiconductor layer.
- the metal oxide semiconductor layer is randomly oriented.
- the noble metal oxide layer and the metal oxide semiconductor layer have a Schottky barrier height of 0.7 eV or more. 18.
- 20. The structure according to any one of 1 to 19, wherein the metal oxide semiconductor layer has one layer or two or more layers, and in the case of two or more layers, any one layer is adjacent to the noble metal oxide layer.
- the noble metal oxide layer and the metal oxide semiconductor layer are continuously formed by sputtering, or the noble metal oxide layer and the metal oxide semiconductor layer are formed between a vacuum and a vacuum. 28.
- Power semiconductor element diode element, Schottky barrier diode element, electrostatic discharge protection diode, transient voltage protection diode, light emitting diode, metal semiconductor field effect transistor, junction field effect transistor, metal oxide semiconductor field effect transistor, Schottky source / 30.
- 31. An electronic circuit using the semiconductor element described in 31.29 or 30.
- the structure which the Schottky barrier functions, the manufacturing method, a semiconductor characterized by being able to form a film at low temperature, excellent in process adaptability, freely selecting a substrate, and having a low reverse current characteristic Devices and electronic circuits can be provided.
- FIG. 6 is a cross-sectional TEM diagram of the elements of Examples 1 to 4. 3 is an enlarged view of a cross-section TEM of the element of Example 1. FIG. 3 is an enlarged view of a cross-section TEM of the element of Example 1. FIG. 6 is a diagram showing the results of CV measurement of the elements of Examples 1 to 4. It is a figure of the IV characteristic evaluation result (semi log plot) of Examples 1-4.
- FIG. 6 is a diagram of an IV forward characteristic evaluation result (semi-log plot) in Example 1.
- FIG. 6 is a diagram in which hv is plotted on the horizontal axis and ( ⁇ hv) 1/2 is plotted on the vertical axis for the quartz substrate with the metal oxide semiconductor layer in Examples 1 to 4.
- FIG. 6 is an XRD pattern diagram of a quartz substrate with a metal oxide semiconductor layer in Examples 1 to 4.
- FIG. 6 is an XRD pattern diagram of a quartz substrate with a metal oxide semiconductor layer in Examples 1 to 4.
- 2 is a diagram of an XRD pattern for the element of Example 1.
- FIG. It is a figure of JCPDS (85-0624) and (89-4897).
- 3 is a cross-sectional TEM view of the device of Example 1.
- FIG. FIG. 6 is an evaluation result diagram of the withstand voltage of the elements of Examples 1 to 4.
- FIG. 10 is a diagram and a cross-sectional view of IV characteristic evaluation results (semi-log plot) of the devices of Examples 5 to 7.
- FIG. 10 is a diagram of differential resistance-voltage (semi-log plot) of the elements of Examples 5 to 7. It is a figure of the IV characteristic evaluation result (semi-log plot) of the element of Example 1, 8, 10 and 22 and Comparative Examples 2-3.
- FIG. 6 is a graph showing the relationship between the on-resistance and breakdown voltage of the elements of Examples 1 to 7.
- the structure of the present invention includes a metal oxide semiconductor layer and a noble metal oxide layer.
- the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and the thickness of the noble metal oxide layer is greater than 10 nm.
- the film can be formed at a low temperature, excellent in process adaptability, and the substrate can be freely selected.
- the Schottky junction can be formed with a thin film, advantages such as process versatility, low-temperature film formation, and selection of no substrate can be obtained.
- device application utilizing flexibility, mixed mounting with various devices, and the like are possible.
- the metal oxide semiconductor layer is preferably one layer or two or more layers. In the case of two or more layers, any one layer may be adjacent to the noble metal oxide layer. Three or more layers, or four or more layers may be used. Usually, it is 5 layers or less, but it may be a multilayer structure of 5 layers or more having a repeating structure.
- the metal oxide semiconductor layer is not particularly limited, and may be amorphous or crystalline, and the crystal may be microcrystalline, single crystal, or polycrystalline. It is preferably microcrystalline, polycrystalline or amorphous, more preferably polycrystalline or amorphous.
- amorphous the large area uniformity is excellent, impact ionization at the time of reverse bias application is reduced, and the breakdown voltage is easily improved.
- variations in electrical characteristics and significant characteristic deterioration can be alleviated.
- a high-current diode and a switching element with high breakdown voltage and high reliability can be manufactured with a high yield. In the case of a polycrystal, it tends to improve large area uniformity and conduction characteristics, and tends to be more stable.
- the crystal structure of the metal oxide semiconductor layer can be measured using, for example, a transmission electron microscope (TEM) or X-ray electron diffraction (XRD).
- TEM transmission electron microscope
- XRD X-ray electron diffraction
- the single crystal can be formed, for example, using a seed crystal as a starting point, or by a method such as MBE (molecular beam epitaxy) or PLD (pulse laser deposition).
- MBE molecular beam epitaxy
- PLD pulse laser deposition
- Amorphous is obtained, for example, by sputtering a metal oxide containing two or more metal elements having different ionic radii as constituent elements, or a metal oxide that generates a plurality of different crystals even if one metal element is used.
- the substrate can be formed by setting the substrate heating temperature during sputtering film formation to 300 ° C. or less and the heat treatment conditions after film formation to 500 ° C. or less for 1 hour or less, and more preferably, the substrate heating temperature is 200 ° C. or less. It can be formed by setting the heat treatment conditions after the film to 400 ° C. or lower. After film formation, a stable amorphous state can be obtained by heating at a low temperature of 200 ° C. or higher and 500 ° C. or lower.
- amorphous means that a clear diffraction spot is obtained when a cross section in the film thickness direction of the metal oxide semiconductor layer is obtained and evaluated by an electron beam diffraction technique such as a transmission electron microscope (TEM). Say what you can't get.
- TEM transmission electron microscope
- a clear spot means that a diffraction point having symmetry is observed from a diffraction image.
- amorphous includes a case where a part is crystallized or microcrystallized. When a partially crystallized portion is irradiated with an electron beam, a diffraction image may be observed.
- Microcrystalline structure refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries. The presence or absence of clear grain boundaries can be observed, for example, by a cross-sectional TEM, and the crystal grain size can be obtained by mapping a diffraction image. The part where the diffraction images are equal can be defined as the same grain. “Polycrystalline” refers to a crystal grain size exceeding micron size and having clear grain boundaries. Clear grain boundaries can be observed, for example, from a cross-sectional TEM. Since there is a clear grain boundary, the particle size can be defined by planar TEM or electron beam backscatter diffraction (EBSD).
- EBSD electron beam backscatter diffraction
- the metal oxide semiconductor layer is preferably randomly oriented regardless of the crystal state from the viewpoint of variation in the Schottky barrier.
- Random orientation means that the orientation of each crystal grain is not biased toward a specific orientation component.
- a thin film is analyzed by XRD
- random orientation is obtained when the relative intensities of a plurality of peaks in the obtained spectrum match the relative intensities in the powder X-ray pattern.
- the second and third peaks of the powder X-ray pattern with respect to the peak intensity of the plane orientation in which the intensity of the powder X-ray pattern is maximum hereinafter referred to as powder X-ray NO.1 peak).
- powder X-ray NO.2 peak and powder X-ray NO.3 peak respectively
- powder X-ray NO. 1 peak / powder X-ray NO. 2 peaks powder X-ray peak intensity ratio 1
- powder X-ray NO.1 peak / powder X-ray NO. 2 peaks powder X-ray NO. 1 peak / powder X-ray NO. 2 peaks
- the peak intensity ratio with 3 peaks is used.
- powder X-ray NO. There are peaks that fall within ⁇ 1 ° with respect to the 2 ⁇ positions of the 1 to NO.3 peaks. 1 corresponds to thin film X-ray peak 1, powder X-ray NO.
- the peak intensity ratio of the thin film X-ray peak 1 / thin film X-ray peak 2 is 0.3 to 3 times the value of the powder X-ray peak intensity ratio 1
- the metal oxide semiconductor layer is Consider random orientation.
- the orientation of the metal oxide semiconductor layer can be measured using, for example, XRD. In the case of a small area, the orientation may be observed from a diffraction image of a cross-sectional TEM.
- Examples of the metal element of the metal oxide of the metal oxide semiconductor layer include In, Sn, Ge, Cd, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. In, Sn, Cd, Zn, Ga and Ge are preferable, and In, Zn, Ga and Sn are more preferable. These may be used alone or in combination of two or more. Thereby, since the spherical orbital of s orbit can be utilized as a conductive path, it is easy to stabilize the electrical characteristics in the in-plane direction regardless of whether it is polycrystalline or amorphous.
- the metal element of the metal oxide of the metal oxide semiconductor layer is essentially one or more selected from the group consisting of In, Sn, Ge, Cd, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. It may consist of only. Further, for example, 95 atomic% or more, 98 atomic% or more, 99 atomic% or more, or 100 atomic% of the metal element of the metal oxide of the metal oxide semiconductor layer is In, Sn, Ge, Cd, Ti, Zn 1 or more selected from the group consisting of Y, Sm, Ce, Nd, Ga and Al.
- the metal element of the metal oxide semiconductor layer contains Ga, In, Zn, or Sn, and the content of Ga, In, Zn, or Sn is 45 atomic% or more with respect to the total metal elements of the metal oxide semiconductor layer. It is preferably 50 to 100 atomic%. In addition, the Ga or In content in the metal oxide semiconductor layer is preferably 45 atomic% or more with respect to the total metal elements in the metal oxide semiconductor layer. When the metal element is Ga, 50 to 100 atomic percent is more preferable, and when In is 50 to 70 atomic percent is more preferable.
- a Schottky interface metal oxide semiconductor layer-noble metal oxide layer interface
- In is 45 atomic% or more
- a metal oxide semiconductor layer having high conductivity and high carrier concentration can be easily obtained, and a Schottky interface having low resistance can be formed.
- Zn is 45 atomic% or more, it is possible to form a Schottky interface that is rich in chemical reactivity and easy to process such as wet etching.
- Sn is 45 atomic% or more, it is rich in chemical stability and can form a Schottky interface superior in terms of durability.
- the metal element of the metal oxide of the metal oxide semiconductor layer preferably satisfies the atomic ratios of the following formulas (A) to (C). This facilitates a high breakdown voltage and low On resistance. 0 ⁇ x / (x + y + z) ⁇ 0.8 (A) 0 ⁇ y / (x + y + z) ⁇ 0.8 (B) 0 ⁇ z / (x + y + z) ⁇ 1.0 (C) (Wherein x represents the number of atoms of one or more elements selected from the group consisting of In, Sn, Ge and Ti, y represents the number of atoms of one or more elements selected from the group consisting of Zn, Y, Sm, Ce and Nd; z represents the number of atoms of one or more elements selected from the group consisting of Ga and Al. )
- x is 0.8 or less, when the element of x is In or Sn, the insulating property of the metal oxide is not too low, and a Schottky junction is easily obtained.
- the element of x is Ge or Ti Can suppress heat generation due to ohmic loss without excessively high insulation of the metal oxide.
- the metal element of the metal oxide of the metal oxide semiconductor layer satisfies the atomic ratio of the following formulas (A-1) to (C-1). 0 ⁇ x / (x + y + z) ⁇ 0.7 (A-1) 0 ⁇ y / (x + y + z) ⁇ 0.8 (B-1)
- the element of z is Ga: 0.02 ⁇ z / (x + y + z) ⁇ 1.0
- the element of z is Al: 0.005 ⁇ z / (x + y + z) ⁇ 0.5 (C-1) (Wherein x, y and z are the same as those in the above formulas (A) to (C)).
- the element of z is Ga, when it is 0.02 or more, oxygen in the metal oxide is difficult to desorb, and variation in electrical characteristics tends to be suppressed.
- the metal element of the metal oxide in the metal oxide semiconductor layer satisfies the atomic ratio of the following formulas (A-2) to (C-2). 0.1 ⁇ x / (x + y + z) ⁇ 0.5 (A-2) 0.1 ⁇ y / (x + y + z) ⁇ 0.5 (B-2) 0.03 ⁇ z / (x + y + z) ⁇ 0.5 (C-2) (Wherein x and y are the same as in the above formulas (A) to (C), and z is the number of Ga atoms.)
- the metal element of the metal oxide of the metal oxide semiconductor layer preferably satisfies the atomic ratios of the following formulas (A-3) and (C-3). 0 ⁇ x / (x + y + z) ⁇ 0.25 (A-3) 0.3 ⁇ z / (x + y + z) ⁇ 1.0 (C-3) (Wherein x, y and z are the same as those in the above formulas (A) to (C)).
- the carrier concentration of the metal oxide semiconductor layer is usually 1 ⁇ 10 11 to 1 ⁇ 10 18 cm ⁇ 3 , for example, 1 ⁇ 10 13 to 1 ⁇ 10 18 cm ⁇ 3 .
- the carrier concentration can be obtained by, for example, CV (capacitance-voltage) measurement.
- the metal oxide of the metal oxide semiconductor layer is InGaZnO (1: 1: 1) (ratio of metal elements in the metal oxide, indicating that In: Ga: Zn is 1: 1: 1. The same applies hereinafter. ), InGaZnO (5: 3: 2), InGaZnO (5: 1: 4), InSnZnO (25:15:60), InSnZnO (48.5: 15: 36.5), InGaO (1: 1) ( Metal element ratio of metal oxide semiconductor, In: Ga is 1: 1, and so on.), InGaO (93: 7), InGaO (47:53), In 2 O 3 , Ga 2 O 3 , InSnZnO, InAlO, GaZnO, ZnSnO, and the like can be given. For example, InGaO (47:53) can obtain a high band gap and a low resistance characteristic.
- the metal oxide of the metal oxide semiconductor layer includes, for example, indium oxide, indium oxide doped with Ga, indium oxide doped with Al, indium oxide doped with Ga and Al, and indium oxide doped with Zn. Or indium oxide doped with Sn.
- the third element is at least one metal element selected from Sn, Ga, Hf, Zr, Ti, Al, Mg, Ge, Sm, Nd, and La.
- a metal oxide etc. are mentioned.
- the metal oxide of the metal oxide semiconductor layer may be, for example, an Sn—In—Zn oxide, In—Zn—Ga—Mg oxide, In oxide, In—Sn oxide, In— Ga oxide, In—Zn oxide, Zn—Ga oxide, Sn—In—Zn oxide, In—Sn—Zn—Al oxide, In—Sn—Zn—Mg oxide, In—Ga—Zn— Al oxide, Ga oxide, etc. are mentioned.
- the composition ratio of the constituent metal elements may or may not be 1.
- Zn and Sn can easily form an amorphous phase by containing In.
- the content of In is preferably 20 atomic% or more in all metal elements.
- the content of In is preferably 80 atomic% or more in all metal elements.
- the content of In in all metal elements is preferably 15 atomic% or more.
- a tetracoordinate structure and a hexacoordinate structure are often mixed, so that an amorphous structure can be maintained even with a Ga 2 O 3 composition or an annealing temperature of about 500 ° C.
- the thickness of the metal oxide semiconductor layer is not limited, but is usually 5 to 8000 nm, preferably 50 to 1000 nm, more preferably 100 to 500 nm. In the case of two or more metal oxide semiconductor layers, the film thickness of each layer may be in the above range, or the total film thickness of all the two or more layers may be in the above range.
- the specific resistance of the metal oxide semiconductor layer is preferably 1 ⁇ 10 ⁇ 2 ⁇ ⁇ cm or more, and more preferably 1 ⁇ 10 0 to 1 ⁇ 10 8 ⁇ ⁇ cm. As a result, a device having a depletion region can be designed.
- the carrier concentration of the metal oxide semiconductor layer is preferably 1 ⁇ 10 18 cm ⁇ 3 or less. If it is 1 ⁇ 10 18 cm ⁇ 3 or less, the contact with the noble metal oxide layer becomes a one-sided step junction, and the characteristics of the Schottky diode such as high-speed response tend to be manifested.
- the mobility of the metal oxide semiconductor layer is preferably 0.1 cm 2 / Vs or higher. If it is the said range, a low resistance diode can be designed.
- the carrier concentration, mobility, and specific resistance of the metal oxide semiconductor layer can be measured using, for example, a Hall effect measuring device.
- the band gap of the metal oxide semiconductor layer is preferably 1 eV or more. When it is 1 eV or more, it is possible to provide a Schottky interface that has better dielectric breakdown characteristics than silicon. More preferably, it is 2 eV or more, More preferably, it is 3 eV or more. Thereby, a Schottky interface that is not affected by visible light can be formed.
- the band gap can be measured using, for example, a UV-VIS apparatus.
- the thickness of the noble metal oxide layer is more than 10 nm, preferably 15 nm or more, and more preferably 30 nm or more. Although there is no restriction
- the average crystal grain size of the noble metal oxide in the noble metal oxide layer is preferably not more than the film thickness of the noble metal oxide layer. Thereby, the polycrystalline grain boundary is divided, the conduction through the grain boundary can be suppressed, the in-plane variation can be reduced, and a uniform Schottky barrier is easily developed.
- the average crystal grain size is 10 crystal grains at the same depth in a cross-sectional TEM image from which an image in the film thickness direction obtained at a magnification of 500,000 times with a transmission electron microscope (TEM) is obtained.
- a crystal grain is defined by using interference fringes and regarding a portion where the interference fringes are parallel as a single crystal.
- the maximum ferret diameter in each single crystal was defined as the crystal grain size.
- the film thickness of the noble metal oxide layer can be measured, for example, by a cross-sectional TEM. In that case, it can confirm that the average crystal grain diameter of a noble metal oxide layer is below the film thickness of a noble metal oxide layer.
- the film thickness of each layer of the structure of the present invention can be measured by the same method as described above.
- the noble metal oxide layer preferably includes a polycrystalline structure. Thereby, the structure can be annealed at a high temperature.
- the noble metal oxide of the noble metal oxide layer from the viewpoint of forming a good Schottky interface with the metal oxide semiconductor layer in view of the relationship between conductivity and work function, palladium oxide, ruthenium oxide, platinum oxide, iridium oxide, One or more selected from the group consisting of silver oxide, rhenium oxide, osmium oxide, rhodium oxide, nickel oxide and gold oxide can be mentioned. From the viewpoint of forming a high Schottky barrier and forming a stable structure, palladium oxide, ruthenium oxide, platinum oxide, and iridium oxide are preferable. Among these, palladium oxide is preferable because it has a wide window during sputtering film formation and has an advantage from an industrial viewpoint.
- oxides of Mo, W, Cr, Te, Mn, Fe, and Co may be used as the noble metal oxide of the noble metal oxide layer.
- Noble metal oxide of the noble metal oxide layer the PdO structure PdO, PtO 2 of RuO 2, ⁇ -PtO 2 Structure of rutile structure, Ag 2 O of IrO 2, Cu 2 O structure of rutile structure, the skutterudite structure
- One or more selected from the group consisting of ReO 3 , rutile OsO 2 , corundum Rh 2 O 3 , NiO NiO, and Au 2 O 3 Au 2 O 3 is preferred. Thereby, it becomes easy to function as a good noble metal oxide layer because of its excellent conductivity, a large work function, and a stable structure.
- a noble metal oxide may be used individually by 1 type, and may combine 2 or more types.
- the crystal structure of the noble metal oxide layer can be measured using, for example, XRD.
- the orientation may be observed from a diffraction image of a cross-sectional TEM.
- the X-ray diffraction pattern of the thin film matches the assumed crystal structure X-ray diffraction pattern. More specifically, it can be confirmed from the coincidence with the crystal structure X-ray diffraction pattern obtained from JCPDS (Joint Committe Powder Diffraction Standard) card or ICSD (The Inorganic Crystal Structure Database).
- JCPDS Joint Committe Powder Diffraction Standard
- ICSD The Inorganic Crystal Structure Database
- a suitable crystal structure of palladium oxide is PdO having a PdO structure.
- the PdO structure PdO can be confirmed by observing the peak of the PdO structure compound as a result of X-ray diffraction measurement of the thin film, for example.
- PdO of the PdO structure shows, for example by X-ray diffraction, an ICSD (26598) or JCPDS (85-0624) peak pattern in the database, or a similar pattern (the peak position of 2 ⁇ / ⁇ is shifted).
- Palladium oxide is generally insoluble in many acids and slightly soluble in aqua regia and 48% hydrobromic acid. Palladium generally dissolves well in aqua regia, potassium iodide solution containing iodine, and sodium cyanide solution containing oxidizing agent. With palladium and palladium oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention. When patterning the palladium oxide layer by etching, it is preferable to use aqua regia heated to about 60 ° C. Selective etching can be used by utilizing the etching rate difference between palladium and palladium oxide with respect to aqua regia.
- a suitable crystal structure of ruthenium oxide is RuO 2 having a rutile structure.
- the rutile structure of RuO 2 can be confirmed by observing the peak of the rutile structure of RuO 2 compound as a result of X-ray diffraction measurement of the thin film.
- Rutile RuO 2 shows a database ICSD (15071) or similar (shifted) pattern, for example by X-ray diffraction.
- Ruthenium oxide is generally insoluble in many acids and is soluble in molten potassium hydroxide. Ruthenium is generally soluble in alkali hypochlorite solution and gradually dissolves in hydrochloric acid and aqua regia containing air. In ruthenium and ruthenium oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention. When patterning the ruthenium oxide layer by etching, it is preferable to use aqua regia heated to about 60 ° C. containing a large amount of air. Selective etching can be used by utilizing the etching rate difference between ruthenium and ruthenium oxide with respect to aqua regia. Ruthenium oxide can be patterned by dry etching.
- reactive etching can be performed with oxygen gas, carbon fluoride gas, fluorine gas, chlorine gas, bromine gas, iodine gas, ozone gas, hydrogen halide gas, and halogenated carbon gas.
- oxygen gas oxygen gas
- carbon fluoride gas fluorine gas
- chlorine gas bromine gas
- iodine gas ozone gas
- hydrogen halide gas and halogenated carbon gas.
- the preferred crystal structure of platinum oxide is PtO 2 with an ⁇ -PtO 2 structure. It is ⁇ -PtO 2 PtO 2 structures, for example, a thin film X-ray diffraction measurement results can be confirmed by the peak of PtO 2 compounds of alpha-PtO 2 structure is observed.
- PtO 2 of alpha-PtO 2 structure for example, X-ray diffraction shows the database ICSD (one hundred and sixty-four thousand two hundred eighty-nine), or similar to (shifted) pattern.
- Platinum oxide is generally insoluble in hydrochloric acid, sulfuric acid, nitric acid, and aqua regia, and soluble when heated with sulfurous acid. Platinum is generally soluble in aqua regia.
- the difference in etching rate with various solutions can be used when patterning the structure of the present invention. When patterning the platinum oxide layer by etching, heating with sulfurous acid is preferable. Selective etching can be used by utilizing the etching rate difference between platinum and platinum oxide for aqua regia.
- Suitable crystalline structure of iridium oxide is IrO 2 of rutile structure.
- the fact that it is IrO 2 having a rutile structure can be confirmed, for example, by observing a peak of an IrO 2 compound having a rutile structure as a result of X-ray diffraction measurement of the thin film.
- Rutile IrO 2 shows the database ICSD (81028), or similar (shifted) pattern, for example by X-ray diffraction.
- Iridium oxide is generally insoluble in many acids and bases. Iridium is generally slightly soluble in aqua regia. With iridium and iridium oxide, when patterning the structure of the present invention, an etching rate difference with various solutions can be used. Since the iridium oxide layer is difficult to etch, it is preferable to use a lift-off method when patterning. Selective etching can be used by utilizing the etching rate difference between iridium and iridium oxide with respect to aqua regia.
- the preferred crystal structure of silver oxide is Ag 2 O with a Cu 2 O structure. It is Ag 2 O of Cu 2 O structure, for example a thin film results of measurement X-ray diffraction, can be confirmed by a peak of Ag 2 O compound of Cu 2 O structure is observed. Ag 2 O of Cu 2 O structure, for example, by X-ray diffraction shows ICSD database (605,623), or similar to (shifted) pattern.
- Silver oxide is generally soluble in aqueous ammonia and nitric acid. Silver is generally soluble in dilute nitric acid and hot concentrated sulfuric acid. With silver and silver oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention. When patterning the silver oxide layer by etching, it is preferable to use a solution containing nitric acid. Selective etching can be used by using the etching rate difference between silver and silver oxide with respect to nitric acid.
- the preferred crystal structure of rhenium oxide is skutterudite structure ReO 3 .
- the fact that it is ReO 3 having a skutterudite structure can be confirmed, for example, by observing the peak of the ReO 3 compound having a skutterudite structure as a result of X-ray diffraction measurement of the thin film.
- the skutterudite structure of ReO 3 shows, for example by X-ray diffraction, the database ICSD (201875) or a similar (shifted) pattern.
- Rhenium oxide is generally soluble in water. Rhenium is generally soluble in nitric acid and hot concentrated sulfuric acid. Soluble in hydrogen peroxide and bromine water. For rhenium and rhenium oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention.
- the preferred crystal structure of osmium oxide is rutile OsO 2 .
- the fact that it is OsO 2 having a rutile structure can be confirmed, for example, by observing the peak of the OsO 2 compound having a rutile structure as a result of X-ray diffraction measurement of the thin film.
- the rutile OsO 2 shows a database ICSD (15070) or similar (shifted) pattern, for example by X-ray diffraction.
- Osmium oxide is generally soluble in ethanol and gradually dissolves in water. Osmium generally reacts with halogens at high temperatures, but is not very soluble in aqua regia. In osmium and osmium oxide, when patterning the structure of the present invention, an etching rate difference with various solutions can be used.
- the preferred crystal structure of rhodium oxide is corundum Rh 2 O 3 .
- the corundum-structured Rh 2 O 3 can be confirmed, for example, by observing the peak of the corundum-structured Rh 2 O 3 compound as a result of X-ray diffraction measurement of the thin film.
- Corundum-structured Rh 2 O 3 shows the database ICSD (647369) or a similar (shifted) pattern, for example by X-ray diffraction.
- Rhodium oxide is generally soluble in hydrochloric acid and perchloric acid. Rhodium is generally soluble in hot sulfuric acid and heated aqua regia. For rhodium and rhodium oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention.
- NiO having a NiO structure A suitable crystal structure of nickel oxide is NiO having a NiO structure.
- NiO having a NiO structure can be confirmed by observing the peak of a NiO compound having a NiO structure as a result of X-ray diffraction measurement of the thin film, for example.
- NiO with a NiO structure shows, for example, X-ray diffraction, database ICSD (9866), or similar (shifted) patterns.
- Nickel oxide is generally hardly soluble in hydrochloric acid, sulfuric acid and nitric acid, and hardly soluble in water and sodium hydroxide solution. Nickel is generally soluble in hydrochloric acid and dilute nitric acid, but the reaction is slow. It dissolves in dilute nitric acid and forms a passive state in concentrated nitric acid. In nickel and nickel oxide, when patterning the structure of the present invention, an etching rate difference with various solutions can be used.
- Suitable crystal structure of gold oxide is Au 2 O 3 of Au 2 O 3 structure.
- Au 2 O 3 that structure is au 2 O 3 of, for example, a thin film results of measurement X-ray diffraction, can be confirmed by the peak of the Au 2 O 3 compound of Au 2 O 3 structure is observed.
- Au 2 O of au 2 O 3 structure 3, for example, by X-ray diffraction shows the database ICSD (8014), or similar to (shifted) pattern.
- the noble metal oxide layer may contain an element having a strong binding force with oxygen.
- the noble metal element in the noble metal oxide layer may be contained in a ratio of preferably 70% or less, more preferably 50% or less, and even more preferably 30% or less.
- the noble metal oxide layer preferably has a polycrystalline structure, but may take a form in which the amorphous structure is included in the amorphous structure.
- the element having a strong binding force with oxygen include elements having a large standard free energy of formation of oxides such as Ti, Si, Zr, Y, Al, Mg, Zr, and Hf.
- Ru—Si—O is preferable because it can achieve both a high work function and a low specific resistance.
- Gold oxide is generally soluble in concentrated basic solutions. Gold generally dissolves well in aqua regia, potassium iodide solution containing iodine, and sodium cyanide solution containing oxidizing agent. For gold and gold oxide, the difference in etching rate with various solutions can be used when patterning the structure of the present invention.
- the database used for X-ray diffraction is generally a powder pattern or the like and is randomly oriented. If the noble metal oxide layer is a randomly oriented polycrystalline thin film, generally the main peak obtained from XRD measurement is observed as a spectrum having a peak median at a position of ⁇ 1 ° with respect to the 2 ⁇ position in the database. . Further, when the intensity of the spectrum having the second and third peak in the database is compared with the peak intensity in the plane orientation where the intensity of the database is the maximum, the generally measured spectrum is 2 ⁇ in the database. It falls within ⁇ 1 ° with respect to the position, and the peak intensity ratio is 0.3 to 3 times the database ratio.
- the noble metal oxide layer has a specific intensity. Often oriented in a plane.
- the noble metal oxide layer is preferably polycrystalline from the viewpoints of stability and stress relaxation, and random orientation is preferred from the viewpoint of variations in the Schottky barrier.
- the ratio of the specific plane orientation component is large, a step is likely to be formed on the surface, and the weak orientation component is not stable in the plane, so that the substantial Schottky barrier may be lowered.
- the carrier concentration of the noble metal oxide layer is preferably 1 ⁇ 10 18 cm ⁇ 3 or more. If it is 1 ⁇ 10 18 cm ⁇ 3 or more, the contact with the metal oxide semiconductor layer is a one-sided step junction, and the characteristics of the Schottky diode such as high-speed response tend to be exhibited.
- the carrier concentration can be obtained, for example, by hole measurement.
- the interface roughness of the noble metal oxide layer is preferably 5 nm or less, and more preferably 2 nm or less. As a result, fluctuations at the interface of the Schottky barrier can be reduced, and a substantially high Schottky barrier can be obtained.
- the interface roughness of the noble metal oxide layer can be measured using, for example, a cross-sectional TEM. Specifically, three cross-sectional TEM images are taken, the unevenness at the interface between the noble metal oxide layer and the metal oxide semiconductor layer is traced, and the traced line is used for the root mean square roughness (RMS) standardized by JISB0601-2001. ), The roughness of the interface of the noble metal oxide layer can be obtained.
- the cross-sectional TEM has a maximum value of 5 or more when a trace line at the interface between the noble metal oxide layer and the metal oxide semiconductor is drawn, and a magnification at which the difference between the adjacent maximum value and the minimum value can be clearly determined. It is preferable to obtain.
- the specific resistance of the noble metal oxide layer is preferably 1 ⁇ 10 ⁇ 2 ⁇ ⁇ cm or less, more preferably 1 ⁇ 10 ⁇ 3 to 1 ⁇ 10 ⁇ 5 ⁇ ⁇ cm. Thereby, device design can be performed regardless of the resistance of the noble metal oxide layer.
- specific resistance has the same meaning as resistivity or electrical resistivity, and does not cause a difference in physical property value depending on the name.
- the specific resistance of the noble metal oxide layer can be measured using, for example, the van der Pauw method. You may measure by direct electrical measurement.
- the work function of the noble metal oxide in the noble metal oxide layer is preferably 4.8 eV or more, more preferably 5.0 to 6.0 eV. Thereby, a work function difference with a metal oxide semiconductor becomes large, and a structure having a high Schottky barrier height can be formed.
- the work function of the noble metal oxide of the noble metal oxide layer can be measured using, for example, X-ray photoelectron spectroscopy (XPS), ultraviolet photoelectron spectroscopy (UPS), atmospheric photoelectron spectroscopy, Kelvin probe microscope (KPM). it can.
- the structure of the present invention preferably has a depletion region, and more preferably has a depletion region in a portion of the metal oxide semiconductor layer adjacent to the noble metal oxide layer.
- the thickness of the depletion region varies depending on the sign of the applied voltage and the magnitude, it is preferable that the maximum thickness of the depletion region is the same as the thickness of the metal oxide semiconductor layer. 50 to 100% of the thickness of the metal oxide semiconductor layer is preferable, and 70 to 100% is more preferable.
- the thickness of the depletion region may exceed the thickness of the metal oxide semiconductor layer, and the maximum thickness of the depletion region may be 110% of the thickness of the metal oxide semiconductor layer.
- the thickness of the depletion region can be obtained by, for example, CV (capacitance-voltage) measurement.
- CV capactance-voltage
- the thickness of the depletion region may be in the above range in the metal oxide semiconductor layer adjacent to the noble metal oxide layer, or the total film of all the two or more layers. The above range may be used for the thickness.
- the carbon concentration at the Schottky interface between the metal oxide semiconductor layer and the noble metal oxide layer is preferably 2 ⁇ 10 19 cm ⁇ 3 or less, and more preferably 1 ⁇ 10 12 to 2 ⁇ 10 19 cm ⁇ 3 .
- a good interface between the metal oxide semiconductor layer and the noble metal oxide layer can be formed, and stability can be increased, variation can be reduced, and a substantial Schottky barrier can be increased.
- the carbon concentration at the Schottky interface can be measured, for example, using a secondary ion mass spectrometry (SIMS) depth profile.
- SIMS secondary ion mass spectrometry
- the height of the Schottky barrier between the noble metal oxide layer and the metal oxide semiconductor layer is preferably 0.7 eV or more, and more preferably 1.0 to 2.0 eV. Thereby, a rectification characteristic can be improved.
- the diode ideality factor when a forward bias is applied is preferably 1.5 or less, more preferably 1.0 to 1.3. This makes it easy to design a device with low power consumption.
- the ideality factor of the diode when the Schottky barrier height and forward bias are applied follows the thermal electron emission model, and resistance components other than the Schottky barrier, such as semiconductor resistance, electrode resistance, and contact resistance, have no bias dependence For example, it can obtain
- Equation (1) is established between the measured current value I and the applied voltage V.
- Draw a graph of current and voltage lnI-V plots from equation (1) and draw a tangent line with a good linearity of about 50 mV to 1000 mV to obtain I 0 from V 0 and the tangent intercept. be able to. More specifically, as shown in the literature (Appl. Phys. Lett., 49, 85, 1986), it is possible to obtain I 0 by eliminating the influence of the R component using a Cheung plot.
- I 0 represents a saturation current and corresponds to a current value when 0 V is applied.
- the relationship of the formula (2) is established between the saturation current value and the Schottky barrier height.
- ⁇ bo Schottky barrier height [eV]
- the Richardson coefficient depends on the effective mass value of the semiconductor, and when the effective mass is 1, it is 120 Acm ⁇ 2 K ⁇ 2 .
- the metal oxide of the metal oxide semiconductor layer is InGaZnO (1: 1: 1), it is reported that the effective mass is 0.3, so A ** can be regarded as 36 Acm ⁇ 2 K ⁇ 2. it can.
- the Schottky barrier height can be obtained from I ( 0 ) obtained from room temperature measurement from the equation (3).
- the diode ideality coefficient can be obtained from the slope of a portion having a good linearity of about 50 mV to 1000 mV in the plot of lnI-V, as shown by (4) obtained by differentially modifying the equation (1).
- the Schottky barrier height and the diode ideality coefficient when the forward bias is applied can be obtained, for example, as follows.
- Each parameter can be obtained by simulation of an SCLC model mediated by an exponential trap, assuming the presence of an initial free carrier concentration, with reference to the literature (J. Appl. Phys., 104, 123706, 2008).
- Equation (6) is an equation representing the current density in consideration of the constant carrier current and the initial carrier concentration at the distance x from the ohmic electrode and the free carriers injected from the ohmic electrode side.
- e is an elementary charge and u is a mobility.
- n 0 and n i, c (x) are the initial free carrier concentration and the concentration of electrons involved in conduction among the injected electrons at the distance x.
- Equation (7) is a Poisson equation, which means that the change in the electric field E continuously changes depending on the injected free carriers and trapped carriers at the position x according to the total amount of injected electrons. ing.
- Equation (10) represents the concentration of trapped electrons among the injected electrons at the position x, assuming an exponential trap.
- N t is the trap level concentration existing from the conductivity edge to the Fermi level, and N c is the effective density of states.
- T t is the characteristic temperature, and n (x) is the free carrier concentration at position x.
- Equations (6) to (10) n 0 , T t , and N t are parameters, and dielectric constant ⁇ , mobility u, and effective state density N c are values obtained from separate measurements. Temperature and film thickness Is known. As a result, it is possible to obtain the IV semi characteristic when there is no Schottky barrier, that is, the variable resistance value R (V semi ) caused by the semiconductor.
- V V shotkey + V semi
- the V-IR term in the equation (1) is assumed to be V-V semi and the V semi relation to I obtained from the simulation is used.
- V semi is introduced into the equation (1), and ⁇ bo and n are further fitting parameters, and numerical simulation is performed to obtain n 0 , T t and N t. , ⁇ bo , n can be obtained simultaneously. From this, ⁇ bo , n can be obtained.
- the structure of the present invention has one or more compositions on the side of the noble metal oxide layer opposite to the metal oxide semiconductor layer in order to reduce the contact resistance with the substrate or the current extraction electrode and improve the adhesion. Layers of different metals and metal oxides can be included.
- the structure of the present invention may further include a noble metal layer adjacent to the noble metal oxide layer and on the side opposite to the metal oxide semiconductor layer. Thereby, reduction
- Examples of the metal element of the noble metal layer include Pd, Mo, Pt, Ir, Ru, Au, Ag, Ni, W, Cr, Re, Te, Tc, Mn, Os, Fe, Rh, Co, and two or more of these.
- An alloy is mentioned. 1 type may be used independently and 2 or more types may be combined.
- the same metal element as the metal element of the noble metal oxide layer as the metal element of the noble metal layer.
- the combination of the noble metal layer and the noble metal oxide layer include Pd / PdO, Pt / PtO, Ir / IrO, and Ru / RuO.
- the film thickness of the noble metal layer is usually 1 nm to 1 ⁇ m, preferably 10 nm to 500 nm, more preferably 20 nm to 200 nm, and particularly preferably 25 nm to 100 nm. In the case of the above range, the reduction due to the influence from the side opposite to the metal oxide semiconductor layer can be suppressed adjacent to the noble metal oxide layer, and the flatness of the noble metal oxide layer can be improved.
- the structure of the present invention may further include a low-resistance base metal layer adjacent to the noble metal layer and on the opposite side of the noble metal oxide layer.
- a low-resistance base metal layer adjacent to the noble metal layer and on the opposite side of the noble metal oxide layer.
- the metal element of the low resistance base metal layer examples include Ti, Mo, Ag, In, Al, W, Co and Ni, two or more alloys thereof, or two or more silicides thereof.
- Ti, Mo, Ag, In, or Al that forms a low resistance silicide when combined with a Si-containing substrate, and more preferably a low Schottky contact when combined with a noble metal oxide.
- the thickness of the low resistance base metal layer is usually 1 nm to 1 ⁇ m, preferably 2 nm to 100 nm, and more preferably 5 nm to 50 nm. In the above range, there is a tendency that the adhesiveness is sufficient and the increase in resistance is small.
- the structure of the present invention may further have an ohmic electrode layer. It is preferable that the ohmic electrode layer and the noble metal oxide layer do not contact each other. Thereby, the rectification characteristic control and the thickness of the depletion region can be controlled.
- the ohmic electrode layer is preferably one layer or two or more layers. Three or more layers, or four or more layers may be used. Usually, it is 5 layers or less.
- the material of the ohmic electrode layer is not particularly limited as long as it can form a good ohmic connection with the metal oxide semiconductor layer, but is preferably selected from the group consisting of Ti, Mo, Ag, In, Al, W, Co, and Ni. One or more selected from the group consisting of Mo, Ti, Au, Ag, In and Al, more preferably a metal element (including an alloy) or a compound (oxide or the like) of one or more of these metal elements. Metal elements (including alloys) or compounds thereof. Further, the ohmic electrode layer can be composed of two or more layers.
- a Mo electrode layer is used on the side in contact with the metal oxide semiconductor layer, and a metal layer such as Au or Al, which is a low-resistance metal, is thickly stacked, and this layer can be used as a base for wire bonding.
- a metal layer such as Au or Al, which is a low-resistance metal, is thickly stacked, and this layer can be used as a base for wire bonding.
- the film thickness of the ohmic electrode layer is usually 1 nm to 5 ⁇ m.
- the thickness is preferably 5 to 1000 nm, more preferably 10 to 500 nm.
- the film thickness of each layer may be in the above range, or the total film thickness of all the two or more layers may be in the above range.
- the structure of the present invention may further include a substrate (support substrate) on the side of the noble metal oxide layer opposite to the metal oxide semiconductor layer.
- the substrate is not particularly limited and a known material can be used, and examples thereof include a conductive substrate, a semiconductor substrate, and an insulating substrate.
- An insulating substrate may be a substrate capable of piezoelectric characteristics and optical application.
- a substrate having a circuit or a multilayer structure on the substrate may be used.
- an electric device having an electronic circuit, a vehicle, or a power engine may be used as the substrate.
- the conductive substrate a conventionally known substrate having excellent surface smoothness, such as a silicon single crystal substrate, a silicon polycrystalline substrate, or a silicon crystal substrate, in which a semiconductor substrate is doped at a high concentration can be used. Further, a SiC substrate, a GaN substrate, a GaAs substrate, or the like may be used. Moreover, you may use metal substrates, such as Al, Cu, Ni, SUS (stainless steel), Au, Ag, W, and Ti.
- metal substrates such as Al, Cu, Ni, SUS (stainless steel), Au, Ag, W, and Ti.
- a substrate having conductivity by forming a conductive layer on the surface of the insulating substrate may be used.
- a silicon substrate is preferable as the conductive substrate.
- the silicon substrate may be n-type, i-type, or p-type.
- n-type or p-type having a small electric resistance is preferable.
- Conventionally known B, P, Sb and the like can be used as the dopant.
- As or red phosphorus may be used as a dopant.
- the semiconductor substrate may be placed in contact with the noble metal layer or the low resistance base metal layer.
- the material of the semiconductor substrate is not particularly limited as long as the surface smoothness is maintained.
- a semiconductor substrate a Si substrate, a GaN substrate, a SiC substrate, a GaP substrate, a GaAs substrate, a ZnO substrate, a Ga 2 O 3 substrate, a GaSb substrate, an InP substrate, and an InAs whose carrier concentration is adjusted to 1 ⁇ 10 18 cm ⁇ 3 or less.
- a substrate, an InSb substrate, a ZnS substrate, a ZnTe substrate, a diamond substrate, or the like can be used.
- the semiconductor substrate may be single crystal or polycrystalline.
- an amorphous substrate or a substrate partially containing amorphous may be used.
- a substrate in which a semiconductor film is formed using a method such as chemical vapor deposition (CVD) over a conductive substrate, a semiconductor substrate, or an insulating substrate may be used.
- the insulating substrate is not particularly limited as long as it is an insulating substrate, and a generally used substrate can be arbitrarily selected.
- a generally used substrate can be arbitrarily selected.
- a plastic substrate for example, a polyimide substrate
- a dielectric substrate may be used as the insulating substrate.
- the dielectric substrate examples include a lithium niobate substrate, a lithium tantalate substrate, a zinc oxide substrate, a quartz substrate, and a sapphire substrate. Further, a substrate in which an insulating film or a dielectric film is provided on the surface of a metal substrate such as a stainless alloy may be used. An insulating film may be formed over the substrate as a base film. As the base film, a single layer or a stacked layer such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be formed by a CVD method, a sputtering method, or the like.
- a base material having an arbitrary structure, layer structure, circuit, wiring, electrode, or the like made of a plurality of materials on the above-described conductive substrate, semiconductor substrate, or insulating substrate may be used.
- the material having an arbitrary structure include composite materials of various metals and insulators such as a metal that forms a back end of line on a large scale integrated circuit (LSI) and an interlayer insulating film.
- LSI large scale integrated circuit
- the layer structure is not particularly limited, and is an electrode layer, an insulating layer, a semiconductor layer, a dielectric layer, a protective film layer, a stress buffer layer, a light shielding layer, an electron / hole injection layer, an electron / hole transport layer, a light emitting layer.
- Known layers such as an electron / hole blocking layer, a crystal growth layer, an adhesion improving layer, a memory layer, a liquid crystal layer, a capacitor layer, and a power storage layer can be used.
- an insulating layer generally Al, Si, Sc, Ti, V, Cr, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Examples thereof include an oxide insulating film and a nitride film containing one or more metals selected from the group consisting of Sn, Sb, Te, Hf, Ta, W, Re, Os, Ir, Pt, and Au.
- oxide semiconductor layers, organic semiconductor layers such as pentacene, and the like are widely used regardless of the crystalline state of single crystal, polycrystal, or amorphous.
- a lithium niobate layer As the dielectric layer, a lithium niobate layer, a lithium tantalate layer, a zinc oxide layer, a quartz substrate layer, a sapphire layer, a BaTiO 3 layer, a Pb (Zr, Ti) O 3 (PZT) layer, (Pb, La) ( Zr, Ti) O 3 (PLZT) layer, Pb (Zr, Ti, Nb) O 3 (PZTN) layer, Pb (Ni, Nb) O 3 —PbTiO 3 (PNN-PT) layer, Pb (Ni, Nb) O 3 —PbZnO 3 (PNN—PZ) layer, Pb (Mg, Nb) O 3 —PbTiO 3 (PMN—PT) layer, SrBi 2 Ta 2 O 9 (SBT) layer, (K, Na) TaO 3 layer, (K, Na) NbO 3 layer, BiFeO 3 layer, Bi (Nd, La
- a film having excellent insulating properties and low permeability to water or the like can be used regardless of an inorganic material or an organic material.
- the stress buffer layer include an AlGaN layer.
- the light shielding layer include a black matrix layer containing a metal, a metal-organic material, and a color filter layer.
- Examples of the electron / hole injection layer include an oxide semiconductor layer and an organic semiconductor layer.
- Examples of the electron / hole transport layer include an oxide semiconductor layer and an organic semiconductor layer.
- Examples of the light emitting layer include an inorganic semiconductor layer and an organic semiconductor layer.
- Examples of the electron / hole blocking layer include an oxide semiconductor layer.
- the base material examples include a power generation device, a light emitting device, a sensor, a power conversion device, an arithmetic device, a protection device, an optoelectronic device, a display, a memory, a semiconductor device having a back-end-of-line, and a power storage device.
- the layer having a layer structure may be a single layer or two or more layers.
- the breakdown voltage of the structure of the present invention when a reverse voltage is applied is preferably 0.5 MV / cm or more, and more preferably 0.6 to 5.0 MV / cm. This makes it easy to design a device with a high breakdown voltage.
- the variation in breakdown voltage is preferably 0.1 MV / cm or less.
- the breakdown voltage can be calculated by measuring a breakdown voltage when a reverse voltage is applied and dividing the breakdown voltage by the film thickness of the metal oxide semiconductor layer.
- the variation in breakdown voltage is, for example, a standard deviation value of 50 or more breakdown voltages measured on the same substrate in the same process.
- the current density is preferably 1 ⁇ 10 ⁇ 6 A / cm 2 or less when a reverse bias of 0.2 MV / cm is applied, and is 1 ⁇ 10 ⁇ 7 to 1 ⁇ 10 ⁇ 13 A / cm. 2 is more preferable. This facilitates designing a device with low leakage and low noise.
- the forward bias is 5 V or less, and the current density preferably reaches 1000 A / cm 2 , more preferably 5000 to 100,000 A / cm 2 . This facilitates designing a low resistance device.
- the film formation method of each layer is not particularly limited, but the CVD method such as thermal CVD method, catalytic chemistry (CAT) -CVD method, photo CVD method, mist CVD method, organometallic (MO) -CVD method, plasma CVD method, MBE , Atomic layer controlled deposition methods such as atomic layer deposition equipment (ALD), physical vapor deposition (PVD) methods such as ion plating, ion beam sputtering, magnetron sputtering, DC sputtering, pulse sputtering, doctor blade method, injection Method, extrusion method, hot press method, sol-gel method, aerosol deposition method, etc., using conventional ceramic processes, coating method, spin coating method, printing method, spraying method, electrodeposition method, plating method, micelle electrolysis A wet method such as a method can be used.
- CVD method such as thermal CVD method, catalytic chemistry (CAT) -CVD method, photo CVD method, mist CVD method, organ
- the method for forming the noble metal oxide layer is not particularly limited, a method of performing reactive sputtering of a desired metal target in an oxygen-containing atmosphere can be suitably used.
- the method for forming the metal oxide semiconductor layer is not particularly limited, but sputtering is preferable.
- the gas for forming (introducing) the metal oxide semiconductor layer it is preferable to select at least one kind of rare gas, oxygen, hydrogen and water.
- the rare gas include Ar and He.
- the metal oxide semiconductor layer is preferably formed in an atmosphere into which hydrogen or water is introduced. Thereby, a metal oxide semiconductor layer can be made into random orientation.
- As an atmosphere for forming the noble metal oxide layer it is preferable that 50% or more (more preferably 70 to 100%) of the introduced gas flow rate is oxygen. Thereby, a stable noble metal oxide layer can be formed, and the stability of the Schottky barrier can be improved.
- the distance between the sputtering target and the substrate (TS interval) is preferably 10 mm to 200 mm. When it is less than 10 mm, there is a possibility that electric discharge cannot be performed. When it exceeds 200 mm, the film quality of the semiconductor becomes sparse, and there is a possibility that the film has a large characteristic temperature.
- Annealing is preferably performed after the noble metal oxide layer and the metal oxide semiconductor layer are formed.
- the annealing temperature is preferably 220 to 500 ° C., more preferably 250 to 450 ° C. Thereby, the reliability and stability resulting from the metal oxide semiconductor layer can be improved.
- the noble metal oxide layer and the metal oxide semiconductor layer are continuously formed by sputtering, or a vacuum or an inert atmosphere between the noble metal oxide layer and the metal oxide semiconductor layer is formed. It is preferable that As a result, the structure can be manufactured while maintaining the cleanliness of the interface.
- the inert atmosphere examples include an atmosphere of Ar, N 2 or the like.
- the vacuum is preferably 1/100 atm or less than atmospheric pressure, and more preferably about the back pressure of the sputtering chamber.
- Plasma treatment or the like may be included during the process as long as the carbon concentration at the interface between the noble metal oxide layer and the metal oxide semiconductor layer is not increased. Thereby, a stable Schottky interface can be formed.
- FIG. 1 A cross-sectional view schematically showing one embodiment of the structure of the present invention is shown in FIG.
- a low-resistance base metal layer 20, a noble metal layer 30, a noble metal oxide layer 40, a metal oxide semiconductor layer 50, a first ohmic electrode layer 60, and a second ohmic electrode are formed on a substrate 10.
- the electrode layer 61 is laminated in this order.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 may be long in consideration of drawing in the lateral direction.
- the low-resistance base metal layer 20 and the noble metal layer 30 may be long in consideration of drawing in the lateral direction.
- the substrate 10 When the substrate 10 is a conductive substrate, it may have an extraction electrode layer on the back surface.
- the extraction electrode layer may be a single layer or two or more layers.
- the take-out electrode on the back surface of the substrate 10 is preferably a metal from the viewpoint of conductivity.
- an interlayer insulating film that electrically insulates the respective layers may be provided. Depending on the method of forming the interlayer insulating film, each layer may have a step in the lateral direction.
- a part of each layer may be short-circuited and the remaining part may be insulated by an interlayer insulating film.
- the region where the first ohmic electrode layer 60 is in contact with the metal oxide semiconductor layer 50 preferably does not reach the end of the metal oxide semiconductor layer 50. Furthermore, when the region where the first ohmic electrode layer 60 is in contact with the metal oxide semiconductor layer 50 does not reach the end of the metal oxide semiconductor layer 50 and is viewed from the direction perpendicular to the stacked surface, The end of the region where the ohmic electrode layer 60 is in contact with the metal oxide semiconductor layer 50 is preferably present inside the end of the region where the noble metal oxide layer 40 is in contact with the metal oxide semiconductor layer 50. With the above arrangement, the leakage current can be further suppressed.
- FIGS. 2 to 9 schematically show other embodiments of the structure of the present invention.
- the ohmic electrode layers 61 are laminated in this order.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 may be long in consideration of drawing in the lateral direction.
- the low-resistance base metal layer 20, the noble metal layer 30, the noble metal oxide layer 40, the first metal oxide semiconductor layer 51, and the second metal oxide semiconductor are formed on the conductive substrate 11.
- the layer 52, the first ohmic electrode layer 60, and the second ohmic electrode layer 61 are laminated in this order.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 may be long in consideration of drawing in the lateral direction.
- the first ohmic electrode layer (bonding layer) 62, the second ohmic electrode layer (contact metal layer) 63, the metal oxide semiconductor layer 50, and the noble metal are formed on the conductive substrate 11.
- the oxide layer 40, the noble metal layer 30, the low resistance base metal layer 20, and the cap metal 70 are laminated in this order.
- the low-resistance base metal layer 20 and the cap metal 70 may be long in consideration of drawing in the lateral direction.
- the first ohmic electrode layer (bonding layer) 62, the second ohmic electrode layer (contact metal layer) 63, the metal oxide semiconductor layer 50, and the noble metal are formed on the conductive substrate 11.
- the oxide layer 40, the noble metal layer 30, the low resistance base metal layer 20, and the cap metal 70 are laminated in this order. Note that a portion between the conductive substrate 11 and the metal oxide semiconductor layer 50 where the first ohmic electrode layer (bonding layer) 62 and the second ohmic electrode layer (contact metal layer) 63 are not provided is the interlayer insulating film 80.
- the region where the second ohmic electrode layer 63 is in contact with the metal oxide semiconductor layer 50 does not reach the end of the metal oxide semiconductor layer 50 and is viewed from the direction perpendicular to the stacked surface.
- the end of the region where the second ohmic electrode layer 63 is in contact with the metal oxide semiconductor layer 50 is present inside the end of the region where the noble metal oxide layer 40 is in contact with the metal oxide semiconductor layer 50.
- the low-resistance base metal layer 20 and the cap metal 70 may be long in consideration of drawing in the lateral direction.
- the ohmic electrode layer 61 is laminated in this order.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 may be long in consideration of drawing in the lateral direction.
- the low-resistance base metal layer 20, the noble metal layer 30, the noble metal oxide layer 40, the first metal oxide semiconductor layer 51, and the second metal oxide semiconductor layer are formed on the glass substrate 12.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 are laminated in this order.
- the first ohmic electrode layer 60 and the second ohmic electrode layer 61 may be long in consideration of drawing in the lateral direction.
- the first ohmic electrode layer (bonding layer) 62, the second ohmic electrode layer (contact metal layer) 63, the metal oxide semiconductor layer 50, and the noble metal oxide are formed on the glass substrate 12.
- the physical layer 40, the noble metal layer 30, the low resistance base metal layer 20, and the cap metal 70 are laminated in this order.
- the low-resistance base metal layer 20 and the cap metal 70 may be long in consideration of drawing in the lateral direction.
- the metal oxide semiconductor layer 50 is stacked on the glass substrate 12, and the noble metal oxide layer 40 and the ohmic electrode layer 64 are spaced on the metal oxide semiconductor layer 50. Has been placed.
- FIGS. 10A, 10C and 10E are cross-sectional views schematically showing other embodiments of the structure of the present invention
- FIGS. 10B, 10D and 10F are other structures of the structure of the present invention. It is the top view which showed typically the embodiment.
- FIG. 10A is a sectional view schematically showing another embodiment of the structure of the present invention
- FIG. 10B is a plan view of FIG. 10A excluding the substrate and polyimide.
- 10A in the structure 101, a low resistance base metal layer 20, a noble metal layer 30, a noble metal oxide layer 40, and a metal oxide semiconductor layer 50 are laminated in this order on a glass substrate 12 to form a polyimide 81.
- FIG. 10B is a plan view excluding the glass substrate 12 and polyimide 81 of FIG. 10A
- FIG. 10A is a cross-sectional view of the broken line part of FIG. 10B.
- FIG. 10C is a cross-sectional view schematically showing another embodiment of the structure of the present invention
- FIG. 10D is a plan view of FIG. 10C excluding the substrate and polyimide.
- the low resistance base metal layer 20, the noble metal layer 30, the noble metal oxide layer 40, and the metal oxide semiconductor layer 50 are laminated in this order on the glass substrate 12, and the polyimide 81 is formed.
- the polyimide 81 is opened, and the first ohmic electrode layer 60 and the second ohmic electrode layer 61 are laminated in this order.
- FIG. 10D is a plan view excluding the glass substrate 12 and the polyimide 81 in FIG. 10C
- FIG. 10D is a cross-sectional view of the broken line part in FIG. 10D.
- FIG. 10E is a cross-sectional view schematically showing another embodiment of the structure of the present invention
- FIG. 10F is a plan view of FIG. 10E excluding the substrate and polyimide.
- the low resistance base metal layer 20, the noble metal layer 30, the noble metal oxide layer 40, and the metal oxide semiconductor layer 50 are laminated in this order on the glass substrate 12, and the polyimide 81 is formed. After that, the polyimide 81 is opened, and the first ohmic electrode layer 60 and the second ohmic electrode layer 61 are laminated in this order.
- FIG. 10F is a plan view excluding the glass substrate 12 and polyimide 81 of FIG. 10E
- FIG. 10E is a cross-sectional view of the broken line portion of FIG. 10F.
- the elements shown in FIGS. 1 to 10 can be used in a multi-stage connection.
- circuit design in which two or more identical elements are prepared on the substrate surface and one noble metal oxide layer is electrically connected in series to the other ohmic electrode so that the applied voltage is distributed to each element.
- a circuit configuration in which one noble metal oxide layer is electrically connected to the other noble metal oxide layer is also possible. It is also possible to use the elements and the circuit configuration as described above connected in parallel in a plurality of stages. By combining the connections of these elements, it is possible to adjust the rising voltage when the voltage is applied, to adjust the withstand voltage, and to separate the waveforms.
- the structure of the present invention includes a power semiconductor element, a (rectifier) diode element, a Schottky barrier diode element, an electrostatic discharge (ESD) protection diode, a transient voltage protection (TVS) protection diode, a light emitting diode, and a metal semiconductor field effect transistor (MESFET). ), Junction field effect transistor (JFET), metal oxide semiconductor field effect transistor (MOSFET), Schottky source / drain MOSFET, avalanche multiplication type photoelectric conversion element, solid-state imaging device, solar cell element, photosensor element, touch It can be used for semiconductor elements such as sensor elements, display elements, resistance change memories, protective elements, power conversion elements, and arithmetic elements.
- semiconductor elements such as sensor elements, display elements, resistance change memories, protective elements, power conversion elements, and arithmetic elements.
- the semiconductor element can be used for a Schottky barrier diode, a junction transistor (JFET), or a field effect transistor.
- JFET junction transistor
- An electronic circuit using this element, a Schottky barrier diode, or a junction transistor can be used in an electric device, an electronic device, a vehicle, a power engine, and the like.
- the power generation device, the light-emitting device, the sensor, the power conversion device, the arithmetic device, the protection device, the optoelectronics, the display, and the memory can be used as a part or a combination thereof.
- the circuit having a multilayer structure on the substrate include a back-end-of-line structure having a multilayer wiring on the Si substrate, a resistance change memory, and a logic IC.
- Example 1 An n-type Si substrate (diameter 4 inches, P-doped) having an electrical resistivity of 1 m ⁇ ⁇ cm was mounted on a sputtering apparatus CS-200 (manufactured by ULVAC, Inc.), and the atmosphere was evacuated. A Ti film having a thickness of 15 nm was formed as a low-resistance base metal layer. The film forming conditions were DC 300 W, 0.5 Pa in an Ar atmosphere, and 100 seconds. Subsequently, 50 nm of Pd was deposited as a noble metal layer. The film forming conditions were DC 300 W, 0.5 Pa in an Ar atmosphere, and 60 seconds. Next, 40 nm of PdO was deposited as a noble metal oxide layer.
- the film forming conditions were DC 300 W, O 2 atmosphere, 0.5 Pa (100% oxygen in the introduced gas flow rate), and 270 seconds.
- a metal oxide semiconductor InGaZnO (1: 1: 1) was formed to a thickness of 200 nm.
- the film forming conditions were 0.5 Pa and 780 seconds in a mixed gas atmosphere of DC 300 W, Ar 99%, and H 2 O 1%. Film formation from the low-resistance base metal layer to the metal oxide semiconductor layer is performed consistently without removing the substrate after mounting the n-type Si substrate and evacuating it using three types of 4-inch targets set in CS-200. Filmed. After the film formation, the substrate was taken out and annealed in an electric furnace at 300 ° C. for 1 hour.
- This substrate was set again on the CS-200 together with an area mask (for forming a 500 ⁇ m diameter film), and then Mo150 nm as a first ohmic electrode layer and Au500 nm as a second ohmic electrode layer were stacked (first ohmic film).
- the electrode layer and the second ohmic electrode layer are collectively referred to as an ohmic electrode layer.
- the film forming conditions were DC 100 W and Ar atmosphere 0.5 Pa. Note that a film of Ti having a thickness of 100 nm was formed on the back surface as an extraction electrode for measurement.
- the film forming conditions were CS-200, DC 300 W, Ar atmosphere, 0.5 Pa, 700 seconds.
- the obtained element has the structure shown in FIG.
- the film thickness of each layer was measured by cross-sectional TEM.
- “200 nm” in FIG. 11 shows a cross-sectional TEM of the device of Example 1.
- “100 nm”, “500 nm”, and “1000 nm” in FIG. 11 are cross-sectional TEMs of Examples 2 to 4 to be described later.
- 11 is an enlarged view of the interface between the ohmic electrode layer and the metal oxide semiconductor layer in Example 1 (when the metal oxide semiconductor layer is 200 nm), and the interface between the noble metal oxide layer and the metal oxide semiconductor layer. It is an enlarged view.
- the cross-sectional TEM measurement it was confirmed that the average crystal grain size of the noble metal oxide layer was not more than the film thickness of the noble metal oxide layer. Enlarged views of the cross-section TEM of the element of Example 1 are shown in FIGS.
- the obtained element was subjected to CV (capacitance-voltage) measurement using E4980 (manufactured by Keysight Technology) to determine the thickness of the depletion region.
- the measurement frequency was 1 kHz, and the AC amplitude was 0.03V.
- FIG. 14 shows the results of CV measurement of the elements of Example 1 and Examples 2 to 4 described later.
- the bottom graph among the graphs marked with ⁇ is the result of CV measurement of the element of Example 2, and the results of CV measurement of the element of Example 1 in order from the bottom are shown in Example.
- the top graph is the result of CV measurement of the element of Example 4.
- the thickness of the depletion region was 210 nm.
- a broken line represents a change in the thickness of the depletion region corresponding to Vshotky obtained from FIG. 15 described later and the temperature dependence result thereof. J. et al. Appl. Phys. 104, 123706, 2008, and an analysis based on the simulation from an exponential trap-mediated SCLC model that assumed the presence of an initial free carrier concentration.
- C is the capacitance value (F)
- A is the effective area (cm 2 ) of the electrode
- ⁇ is the relative dielectric constant of the metal oxide semiconductor (16 in the case of InGaZnO (1: 1: 1)).
- the relative dielectric constant is obtained from the film thickness dependence result of CV measurement of a sample whose film thickness is known.
- ⁇ 0 is the dielectric constant of vacuum (8.854 ⁇ 10 ⁇ 14 F / cm).
- the effective area A of the electrode represents an area of a portion where the noble metal oxide layer, the metal oxide semiconductor layer, and the ohmic electrode layer overlap when viewed from the direction perpendicular to the stacking surface of the element.
- the area of the ohmic electrode layer having a diameter of 500 ⁇ m was defined as A.
- the carbon concentration in the Schottky interface of a noble metal oxide layer and a metal oxide semiconductor layer was measured using ADEPT1010 (made by ULVAC-PHI Co., Ltd.) by SIMS. The measurement was performed by selecting C (carbon, mass number 12) as the element of interest, and using the primary ion species Cs + , the acceleration energy of primary ions 3 keV, and the secondary ion polarity Negative. The charge compensation was not performed and the mass resolution was set to Normal. The carbon concentration was quantified using the ratio of the strength and carbon concentration of an indium oxide-tin oxide (ITO) standard thin film sample.
- ITO indium oxide-tin oxide
- the Schottky interface is a point where the depth profile of the GaO intensity value of the metal oxide semiconductor layer and the depth profile of the PdO intensity value of the noble metal oxide layer intersect, and the C spectrum existing at ⁇ 20 nm (C depth profile) was the carbon concentration at the Schottky interface.
- the results are shown in Table 1.
- Schottky barrier height and diode ideality coefficient are obtained by measuring forward current using Semiconductor Analyzer B1500 (manufactured by Keysight Technology) (measuring minute current with Atto Sense Unit (ASU)). It was. In addition to the measurement at room temperature (25 ° C.), temperature dependency measurement was performed using a temperature control chuck PA200 (manufactured by Cascade Microtech). In Example 1, when the Schottky barrier height at room temperature was determined using I 0 calculated from the Cheung plot and an effective mass of 0.3, it was 1.2 eV.
- the Anderson plot was performed based on the temperature dependence, and the Schottky barrier height and the Richardson constant were determined to be 1.24 eV and 42 Acm ⁇ 2 K ⁇ 2 , respectively.
- the diode ideality factor was 1.2. Table 1 shows the values calculated from the Cheung plot as the Schottky barrier height.
- FIG. 15 shows IV characteristic evaluation results (semi-log plots) of Example 1 and Examples 2 to 4 described later, and FIG. 15 shows IV characteristic evaluation results (linear) of Example 1 and Examples 2 to 4 described later.
- 16 shows the IV forward temperature dependency evaluation result (semilog plot) of Example 1
- FIG. 17 shows the differential resistance evaluation result (semilog) of Example 1 and Examples 2 to 4 described later.
- 18 shows the results of evaluation of IV forward characteristics (semi-log plot) and the power dependence of the power index (inset) in FIG. 19 (circles are experimental values, dotted lines are simulation results).
- FIG. 20 shows experimental values and simulation comparisons in FIG.
- the results of Examples 1 to 4 are shown as “200 nm”, “100 nm”, “500 nm” and “1000 nm”, respectively.
- the bottom graph is a 298K graph, and from the bottom, the graph is 308K graph, 318K graph, 323K graph, 328K graph, 333K graph, 338K graph, The upper graph is a 343K graph.
- ⁇ represents the experimental value
- the dotted line represents the simulation result
- the bottom graph is the experimental value and simulation result of 298K
- the second graph from the bottom is the experimental value and simulation result of 323K
- the top graph is the experimental value and simulation result of 343K.
- FIG. 21 is an IV forward characteristic evaluation result (semi-log plot) in Example 1, and is a diagram showing a partial pressure relationship of an applied voltage at the time of current value measurement. From the simulation results, it was found that the voltage V diode to the Schottky interface and the voltage V SCLC to the metal oxide semiconductor layer are distributed as in the illustrated equivalent circuit. Since the details of the voltage value applied to the diode can be understood from FIG. 21, more detailed values of the ideality factor and the Schottky barrier height of the diode can be obtained.
- a metal oxide semiconductor layer was formed on a quartz substrate in the same manner as the metal oxide semiconductor layer of the element described above, and annealing after the film formation was performed in the same manner to obtain a quartz substrate with a metal oxide semiconductor layer.
- UV-VIS apparatus V-370 manufactured by JASCO Corporation
- the transmission spectrum was measured using a graph, and the figure shown in FIG. 22 was plotted with hv on the horizontal axis and ( ⁇ hv) 1/2 on the vertical axis.
- ⁇ is an absorption coefficient
- h is a Planck constant
- v is a frequency of incident light.
- Example 1 The results of Examples 1 to 4 are shown as “200 nm”, “100 nm”, “500 nm”, and “1000 nm”, respectively. A plotted curve on the graph was drawn, a tangent line was drawn at the position of the inflection point, and the point where the horizontal axis and the tangent line intersected was defined as the band gap. The results are shown in Table 1.
- a noble metal oxide layer was formed on a quartz substrate in the same manner as the noble metal oxide layer of the element described above to obtain a quartz substrate with a noble metal oxide layer.
- the obtained quartz substrate with a noble metal oxide layer and the above-mentioned quartz substrate with a metal oxide semiconductor layer are subjected to noble metal oxidation using a fully automatic horizontal multi-purpose X-ray diffraction (XRD) apparatus SmartLab (manufactured by Rigaku Corporation).
- XRD X-ray diffraction
- SmartLab manufactured by Rigaku Corporation
- the crystal structures of the physical layer and the metal oxide semiconductor layer were measured.
- X-rays were Cu-K ⁇ rays (wavelength 1.5406 mm, monochromatized with a graphite monochromator).
- FIG. 23 shows the XRD pattern (result of subtracting substrate information) of the quartz substrate with the metal oxide semiconductor layer in Example 1 and Examples 2 to 4 to be described later.
- FIG. 23 shows Examples 1 and Examples 2 to 4 to be described later.
- FIG. 24 shows the XRD pattern of the quartz substrate with the metal oxide semiconductor layer (the result of further normalizing FIG. 23 with the film thickness of the metal oxide semiconductor layer).
- the bottom graph is the XRD pattern for Example 2, the XRD pattern for Example 1, the XRD pattern for Example 3, and the top graph for Example 4 in order from the bottom. This is an XRD pattern.
- the bottom graph is the XRD pattern for Example 2, the XRD pattern for Example 1, the XRD pattern for Example 3, and the top graph for Example 4 in order from the bottom. This is an XRD pattern.
- Table 1 shows the results of the crystal structures of the noble metal oxide layer and the metal oxide semiconductor layer.
- the noble metal oxide layer was exposed by chemical etching, and the XRD pattern was measured using XRD (SmartLab (manufactured by Rigaku Corporation)) of oblique incidence X-rays.
- the XRD pattern is shown in FIG. ⁇ is the incident angle of the X-ray with respect to the sample surface, and ⁇ is the angle of the detector with respect to the sample surface.
- the second XRD pattern of ⁇ 0.4 ° from the bottom
- JCPDS (85-0624) is shown in the upper part of FIG. 26, and JCPDS (89-4897) is shown in the lower part of FIG. From these results, it was identified that the noble metal oxide was PdO having a randomly oriented polycrystalline PdO structure.
- FIG. 27 shows a cross-sectional TEM of the element of Example 1.
- the three regions shown in FIG. 27 are photographed, and the irregularities at the interface between the noble metal oxide layer and the metal oxide semiconductor layer are traced, and this traced line is the root mean square roughness (RMS) standardized by JISB0601-2001.
- RMS root mean square roughness
- the work function of the noble metal oxide in the noble metal oxide layer was measured using an atmospheric photoelectron spectrometer AC-3 (manufactured by Riken Keiki Co., Ltd.). The results are shown in Table 1.
- the orientation of the metal oxide semiconductor layer was measured using a transmission electron microscope (TEM). The results are shown in Table 1.
- the carrier concentration, mobility, and specific resistance of the metal oxide semiconductor layer, and the specific resistance of the noble metal oxide layer were measured as follows. About the quartz substrate with the above-mentioned noble metal oxide layer and the quartz substrate with the metal oxide semiconductor layer, the substrate is cut into 1 cm squares, In electrodes are attached to the four corners, and the Hall effect measurement device Reset8400 (Toyo Technica) is installed at room temperature. The specific resistance of the metal oxide semiconductor layer and the noble metal oxide layer was measured by van der Pauw method. Further, the carrier concentration of the metal oxide semiconductor layer was measured by Hall effect measurement. The mobility of the metal oxide semiconductor layer was calculated using the specific resistance value and the carrier concentration value of the metal oxide semiconductor layer.
- differential on-resistance was evaluated using B1500.
- the results are shown in Table 1.
- the current density when a reverse bias of 0.2 MV / cm was applied and the current density when a forward bias of 0 to 5 V was applied were evaluated using B1500. The results are shown in Table 1.
- FIG. 28 shows the evaluation results of the breakdown voltage corresponding to the elements of Example 1 and Examples 2 to 4 described later (represented as “200 nm”, “100 nm,“ 500 nm ”, and“ 1000 nm ”, respectively).
- the height of the bar graph is an average withstand voltage value measured for 50 or more elements. Error bars represent standard deviation, and green stars represent maximum pressure resistance.
- FIG. 29 is a histogram of actual breakdown voltage values corresponding to FIG. 28, and FIG. 30 is a histogram of breakdown voltage obtained by normalizing FIG. From this result, the breakdown voltage and the variation in breakdown voltage in Table 1 were obtained.
- FIG. 29 is a histogram of actual breakdown voltage values corresponding to FIG. 28
- FIG. 30 is a histogram of breakdown voltage obtained by normalizing FIG. From this result, the breakdown voltage and the variation in breakdown voltage in Table 1 were obtained.
- FIG. 29 is a histogram of actual breakdown voltage values corresponding to FIG. 28
- FIG. 30 is a histogram of breakdown voltage obtained
- the upper left is a histogram of breakdown voltage values of Example 2
- the upper right is a histogram of breakdown voltages of Example 1
- the lower left is a histogram of breakdown voltage values of Example 3
- the lower right is an example.
- 4 is a histogram of dielectric breakdown voltage values of 4;
- the upper left is the breakdown voltage histogram of the second embodiment
- the upper right is the breakdown voltage histogram of the first embodiment
- the lower left is the breakdown voltage histogram of the third embodiment
- the lower right is the breakdown voltage histogram of the fourth embodiment.
- Examples 2 to 47 and Comparative Examples 1 to 14 Devices were fabricated and evaluated in the same manner as in Example 1 under the conditions shown in Tables 1-13. The results are shown in Tables 1-13.
- InGaO (1: 1) indicates the ratio of metal elements of the metal oxide semiconductor, In: Ga being 1: 1. Further, in the table, a layer without a film thickness is not laminated.
- Ga 2 O 3 / InGaZnO (1: 1: 1) represents Ga 2 O 3 as the first metal oxide semiconductor layer and the second metal oxide semiconductor layer. Shows that InGaZnO (1: 1: 1) was stacked. The crystal structure, orientation carrier concentration, mobility, specific resistance, and band gap of the metal oxide semiconductor layer when the metal oxide semiconductor layer is stacked are not described.
- aluminum of the support substrate is an aluminum substrate (diameter 4 inches) with an electrical resistivity of less than 0.01 m ⁇ ⁇ cm
- polysilicon is a polysilicon substrate (diameter 4 inches) with an electrical resistivity of 10 m ⁇ ⁇ cm
- the alkali-free glass is an Eagle XG substrate (diameter 4 inches) (made by Corning) having an electrical resistivity ⁇ m ⁇ ⁇ cm
- the polyimide is a polyimide substrate (diameter 4 inches) having an electrical resistivity ⁇ m ⁇ ⁇ cm.
- the relative permittivity of the metal oxide semiconductor Ga 2 O 3 is 14, the relative permittivity of InGaZnO (5: 3: 2) is 19, and the relative permittivity of InGaZnO (5: 1: 4) is 20
- the relative dielectric constant of InSnZnO (25:15:60) is 21, the relative dielectric constant of InSnZnO (48.5: 15: 36.5) is 25, and the relative dielectric constant of InGaO (1: 1).
- the ratio is 17, and the relative dielectric constant of InGaO (93: 7) is 12. In either case, the relative dielectric constant is obtained from the film thickness dependence result of CV measurement of a sample whose film thickness is known.
- FIG. 31 shows IV characteristic evaluation results (semi-log plots) and sectional views of the devices of Examples 5 to 7.
- FIG. 32 shows the differential resistance-voltage (semi-log plot) of the elements of Examples 5 to 7.
- “Ga2O3 200 nm” indicates Example 5 (43.0 V, 2.15 MV / cm)
- “Ga2O3 / IGZO 50/300 nm” indicates Example 6 (63.0 V, 1.80 MV / cm).
- “Ga2O3 / IGZO 50 / 500nm” shows Example 7 (97.5V, 1.77MV / cm).
- “Ga 2 O 3 200 nm” indicates Example 5
- “Ga 2 O 3 / IGZO 50/300 nm” indicates Example 6
- “Ga 2 O 3 / IGZO 50/500 nm” indicates Example 7.
- FIG. 33 shows the IV characteristic evaluation results (semi-log plots) of the devices of Examples 1, 8, 10 and 22 and Comparative Examples 2 and 3.
- PdO (40) Pd (50) Ti (15) represents Example 1
- PdO (15) Pd (50) Ti (15) represents Example 8
- PdO (50) “Ti (15)” indicates Example 10
- PdO (40)” indicates Example 22
- Ti (15) indicates Comparative Example 2
- Pd (10) Ti (15) compares Example 3 is shown.
- FIG. 34 shows the relationship between the on-resistance and breakdown voltage of the elements of Examples 1 to 7. It was found that the devices of Examples 6 and 7 achieved the single crystal silicon limit. “IGZO 100 nm” indicates Example 2, “IGZO 200 nm” indicates Example 1, “IGZO 500 nm” indicates Example 3, “IGZO 1000 nm” indicates Example 4, and “Ga 2 O 3 200 nm” indicates Example 2. Example 5 is shown, “Ga 2 O 3 / IGZO 50/300 nm” shows Example 6, and “Ga 2 O 3 / IGZO 50/500 nm” shows Example 7.
- Example 48 An n-type Si substrate (diameter 4 inches, P-doped) having a resistivity of 1 m ⁇ ⁇ cm was mounted on CS-200, and the atmosphere was evacuated. Note that a Ti film having a thickness of 100 nm is formed on the back surface as a lead electrode for measurement.
- the film forming conditions were CS-200, DC 300 W, Ar atmosphere, 0.5 Pa, 700 seconds. Mo15 nm was deposited as an ohmic electrode layer.
- the film forming conditions were DC 100 W and Ar atmosphere 0.5 Pa.
- a metal oxide semiconductor InGaZnO (1: 1: 1) was formed to a thickness of 200 nm as a metal oxide semiconductor layer.
- the film forming conditions were 0.5 Pa and 780 seconds in a mixed gas atmosphere of DC 300 W, Ar 99%, and H 2 O 1%.
- the film formation from the ohmic electrode layer to the metal oxide semiconductor was performed consistently without removing the substrate after mounting the n-type Si substrate using a 4-inch target set in CS-200 and evacuating.
- a metal mask to form a noble metal oxide layer, noble metal layer, and low-resistance base metal layer without removing the substrate after mounting and evacuating the substrate so that it is patterned to an electrode size of 500 ⁇ m in diameter.
- a PdO film having a thickness of 40 nm was formed as a noble metal oxide layer.
- the film forming conditions were set to 0.5 Pa and 270 seconds in a DC 300 W, O 2 atmosphere. Subsequently, 50 nm of Pd was deposited as a noble metal layer.
- the film forming conditions were DC 300 W, 0.5 Pa in an Ar atmosphere, and 60 seconds. Al was deposited to a thickness of 1000 nm as a low resistance base metal layer.
- the film formation conditions were DC 300 W, Ar atmosphere, 0.5 Pa, and 6000 seconds. After the film formation, this substrate was taken out and annealed in an electric furnace at 300 ° C. for 1 hour to obtain an element (structure).
- a layer without a film thickness is not laminated.
- “In / Mo” indicates that Mo was used as the first ohmic electrode layer, and In was stacked as the second ohmic electrode layer.
- the film formation conditions were set to 100 W DC for both In and Mo and 0.5 Pa for Ar atmosphere. In was used as an upper layer so as to be in contact with the metal oxide semiconductor.
- the alkali-free glass is an Eagle XG substrate (4 inches in diameter) (made by Corning) having an electrical resistivity of ⁇ m ⁇ ⁇ cm.
- the effective area A (cm 2 ) of the electrode in CV measurement is the area where the noble metal oxide layer, the metal oxide semiconductor layer, and the ohmic electrode layer overlap when viewed from the direction perpendicular to the stack surface of the element. Represents.
- the area of the noble metal oxide layer having a diameter of 500 ⁇ m was defined as A.
- Example 52 An element was fabricated on a glass substrate (4 inch Eagle XG substrate) using a photomask. The film forming conditions of Example 1 and each layer are the same. First, Mo was sputtered on one surface of a glass substrate as a low resistance base metal layer, and Pd was sputtered as a noble metal layer at 150 nm and 50 nm, respectively. Next, the Mo / Pd laminated film was patterned using the photomask 1. For the photoresist, AZ1500 (manufactured by AZ Electronic Materials) was used. After exposure through the photomask 1, development was performed with tetramethylammonium hydroxide (TMAH), and Pd was developed with AURUM-302 (manufactured by Kanto Chemical). The first patterning was performed, and when Mo was exposed, Mo was second patterned with a PAN (phosphoric acid-acetic acid-nitric acid mixed acid) etchant to form a lower layer electrode.
- TMAH tetramethylammonium hydro
- patterning is performed by a lift-off process using PdO as a noble metal oxide layer and InGaZnO (1: 1: 1) as a metal oxide semiconductor layer.
- AZ5214 was exposed through the photomask 2, exposed to the entire surface after the reversal baking process, and developed with TMAH.
- PdO 40 nm and InGaZnO (1: 1: 1) 200 nm were consistently deposited on the patterned resist-coated substrate.
- lift-off in acetone was performed to pattern PdO as a noble metal oxide layer and InGaZnO (1: 1: 1) as a metal oxide semiconductor layer.
- thermosetting non-photosensitive polyimide was patterned using thermosetting non-photosensitive polyimide and photomask 3.
- a thermosetting non-photosensitive polyimide solution was applied on the entire surface of the substrate with a spin coater, and then patterned using AZ5214 and the photomask 3.
- AZ5214 was exposed through the photomask 3, and the entire surface was exposed after the reversal baking process, and developed with TMAH.
- the thermosetting non-photosensitive polyimide was etched with TMAH and patterned. After patterning, the thermosetting non-photosensitive polyimide was heated and cured in the atmosphere at 200 ° C. for 1 hour.
- the ohmic electrode layer was patterned by a lift-off process using the image reversal resist AZ5214 and the photomask 4. AZ5214 was exposed through the photomask 4, and the entire surface was exposed after the reversal baking process, and developed with TMAH. On the patterned substrate with resist, Mo 150 nm was consistently formed as the first ohmic electrode layer, and Au 500 nm was consistently formed as the second ohmic electrode layer. Thereafter, the ohmic electrode layer was patterned by lifting off in acetone. An element having the structure shown in FIGS. 10A and 10B was obtained. Evaluation was performed in the same manner as in Example 1. The results are shown in Table 15.
- Example 53 Elements were fabricated in the same manner as in Example 52 except that photomasks 5 to 8 having patterns different from those of Photomasks 1 to 4 used in Example 52 were used, and elements having the structures shown in FIGS. 10C and 10D were obtained. . Evaluation was performed in the same manner as in Example 1. The results are shown in Table 15.
- Example 54 Elements were fabricated in the same manner as in Example 52 except that photomasks 9 to 12 having patterns different from those of Photomasks 1 to 4 used in Example 52 were used, and elements having the structures shown in FIGS. 10E and 10F were obtained. . Evaluation was performed in the same manner as in Example 1. The results are shown in Table 15.
- the structure of the present invention can be used for semiconductor elements and the like.
- the semiconductor element of the present invention can be used for electronic circuits, electrical equipment, electronic equipment, vehicles, power engines, and the like.
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Abstract
Description
低逆方向電流特性を有するショットキー接合は、形成することが困難であった。
本発明者らは、ショットキー接合の制御が困難であった金属酸化物半導体薄膜に対し、鋭意研究を行った結果、低逆方向電流特性を特徴とするショットキーバリアが機能するショットキー接合を見出し、本発明に至った。
1.金属酸化物半導体層と、
貴金属酸化物層と、を含み、
前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、
前記貴金属酸化物層の膜厚が10nm超である構造物。
2.空乏領域を有する1に記載の構造物。
3.前記貴金属酸化物層が多結晶構造を含む1又は2に記載の構造物。
4.前記貴金属酸化物層と隣接して、前記金属酸化物半導体層と反対の側に、さらに、貴金属層を含む1~3のいずれかに記載の構造物。
5.前記貴金属層と隣接して、前記貴金属酸化物層の反対の側に、さらに、低抵抗卑金属層を含む4に記載の構造物。
6.前記貴金属酸化物層の貴金属酸化物が、酸化パラジウム、酸化ルテニウム、酸化白金、酸化イリジウム、酸化銀、酸化レニウム、酸化オスミウム、酸化ロジウム、酸化ニッケル及び酸化金からなる群から選択される1以上である1~5のいずれかに記載の構造物。
7.前記貴金属酸化物層の貴金属酸化物が、PdO構造のPdO、ルチル構造のRuO2、α-PtO2構造のPtO2、ルチル構造のIrO2、Cu2O構造のAg2O、スクッテルダイト構造のReO3、ルチル構造のOsO2、コランダム構造のRh2O3、NiO構造のNiO、及びAu2O3構造のAu2O3からなる群から選択される1以上である1~6のいずれかに記載の構造物。
8.前記貴金属酸化物層の貴金属酸化物の平均結晶粒径が、前記貴金属酸化物層の膜厚以下である1~7のいずれかに記載の構造物。
9.前記貴金属酸化物層の界面粗さが5nm以下である1~8のいずれかに記載の構造物。
10.前記金属酸化物半導体層と前記貴金属酸化物層とのショットキー界面の炭素濃度が2×1019cm-3以下である1~9のいずれかに記載の構造物。
11.前記貴金属酸化物層の抵抗率が1×10-2Ω・cm以下である1~10のいずれかに記載の構造物。
12.前記貴金属酸化物層の貴金属酸化物の仕事関数が4.8eV以上である1~11のいずれかに記載の構造物。
13.前記金属酸化物半導体層が、アモルファス又は多結晶である1~12のいずれかに記載の構造物。
14.前記金属酸化物半導体層の金属酸化物が、In、Sn、Cd、Zn、Ga及びGeからなる群から選択される1以上の金属元素の酸化物である1~13のいずれかに記載の構造物。
15.前記金属酸化物半導体層におけるGa又はInの含有率が、前記金属酸化物半導体層の全金属元素に対し、45原子%以上である1~14のいずれかに記載の構造物。
16.前記金属酸化物半導体層がランダム配向である1~15のいずれかに記載の構造物。
17.前記貴金属酸化物層と、前記金属酸化物半導体層との、ショットキー障壁高さが0.7eV以上である1~16のいずれかに記載の構造物。
18.前記貴金属酸化物層の、前記金属酸化物半導体層と反対の側に、さらに、基板を含む1~17のいずれかに記載の構造物。
19.さらに、オーミック電極層を有し、前記オーミック電極層と前記貴金属酸化物層が接触しない1~18のいずれかに記載の構造物。
20.前記金属酸化物半導体層が、1層又は2層以上であり、2層以上の場合には、いずれか1層が貴金属酸化物層に隣接する1~19のいずれかに記載の構造物。
21.逆方向電圧印加時の耐圧が0.5MV/cm以上である1~20のいずれかに記載の構造物。
22.0.2MV/cmの逆バイアス印加時に電流密度が1×10-6A/cm2以下である1~21のいずれかに記載の構造物。
23.順方向バイアス印加時のダイオード理想係数が1.5以下である1~22のいずれかに記載の構造物。
24.順方向バイアスが5V以下で、電流密度が1000A/cm2に達する1~23のいずれかに記載の構造物。
25.前記金属酸化物半導体層を、水素又は水を導入した雰囲気中で、スパッタリングによって成膜し、1~24のいずれかに記載の構造物を得る、構造物の製造方法。
26.前記貴金属酸化物層を、導入ガス流量の50%以上が酸素である雰囲気で、スパッタリングによって成膜し、1~24のいずれかに記載の構造物を得る、構造物の製造方法。
27.前記貴金属酸化物層及び前記金属酸化物半導体層を成膜した後、220~500℃でアニールを行う25又は26に記載の構造物の製造方法。
28.前記貴金属酸化物層及び前記金属酸化物半導体層をスパッタリングによって連続で成膜するか、又は前記貴金属酸化物層の成膜と、前記金属酸化物半導体層の成膜との間を、真空又は不活性の雰囲気とする25~27のいずれか記載の構造物の製造方法。
29.1~24のいずれかに記載の構造物を用いた半導体素子。
30.パワー半導体素子、ダイオード素子、ショットキーバリアダイオード素子、静電気放電保護ダイオード、過渡電圧保護ダイオード、発光ダイオード、金属半導体電界効果トランジスタ、接合型電界効果トランジスタ、金属酸化膜半導体電界効果トランジスタ、ショットキーソース/ドレイン金属酸化膜半導体電界効果トランジスタ、アバランシェ増倍型光電変換素子、固体撮像素子、太陽電池素子、光センサ素子、タッチセンサ素子、表示素子、又は抵抗変化メモリである29に記載の半導体素子。
31.29又は30に記載の半導体素子を用いた電子回路。
32.31に記載の電子回路を用いた電気機器、電子機器、車両、又は動力機関。
これを用いることで、面内均一性に優れ、低接触抵抗、高on-off比、高障壁高さ、低逆方向電流特性であるショットキーバリアが機能する半導体素子を形成することができる。
また、低温成膜可能でプロセス適応性に優れ、基板を自由に選択できる。
また、薄膜にてショットキー接合を形成できるため、プロセス汎用性、低温成膜、基板を選択しない等の利点を得ることができる。また、フレキシビリティを活かしたデバイス応用、様々なデバイスとの混載等が可能となる。
アモルファスの場合、大面積均一性に優れ、逆バイアス印加時のインパクトイオン化を低減し、耐圧向上させやすい。また、電気特性のバラつきや大幅な特性劣化を緩和することができる。また、高耐圧で信頼性の高い大電流ダイオードやスイッチング素子を高い歩留まりで製造することができる。多結晶の場合、大面積均一性及び伝導特性を向上させやすく、より安定性に優れる傾向がある。
また、「非晶質」は一部に結晶化や微結晶化した部分がある場合も含む。一部結晶化した部分に電子線を照射すると、回折像が認められることがある。
「微結晶構造」とは、結晶粒径のサイズがサブミクロン以下であり、明解な粒界が存在しないものを言う。明解な粒界の有無は、例えば断面TEMより観察でき、結晶粒径サイズは回折像のマッピングより取得できる。回折像が等しい部分が同一粒内と定義できる。
「多結晶」とは、結晶粒径のサイズがミクロンサイズを超え、明解な粒界が存在するものを言う。明解な粒界は、例えば断面TEMより観察できる。明確な粒界が存在するため、平面TEMや電子線後方散乱回折法(EBSD)によって粒径サイズを定義することができる。
ランダム配向とは、各結晶粒の配向が特定の配向成分に偏っていないことを意味する。
例えば、XRDにて薄膜を分析したときに、得られたスペクトル中の複数のピークの相対強度が粉末X線パターンにおける相対強度と一致する場合、ランダム配向である。具体的には、粉末X線パターンの強度が最大である面方位のピーク強度(以下、粉末X線NO.1ピークと言う。)に対して、粉末X線パターンの2番目及び3番目のピーク強度(以下、それぞれ粉末X線NO.2ピーク、粉末X線NO.3ピークと言う。)とし、粉末X線NO.1ピーク/粉末X線NO.2ピーク(粉末X線ピーク強度比1)及び粉末X線NO.1ピーク/粉末X線NO.3ピークとのピーク強度比(粉末X線ピーク強度比2)とする。その場合に、測定して得られたスペクトル中の複数のピークのうち、粉末X線NO.1~NO.3ピークの2θ位置に対して±1°に収まるピークがそれぞれ存在し、粉末X線NO.1に対応するピークを薄膜X線ピーク1、粉末X線NO.2に対応するピークを薄膜X線ピーク2、粉末X線NO.3に対応するピークを薄膜X線ピーク3としたときに、薄膜X線ピーク1/薄膜X線ピーク2のピーク強度比の値が粉末X線ピーク強度比1の値の0.3~3倍の値となり、薄膜X線ピーク1/薄膜X線ピーク3のピーク強度比の値が粉末X線ピーク強度比2の値の0.3~3倍の値となる場合、金属酸化物半導体層はランダム配向であるとみなす。
これにより、s軌道の球状のオービタルを導電パスとして利用できるため、多結晶、アモルファスを問わず、電気特性を面内方向で安定させやすい。
また、金属酸化物半導体層におけるGa又はIn含有率が、金属酸化物半導体層の全金属元素に対し、45原子%以上であることが好ましい。金属元素がGaの場合、50~100原子%がより好ましく、Inの場合50~70原子%がより好ましい。
Inが45原子%以上の場合、高導電性や高キャリア濃度の金属酸化物半導体層を得やすく、低抵抗であるショットキー界面を形成することができる。
Znが45原子%以上の場合、化学的反応性に富み、ウェットエッチング等の加工がしやすいショットキー界面を形成することができる。
Snが45原子%以上の場合、化学的安定性に富み、耐久性の観点で優位なショットキー界面を形成することができる。
0≦x/(x+y+z)≦0.8 (A)
0≦y/(x+y+z)≦0.8 (B)
0≦z/(x+y+z)≦1.0 (C)
(式中、xはIn、Sn、Ge及びTiからなる群から選択される1種以上の元素の原子数を表し、
yはZn、Y、Sm、Ce及びNdからなる群から選択される1種以上の元素の原子数を表し、
zはGa及びAlからなる群から選択される1種以上の元素の原子数を表す。)
0≦x/(x+y+z)≦0.7 (A-1)
0≦y/(x+y+z)≦0.8 (B-1)
zの元素がGaのとき:0.02≦z/(x+y+z)≦1.0
zの元素がAlのとき:0.005≦z/(x+y+z)≦0.5 (C-1)
(式中、x、y及びzは上記式(A)~(C)と同じである。)
0.1≦x/(x+y+z)≦0.5 (A-2)
0.1≦y/(x+y+z)≦0.5 (B-2)
0.03≦z/(x+y+z)≦0.5 (C-2)
(式中、x及びyは上記式(A)~(C)と同じであり、zはGaの原子数である。)
0≦x/(x+y+z)≦0.25 (A-3)
0.3≦z/(x+y+z)≦1.0 (C-3)
(式中、x、y及びzは上記式(A)~(C)と同じである。)
例えば、InGaO(47:53)は、高バンドギャップと低抵抗特性を得ることができる。
Sn-In-Zn系の場合は、全金属元素において、Inの含有量は15原子%以上が好ましい。
金属酸化物半導体層は、2層以上の場合には、各層の膜厚が上記範囲でもよく、2層以上の層の全層の合計の膜厚が上記範囲でもよい。
また、貴金属酸化物層の貴金属酸化物の平均結晶粒径が、貴金属酸化物層の膜厚以下であることが好ましい。これにより、多結晶粒界が分断され、粒界を伝わる伝導が抑制でき面内でのばらつきが低減でき、均一性を有するショットキーバリアが発現しやすい。
尚、平均結晶粒径は、透過型電子顕微鏡(TEM:Transmission Electron Microscope)にて、50万倍で観察した膜厚方向の像が得られる断面TEM像の同一深度の10点の結晶粒の粒径の平均値である。結晶粒は、干渉縞を利用し、干渉縞が平行となっている箇所を単結晶とみなし定義する。各単結晶における最大フェレ径を結晶粒径とした。
本発明の構造物の各層の膜厚は、上記と同様の方法で測定することができる。
高いショットキー障壁を形成し、安定的な構造物を形成する観点から、酸化パラジウム、酸化ルテニウム、酸化白金、酸化イリジウムが好ましい。中でも、酸化パラジウムはスパッタリング成膜時のウインドウが広く、工業的な観点から優位性をもつため、好ましい。
貴金属酸化物は、1種単独で用いてもよく、2種以上を組み合わせてもよい。
また、酸化ルテニウムは、ドライエッチングによってパターニングすることが可能である。例えば、酸素ガス、フッ化炭素ガス、フッ素ガス、塩素ガス、臭素ガス、沃素ガス、オゾンガス、ハロゲン化水素ガス、ハロゲン化炭素ガスによって反応性エッチングができる。また、上記ガス種を混合して用いてもよい。
特定の面配向成分の割合が大きい場合、表面に段差ができやすく、また弱配向成分が面内で安定しないため、実質的なショットキーバリアが低下してしまうおそれがある。
具体的には、断面TEMを3カ所撮影し、貴金属酸化物層と金属酸化物半導体層の界面の凹凸をトレースし、このトレースした線をJISB0601-2001に規格された二乗平均平方根粗さ(RMS)の算出方法に準拠して、貴金属酸化物層の界面の粗さを求めることができる。断面TEMは、貴金属酸化物層と金属酸化物半導体の界面のトレース線を引いたときに、極大値を5つ以上もち、かつ、隣り合う極大値と極小値の差が明瞭に判断できる倍率で取得することが好ましい。
貴金属酸化物層の比抵抗は、例えばファンデルポー法を用いて、測定することができる。直接電気測定によって測定してもよい。
貴金属酸化物層の貴金属酸化物の仕事関数は、例えばX線光電子分光法(XPS)、紫外光電子分光法(UPS)、大気光電子分光法、ケルビンプローブ顕微鏡(KPM)を用いて、測定することができる。
金属酸化物半導体層が2層以上の場合、空乏領域の厚さは、貴金属酸化物層に隣接する金属酸化物半導体層において、上記範囲でもよく、2層以上の層の全層の合計の膜厚に対して、上記範囲でもよい。
ショットキー界面での炭素濃度は、例えば2次イオン質量分析法(SIMS)のデプスプロファイルを用いて、測定することができる。
I0:飽和電流[A]
q:素電荷[C]
R:金属酸化物半導体及び電極等による接触抵抗[Ω]
n:ダイオード理想係数
k:ボルツマン定数(8.617×10-5eV/K)
T:測定時のサンプル温度(K)
q:素電荷[602×10-19C]
V:印加電圧[V]
A:ダイオード実効面積[cm2]
A**:リチャードソン係数[Acm-2K-2]
これにより、基板と貴金属酸化物層の相互作用を防止し、接触抵抗を低減することができる。また、貴金属酸化物層の基板への密着性を改善し、貴金属酸化物層の表面平滑性を向上させることができる。
これにより、整流特性制御や空乏領域の厚さを制御することができる。
また、オーミック電極層を2以上の層で構成することもできる。例えば、金属酸化物半導体層に接する方に、Mo電極層を用い、さらに低抵抗金属であるAuやAl等の金属層を厚く積層し、この層をワイヤボンディングの土台とすることができる。オーミック電極層を用いることで、電力ロスなく電流を取り出すことができる。
オーミック電極層は、2層以上の場合には、各層の膜厚が上記範囲でもよく、2層以上の層の全層の合計の膜厚が上記範囲でもよい。
また、SiC基板、GaN基板、GaAs基板等を用いてもよい。
また、Al、Cu、Ni、SUS(ステンレス鋼)、Au、Ag、W、Ti等の金属基板を用いてもよい。
半導体基板の材料は、表面の平滑性が保たれていれば、特に限定されない。
半導体基板としては、キャリア濃度を1×1018cm-3以下に調整したSi基板、GaN基板、SiC基板、GaP基板、GaAs基板、ZnO基板、Ga2O3基板、GaSb基板、InP基板、InAs基板、InSb基板、ZnS基板、ZnTe基板、ダイヤモンド基板等を用いることができる。
半導体基板は単結晶であってもよいし、多結晶であってもよい。また、非晶質基板又は非晶質を部分的に含む基板でもよい。導電性基板、半導体基板、絶縁性基板の上に、化学気相成長(CVD)等の手法を用いて半導体膜を形成した基板を使用してもよい。
例えば、石英ガラス、バリウムホウケイ酸ガラス、アルミノホウケイ酸ガラス、アルミノシリケートガラス等の、フュージョン法やフロート法で作製される無アルカリガラス基板、セラミック基板、及び本作製工程の処理温度に耐えうる耐熱性を有するプラスチック基板(例えばポリイミド基板)等を用いることができる。プラスチック基板の場合、フレキシブル性があってもよい。
また、絶縁性基板として、誘電性基板も用いてもよい。誘電性基板としては、ニオブ酸リチウム基板、タンタル酸リチウム基板、酸化亜鉛基板、水晶基板、サファイア基板等が挙げられる。
さらに、ステンレス合金等の金属基板の表面に絶縁膜や誘電膜を設けた基板を用いてもよい。また基板に下地膜として絶縁膜を形成してもよい。下地膜として、CVD法やスパッタリング法等を用いて、酸化珪素膜、窒化珪素膜、酸化窒化珪素膜、又は窒化酸化珪素膜等の単層又は積層を形成できる。
任意の構造の材料としては、例えば、大規模集積回路(LSI)上のバックエンドオブラインを形成する金属、層間絶縁膜等の様々な金属や絶縁物の複合材料が挙げられる。
応力緩衝層としては、AlGaN層等が挙げられる。
遮光層としては、例えば金属、金属-有機物等を含むブラックマトリックス層、カラーフィルタ層が挙げられる。
電子/ホール輸送層としては、酸化物半導体層、有機半導体層等が挙げられる。
発光層としては、無機半導体層、有機半導体層等が挙げられる。
電子/ホールブロッキング層としては、酸化物半導体層等が挙げられる。
層構造の層は、単層でもよく、2以上の層でもよい。
また、耐圧のばらつきは、0.1MV/cm以下であることが好ましい。
例えば、耐圧は、逆方向電圧印加時のブレークダウン電圧を測定し、ブレークダウン電圧を、金属酸化物半導体層の膜厚で割り、算出することができる。耐圧のばらつきは、例えば同一プロセス同一基板上で測定した50点以上の耐圧の標準偏差値とする。
金属酸化物半導体層を、水素又は水を導入した雰囲気中で、成膜することが好ましい。これにより、金属酸化物半導体層をランダム配向にすることができる。
貴金属酸化物層の成膜の雰囲気としては、導入ガス流量の50%以上(より好ましくは70~100%)が酸素であることが好ましい。これにより、安定な貴金属酸化物層を形成でき、ショットキーバリアの安定性を向上することができる。
スパッタリングターゲットと基板距離(TS間隔)は好ましくは、10mm~200mmである。10mm未満の場合、放電ができないおそれがある。200mmを超える場合、半導体の膜質が疎になり、特性温度が大きな膜になるおそれがある。
これにより、界面の清浄度を保った状態で構造体を作製することができる。
これにより、安定したショットキー界面を形成することができる。
図1では、構造物1において、基板10の上に、低抵抗卑金属層20、貴金属層30、貴金属酸化物層40、金属酸化物半導体層50、第1のオーミック電極層60及び第2のオーミック電極層61がこの順で積層されている。
第1のオーミック電極層60及び第2のオーミック電極層61は、横方向への引き出しを考慮して、長くてもよい。
また、各層間を電気的に絶縁する層間絶縁膜を有してもよい。層間絶縁膜の形成方法によっては、各層が横方向に段差を有してもよい。各層間の一部が短絡され、残りの部分が層間絶縁膜によって絶縁されていてもよい。
第1のオーミック電極層60が金属酸化物半導体層50に接する領域は、金属酸化物半導体層50の端部まで及ばないことが好ましい。さらに、第1のオーミック電極層60が金属酸化物半導体層50に接する領域が、金属酸化物半導体層50の端部まで及ばず、かつ、積層面に対し垂直方向から見た場合に、第1のオーミック電極層60が金属酸化物半導体層50に接する領域の端部が、貴金属酸化物層40が金属酸化物半導体層50に接する領域の端部よりも内側に存在していることが好ましい。上記の配置であれば、リーク電流をより抑制できる。
第1のオーミック電極層60及び第2のオーミック電極層61は、横方向への引き出しを考慮して、長くてもよい。
第1のオーミック電極層60及び第2のオーミック電極層61は、横方向への引き出しを考慮して、長くてもよい。
低抵抗卑金属層20及びキャップメタル70は、横方向への引き出しを考慮して、長くてもよい。
低抵抗卑金属層20及びキャップメタル70は、横方向への引き出しを考慮して、長くてもよい。
第1のオーミック電極層60及び第2のオーミック電極層61は、横方向への引き出しを考慮して、長くてもよい。
第1のオーミック電極層60及び第2のオーミック電極層61は、横方向への引き出しを考慮して、長くてもよい。
低抵抗卑金属層20及びキャップメタル70は、横方向への引き出しを考慮して、長くてもよい。
図10Aは、本発明の構造物の他の実施形態を模式的に示した断面図であり、図10Bは、基板とポリイミドを除いた図10Aの平面図である。
図10Aでは、構造物101において、ガラス基板12の上に、低抵抗卑金属層20、貴金属層30、貴金属酸化物層40、金属酸化物半導体層50がこの順で積層され、ポリイミド81が形成された後、ポリイミド81が開口され、さらに、第1のオーミック電極層60及び第2のオーミック電極層61がこの順で積層されている。
図10Bは、図10Aのガラス基板12とポリイミド81を除いた平面図であり、図10Bの破線の部分の断面図が、図10Aである。
図10Cでは、構造物102において、ガラス基板12の上に、低抵抗卑金属層20、貴金属層30、貴金属酸化物層40、金属酸化物半導体層50がこの順で積層され、ポリイミド81が形成された後、ポリイミド81が開口され、さらに、第1のオーミック電極層60及び第2のオーミック電極層61がこの順で積層されている。
図10Dは、図10Cのガラス基板12とポリイミド81を除いた平面図であり、図10Dの破線の部分の断面図が、図10Dである。
図10Eでは、構造物103において、ガラス基板12の上に、低抵抗卑金属層20、貴金属層30、貴金属酸化物層40、金属酸化物半導体層50がこの順で積層され、ポリイミド81が形成された後、ポリイミド81が開口され、さらに、第1のオーミック電極層60及び第2のオーミック電極層61がこの順で積層されている。
図10Fは、図10Eのガラス基板12とポリイミド81を除いた平面図であり、図10Fの破線の部分の断面図が、図10Eである。
基板上に回路、多層構造を有するものとして、Si基板上に多層配線を有するバックエンドオブライン構造、抵抗変化メモリ、ロジックIC等が挙げられる。また、誘電体基板上に形成された高周波デバイスと組み合わせてもよい。
電気抵抗率1mΩ・cmのn型Si基板(直径4インチ、Pドープ)をスパッタリング装置CS-200(株式会社アルバック製)に装着し、雰囲気を真空にした。低抵抗卑金属層としてTiを15nm成膜した。成膜条件は、DC300W、Ar雰囲気にて0.5Pa、100秒間とした。
続いて、貴金属層としてPdを50nm成膜した。成膜条件は、DC300W、Ar雰囲気にて0.5Pa、60秒間とした。
次に貴金属酸化物層としてPdOを40nm成膜した。成膜条件は、DC300W、O2雰囲気にて0.5Pa(導入ガス流量中、100%が酸素)、270秒間とした。
金属酸化物半導体層として、金属酸化物半導体InGaZnO(1:1:1)を200nm成膜した。成膜条件は、DC300W、Ar99%、H2O1%の混合ガス雰囲気にて0.5Pa、780秒間とした。
低抵抗卑金属層から金属酸化物半導体層までの成膜は、CS-200にセットした3種類の4inchターゲットを用いて、n型Si基板を装着し真空にした後、基板を取り出すことなく一貫成膜した。
成膜後、この基板を取り出し、電気炉によって空気中300℃の条件で1時間アニールした。この基板を再度エリアマスク(直径500μm成膜用)とともにCS-200にセットした後、第1のオーミック電極層としてMo150nmを、第2のオーミック電極層としてAu500nmを積層成膜し(第1のオーミック電極層及び第2のオーミック電極層をまとめて、オーミック電極層とよぶ。)、素子(構造物)を得た。成膜条件は、DC100W、Ar雰囲気0.5Paとした。
尚、裏面に測定用の取り出し電極としてTiを100nm成膜した。成膜条件は、CS-200を用い、DC300W、Ar雰囲気にて0.5Pa、700秒間とした。
尚、得られた素子は図1に示す構造である。
断面TEM測定の際に、貴金属酸化物層の平均結晶粒径が、貴金属酸化物層の膜厚以下であることを確認した。実施例1の素子の断面TEMの拡大図を図12及び13に示す。
図14中、○で表記されているグラフの内、一番下のグラフは実施例2の素子のCV測定の結果であり、下から順に、実施例1の素子のCV測定の結果、実施例3の素子のCV測定の結果、一番上のグラフは実施例4の素子のCV測定の結果である。
実施例1において、空乏領域の厚さは、210nmであった。
破線は、後述の図15及びその温度依存性結果より取得したVshottkyに対応する空乏領域の厚みの変化を表す。J. Appl. Phys. 104,123706,2008を参考にして、初期フリーキャリア濃度の存在を仮定した、指数関数型トラップ介在のSCLCモデルよりシミュレーションに沿って解析した。
Cは容量値(F)であり、Aは電極の実効面積(cm2)であり、εは金属酸化物半導体の比誘電率(InGaZnO(1:1:1)の場合、16)である。比誘電率は膜厚既知であるサンプルのCV測定の膜厚依存性結果から求めたものである。
ε0は、真空の誘電率(8.854×10-14F/cm)である。
ここで、電極の実効面積Aは、素子の積層面に対し垂直方向から見た場合に、貴金属酸化物層、金属酸化物半導体層及びオーミック電極層が重複する部分の面積を表す。直径500μmのオーミック電極層の面積をAとした。
測定は、注目元素にC(カーボン、質量数12)を選択し、一次イオン種Cs+、一次イオンの加速エネルギー3keV、二次イオン極性Negativeにて行った。尚、帯電補償は行わず、質量分解能Normalとした。
炭素濃度は、酸化インジウム-酸化スズ(ITO)標準薄膜試料での強度と炭素濃度の比を用い、定量した。
ショットキー界面を、金属酸化物半導体層のGaOの強度値のデプスプロファイル及び貴金属酸化物層のPdOの強度値のデプスプロファイルが交わる箇所とし、その±20nmに存在するCスペクトル(Cのデプスプロファイル)の最大値をショットキー界面での炭素濃度とした。結果を表1に示す。
室温(25℃)での測定の他に、温度依存性測定を、温調チャックPA200(カスケードマイクロテック社製)を用いて実施した。
実施例1では、Cheungプロットから算出したI0及び有効質量0.3を用いて室温でのショットキー障壁高さを求めたところ1.2eVであった。
また、温度依存性よりアンダーソンプロットを実施し、ショットキー障壁高さ及びリチャードソン定数を求めたところ、それぞれ1.24eV、42Acm-2K-2となった。ダイオード理想係数は1.2であった。
ショットキー障壁高さとして、Cheungプロットから算出した値を、表1に示す。
図17中、一番下のグラフが298Kのグラフであり、下から順に、308Kのグラフ、318Kのグラフ、323Kのグラフ、328Kのグラフ、333Kのグラフ、338Kのグラフとなっており、一番上のグラフが343Kのグラフである。
図20中、○は実験値、点線はシミュレーション結果を表し、一番下のグラフが298Kの実験値及びシミュレーション結果であり、下から二番目のグラフが323Kの実験値及びシミュレーション結果であり、一番上のグラフが343Kの実験値及びシミュレーション結果である。
得られた実施例1に関する金属酸化物半導体層付きの石英基板及び後述の実施例2~4に関する金属酸化物半導体層付きの石英基板について、UV-VIS装置V-370(日本分光株式会社製)を用い透過スペクトルを測定し、図22に示す、横軸にhv、縦軸に(αhv)1/2をプロットした図を作成した。αは吸収係数であり、hはプランク定数であり、vは入射光の振動数である。実施例1~4の結果を、それぞれ「200nm」、「100nm」、「500nm」及び「1000nm」として示す。
グラフ上のプロットした曲線を描き、変曲点の位置で接線を引き横軸と接線が交わる点を、バンドギャップとした。結果を表1に示す。
実施例1及び後述の実施例2~4について、金属酸化物半導体層付きの石英基板のXRDパターン(基板情報を差分した結果)を図23に、実施例1及び後述の実施例2~4について、金属酸化物半導体層付きの石英基板のXRDパターン(図23をさらに金属酸化物半導体層の膜厚で規格化した結果)を図24に示す。
図23中、一番下のグラフが実施例2についてのXRDパターンであり、下から順に、実施例1についてのXRDパターン、実施例3についてのXRDパターン、一番上のグラフが実施例4についてのXRDパターンである。
図24中、一番下のグラフが実施例2についてのXRDパターンであり、下から順に、実施例1についてのXRDパターン、実施例3についてのXRDパターン、一番上のグラフが実施例4についてのXRDパターンである。
貴金属酸化物層及び金属酸化物半導体層の結晶構造の結果を表1に示す。
図25中、一番下のグラフはω=0.3°のXRDパターンであり、下から二番目のω=0.4°のXRDパターンであり、一番上のグラフがω=0.5°のXRDパターンである。ω=0.3°のXRDパターンは、サンプルに対してX線を最も浅く入射させた測定結果、下地のPdからの信号が重畳せず、貴金属酸化物層のみに由来するスペクトルである。
これらの結果より、貴金属酸化物はランダム配向の多結晶PdO構造を持つPdOであったと同定した。
上述の貴金属酸化物層付きの石英基板及び金属酸化物半導体層付きの石英基板について、基板をそれぞれ1cm四方にカットし、4隅にIn電極を取り付け、室温にてホール効果測定装置Resitest8400(東陽テクニカ製)を用いて、ファンデルポー法により、金属酸化物半導体層及び貴金属酸化物層の比抵抗測定を行った。また、ホール効果測定より、金属酸化物半導体層のキャリア濃度を測定した。金属酸化物半導体層の比抵抗値及びキャリア濃度値を用い、金属酸化物半導体層の移動度を算出した。
また、0.2MV/cmの逆バイアス印加時の電流密度、及び順方向バイアスを0~5V印加時の電流密度を、B1500を用いて、評価した。結果を表1に示す。
図29中、左上が実施例2の絶縁破壊電圧値のヒストグラムであり、右上が実施例1の絶縁破壊電圧値のヒストグラム、左下が実施例3の絶縁破壊電圧値のヒストグラム、右下が実施例4の絶縁破壊電圧値のヒストグラムである。
図30中、左上が実施例2の耐圧のヒストグラムであり、右上が実施例1の耐圧のヒストグラム、左下が実施例3の耐圧のヒストグラム、右下が実施例4の耐圧のヒストグラムである。
表1~13に示す条件とし、実施例1と同様にして素子を作製し、評価した。結果を表1~13に示す。
また、表中、膜厚の記載のない層については、積層しなかったことを示す。
表中、金属酸化物半導体について、「Ga2O3/InGaZnO(1:1:1)」は、第1の金属酸化物半導体層として、Ga2O3を、第2の金属酸化物半導体層として、InGaZnO(1:1:1)を積層成膜したことを示す。金属酸化物半導体層を積層成膜した場合の、金属酸化物半導体層の結晶構造、配向キャリア濃度、移動度、比抵抗、バンドギャップは記載しない。
図31では、「Ga2O3 200nm」が実施例5(43.0V、2.15MV/cm)を示し、「Ga2O3/IGZO 50/300nm」が実施例6(63.0V、1.80MV/cm)を示し、「Ga2O3/IGZO 50/500nm」が実施例7(97.5V、1.77MV/cm)を示す。
図32では、「Ga2O3 200nm」が実施例5を示し、「Ga2O3/IGZO 50/300nm」が実施例6を示し、「Ga2O3/IGZO 50/500nm」が実施例7を示す。
図33中、「PdO(40)Pd(50)Ti(15)」が実施例1を示し、(PdO(15)Pd(50)Ti(15)が実施例8を示し、「PdO(50)Ti(15)」が実施例10を示し、「PdO(40)」が実施例22を示し、「Ti(15)」が比較例2を示し、「Pd(10)Ti(15)」が比較例3を示す。
「IGZO 100nm」が実施例2を示し、「IGZO 200nm」が実施例1を示し、「IGZO 500nm」が実施例3を示し、「IGZO 1000nm」が実施例4を示し、「Ga2O3 200nm」が実施例5を示し、「Ga2O3/IGZO 50/300nm」が実施例6を示し、「Ga2O3/IGZO 50/500nm」が実施例7を示す。
抵抗率1mΩ・cmのn型Si基板(直径4インチ、Pドープ)をCS-200に装着し、雰囲気を真空にした。尚、裏面に測定用の取り出し電極としてTiを100nm成膜している。成膜条件は、CS-200を用い、DC300W、Ar雰囲気にて0.5Pa、700秒間とした。
オーミック電極層としてMo15nmを、成膜した。成膜条件は、DC100W、Ar雰囲気0.5Paとした。
続いて、金属酸化物半導体層として、金属酸化物半導体InGaZnO(1:1:1)を200nm成膜した。成膜条件は、DC300W、Ar99%、H2O1%の混合ガス雰囲気にて0.5Pa、780秒間とした。
オーミック電極層から金属酸化物半導体までの成膜は、CS-200にセットした4inchターゲットを用いて、n型Si基板を装着し真空にした後、基板を取り出すことなく一貫成膜した。
貴金属酸化物層としてPdOを40nm成膜した。成膜条件は、DC300W、O2雰囲気にて0.5Pa、270秒間とした。
続いて、貴金属層としてPdを50nm成膜した。成膜条件は、DC300W、Ar雰囲気にて0.5Pa、60秒間とした。
低抵抗卑金属層としてAlを1000nm成膜した。成膜条件は、DC300W、Ar雰囲気にて0.5Pa、6000秒間とした。
成膜後、この基板を取り出し、電気炉によって空気中300℃の条件で1時間アニールし、素子(構造物)を得た。
表14に示す条件とし、実施例48と同様にして素子を作製し、評価した。結果を表14に示す。
表中、オーミック電極層の電極構成について、「In/Mo」は、第1のオーミック電極層として、Moを、第2のオーミック電極層として、Inを積層成膜したことを示す。成膜条件は、In及びMoともDC100W、Ar雰囲気0.5Paとした。Inが上層となるようにし、金属酸化物半導体と接触するようにした。
ガラス基板上(4inch Eagle XG基板)にフォトマスクを用い素子を作製した。実施例1と各層の成膜条件は同一である。
まず、ガラス基板の一面に、低抵抗卑金属層としてMoを、貴金属層としてPdを、それぞれ150nm及び50nmスパッタリングした。次に、フォトマスク1を用い、Mo/Pdの積層膜をパターニングした。フォトレジストには、AZ1500(AZエレクトロニックマテリアルズ社製)を用い、フォトマスク1を介し露光後、テトラメチルアンモニウムヒドロキサイド(TMAH)にて現像を行い、AURUM-302(関東化学製)でPdを第一のパターニングし、Moが露出したところで、PAN(リン酸―酢酸-硝酸の混酸)エッチャントでMoを第二のパターニングをして、下層電極を形成した。
まず、熱硬化非感光性ポリイミド溶液をスピンコータで基板一面に8μm程度塗布し、続いてAZ5214及びフォトマスク3を用いパターニングした。AZ5214を、フォトマスク3を介して露光し、反転ベーク工程後に全面露光し、TMAHにて現像した。続いて、TMAHで熱硬化非感光性ポリイミドをエッチングし、パターニングした。パターニング後、熱硬化非感光性ポリイミドを200℃1時間、大気中で加熱し硬化した。
続いて、イメージリバーサルレジストAZ5214及びフォトマスク4を用い、オーミック電極層をリフトオフプロセスにてパターニングした。AZ5214を、フォトマスク4を介して露光し、反転ベーク工程後に全面露光し、TMAHにて現像した。パターニングされたレジスト付き基板に対し、第1のオーミック電極層としてMo150nmを、第2のオーミック電極層としてAu500nmを一貫して成膜した。その後、アセトン中でリフトオフすることにより、オーミック電極層をパターニングした。
図10A及びBに示す構造の素子を得た。評価は実施例1と同様に行った。結果を表15に示す。
実施例52で使用したフォトマスク1~4とは異なるパターンのフォトマスク5~8を使用した以外は、実施例52と同様に素子を作製し、図10C及びDに示す構造の素子を得た。評価は実施例1と同様に行った。結果を表15に示す。
実施例52で使用したフォトマスク1~4とは異なるパターンのフォトマスク9~12を使用した以外は、実施例52と同様に素子を作製し、図10E及びFに示す構造の素子を得た。評価は実施例1と同様に行った。結果を表15に示す。
本願のパリ優先の基礎となる日本出願明細書の内容を全てここに援用する。
Claims (32)
- 金属酸化物半導体層と、
貴金属酸化物層と、を含み、
前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、
前記貴金属酸化物層の膜厚が10nm超である構造物。 - 空乏領域を有する請求項1に記載の構造物。
- 前記貴金属酸化物層が多結晶構造を含む請求項1又は2に記載の構造物。
- 前記貴金属酸化物層と隣接して、前記金属酸化物半導体層と反対の側に、さらに、貴金属層を含む請求項1~3のいずれかに記載の構造物。
- 前記貴金属層と隣接して、前記貴金属酸化物層の反対の側に、さらに、低抵抗卑金属層を含む請求項4に記載の構造物。
- 前記貴金属酸化物層の貴金属酸化物が、酸化パラジウム、酸化ルテニウム、酸化白金、酸化イリジウム、酸化銀、酸化レニウム、酸化オスミウム、酸化ロジウム、酸化ニッケル及び酸化金からなる群から選択される1以上である請求項1~5のいずれかに記載の構造物。
- 前記貴金属酸化物層の貴金属酸化物が、PdO構造のPdO、ルチル構造のRuO2、α-PtO2構造のPtO2、ルチル構造のIrO2、Cu2O構造のAg2O、スクッテルダイト構造のReO3、ルチル構造のOsO2、コランダム構造のRh2O3、NiO構造のNiO、及びAu2O3構造のAu2O3からなる群から選択される1以上である請求項1~6のいずれかに記載の構造物。
- 前記貴金属酸化物層の貴金属酸化物の平均結晶粒径が、前記貴金属酸化物層の膜厚以下である請求項1~7のいずれかに記載の構造物。
- 前記貴金属酸化物層の界面粗さが5nm以下である請求項1~8のいずれかに記載の構造物。
- 前記金属酸化物半導体層と前記貴金属酸化物層とのショットキー界面の炭素濃度が2×1019cm-3以下である請求項1~9のいずれかに記載の構造物。
- 前記貴金属酸化物層の抵抗率が1×10-2Ω・cm以下である請求項1~10のいずれかに記載の構造物。
- 前記貴金属酸化物層の貴金属酸化物の仕事関数が4.8eV以上である請求項1~11のいずれかに記載の構造物。
- 前記金属酸化物半導体層が、アモルファス又は多結晶である請求項1~12のいずれかに記載の構造物。
- 前記金属酸化物半導体層の金属酸化物が、In、Sn、Cd、Zn、Ga及びGeからなる群から選択される1以上の金属元素の酸化物である請求項1~13のいずれかに記載の構造物。
- 前記金属酸化物半導体層におけるGa又はInの含有率が、前記金属酸化物半導体層の全金属元素に対し、45原子%以上である請求項1~14のいずれかに記載の構造物。
- 前記金属酸化物半導体層がランダム配向である請求項1~15のいずれかに記載の構造物。
- 前記貴金属酸化物層と、前記金属酸化物半導体層との、ショットキー障壁高さが0.7eV以上である請求項1~16のいずれかに記載の構造物。
- 前記貴金属酸化物層の、前記金属酸化物半導体層と反対の側に、さらに、基板を含む請求項1~17のいずれかに記載の構造物。
- さらに、オーミック電極層を有し、前記オーミック電極層と前記貴金属酸化物層が接触しない請求項1~18のいずれかに記載の構造物。
- 前記金属酸化物半導体層が、1層又は2層以上であり、2層以上の場合には、いずれか1層が貴金属酸化物層に隣接する請求項1~19のいずれかに記載の構造物。
- 逆方向電圧印加時の耐圧が0.5MV/cm以上である請求項1~20のいずれかに記載の構造物。
- 0.2MV/cmの逆バイアス印加時に電流密度が1×10-6A/cm2以下である請求項1~21のいずれかに記載の構造物。
- 順方向バイアス印加時のダイオード理想係数が1.5以下である請求項1~22のいずれかに記載の構造物。
- 順方向バイアスが5V以下で、電流密度が1000A/cm2に達する請求項1~23のいずれかに記載の構造物。
- 前記金属酸化物半導体層を、水素又は水を導入した雰囲気中で、スパッタリングによって成膜し、請求項1~24のいずれかに記載の構造物を得る、構造物の製造方法。
- 前記貴金属酸化物層を、導入ガス流量の50%以上が酸素である雰囲気で、スパッタリングによって成膜し、請求項1~24のいずれかに記載の構造物を得る、構造物の製造方法。
- 前記貴金属酸化物層及び前記金属酸化物半導体層を成膜した後、220~500℃でアニールを行う請求項25又は26に記載の構造物の製造方法。
- 前記貴金属酸化物層及び前記金属酸化物半導体層をスパッタリングによって連続で成膜するか、又は
前記貴金属酸化物層の成膜と、前記金属酸化物半導体層の成膜との間を、真空又は不活性の雰囲気とする請求項25~27のいずれか記載の構造物の製造方法。 - 請求項1~24のいずれかに記載の構造物を用いた半導体素子。
- パワー半導体素子、ダイオード素子、ショットキーバリアダイオード素子、静電気放電保護ダイオード、過渡電圧保護ダイオード、発光ダイオード、金属半導体電界効果トランジスタ、接合型電界効果トランジスタ、金属酸化膜半導体電界効果トランジスタ、ショットキーソース/ドレイン金属酸化膜半導体電界効果トランジスタ、アバランシェ増倍型光電変換素子、固体撮像素子、太陽電池素子、光センサ素子、タッチセンサ素子、表示素子、又は抵抗変化メモリである請求項29に記載の半導体素子。
- 請求項29又は30に記載の半導体素子を用いた電子回路。
- 請求項31に記載の電子回路を用いた電気機器、電子機器、車両、又は動力機関。
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CN201780062422.3A CN109863607A (zh) | 2016-10-11 | 2017-10-11 | 结构物、该结构物的制造方法、半导体元件以及电子电路 |
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WO2021066137A1 (ja) * | 2019-10-03 | 2021-04-08 | 株式会社Flosfia | 半導体素子および半導体装置 |
WO2022091693A1 (ja) * | 2020-10-26 | 2022-05-05 | 株式会社タムラ製作所 | 酸化ガリウムダイオード |
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KR102333036B1 (ko) * | 2017-08-31 | 2021-12-02 | 마이크론 테크놀로지, 인크 | 금속 산화물 반도체 디바이스의 접촉을 위한 반도체 디바이스, 트랜지스터, 및 관련된 방법 |
US11011614B2 (en) * | 2018-06-29 | 2021-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | High electron mobility transistor (HEMT) device and method of forming same |
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CN114514615A (zh) * | 2019-07-16 | 2022-05-17 | 株式会社Flosfia | 半导体装置和半导体系统 |
US20220316091A1 (en) * | 2019-08-27 | 2022-10-06 | Shin-Etsu Chemical Co., Ltd. | Laminated structure and method for manufacturing laminated structure |
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US20210143248A1 (en) * | 2019-11-13 | 2021-05-13 | Semiconductor Components Industries, Llc | Semiconductor structure having laminate dielectric films and method of manufacturing a semiconductor structure |
CN116682910B (zh) * | 2023-08-04 | 2023-11-28 | 湖北九峰山实验室 | 一种氮化镓外延片结构及其制备方法 |
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TW201820625A (zh) | 2018-06-01 |
TWI798187B (zh) | 2023-04-11 |
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