WO2018054111A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

Info

Publication number
WO2018054111A1
WO2018054111A1 PCT/CN2017/089717 CN2017089717W WO2018054111A1 WO 2018054111 A1 WO2018054111 A1 WO 2018054111A1 CN 2017089717 W CN2017089717 W CN 2017089717W WO 2018054111 A1 WO2018054111 A1 WO 2018054111A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
active layer
thin film
thickness
film transistor
Prior art date
Application number
PCT/CN2017/089717
Other languages
English (en)
French (fr)
Inventor
苏同上
成军
赵策
周斌
王东方
袁广才
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/580,240 priority Critical patent/US10559601B2/en
Priority to JP2018501215A priority patent/JP7036710B2/ja
Publication of WO2018054111A1 publication Critical patent/WO2018054111A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • a thin film transistor is a field effect transistor formed of a multilayer film such as an active semiconductor layer, a dielectric layer, and a metal electrode layer. Due to its advantages for integration and mass production, TFTs as display control units play an important role in the field of flat panel displays such as liquid crystal display (LCD), organic light emitting diode display (OLED), and electronic paper display (EPD). effect. Therefore, there is a need to continuously improve the display performance of a TFT-integrated display panel.
  • LCD liquid crystal display
  • OLED organic light emitting diode display
  • EPD electronic paper display
  • Embodiments of the present disclosure provide an array substrate and a method of fabricating the same, a display panel, and a display device capable of improving display performance.
  • an array substrate comprising a thin film transistor and having at least a first region and a second region.
  • An active layer thickness of the thin film transistor in the first region is greater than an active layer thickness of the thin film transistor in the second region, and a source electrode or a drain electrode and an active layer of the thin film transistor in the first region.
  • the overlap area between is larger than the overlap area between the source electrode or the drain electrode of the thin film transistor in the second region and the active layer, so that the overlapping area between the source electrode or the drain electrode of the thin film transistor and the active layer is The ratio of the thickness of the active layer remains uniform over the first and second regions.
  • the weight between the source electrode or the drain electrode of the thin film transistor and the active layer The ratio of the stacked area to the thickness of the active layer remains uniform over the first and second regions, so that the source and drain electrode currents of the thin film transistors in the first and second regions due to the difference in thickness of the active layer can be avoided.
  • the difference is that the control of the pixel unit of the array substrate is kept uniform on the first area and the second area, thereby improving the display effect.
  • the length of the overlapping portion between the source electrode or the drain electrode of the thin film transistor and the active layer is the width of the active layer channel region, and the width of the overlapping portion is a fixed value.
  • the ratio of the width of the active layer channel region of the thin film transistor to the thickness of the active layer remains uniform over the first and second regions.
  • a curve of an active layer thickness of each thin film transistor in at least one of the first region and the second region as a function of an active layer position is represented by a fitting function.
  • the area of overlap between the source or drain electrode of each thin film transistor in the at least one region and the active layer varies proportionally with respect to the fitting function.
  • a curve of an active layer thickness of each thin film transistor in at least one of the first region and the second region as a function of an active layer position is represented by a fitting function.
  • the width of the active layer channel region of each of the thin film transistors in the at least one region varies proportionally with respect to the fitting function.
  • the first area and the second area are periodically alternately arranged.
  • the thin film transistor includes a driving thin film transistor for applying a driving current to the organic light emitting diode, and a switching thin film transistor for applying a driving voltage to the driving thin film transistor.
  • the array substrate can be used for the OLED display panel, and since the driving current applied to the OLED can be kept uniform over the first region and the second region under the same driving condition, and is used for applying a driving voltage to the driving thin film transistor
  • the source-drain electrode current of the switching thin film transistor can be kept uniform in the first region and the second region under the same driving condition, so that the display effect of the OLED display panel can be improved.
  • the thin film transistor includes a switching thin film transistor for applying a data voltage to a liquid crystal layer.
  • the array substrate can be used for the LCD display panel, and the source-drain electrode current of the switching thin film transistor for applying the data voltage to the liquid crystal layer can be uniform in the first region and the second region under the same driving condition. Therefore, it is possible to improve the display effect of the LCD display panel.
  • a method of fabricating an array substrate includes obtaining a change in thickness of the active layer with respect to position on the substrate.
  • the active layer has at least a first region having a larger thickness and a second region having a smaller thickness.
  • the manufacturing method further includes: determining an overlapping area between a source electrode or a drain electrode of the thin film transistor to be formed and an active layer according to the variation, such that a ratio of the overlap area to an active layer thickness is The first area and the second area remain uniform.
  • the fabrication method further includes forming a thin film transistor on the base substrate such that the formed thin film transistor has a determined overlap area.
  • the ratio of the overlapping area between the source electrode or the drain electrode of the thin film transistor and the active layer to the thickness of the active layer remains uniform over the first region and the second region, it is possible to avoid the first region and the first region
  • the thin film transistor formed in the two regions causes a difference in source and drain electrode currents due to the difference in thickness of the active layer, so that the control of the pixel unit of the array substrate is kept uniform on the first region and the second region, thereby improving the display effect.
  • obtaining a change in thickness of the active layer on the substrate substrate includes: forming an active film on the same test substrate as the substrate substrate .
  • Obtaining the change further includes measuring an active film thickness in the first region and the second region.
  • determining the overlap area includes: determining active in at least one of the first region and the second region according to the measured active film thickness A fitting function of the curve of the layer thickness as a function of the position of the active layer. Determine the said The overlapping area further includes determining the overlap area in the at least one region such that the overlap area varies proportionally with respect to the fitting function.
  • the determined fitting function can be used to determine the thickness of the active layer at the unmeasured position, and further the overlap corresponding to each thickness is determined. Area, which increases efficiency.
  • determining the width of the active layer channel region to be formed includes: determining the first region and the second region according to the measured active film thickness A fitting function of a curve of the thickness of the active layer in at least one region as a function of the position of the active layer. Determining a width of the active layer channel region to be formed further includes: determining a width of the active layer channel region in the at least one region such that a width of the active layer channel region is related to the fitting function Change in proportion.
  • the determined fitting function can be used to determine the thickness of the active layer at the unmeasured position, and further determine that each thickness corresponds to The width of the source layer channel region, thereby increasing efficiency.
  • forming the thin film transistor on the base substrate includes forming a gate electrode on the base substrate. Forming the thin film transistor on the base substrate further includes forming a gate insulating layer on the gate electrode. Forming the thin film transistor on the base substrate further includes forming an active thin film on the gate insulating layer. Forming the thin film transistor on the base substrate further includes patterning the active film to form an active layer. Forming the thin film transistor on the base substrate further includes forming a source electrode and a drain electrode on the active layer.
  • the change is obtained and the overlap area is determined.
  • FIG. 1 is a schematic view of an active film formed on a substrate of an array substrate by using a prior art
  • FIG. 2 is a circuit schematic of an array substrate in which the principles of the present disclosure may be applied;
  • FIG. 3 is a schematic structural view of a thin film transistor in which the principles of the present disclosure may be applied;
  • FIG. 4 is a view showing a fitting function of a curve of a thickness of an active film formed on a base substrate of an array substrate as a function of position using a prior art
  • FIG. 5 is a flowchart of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • Fig. 6 is a flow chart for further explaining the manufacturing method of Fig. 5.
  • Embodiments of the present disclosure provide an array substrate and a method of fabricating the same, a display panel, and a display device capable of improving display performance.
  • the array substrate of the present disclosure a method of fabricating the same, a display panel, and a display device will be specifically described in the corresponding embodiments.
  • the magnetron sputtering device is a device that realizes high-rate sputtering film formation by using an orthogonal electromagnetic field formed on the surface of the target to bind electrons to a specific region of the target surface to improve ionization efficiency and increase plasma density and energy.
  • Magnetron sputtering equipment typically includes a planar target magnetron sputtering apparatus and a rotating target magnetron sputtering apparatus.
  • the deposited film may appear at different positions on the substrate. Thick difference. As shown in FIG. 1, a film of a thin film deposited on a substrate by using a conventional rotating target magnetron sputtering apparatus There are periodic differences in thickness. At a position where the target is facing, the film thickness is thick, as shown in the A region of FIG.
  • the film thickness is small
  • the width of the A and B regions is on the order of a few centimeters (e.g., about 8 cm).
  • TFT thin film transistor
  • Target Mura i.e., display unevenness
  • the array substrate includes a plurality of scan lines and a plurality of data lines defining a plurality of rectangular pixel units.
  • Each of the pixel units includes a switching TFT (ie, an S-TFT), a charge storage capacitor C, a driving TFT (ie, a D-TFT), and an OLED.
  • each data line In synchronization with the scanning of the scanning line, each data line records the data signal voltage through the turned-on switching TFT to the charge storage capacitor C, and the data signal voltage turns on the driving TFT to output a driving current, that is, a source-drain electrode current (wherein Vdd is the operating voltage of the driving TFT), so that the OLED emits light of corresponding color and intensity.
  • a driving current that is, a source-drain electrode current (wherein Vdd is the operating voltage of the driving TFT)
  • Vdd is the operating voltage of the driving TFT
  • the exemplary structure shown in FIG. 3 can be employed.
  • 3 is a schematic structural view of a staggered bottom-gate TFT.
  • the bottom gate overlap type TFT includes: a gate electrode 302 formed on a base substrate, which may be made of a material such as metal, indium tin oxide, or the gate insulating layer 304 formed on the gate electrode 302.
  • an insulating material for example, SiO 2 , Al 2 O 3 , an organic insulating material, etc.
  • an active layer 306 formed on the gate insulating layer 304 which may be composed of inorganic and organic semiconductor materials (for example, IGZO, InSb) , a polythiophene or the like); and a source electrode 308 and a drain electrode 310 formed on the active layer 306, which may be made of a material such as metal, indium tin oxide or the like.
  • the source and drain electrode currents of the driving TFTs formed in the A region and the B region ie, the driving current
  • the size of the overlapping portion between the layers 306 (i.e., the width of the active layer channel region), d is the width of the overlapping portion, that is, in the direction parallel to the cross section of the TFT, the source electrode 308 or the drain electrode 310 has The size of the overlapping portion between the source layers 306, L shown in the drawing is the distance between the source electrode 308 and the drain electrode 310 in the direction perpendicular to the cross section of the TFT (ie, the length of the active layer channel region) ).
  • the current I DS flowing between the source and drain electrodes of the TFT can be expressed as follows:
  • U DS is the voltage difference between the source and drain electrodes of the TFT. Therefore, in the case where the voltage difference U DS is constant, the overlapping area S between the I DS and the source electrode 308 or the drain electrode 310 and the active layer 306 is proportional to the thickness t of the active film. Further, since the width d of the overlapping portion is not excessively large (causing the size of the TFT to be increased) or too small (causing the on-state current of the TFT to decrease), d is usually fixed to a preferable value. Therefore, in one embodiment of the present disclosure, the width d of the overlapping portion may be a fixed value, and in this case, I DS is proportional to the width W of the active layer channel region, and the thickness of the active film t In inverse proportion.
  • the source electrode 308 or the drain electrode 310 of the A region and the active layer are The overlap area S A between 306 is set to be larger than the overlap area S B between the source electrode 308 or the drain electrode 310 of the B region and the active layer 306 such that the source electrode 308 or the drain electrode 310 and the active layer 306 are
  • the ratio S/t of the overlap area S to the thickness t of the active film remains uniform over the A area and the B area.
  • the source-drain electrode current I DS of the TFTs in the A region and the B region remain uniform, so that the color and intensity of light emitted by the OLEDs in the A region and the B region remain uniform, thereby eliminating Target Mura. phenomenon.
  • the width d of the overlapping portion mentioned above is a fixed value
  • the ratio W/t of the width W of the active layer channel region to the thickness t of the active film is maintained in the A region and the B region. Uniform.
  • the thickness of the active film formed on the substrate of the array substrate is stable with different process conditions depending on the substrate.
  • the situation remains substantially unchanged, and the thickness of the active film can be obtained as a function of position on the substrate (for example, an active film is formed on the same test substrate as the substrate), and the thickness of the active film is measured.
  • the overlapping area S of the corresponding active layer or the width W of the channel region is determined according to the measured film thickness t, and then the corresponding mask is designed to realize the determined overlapping area S or channel. Zone width W.
  • the present disclosure is not limited to the above examples.
  • the active layer 306 is formed first, and the source electrode 308 and the drain electrode 310 are formed.
  • the thicknesses of the active layers 306 in the A region and the B region may be measured, and the corresponding active layers may be determined according to the measured thicknesses t.
  • Overlap area S or channel region width W such that the S/t or W/t of the active layer is in the A region and B The area remains uniform. Then, the source electrode 308 and the drain electrode 310 may be formed such that the formed active layer has the determined overlap area S or channel region width W. As can be seen from the top view corresponding to the cross-sectional view in FIG. 3, the overlap area S of the active layer or the width W of the channel region can be adjusted by the pattern of the source electrode 308 and the drain electrode 310. Therefore, the determined overlap area S or channel region width W can be achieved by, for example, designing and preparing a mask for forming the source electrode 308 and/or the drain electrode 310.
  • the width of the A region and the B region is on the order of several centimeters, and the size of the TFT is about 5-30 micrometers, so if the A region where the film thickness varies with the position of the curve, if the A region is to be measured In the thickness of the corresponding position of each TFT in the middle, it is necessary to measure the thickness at a very large number of positions.
  • the curve of the film thickness of the A region shown in FIG. 1 is approximately an axisymmetric curve, and may be at a relatively large interval in the half cycle of the A region (for example, every 300-500).
  • Micrometer measures the thickness of one time and determines the fitted function of the curve of film thickness as a function of position based on the measured thickness value.
  • the film thickness at any point on the A region can be determined by substituting the coordinates of the point into the fit function.
  • T A is a period of the A region
  • T B is the period of the B region
  • the x coordinate represents the coordinates in the width direction of the A region and the B region.
  • f(x) a 0 +a 1 (T A +x 0 -x)+a 2 (T A +x 0 -x) 2 +a 3 (T A +x 0 -x) 3 .
  • (W 0 /a 0 ) is the value of W/t of the active layer channel region on the B region.
  • x located in other period ranges it can be deduced by analogy. It should be noted that the coordinate x has a certain range of variation in the space occupied by one TFT. For example, for a 10 micron TFT, the thickness at 5 micrometers may be taken as the thickness of the entire TFT, and the average value of the thickness in the range of 0-10 micrometers may be taken as the thickness of the entire TFT.
  • the thickness of the active film on the B region changes little with position, so there is no need to perform a function fitting on the film thickness variation of the B region with respect to the position.
  • the film thickness of the active film formed by other processes is large, the film thickness of at least one of the region where the film thickness is large and the region where the film thickness is small varies greatly with position (for example, changes with a predetermined position). If the amount of change in film thickness corresponding to the amount is greater than a predetermined threshold), a function fit can be performed on the at least one region.
  • the present disclosure is not limited to the examples described above.
  • the process of causing the film thickness of the active film to differ at different positions is not limited to magnetron sputtering, and may be other sputtering (for example, general sputtering without using magnetron), or other film forming processes. (for example, evaporation).
  • the array substrate in which the principles of the present disclosure can be applied is not limited to the OLED array substrate.
  • the array substrate may also be an array substrate for an LCD display panel. Similar to the OLED array substrate described above, the LCD array substrate may include a plurality of scan lines and a plurality of data lines defining a plurality of rectangular pixel units.
  • Each of the pixel units includes a switching TFT, a holding capacitor C, and a liquid crystal layer.
  • each of the scanning lines is sequentially driven with a signal having, for example, a high level VGH, so that all of the switching TFTs connected to the scanning line are turned on.
  • each of the data lines records the data signal voltage to the holding capacitor through the turned-on switching TFT.
  • the switching TFT is turned off, the recorded data signal voltage is held and the liquid crystal layer is continuously driven until the next frame scan arrives.
  • the array substrate may also be an array substrate for electrowetting the display panel.
  • the OLED array substrate is not limited to the configuration of 2T1C (two TFTs, one capacitor), and may be a configuration of 3T1C (three TFTs, one capacitor) or various other existing configurations including TFTs.
  • the TFTs provided on the array substrate are not limited to the driving TFTs and the switching TFTs for controlling the pixel units, and may be, for example, TFTs in a driving module for controlling scanning lines and/or data lines.
  • the principles of the present disclosure can be applied to any type of array substrate provided with TFTs, as long as the thickness of the active thin film formed at the time of fabricating the TFT is different at different positions and the TFT A U-type current loop may be present in the active layer in the on state.
  • the TFT whose channel region width W is adjusted with the film thickness t may be a TFT on the array substrate that performs any of the functions or a combination thereof.
  • At least one embodiment of the present disclosure provides an array substrate including a thin film transistor and having at least a first region and a second region.
  • An active layer thickness of the thin film transistor in the first region is greater than an active layer thickness of the thin film transistor in the second region, and a source electrode or a drain electrode and an active layer of the thin film transistor in the first region
  • the overlap area between is larger than the overlap area between the source electrode or the drain electrode of the thin film transistor in the second region and the active layer, so that the overlapping area between the source electrode or the drain electrode of the thin film transistor and the active layer is The ratio of the thickness of the active layer remains uniform over the first and second regions.
  • a display panel includes the array base described above in Part I board. Accordingly, a display device (eg, an OLED display device, an LCD display device, etc.) according to an embodiment of the present disclosure also includes the array substrate described above in Section 1. Since the array substrate described above in the first section is employed, the display effects of the display panel and the display device can be improved, and will not be described herein.
  • a display device eg, an OLED display device, an LCD display device, etc.
  • the array substrate described above in Section 1 Since the array substrate described above in the first section is employed, the display effects of the display panel and the display device can be improved, and will not be described herein.
  • FIG. 5 is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 5, the method of fabricating the array substrate includes steps 502, 504, and 506.
  • a change in the thickness of the active layer with respect to position on the substrate is obtained.
  • the active layer has at least a first region having a larger thickness and a second region having a smaller thickness.
  • this step 502 can include the following two sub-steps.
  • an active film is formed on the same test substrate as the substrate.
  • the active film can be formed directly on the test substrate, or can be performed from the first step of the process of normally fabricating the TFT to the formation of the active film.
  • the thickness of the active film in the first and second regions is measured. This step can be accomplished using any of the existing techniques for measuring film thickness.
  • the overlapping area between the source electrode or the drain electrode of the thin film transistor to be formed and the active layer is determined such that the ratio of the overlap area to the thickness of the active layer is in the first region. It is uniform with the second area.
  • the width d of the overlapping portion is a fixed value.
  • the width of the active layer channel region to be formed is determined such that the ratio of the width of the active layer channel region to the thickness of the active layer is on the first region and the second region. Keep it even.
  • the thickness of the corresponding position of each of the TFTs in the first and second regions can be measured, which requires measurement of the thickness at a very large number of positions.
  • the thickness can also be measured every relatively large interval (for example, every 300-500 micrometers), and the fitting function of the curve of the film thickness as a function of position can be determined from the measured thickness value. Details regarding the fitting function and details of determining the overlapping area or the width of the channel region of the active layer using the fitting function have been described in detail in Section I, and will not be described herein.
  • a thin film transistor is formed on the base substrate such that the formed thin film transistor has a determined overlap area.
  • the width d of the overlapping portion is a fixed value
  • a thin film transistor is formed on a base substrate such that the formed active layer channel region has a determined width.
  • the determined overlap area S or channel region width W can be achieved by designing and fabricating one or more masks for forming a thin film transistor.
  • the implementation of the thin film transistor can be as shown in FIG. 6, which corresponds to the bottom gate overlap type TFT shown in FIG.
  • forming the thin film transistor includes steps 602-610.
  • a gate electrode is formed on the base substrate. This can be achieved using deposition and photolithography processes.
  • the substrate may be deposited on a substrate by sequentially performing a deposition of a gate electrode material layer, applying a photoresist, exposing with a mask, developing with a developer, etching with an etching solution, and stripping the photoresist.
  • a gate electrode is formed.
  • a gate insulating layer is formed on the gate electrode.
  • an active film is formed over the gate insulating layer. This can be achieved by processes such as sputtering or evaporation.
  • the active film is patterned to form an active layer. This can be achieved using a photolithography process.
  • a source electrode and a drain electrode are formed on the active layer. This can be achieved using deposition and photolithography processes.
  • steps 502 and 504 can also be performed during execution of step 506.
  • an active layer is formed first, and a source electrode and a drain electrode are formed.
  • steps 502 and 504 can be performed after forming the active film or active layer (ie, after step 606 or 608 of FIG. 6).
  • the source and drain electrodes may be formed in step 610 to achieve the determined overlap area or channel region width.
  • the determined overlap area or channel region width can be achieved, for example, by designing and fabricating a mask for forming the source and/or drain electrodes.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: obtaining a change in thickness of an active layer along a position on a substrate.
  • the active layer has at least a first region having a larger thickness and a second region having a smaller thickness.
  • the manufacturing method further includes: determining an overlapping area between a source electrode or a drain electrode of the thin film transistor to be formed and an active layer according to the variation, such that a ratio of the overlap area to an active layer thickness is The first area and the second area remain uniform.
  • the manufacturing method further includes: forming on a substrate The thin film transistor is formed such that the formed thin film transistor has a determined overlap area.
  • the ratio of the overlapping area between the source electrode or the drain electrode of the thin film transistor and the active layer to the thickness of the active layer remains uniform over the first region and the second region, the first region and the second region can be avoided.
  • the thin film transistor formed in the film causes a difference in source and drain electrode currents due to the difference in thickness of the active layer, so that the control of the pixel unit of the array substrate is kept uniform on the first region and the second region, thereby improving the display effect.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

公开了一种阵列基板及其制作方法。阵列基板包括薄膜晶体管，且至少具有第一区域和第二区域。第一区域中的薄膜晶体管的有源层厚度大于第二区域中的薄膜晶体管的有源层厚度，且第一区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积大于第二区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在第一区域和第二区域上保持均一。

Description

阵列基板及其制作方法
本申请要求于2016年9月26日递交的中国专利申请第201610849162.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，特别涉及一种阵列基板及其制作方法。
背景技术
薄膜晶体管(TFT)是一种由多层薄膜(例如有源半导体层、介电层和金属电极层)形成的场效应晶体管。由于具有适于集成和大规模生产等优点，TFT作为显示控制单元在平板显示领域诸如液晶显示(LCD)、有机发光二极管显示(OLED)、电子纸显示(EPD)等领域中起着非常重要的作用。因此，存在着不断提高集成有TFT的显示面板的显示性能的需求。
发明内容
本公开的实施例提供了一种阵列基板及其制作方法、显示面板和显示装置，其能够使显示性能得到改善。
根据本公开的第一方面，提供了一种阵列基板，包括薄膜晶体管，且至少具有第一区域和第二区域。所述第一区域中的薄膜晶体管的有源层厚度大于所述第二区域中的薄膜晶体管的有源层厚度，且所述第一区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积大于所述第二区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一。
根据上述配置，由于薄膜晶体管的源电极或漏电极与有源层之间的重 叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一，所以能够避免第一区域和第二区域中的薄膜晶体管由于有源层厚度的差异而导致源漏电极电流的差异，使阵列基板对像素单元的控制在第一区域和第二区域上保持均一，从而改善显示效果。
在本公开的一个实施例中，薄膜晶体管的源电极或漏电极与有源层之间的重叠部分的长度为有源层沟道区的宽度，且所述重叠部分的宽度为固定值。薄膜晶体管的有源层沟道区的宽度与有源层厚度的比率在所述第一区域和第二区域上保持均一。
在本公开的一个实施例中，所述第一区域和第二区域中的至少一个区域中的各薄膜晶体管的有源层厚度随有源层位置变化的曲线由拟合函数表示。所述至少一个区域中的各薄膜晶体管的源电极或漏电极与有源层之间的重叠面积关于所述拟合函数成比例地变化。
在本公开的一个实施例中，所述第一区域和第二区域中的至少一个区域中的各薄膜晶体管的有源层厚度随有源层位置变化的曲线由拟合函数表示。所述至少一个区域中的各薄膜晶体管的有源层沟道区的宽度关于所述拟合函数成比例地变化。
在本公开的一个实施例中，所述第一区域和第二区域周期性地交替排列。
在本公开的一个实施例中，所述薄膜晶体管包括用于向有机发光二极管施加驱动电流的驱动薄膜晶体管，以及用于向所述驱动薄膜晶体管施加驱动电压的开关薄膜晶体管。
根据上述配置，阵列基板可以用于OLED显示面板，而且由于向OLED施加的驱动电流在相同的驱动条件下能够在第一区域和第二区域上保持均一、并且用于向驱动薄膜晶体管施加驱动电压的开关薄膜晶体管的源漏电极电流在相同的驱动条件下能够在第一区域和第二区域上也保持均一，所以能够改善OLED显示面板的显示效果。
在本公开的一个实施例中，所述薄膜晶体管包括用于向液晶层施加数据电压的开关薄膜晶体管。
根据上述配置，阵列基板可以用于LCD显示面板，且由于用于向液晶层施加数据电压的开关薄膜晶体管的源漏电极电流在相同的驱动条件下能够在第一区域和第二区域上保持均一，所以能够改善LCD显示面板的显示效果。
根据本公开的第二方面，提供了一种阵列基板的制作方法。该制作方法包括：获得有源层的厚度在衬底基板上随位置的变化情况。所述有源层至少具有厚度较大的第一区域和厚度较小的第二区域。所述制作方法还包括：根据所述变化情况，确定要形成的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得所述重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一。所述制作方法还包括：在所述衬底基板上形成薄膜晶体管，使得所形成的薄膜晶体管具有所确定的重叠面积。
根据上述配置，由于薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在第一区域和第二区域上保持均一，所以能够避免在第一区域和第二区域中形成的薄膜晶体管由于有源层厚度的差异而导致源漏电极电流的差异，使阵列基板对像素单元的控制在第一区域和第二区域上保持均一，从而改善显示效果。
在本公开的一个实施例中，薄膜晶体管的源电极或漏电极与有源层之间的重叠部分的长度为有源层沟道区的宽度，且所述重叠部分的宽度为固定值。确定所述重叠面积包括：确定要形成的有源层沟道区的宽度，使得有源层沟道区的宽度与有源层厚度的比率在所述第一区域和第二区域上保持均一。
在本公开的一个实施例中，在上述制作方法中，获得有源层的厚度在衬底基板上随位置的变化情况包括：在与所述衬底基板相同的测试用基板上形成有源薄膜。获得所述变化情况还包括：测量所述第一区域和第二区域中的有源薄膜厚度。
在本公开的一个实施例中，在上述制作方法中，确定所述重叠面积包括：根据测得的有源薄膜厚度，确定所述第一区域和第二区域中的至少一个区域中的有源层厚度随有源层位置变化的曲线的拟合函数。确定所述 重叠面积还包括：确定所述至少一个区域中的所述重叠面积，使所述重叠面积关于所述拟合函数成比例地变化。
根据上述配置，仅测量有源层在较少数量的位置处的厚度，就可以利用所确定的拟合函数确定有源层在未测量的位置处的厚度，并进而确定各厚度所对应的重叠面积，从而提高效率。
在本公开的一个实施例中，在上述制作方法中，确定要形成的有源层沟道区的宽度包括：根据测得的有源薄膜厚度，确定所述第一区域和第二区域中的至少一个区域中的有源层厚度随有源层位置变化的曲线的拟合函数。确定要形成的有源层沟道区的宽度还包括：确定所述至少一个区域中的有源层沟道区的宽度，使所述有源层沟道区的宽度关于所述拟合函数成比例地变化。
根据上述配置，仅测量有源层在较少数量的位置处的厚度，就可以利用所确定的拟合函数确定有源层在未测量的位置处的厚度，并进而确定各厚度所对应的有源层沟道区的宽度，从而提高效率。
在本公开的一个实施例中，在衬底基板上形成薄膜晶体管包括：在所述衬底基板上形成栅电极。在衬底基板上形成薄膜晶体管还包括：在所述栅电极上形成栅绝缘层。在衬底基板上形成薄膜晶体管还包括：在所述栅绝缘层上形成有源薄膜。在衬底基板上形成薄膜晶体管还包括：对所述有源薄膜进行构图以形成有源层。在衬底基板上形成薄膜晶体管还包括：在所述有源层上形成源电极和漏电极。
在本公开的一个实施例中，在形成有源薄膜或有源层之后，获得所述变化情况并确定所述重叠面积。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图作简单地介绍。明显地，以下附图中的结构示意图不一定按比例绘制，而是以简化形式呈现各特征。而且，下面描述中的附图仅仅涉及本公开的一些实施例，而并非对本公开进行限制。
图1是利用现有技术在阵列基板的衬底基板上形成的有源薄膜的示意图；
图2是可以在其中应用本公开的原理的阵列基板的电路示意图；
图3是可以在其中应用本公开的原理的薄膜晶体管的结构示意图；
图4示出利用现有技术在阵列基板的衬底基板上形成的有源薄膜的厚度随位置变化的曲线的拟合函数；
图5是根据本公开的实施例的阵列基板的制作方法的流程图；以及
图6是用于进一步说明图5的制作方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
本公开的实施例提供了一种阵列基板及其制作方法、显示面板和显示装置，其能够使显示性能得到改善。在下文中，将以相应的实施例对本公开的阵列基板及其制作方法、显示面板和显示装置进行具体说明。
I.阵列基板
图1是利用现有的旋转靶磁控溅射设备在阵列基板的衬底基板上形成的有源薄膜的示意图。磁控溅射设备是利用在靶表面上形成的正交电磁场，把电子束缚在靶表面特定区域来提高电离效率，增加等离子体的密度和能量，从而实现高速率溅射成膜的设备。磁控溅射设备通常包括平面靶磁控溅射设备和旋转靶磁控溅射设备。不论是哪一种类型的磁控溅射设备，由于靶材之间存在间隙、并且磁控溅射设备上的磁场分布不均匀，导致所沉积的薄膜在衬底基板上的不同位置会出现膜厚的差异。如图1所示，利用现有的旋转靶磁控溅射设备在衬底基板上沉积的薄膜的膜 厚存在着周期性差异。在靶材正对的位置，薄膜厚度较厚，如图1中的A区域(对应于权利要求中的“第一区域”)所示；而在靶材之间的位置，薄膜厚度较小，如图1中的B区域(对应于权利要求中的“第二区域”)所示，其中A区域和B区域的宽度为数厘米的量级(例如约为8厘米)。这种薄膜周期性的厚度变化，会导致在衬底基板的A区域和B区域上形成的薄膜晶体管(TFT)的工作性能存在差异，最终导致所谓的Target Mura(即，显示不均匀)现象。下面以有机发光二极管(OLED)阵列基板为例说明由于A区域和B区域的膜厚差异所导致的问题。
图2是可以在其中应用本公开的原理的OLED阵列基板的电路示意图。如图2所示，该阵列基板包括多条扫描线和多条数据线，其限定出多个矩形像素单元。每个像素单元包括开关TFT(即S-TFT)、电荷存储电容C、驱动TFT(即D-TFT)以及OLED。在配备有该阵列基板的显示面板正常工作时，以具有例如高电平VGH的信号顺次驱动每条扫描线，使该条扫描线上连接的所有开关TFT导通。与扫描线的扫描同步，各条数据线将数据信号电压通过导通的开关TFT记录到电荷存储电容C上，同时该数据信号电压使驱动TFT导通从而输出驱动电流即源漏电极电流(其中Vdd为驱动TFT的工作电压)，使OLED发出相应颜色和强度的光。当该条扫描线的扫描结束时，开关TFT被关断，所记录的数据信号电压被保持并持续使驱动TFT输出相应的驱动电流，使OLED持续发出相应颜色和强度的光，直到下一帧扫描到来之前。
关于开关TFT和驱动TFT，其可以采用图3所示的示例性结构。图3是底栅交叠型TFT(staggered bottom-gate TFT)的结构示意图。如图3所示，底栅交叠型TFT包括：形成在衬底基板上的栅电极302，其可以由例如金属、氧化铟锡等材料制成；形成在栅电极302上的栅绝缘层304，其可以由绝缘材料(例如SiO2、Al2O3、有机绝缘材料等)制成；形成在栅绝缘层304上的有源层306，其可以由无机和有机半导体材料(例如IGZO、InSb、聚噻吩等)制成；以及形成在有源层306上的源电极308和漏电极310，其可以由例如金属、氧化铟锡等材料制成。
如前面关于图1所述，利用现有的旋转靶磁控溅射设备在衬底基板上沉积的薄膜的膜厚存在着周期性差异。在图2所示的OLED阵列基板的情况下，由于A区域和B区域的宽度为数厘米的量级、而像素单元的宽度为数十微米的量级(例如约为50微米)，因此A区域和B区域均包含多个像素单元，图2中仅示意性地示出一个像素单元。此外，由于A区域中的有源薄膜的膜厚较大、B区域中的有源薄膜的膜厚较小，所以在A区域和B区域中形成的驱动TFT的源漏电极电流(即驱动电流)存在差异，导致在相同的驱动电压下，A区域和B区域中的OLED发出的光的颜色和强度存在差异，从而引起Target Mura现象。
为了消除该Target Mura现象，本公开的发明人认识到，当TFT处于工作状态的时候，如图3所示，其电流在有源层中的流向是一个U型的回路，该回路上的电阻R＝2R1+R2，其中R1是源/漏电极下方垂直方向的电阻，R2是沟道区水平方向的电阻。由于导电沟道区的电阻R2<<R1，因此回路电阻近似表示为R＝2R1。根据电阻的计算公式，有源层的回路电阻可表示为：R＝2R1＝2ρt/(Wd)＝2ρt/S，其中ρ为有源薄膜的电阻率，t为有源层的厚度，S＝Wd是源电极308或漏电极310与有源层306之间的重叠面积，W是该重叠部分的长度，即在与TFT的横截面垂直的方向上，源电极308或漏电极310与有源层306之间的重叠部分的尺寸(即有源层沟道区的宽度)，d是该重叠部分的宽度，即在与TFT的横截面平行的方向上，源电极308或漏电极310与有源层306之间的重叠部分的尺寸，图中所示的L为在与TFT的横截面垂直的方向上，源电极308和漏电极310之间的距离(即有源层沟道区的长度)。
根据电流I与电压U间的关系的公式I＝U/R，流过TFT的源漏电极之间的电流IDS可以表示如下：
IDS＝UDS/R＝UDSS/(2ρt)＝UDSWd/(2ρt)，
其中UDS为TFT的源漏电极之间的电压差。因此，在电压差UDS一定的情况下，IDS和源电极308或漏电极310与有源层306之间的重叠面积S成正比，和有源薄膜的厚度t成反比。另外，由于重叠部分的宽度d不宜 过大(导致TFT的尺寸增大)或过小(导致TFT的开态电流降低)，所以d通常固定为一个较佳的值。因此，在本公开的一个实施例中，重叠部分的宽度d可以是固定值，且在这种情况下，IDS和有源层沟道区的宽度W成正比，和有源薄膜的厚度t成反比。
因此，根据本公开的实施例，由于A区域的有源薄膜的膜厚tA大于B区域的有源薄膜的膜厚tB，所以将A区域的源电极308或漏电极310与有源层306之间的重叠面积SA设置为大于B区域的源电极308或漏电极310与有源层306之间的重叠面积SB，使得源电极308或漏电极310与有源层306之间的重叠面积S与有源薄膜的厚度t的比率S/t在A区域和B区域上保持均一。这样，在相同的驱动电压下，A区域和B区域中的TFT的源漏电极电流IDS保持均一，使得A区域和B区域中的OLED发出的光的颜色和强度保持均一，从而消除Target Mura现象。相应地，在上面提到的重叠部分的宽度d为固定值的实施例中，有源层沟道区的宽度W与有源薄膜的厚度t的比率W/t在A区域和B区域上保持均一。
为了实现有源层的S/t或W/t在A区域和B区域上保持均一，考虑到在工艺条件稳定的情况下在阵列基板的衬底基板上形成的有源薄膜的厚度随不同基板的情况基本保持不变，可以先获得有源薄膜的厚度在衬底基板上随位置的变化情况(例如在与衬底基板相同的测试用基板上形成有源薄膜，并测量有源薄膜的厚度随位置的变化情况)，根据测得的各膜厚t确定其相应的有源层的重叠面积S或沟道区宽度W，然后设计相应的掩膜来实现所确定的重叠面积S或沟道区宽度W。
然而，本公开并不限于上述示例。作为另一示例，也可以在形成TFT的过程中获得有源薄膜的厚度在衬底基板上随位置的变化情况，并根据测得的各膜厚确定其相应的有源层的重叠面积S或沟道区宽度W。如前所述，在图3中，先形成有源层306，再形成源电极308和漏电极310。在这种情况下，可以在形成有源薄膜或有源层306之后，测量A区域和B区域中的各有源层306的厚度，并根据测得的各厚度t确定其对应的有源层的重叠面积S或沟道区宽度W，使得有源层的S/t或W/t在A区域和B 区域上保持均一。然后，可以形成源电极308和漏电极310，使所形成的有源层具有所确定的重叠面积S或沟道区宽度W。从图3中与截面图对应的俯视图可以看出，有源层的重叠面积S或沟道区宽度W可以通过源电极308和漏电极310的图形进行调节。因此，可以通过例如设计和制备用于形成源电极308和/或漏电极310的掩膜，来实现所确定的重叠面积S或沟道区宽度W。
如前所述，A区域和B区域的宽度在数厘米的量级、而TFT的尺寸约为5-30微米，因此对于膜厚随位置以曲线变化的A区域而言，如果要测量A区域中的各TFT对应位置的厚度，则需要测量非常大量的位置处的厚度。为了提高效率，考虑到图1所示的A区域的膜厚随位置变化的曲线近似呈轴对称曲线，可以在A区域的半个周期上，每隔相对较大的间隔(例如每300-500微米)测量一次厚度，并根据测得的厚度值来确定膜厚随位置变化的曲线的拟合函数。这样，A区域上任意一点的膜厚就可以通过将该点的坐标代入该拟合函数来确定。
图4示出利用现有的旋转靶磁控溅射设备在阵列基板的衬底基板上形成的有源薄膜的厚度随位置变化的曲线的拟合函数，其中TA为A区域的周期，TB为B区域的周期，且x坐标表示A区域和B区域的宽度方向上的坐标。假设通过拟合算法利用A区域的半个周期[x0,x1]上的多个点的坐标和测得的膜厚所确定的拟合函数的表达式为：
f(x)＝a0+a1(x-x0)+a2(x-x0)2+a3(x-x0)3,
其中a0、a1、a2和a3为利用拟合算法得到的系数。那么，A区域的另半个周期[x1,x2]上的拟合函数的表达式可以表示为：
f(x)＝a0+a1(TA+x0-x)+a2(TA+x0-x)2+a3(TA+x0-x)3。
由于有源层的S/t或W/t比率在A区域和B区域上保持均一，所以在由A区域和B区域组成的一个周期[x0,x3]上，有源层的重叠面积S随位置变化的曲线的表达式g(x)可以表示为：
Figure PCTCN2017089717-appb-000001
其中(S0/a0)为B区域上的有源层的S/t的比值。相应地，有源层沟道区的宽度W随位置变化的曲线的表达式h(x)可以表示为：
Figure PCTCN2017089717-appb-000002
其中(W0/a0)为B区域上的有源层沟道区的W/t的值。关于位于其它周期范围的x，可以以此类推。应注意的是，在一个TFT所占的空间范围内，坐标x有一定的变化范围。例如，对于10微米的TFT，可以取5微米处的厚度作为整个TFT的厚度，也可以取0-10微米范围的厚度的平均值作为整个TFT的厚度。此外，在本示例的旋转靶磁控溅射设备的情况下，B区域上的有源薄膜的厚度随位置变化很小，所以无需对B区域的膜厚随位置的变化情况进行函数拟合。然而，如果例如采用其他工艺所形成的有源薄膜的膜厚在膜厚较大的区域和膜厚较小的区域中的至少一个区域的膜厚随位置变化较大(例如，与预定位置变化量对应的膜厚变化量大于预定阈值)，则可以对该至少一个区域进行函数拟合。
应注意的是，本公开并不限于上面描述的示例。首先，引起有源薄膜的膜厚在不同位置出现差异的工艺并不限于磁控溅射，也可以是其它溅射(例如未使用磁控的一般溅射)，或者也可以是其他成膜工艺(例如，蒸镀)。其次，可以在其中应用本公开的原理的阵列基板并不限于OLED阵列基板。作为另一示例，阵列基板也可以是用于LCD显示面板的阵列基板。与上述OLED阵列基板类似，该LCD阵列基板可以包括多条扫描线和多条数据线，其限定出多个矩形像素单元。每个像素单元包括开关TFT、保持电容C以及液晶层。在配备有该LCD阵列基板的显示面板正常工作时，以具有例如高电平VGH的信号顺次驱动每条扫描线，使该条扫描线上连接的所有开关TFT导通。与扫描线的扫描同步，各条数据线将数据信号电压通过导通的开关TFT记录到保持电容上。当该条扫描线 的扫描结束时，开关TFT被关断，所记录的数据信号电压被保持并持续驱动液晶层，直到下一帧扫描到来之前。通过将本公开的实施例应用于该LCD阵列基板，由于在具有不同膜厚的区域中形成的开关TFT的源漏电极电流在相同的驱动条件下能够保持均一，所以通过源漏电极电流记录到保持电容上的数据信号电压也保持均一，从而改善LCD显示面板的显示效果。作为再一示例，阵列基板也可以是用于电润湿显示面板的阵列基板。
此外，OLED阵列基板并不限于2T1C(两个TFT、一个电容)的配置，也可以是3T1C(三个TFT、一个电容)的配置或者包含TFT的各种其它现有配置。而且，在上述OLED阵列基板的实施例中，可以仅调节驱动TFT的沟道区宽度W，也可以既调节驱动TFT又调节开关TFT的沟道区宽度W，从而进一步改善显示效果。此外，阵列基板上设置的TFT并不限于用于控制像素单元的驱动TFT和开关TFT，也可以是例如用于控制扫描线和/或数据线的驱动模块中的TFT。综上，本领域技术人员能够理解的是，本公开的原理可以应用于任何类型的设有TFT的阵列基板，只要在制作TFT时所形成的有源薄膜的厚度在不同位置存在差异且该TFT在导通状态下在有源层中存在U型电流回路即可。而且，沟道区宽度W随膜厚t而被调节的TFT可以是阵列基板上的执行任何一种功能的TFT或其组合。
也就是说，本公开的至少一个实施例提供了一种阵列基板，包括薄膜晶体管，且至少具有第一区域和第二区域。所述第一区域中的薄膜晶体管的有源层厚度大于所述第二区域中的薄膜晶体管的有源层厚度，且所述第一区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积大于所述第二区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一。
II.显示面板和显示装置
根据本公开的实施例的显示面板包括上面在第I部分中描述的阵列基 板。相应地，根据本公开的实施例的显示装置(例如OLED显示装置、LCD显示装置等)也包括上面在第I部分中描述的阵列基板。由于采用了上面在第I部分中描述的阵列基板，所以可以改善该显示面板和显示装置的显示效果，在此不再赘述。
III.阵列基板的制作方法
图5是根据本公开的实施例的阵列基板的制作方法的流程图。如图5所示，阵列基板的制作方法包括步骤502、504和506。
在步骤502，获得有源层的厚度在衬底基板上随位置的变化情况。所述有源层至少具有厚度较大的第一区域和厚度较小的第二区域。例如，如前所述，该步骤502可以包括以下两个子步骤。在第一子步骤，在与衬底基板相同的测试用基板上形成有源薄膜。可以直接在测试用基板上形成有源薄膜，也可以从正常制作TFT的过程的第一步骤开始执行到有源薄膜的形成完毕。在第二子步骤，测量所述第一区域和第二区域中的有源薄膜厚度。该步骤可以利用任何现有的测量膜厚的技术来实现。
接着，在步骤504，根据所述变化情况，确定要形成的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得所述重叠面积与有源层厚度的比率在第一区域和第二区域上保持均一。如前所述，在本公开的一个实施例中，重叠部分的宽度d为固定值。在这种情况下，根据所述变化情况，确定要形成的有源层沟道区的宽度，使得有源层沟道区的宽度与有源层厚度的比率在第一区域和第二区域上保持均一。
此外，如前所述，可以测量第一和第二区域中的各TFT对应位置的厚度，这需要测量非常大量的位置处的厚度。为了提高效率，也可以每隔相对较大的间隔(例如每300-500微米)测量一次厚度，并根据测得的厚度值来确定膜厚随位置变化的曲线的拟合函数。关于拟合函数的细节以及利用拟合函数确定有源层的重叠面积或沟道区宽度的细节，前面在第I部分中已进行了详细描述，在此不再赘述。
在步骤506，在衬底基板上形成薄膜晶体管，使得所形成的薄膜晶体管具有所确定的重叠面积。相应地，在上述重叠部分的宽度d为固定值的 实施例中，在衬底基板上形成薄膜晶体管，使得所形成的有源层沟道区具有所确定的宽度。例如，可以通过设计和制备用于形成薄膜晶体管的一个或多个掩膜，来实现所确定的重叠面积S或沟道区宽度W。
作为一个示例，薄膜晶体管的实现可以如图6所示，其对应于图3所示的底栅交叠型TFT。在该情况下，形成薄膜晶体管包括步骤602-610。在步骤602，在衬底基板上形成栅电极。这可以利用沉积和光刻工艺来实现。例如，可以通过依次执行沉积栅电极材料层、涂光刻胶、使用掩膜板进行曝光、用显影液进行显影、用刻蚀液进行刻蚀、和剥离光刻胶，来在衬底基板上形成栅电极。在步骤604，在栅电极上形成栅绝缘层。这可以利用沉积工艺来实现，或者可以利用沉积和光刻工艺来实现。在步骤606，在栅绝缘层上形成有源薄膜。这可以通过溅射或蒸镀等工艺来实现。在步骤608，对有源薄膜进行构图以形成有源层。这可以利用光刻工艺来实现。在步骤610，在有源层上形成源电极和漏电极。这可以利用沉积和光刻工艺来实现。
然而，本公开并不限于上面描述的示例。作为另一示例，步骤502和504也可以在步骤506的执行过程中执行。例如，在图6所示的示例中，先形成有源层，再形成源电极和漏电极。因此，步骤502和504可以在形成有源薄膜或有源层之后(即，在图6的步骤606或608之后)执行。这样，在步骤504确定要形成的有源层的重叠面积或沟道区宽度之后，可以在步骤610中形成源电极和漏电极来实现所确定的重叠面积或沟道区宽度。如前所述，可以通过例如设计和制备用于形成源电极和/或漏电极的掩膜，来实现所确定的重叠面积或沟道区宽度。
综上所述，本公开的至少一个实施例提供了一种阵列基板的制作方法，包括：获得有源层的厚度在衬底基板上随位置的变化情况。所述有源层至少具有厚度较大的第一区域和厚度较小的第二区域。所述制作方法还包括：根据所述变化情况，确定要形成的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得所述重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一。所述制作方法还包括：在衬底基板上形 成薄膜晶体管，使得所形成的薄膜晶体管具有所确定的重叠面积。
这样，由于薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在第一区域和第二区域上保持均一，所以能够避免在第一区域和第二区域中形成的薄膜晶体管由于有源层厚度的差异而导致源漏电极电流的差异，使阵列基板对像素单元的控制在第一区域和第二区域上保持均一，从而改善显示效果。
应注意的是，以上所述仅是本公开的示范性实施方式，而并非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种阵列基板，包括薄膜晶体管，其中所述阵列基板至少具有第一区域和第二区域，所述第一区域中的薄膜晶体管的有源层厚度大于所述第二区域中的薄膜晶体管的有源层厚度，且所述第一区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积大于所述第二区域中的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得薄膜晶体管的源电极或漏电极与有源层之间的重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一。
  2. 根据权利要求1所述的阵列基板，其中，薄膜晶体管的源电极或漏电极与有源层之间的重叠部分的长度为有源层沟道区的宽度，且所述重叠部分的宽度为固定值；以及
    薄膜晶体管的有源层沟道区的宽度与有源层厚度的比率在所述第一区域和第二区域上保持均一。
  3. 根据权利要求1所述的阵列基板，其中，所述第一区域和第二区域中的至少一个区域中的各薄膜晶体管的有源层厚度随有源层位置变化的曲线由拟合函数表示，且所述至少一个区域中的各薄膜晶体管的源电极或漏电极与有源层之间的重叠面积关于所述拟合函数成比例地变化。
  4. 根据权利要求2所述的阵列基板，其中，所述第一区域和第二区域中的至少一个区域中的各薄膜晶体管的有源层厚度随有源层位置变化的曲线由拟合函数表示，且所述至少一个区域中的各薄膜晶体管的有源层沟道区的宽度关于所述拟合函数成比例地变化。
  5. 根据权利要求1至4中任一项所述的阵列基板，其中，所述第一区域和第二区域周期性地交替排列。
  6. 根据权利要求1至5中任一项所述的阵列基板，其中，所述薄膜晶体管包括用于向有机发光二极管施加驱动电流的驱动薄膜晶体管，以及用于向所述驱动薄膜晶体管施加驱动电压的开关薄膜晶体管。
  7. 根据权利要求1至5中任一项所述的阵列基板，其中，所述薄膜晶体管包括用于向液晶层施加数据电压的开关薄膜晶体管。
  8. 一种阵列基板的制作方法，包括：
    获得有源层的厚度在衬底基板上随位置的变化情况，所述有源层至少具有厚度较大的第一区域和厚度较小的第二区域；
    根据所述变化情况，确定要形成的薄膜晶体管的源电极或漏电极与有源层之间的重叠面积，使得所述重叠面积与有源层厚度的比率在所述第一区域和第二区域上保持均一；以及
    在所述衬底基板上形成薄膜晶体管，使得所形成的薄膜晶体管具有所确定的重叠面积。
  9. 根据权利要求8所述的制作方法，其中，薄膜晶体管的源电极或漏电极与有源层之间的重叠部分的长度为有源层沟道区的宽度，且所述重叠部分的宽度为固定值；以及
    确定所述重叠面积包括：确定要形成的有源层沟道区的宽度，使得有源层沟道区的宽度与有源层厚度的比率在所述第一区域和第二区域上保持均一。
  10. 根据权利要求8所述的制作方法，其中，获得有源层的厚度在衬底基板上随位置的变化情况包括：
    在与所述衬底基板相同的测试用基板上形成有源薄膜；以及
    测量所述第一区域和第二区域中的有源薄膜厚度。
  11. 根据权利要求10所述的制作方法，其中，确定所述重叠面积包括：
    根据测得的有源薄膜厚度，确定所述第一区域和第二区域中的至少一个区域中的有源层厚度随有源层位置变化的曲线的拟合函数；以及
    确定所述至少一个区域中的所述重叠面积，使所述重叠面积关于所述拟合函数成比例地变化。
  12. 根据权利要求9所述的制作方法，其中，获得有源层的厚度在衬底基板上随位置的变化情况包括：
    在与所述衬底基板相同的测试用基板上形成有源薄膜；以及
    测量所述第一区域和第二区域中的有源薄膜厚度。
  13. 根据权利要求12所述的制作方法，其中，确定要形成的有源层沟道区的宽度包括：
    根据测得的有源薄膜厚度，确定所述第一区域和第二区域中的至少一个区域中的有源层厚度随有源层位置变化的曲线的拟合函数；以及
    确定所述至少一个区域中的有源层沟道区的宽度，使所述有源层沟道区的宽度关于所述拟合函数成比例地变化。
  14. 根据权利要求8至13中任一项所述的制作方法，其中，在衬底基板上形成薄膜晶体管包括：
    在所述衬底基板上形成栅电极；
    在所述栅电极上形成栅绝缘层；
    在所述栅绝缘层上形成有源薄膜；
    对所述有源薄膜进行构图以形成有源层；以及
    在所述有源层上形成源电极和漏电极。
  15. 根据权利要求14所述的制作方法，其中，
    在形成有源薄膜或有源层之后，获得所述变化情况并确定所述重叠面积。
PCT/CN2017/089717 2016-09-26 2017-06-23 阵列基板及其制作方法 WO2018054111A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/580,240 US10559601B2 (en) 2016-09-26 2017-06-23 Array substrate and method for manufacturing the same
JP2018501215A JP7036710B2 (ja) 2016-09-26 2017-06-23 アレイ基板及びその製作方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610849162.1A CN106356378B (zh) 2016-09-26 2016-09-26 阵列基板及其制作方法
CN201610849162.1 2016-09-26

Publications (1)

Publication Number Publication Date
WO2018054111A1 true WO2018054111A1 (zh) 2018-03-29

Family

ID=57859270

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/089717 WO2018054111A1 (zh) 2016-09-26 2017-06-23 阵列基板及其制作方法

Country Status (4)

Country Link
US (1) US10559601B2 (zh)
JP (1) JP7036710B2 (zh)
CN (1) CN106356378B (zh)
WO (1) WO2018054111A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11087978B2 (en) * 2018-07-19 2021-08-10 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Oxide semiconductor layer and preparation method thereof, device, substrate and means

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356378B (zh) * 2016-09-26 2023-10-27 合肥鑫晟光电科技有限公司 阵列基板及其制作方法
CN109713043A (zh) * 2017-10-25 2019-05-03 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、电子装置
CN110299103A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2326019A (en) * 1997-06-03 1998-12-09 Philips Electronics Nv Thin film transistor
CN1540602A (zh) * 2003-04-24 2004-10-27 ����Sdi��ʽ���� 具有薄膜晶体管的平板显示器
CN101101420A (zh) * 2006-07-06 2008-01-09 爱普生映像元器件有限公司 电光装置、其制造方法以及电子设备
CN101325220A (zh) * 2007-06-13 2008-12-17 三星Sdi株式会社 薄膜晶体管及其制造方法及包括该薄膜晶体管的显示装置
CN101656270A (zh) * 2008-08-21 2010-02-24 三星移动显示器株式会社 薄膜晶体管及其制造方法
CN105116653A (zh) * 2015-09-14 2015-12-02 深超光电（深圳）有限公司 显示面板
CN106356378A (zh) * 2016-09-26 2017-01-25 合肥鑫晟光电科技有限公司 阵列基板及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267662A (ja) * 1992-03-19 1993-10-15 Hitachi Ltd 相補型薄膜半導体装置およびそれを用いた画像情報処理装置
JP2005108930A (ja) * 2003-09-29 2005-04-21 Sony Corp 薄膜トランジスタの製造方法および薄膜トランジスタ
US8581260B2 (en) * 2007-02-22 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a memory
JP5294651B2 (ja) * 2007-05-18 2013-09-18 キヤノン株式会社 インバータの作製方法及びインバータ
JP5111949B2 (ja) * 2007-06-18 2013-01-09 株式会社日立製作所 薄膜トランジスタの製造方法及び薄膜トランジスタ装置
US20110227878A1 (en) * 2008-11-20 2011-09-22 Sharp Kabushiki Kaisha Semiconductor device, method for manufacturing same, and display device using semiconductor device
US20120256185A1 (en) * 2009-12-21 2012-10-11 Sharp Kabushiki Kaisha Semiconductor device and process for production thereof, and display device
CN103489826B (zh) * 2013-09-26 2015-08-05 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
KR20160038150A (ko) * 2014-09-29 2016-04-07 삼성디스플레이 주식회사 표시장치
KR20160044168A (ko) * 2014-10-14 2016-04-25 삼성디스플레이 주식회사 표시 기판 및 이의 제조 방법
CN104701265A (zh) * 2015-03-27 2015-06-10 深圳市华星光电技术有限公司 低温多晶硅tft基板结构及其制作方法
CN206022363U (zh) * 2016-09-26 2017-03-15 合肥鑫晟光电科技有限公司 阵列基板、显示面板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2326019A (en) * 1997-06-03 1998-12-09 Philips Electronics Nv Thin film transistor
CN1540602A (zh) * 2003-04-24 2004-10-27 ����Sdi��ʽ���� 具有薄膜晶体管的平板显示器
CN101101420A (zh) * 2006-07-06 2008-01-09 爱普生映像元器件有限公司 电光装置、其制造方法以及电子设备
CN101325220A (zh) * 2007-06-13 2008-12-17 三星Sdi株式会社 薄膜晶体管及其制造方法及包括该薄膜晶体管的显示装置
CN101656270A (zh) * 2008-08-21 2010-02-24 三星移动显示器株式会社 薄膜晶体管及其制造方法
CN105116653A (zh) * 2015-09-14 2015-12-02 深超光电（深圳）有限公司 显示面板
CN106356378A (zh) * 2016-09-26 2017-01-25 合肥鑫晟光电科技有限公司 阵列基板及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11087978B2 (en) * 2018-07-19 2021-08-10 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Oxide semiconductor layer and preparation method thereof, device, substrate and means

Also Published As

Publication number Publication date
CN106356378A (zh) 2017-01-25
JP2019531589A (ja) 2019-10-31
CN106356378B (zh) 2023-10-27
US10559601B2 (en) 2020-02-11
JP7036710B2 (ja) 2022-03-15
US20190221588A1 (en) 2019-07-18

Similar Documents

Publication Publication Date Title
WO2018054111A1 (zh) 阵列基板及其制作方法
CN103165598B (zh) 包括薄膜晶体管的阵列基板及其制造方法
CN104362125A (zh) 阵列基板及其制作方法、显示装置
US9548324B2 (en) Array substrate and method for fabricating the same
CN109148491B (zh) 一种阵列基板及其制备方法、显示装置
WO2016176884A1 (zh) Tft基板的制作方法及其结构
US20180090521A1 (en) Thin Film Transistor, Array Substrate, Methods For Fabricating The Same, And Display Device
WO2015096392A1 (zh) 阵列基板及其制造方法、显示装置
US20160013209A1 (en) Thin Film Transistor and Mnaufacturing Method Thereof, Array Substrate and Display Device
US11088283B2 (en) Thin film transistor, method of fabricating thin film transistor and array substrate
US7170092B2 (en) Flat panel display and fabrication method thereof
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
US20160284737A1 (en) Display substrate, its manufacturing method, and display device
WO2019157822A1 (zh) 像素单元及其制作方法和阵列基板
KR101689886B1 (ko) 산화물 반도체를 이용한 박막트랜지스터 기판의 제조방법
US9553170B2 (en) Manufacturing method of thin film transistor and thin film transistor
JP5370637B2 (ja) 薄膜トランジスタ、アクティブマトリックス回路並びに表示装置
KR101604480B1 (ko) 산화물 반도체를 이용한 박막트랜지스터 어레이 기판의 제조방법
CN106328554B (zh) 对位结构、显示装置及利用对位结构测量对位精度的方法
US9891495B2 (en) Array substrate and fabricating method thereof, and display panel
CN205092238U (zh) 测试组件单元、基板、显示面板以及显示装置
CN110998857A (zh) 一种薄膜晶体管及其制备方法与薄膜晶体管阵列
WO2020207198A1 (zh) 阵列基板及其制备方法、显示装置
WO2015014070A1 (zh) 阵列基板及其制作方法、显示装置
KR101644321B1 (ko) 산화물 반도체층을 이용한 박막트랜지스터 기판 및 그의 제조방법

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2018501215

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17852183

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.07.2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17852183

Country of ref document: EP

Kind code of ref document: A1