WO2018032594A1 - Goa电路及液晶显示面板 - Google Patents

Goa电路及液晶显示面板 Download PDF

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Publication number
WO2018032594A1
WO2018032594A1 PCT/CN2016/101913 CN2016101913W WO2018032594A1 WO 2018032594 A1 WO2018032594 A1 WO 2018032594A1 CN 2016101913 W CN2016101913 W CN 2016101913W WO 2018032594 A1 WO2018032594 A1 WO 2018032594A1
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WO
WIPO (PCT)
Prior art keywords
signal
pmos transistor
inverting amplifier
driving
cascade
Prior art date
Application number
PCT/CN2016/101913
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English (en)
French (fr)
Inventor
龚强
陈归
洪光辉
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/321,389 priority Critical patent/US10235957B2/en
Publication of WO2018032594A1 publication Critical patent/WO2018032594A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present invention relates to the field of display screen driving, and in particular to a GOA circuit and a liquid crystal display panel.
  • GOA circuit Gate Driver On Array, abbreviated as GOA circuit, that is, an array substrate process of an existing thin film transistor liquid crystal display is used to fabricate a scan line driver circuit on an array substrate, thereby implementing progressive scan of the scan line.
  • the current GOA circuit includes a cascade signal latch module, a gate drive signal generation module, and a gate drive signal output module.
  • Each of the above modules has a plurality of thin film transistors.
  • the space occupied by the GOA circuit is large, which is disadvantageous for the narrow frame design of the corresponding liquid crystal display panel.
  • the object of the present invention is to provide a GOA circuit and a liquid crystal display panel which can better realize the narrow bezel design of the liquid crystal display panel, so as to solve the problem that the occupied space of the GOA circuit in the existing liquid crystal display panel is large, which is disadvantageous for liquid crystal display.
  • the technical problem of the narrow bezel design of the panel is to provide a GOA circuit and a liquid crystal display panel which can better realize the narrow bezel design of the liquid crystal display panel, so as to solve the problem that the occupied space of the GOA circuit in the existing liquid crystal display panel is large, which is disadvantageous for liquid crystal display.
  • An embodiment of the present invention provides a GOA circuit including a first driving module for driving odd-numbered rows of pixel units and a second driving module for driving even-numbered rows of pixel units;
  • the first driving module includes:
  • a first driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a first output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the first state through a clock inverter;
  • a first reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the second driving module includes:
  • a second driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a second output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the second state to pass through the transmission gate;
  • a second reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the clock signal is changed in state by a transmission period of the cascade signal; when the reset signal is low, a reset operation is performed on the corresponding first driving module or the corresponding second driving module.
  • An embodiment of the present invention provides a GOA circuit including a first driving module for driving odd-numbered rows of pixel units and a second driving module for driving even-numbered rows of pixel units;
  • the first driving module includes:
  • a first driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a first output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the first state through a clock inverter;
  • a first reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the second driving module includes:
  • a second driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a second output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the second state to pass through the transmission gate;
  • a second reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the potential of the clock signal of the first state and the clock signal of the second state are opposite.
  • the first driving unit includes a first PMOS transistor, a first NMOS transistor, and a first inverting amplifier
  • a control terminal of the first PMOS transistor is connected to a reset signal source, an input end of the first PMOS transistor is connected to a high-level signal source, and an output end of the first PMOS transistor is respectively connected to an input of the first inverting amplifier And connecting an output end of the first NMOS transistor;
  • the control terminal of the first NMOS transistor inputs the cascaded signal of the upper stage, and the input end of the first NMOS transistor is connected to the low level signal source.
  • the first output unit includes a clocked inverter, a second inverting amplifier, a third inverting amplifier, and a fourth inverting amplifier;
  • a control end of the clocked inverter is connected to an output of the first driving unit, an input end of the clocked inverter inputs a clock signal of the first state, and an output end of the clocked inverter Connecting the input end of the second inverting amplifier;
  • An output end of the second inverting amplifier is connected to an input end of the third inverting amplifier, and an output end of the third inverting amplifier is connected to an input end of the fourth inverting amplifier, the fourth An output of the inverting amplifier outputs a scan drive signal of the current stage; an output of the second inverting amplifier outputs a cascade signal of the current stage.
  • the first reset unit includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;
  • An output end of the second PMOS transistor is connected to an output end of the first PMOS transistor, and a control end of the second PMOS transistor inputs a cascade signal of the upper stage, and an input end of the second PMOS transistor Connected to an output end of the third PMOS transistor;
  • a control terminal of the third PMOS transistor is input to the cascade signal of the current stage; an input end of the third PMOS transistor is connected to the high-level signal source;
  • An input end of the fourth PMOS transistor is connected to the high-level signal source, an output end of the fourth PMOS transistor is connected to an output end of the clock inverter, and a control end of the fourth PMOS transistor is The output of the first inverting amplifier is connected.
  • the second driving unit includes a fifth PMOS transistor, a second NMOS transistor, and a fifth inverting amplifier;
  • a control terminal of the fifth PMOS transistor is connected to a reset signal source, an input end of the fifth PMOS transistor is connected to a high-level signal source, and an output end of the fifth PMOS transistor is respectively connected to an input of the fifth inverting amplifier And connecting an output end of the second NMOS transistor;
  • the control terminal of the second NMOS transistor inputs the cascaded signal of the upper stage, and the input end of the second NMOS transistor is connected to the low level signal source.
  • the second output unit includes a transfer gate, a sixth inverting amplifier, a seventh inverting amplifier, and an eighth inverting amplifier;
  • a control end of the transmission gate is connected to an output of the second driving unit, an input end of the transmission gate inputs a clock signal of the first state, an output end of the transmission gate and the sixth inverting amplifier Input connection;
  • An output end of the sixth inverting amplifier is connected to an input end of the seventh inverting amplifier, and an output end of the seventh inverting amplifier is connected to an input end of the eighth inverting amplifier, the eighth An output of the inverting amplifier outputs a scan drive signal of the current stage; an output of the sixth inverting amplifier outputs a cascade signal of the current stage.
  • the second reset unit includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor;
  • An output end of the sixth PMOS transistor is connected to an output end of the fifth PMOS transistor, and a control end of the sixth PMOS transistor inputs a cascade signal of the upper stage, and an input end of the sixth PMOS transistor Connected to an output end of the seventh PMOS transistor;
  • a control terminal of the seventh PMOS transistor is input to the cascade signal of the current stage; an input end of the seventh PMOS transistor is connected to the high-level signal source;
  • An input end of the eighth PMOS transistor is connected to the high-level signal source, an output end of the eighth PMOS transistor is connected to an output end of the transmission gate, and a control end of the eighth PMOS transistor is opposite to the first The output of the five inverting amplifiers is connected.
  • the clock signal changes state in a transmission cycle of the cascaded signal.
  • the reset signal when the reset signal is at a low level, a reset operation is performed on the corresponding first driving module or the corresponding second driving module.
  • Embodiments of the present invention also provide a liquid crystal display panel including a GOA circuit, wherein the GOA circuit includes a first driving module for driving odd-numbered rows of pixel units and a second driving module for driving even-numbered rows of pixel units ;
  • the first driving module includes:
  • a first driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a first output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the first state through a clock inverter;
  • a first reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the second driving module includes:
  • a second driving unit configured to receive a cascade signal of the upper stage, and generate a cascade driving signal and a reset signal according to the cascade signal;
  • a second output unit configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the second state to pass through the transmission gate;
  • a second reset unit configured to cancel the scan driving signal of the current stage according to the reset signal
  • the potential of the clock signal of the first state and the clock signal of the second state are opposite.
  • the first driving unit includes a first PMOS transistor, a first NMOS transistor, and a first inverting amplifier
  • a control terminal of the first PMOS transistor is connected to a reset signal source, an input end of the first PMOS transistor is connected to a high-level signal source, and an output end of the first PMOS transistor is respectively connected to an input of the first inverting amplifier And connecting an output end of the first NMOS transistor;
  • the control terminal of the first NMOS transistor inputs the cascaded signal of the upper stage, and the input end of the first NMOS transistor is connected to the low level signal source.
  • the first output unit includes a clocked inverter, a second inverting amplifier, a third inverting amplifier, and a fourth inverting amplifier;
  • a control end of the clocked inverter is connected to an output of the first driving unit, an input end of the clocked inverter inputs a clock signal of the first state, and an output end of the clocked inverter Connecting the input end of the second inverting amplifier;
  • An output end of the second inverting amplifier is connected to an input end of the third inverting amplifier, and an output end of the third inverting amplifier is connected to an input end of the fourth inverting amplifier, the fourth An output of the inverting amplifier outputs a scan drive signal of the current stage; an output of the second inverting amplifier outputs a cascade signal of the current stage.
  • the first reset unit includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;
  • An output end of the second PMOS transistor is connected to an output end of the first PMOS transistor, and a control end of the second PMOS transistor inputs a cascade signal of the upper stage, and an input end of the second PMOS transistor Connected to an output end of the third PMOS transistor;
  • a control terminal of the third PMOS transistor is input to the cascade signal of the current stage; an input end of the third PMOS transistor is connected to the high-level signal source;
  • An input end of the fourth PMOS transistor is connected to the high-level signal source, an output end of the fourth PMOS transistor is connected to an output end of the clock inverter, and a control end of the fourth PMOS transistor is The output of the first inverting amplifier is connected.
  • the second driving unit includes a fifth PMOS transistor, a second NMOS transistor, and a fifth inverting amplifier;
  • a control terminal of the fifth PMOS transistor is connected to a reset signal source, an input end of the fifth PMOS transistor is connected to a high-level signal source, and an output end of the fifth PMOS transistor is respectively connected to an input of the fifth inverting amplifier And connecting an output end of the second NMOS transistor;
  • the control terminal of the second NMOS transistor inputs the cascaded signal of the upper stage, and the input end of the second NMOS transistor is connected to the low level signal source.
  • the second output unit includes a transfer gate, a sixth inverting amplifier, a seventh inverting amplifier, and an eighth inverting amplifier;
  • a control end of the transmission gate is connected to an output of the second driving unit, an input end of the transmission gate inputs a clock signal of the first state, an output end of the transmission gate and the sixth inverting amplifier Input connection;
  • An output end of the sixth inverting amplifier is connected to an input end of the seventh inverting amplifier, and an output end of the seventh inverting amplifier is connected to an input end of the eighth inverting amplifier, the eighth An output of the inverting amplifier outputs a scan drive signal of the current stage; an output of the sixth inverting amplifier outputs a cascade signal of the current stage.
  • the second reset unit includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor;
  • An output end of the sixth PMOS transistor is connected to an output end of the fifth PMOS transistor, and a control end of the sixth PMOS transistor inputs a cascade signal of the upper stage, and an input end of the sixth PMOS transistor Connected to an output end of the seventh PMOS transistor;
  • a control terminal of the seventh PMOS transistor is input to the cascade signal of the current stage; an input end of the seventh PMOS transistor is connected to the high-level signal source;
  • An input end of the eighth PMOS transistor is connected to the high-level signal source, an output end of the eighth PMOS transistor is connected to an output end of the transmission gate, and a control end of the eighth PMOS transistor is opposite to the first The output of the five inverting amplifiers is connected.
  • the clock signal changes state in a transmission cycle of the cascaded signal.
  • the reset signal when the reset signal is at a low level, a reset operation is performed on the corresponding first driving module or the corresponding second driving module.
  • the GOA circuit and the liquid crystal display panel of the present invention share the clock signal by setting the first driving module and the second driving module, thereby reducing the occupation space of the GOA circuit and facilitating the liquid crystal display panel.
  • the narrow bezel design solves the technical problem that the occupied space of the GOA circuit in the existing liquid crystal display panel is large, which is disadvantageous to the narrow bezel design of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a GOA circuit of the present invention.
  • FIG. 2 is a specific circuit diagram of a first driving module and a second driving module of a preferred embodiment of the GOA circuit of the present invention
  • Figure 3 is a control timing diagram of signals of a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 4 is a detailed circuit diagram of a plurality of first driving modules and a plurality of second driving modules of a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a GOA circuit of the present invention.
  • the GOA circuit of the preferred embodiment is for driving a scan line of a corresponding liquid crystal display panel, the GOA circuit 10 including a first driving module 11 for driving odd-numbered rows of pixel units and driving even-numbered rows of pixel units The second drive module 12.
  • the first driving module 11 includes a first driving unit 111, a first output unit 112, and a first reset unit 113.
  • the second driving module 12 includes a second driving unit 121, a second output unit 122, and a second reset unit 123.
  • the first driving unit 111 is configured to receive the cascaded signal of the previous stage, and generate the cascaded driving signal and the reset signal according to the cascaded signal.
  • the first output unit 112 is configured to generate a scan driving signal of the current stage and a cascade signal of the current stage through the clock inverter using the cascade driving signal and the clock signal of the first state.
  • the first reset unit 113 is configured to cancel the scan driving signal of the current stage according to the reset signal.
  • the second driving unit 121 is configured to receive the cascaded signal of the previous stage, and generate the cascaded driving signal and the reset signal according to the cascaded signal.
  • the second output unit 122 is configured to generate a scan driving signal of the current stage and a cascade signal of the current stage through the transmission gate using the cascade driving signal and the clock signal of the second state.
  • the second reset unit 123 is configured to cancel the scan driving signal of the current stage according to the reset signal.
  • the clock signal of the first state and the clock signal of the second state are opposite.
  • FIG. 2 is a specific circuit diagram of a first driving module and a second driving module according to a preferred embodiment of the GOA circuit of the present invention.
  • the first driving unit 111 of the first driving module 11 includes a first PMOS transistor T11, a first NMOS transistor T21, and a first inverting amplifier D1.
  • the control terminal of the first PMOS transistor T11 is connected to the reset signal source RST, the input end of the first PMOS transistor T11 is connected to the high-level signal source VGH, and the output end of the first PMOS transistor T11 is respectively connected to the input end of the first inverting amplifier D1 and
  • the output terminal of the first NMOS transistor T21 is connected; the control terminal of the first NMOS transistor T21 inputs the cascaded signal STN-1 of the previous stage, and the input terminal of the first NMOS transistor T21 is connected to the low-level signal source VGL.
  • the first output unit 112 includes a clocked inverter DC1, a second inverting amplifier D2, a third inverting amplifier D3, and a fourth inverting amplifier D4.
  • the control terminal of the clocked inverter DC1 is connected to the output of the first driving unit 111, the input terminal of the clocked inverter DC1 inputs the clock signal of the first state, the output of the clocked inverter DC1 and the output of the second inverting amplifier D2 The input is connected.
  • the output of the second inverting amplifier D2 is connected to the input of the third inverting amplifier D3, the output of the third inverting amplifier D3 is connected to the input of the fourth inverting amplifier D4, and the output of the fourth inverting amplifier D4
  • the terminal outputs the scan drive signal GoutN of the present stage, and the output terminal of the second inverting amplifier D2 outputs the cascaded signal STN of the present stage.
  • the first reset unit 113 includes a second PMOS transistor T12, a third PMOS transistor T13, and a fourth PMOS transistor T14.
  • the output end of the second PMOS transistor T12 is connected to the output end of the first PMOS transistor T11, the control end of the second PMOS transistor T12 is input to the cascaded signal STN-1 of the previous stage, and the input end of the second PMOS transistor T12 is connected to the third The output terminal of the PMOS transistor T13 is connected.
  • the control terminal of the third PMOS transistor T13 is input to the cascade signal STN of the present stage, and the input terminal of the third PMOS transistor T13 is connected to the high-level signal source VGH.
  • the input end of the fourth PMOS transistor T14 is connected to the high-level signal source VGH, the input end of the fourth PMOS transistor T14 is connected to the high-level signal source VGH, and the output end of the fourth PMOS transistor T14 is connected to the output end of the clocked inverter DC1.
  • the control terminal of the fourth PMOS transistor T14 is connected to the output terminal of the first inverting amplifier D1.
  • the second driving module 12 is the next-stage driving circuit of the first driving module 11, that is, the cascade signal STN of the first stage of the first driving module 11 is the cascade signal STN of the upper stage of the second driving module 12.
  • the second driving unit 121 of the second driving module 12 includes a fifth PMOS transistor T15, a second NMOS transistor T22, and a fifth inverting amplifier D5.
  • the control terminal of the fifth PMOS transistor T15 is connected to the reset signal source RST, the input terminal of the fifth PMOS transistor T15 is connected to the high-level signal source VGH, and the output terminal of the fifth PMOS transistor T15 is respectively connected to the input terminal of the fifth inverting amplifier D5.
  • the output terminal of the second NMOS transistor T22 is connected; the control terminal of the second NMOS transistor T22 inputs the cascaded signal STN of the previous stage, and the input terminal of the second NMOS transistor T22 is connected to the low-level signal source VGL.
  • the second output unit 122 includes a transfer gate DC2, a sixth inverting amplifier D6, a seventh inverting amplifier D7, and an eighth inverting amplifier D8.
  • the control terminal of the transmission gate DC2 is connected to the output of the second driving unit 121, the input terminal of the transmission gate DC2 inputs the clock signal of the first state, and the output terminal of the transmission gate DC2 is connected with the input terminal of the sixth counter amplifier D6;
  • the output of the phase amplifier D6 is connected to the input of the seventh inverting amplifier D7, the output of the seventh inverting amplifier D7 is connected to the input of the eighth inverting amplifier D8, and the output of the eighth inverting amplifier D8 is output.
  • the level of the scan driving signal GoutN+1, the output of the sixth counter amplifier D6 outputs the cascaded signal STN+1 of the present stage.
  • the second reset unit 123 includes a sixth PMOS transistor T16, a seventh PMOS transistor T17, and an eighth PMOS transistor T18.
  • the output end of the sixth PMOS transistor T16 is connected to the output end of the fifth PMOS transistor T15, the control end of the sixth PMOS transistor T16 is input to the cascaded signal STN of the previous stage, and the input terminal of the sixth PMOS transistor T16 and the seventh PMOS transistor The output of T17 is connected.
  • the control terminal of the seventh PMOS transistor T17 is input to the cascade signal STN+1 of the present stage, and the input terminal of the seventh PMOS transistor T17 is connected to the high-level signal source VGH.
  • the input end of the eighth PMOS transistor T18 is connected to the high level signal source VGH, the output end of the eighth PMOS transistor T18 is connected to the output end of the transfer gate DC2, and the output end of the eighth PMOS transistor T18 and the output of the fifth inverting amplifier D5 End connection.
  • FIG. 3 is a control timing diagram of each signal of the preferred embodiment of the GOA circuit of the present invention.
  • STN-1 is high
  • RST is also high
  • the first NMOS transistor T21 is turned on
  • the first PMOS transistor T11 is turned off
  • the low-level signal source VGL is transmitted to the first inverting amplifier D1 through the first PMOS transistor T11
  • the first inverting amplifier D1 outputs the amplified high-level signal to the clocked inverter DC1.
  • the clock inverter DC1 performs an inversion operation on the clock signal CK1 (high level state) of the first state under the control of the high level signal, and outputs a low level signal to the second inverting amplifier D2, the second inversion.
  • the amplifier D2 outputs the current-stage cascaded signal STN of the high level of the first driving module 11, and at this time, the fourth inverting amplifier D4 outputs the scan driving signal GoutN of the current stage of the high level of the first driving module 11.
  • the current level cascaded signal STN of the high level is transmitted to the second driving unit 121 of the second driving module 12, when STN is high level, RST is also high level, and the second NMOS transistor T22 is turned on, the fifth PMOS Transistor T15 is turned off, the low level signal source VGL transmits T15 to the fifth inverting amplifier D5 through the first PMOS transistor, and the fifth inverting amplifier D5 outputs the amplified high level signal to the transfer gate DC2.
  • the transmission gate DC2 performs a normal phase transmission operation on the clock signal CK1 (low state) of the second state under the control of the high level signal, and outputs a low level signal to the sixth inverting amplifier D6, the sixth inverting amplifier D6 outputs the high-level cascading signal STN+1 of the second driving module 12, and at this time, the eighth inverting amplifier D8 outputs the scanning drive signal GoutN+1 of the current level of the high level of the second driving module 12.
  • the clock signal in the first driving module 11 is also converted into the second state.
  • the clock inverter DC1 inverts the clock signal CK1 (low state) of the second state under the control of the high level signal. Operation, outputting a high level signal to the second inverting amplifier D2, the second inverting amplifier D2 pulling the high level of the first stage cascaded signal STN of the first driving module 11 to a low level, then the fourth inversion The amplifier D4 also pulls the scan drive signal GoutN of the current stage of the high level of the first drive module 11 to the low level.
  • the third PMOS transistor T13 and the second PMOS transistor T12 is both turned on, and the first NMOS transistor T21 is turned off, so that the high-level signal source VGH charges Qn through the third PMOS transistor T13 and the second PMOS transistor T12, so that Qn returns to the high state.
  • the fifth PMOS transistor T15 is also turned on, and the high-level signal source VGH passes through the fifth PMOS transistor T15 while ensuring that the input terminal of the second inverting amplifier D2 is also in a high state.
  • the generation process of the current-stage scan driving signal GoutN of the first driving module 11 is completed.
  • the transmission gate DC2 performs a normal phase transmission operation on the clock signal CK1 (high level state) of the first state under the control of the high level signal.
  • the phase amplifier D8 also pulls the scan drive signal GoutN+1 of the current stage of the high level of the second drive module to a low level.
  • the seventh PMOS transistor T17 and the sixth PMOS transistor T16 is both turned on, and the second NMOS transistor T22 is turned off, so that the high-level signal source VGH charges Qn+1 through the seventh PMOS transistor T17 and the sixth PMOS transistor T16, so that Qn+1 returns to the high state.
  • the eighth PMOS transistor T18 is also turned on, and the high-level signal source VGH passes through the eighth PMOS transistor T18 to simultaneously ensure that the input end of the sixth inverting amplifier D6 is also in a high state.
  • the generation process of the current-stage scan driving signal GoutN+1 of the second driving module 12 is completed.
  • FIG. 4 is a specific circuit diagram of a plurality of first driving modules and a plurality of second driving modules according to a preferred embodiment of the GOA circuit of the present invention.
  • a first driving module and a second driving module of the GOA circuit form a driving unit, such as the driving unit 41, the driving unit 42 and the driving unit 43 in FIG. 4, wherein the input signal of the driving unit 41 is a reset signal RST, a clock The signal CK1 and the cascade signal STV, wherein the cascade signal STV forms the upper cascade signal STN-1 of the first drive module of the drive unit 41.
  • the output signal of the driving unit 41 is the scan driving signal Gout1 of the first driving module, the scan driving signal Gout2 of the second driving module, and the next-stage cascaded signal STN+1 generated by the second driving module, that is, the cascade signal ST2.
  • the input signals of the driving unit 42 are a reset signal RST, a clock signal CK1, and a cascade signal ST2, wherein the cascade signal ST2 forms the upper cascade signal STN-1 of the first driving module of the driving unit 42.
  • the output signal of the driving unit 42 is the scan driving signal Gout3 of the first driving module, the scan driving signal Gout4 of the second driving module, and the next-stage cascade signal STN+1 generated by the second driving module, that is, the cascade signal ST4.
  • the input signals of the drive unit 43 are a reset signal RST, a clock signal CK1, and a cascade signal ST4, wherein the cascade signal ST4 forms the upper cascade signal STN-1 of the first drive module of the drive unit 43.
  • the output signal of the driving unit 43 is the scan driving signal Gout5 of the first driving module, the scan driving signal Gout6 of the second driving module, and the next-stage cascade signal STN+1 generated by the second driving module, that is, the cascade signal ST6.
  • the present invention also provides a liquid crystal display panel including a data line, a scan line, a pixel unit composed of a data line and a scan line, and a corresponding GOA circuit.
  • the GOA circuit includes a first driving module for driving odd-numbered rows of pixel cells and a second driving module for driving even-numbered rows of pixel cells.
  • the first driving module includes a first driving unit, a first output unit, and a first reset unit.
  • the second driving module includes a second driving unit, a second output unit, and a second reset unit.
  • the first driving unit is configured to receive the cascaded signal of the upper stage, and generate the cascaded driving signal and the reset signal according to the cascaded signal.
  • the first output unit is configured to generate a scan driving signal of the current stage and a cascade signal of the current stage through the clock inverter using the cascade driving signal and the clock signal of the first state.
  • the first reset unit is configured to cancel the scan driving signal of the current stage according to the reset signal.
  • the second driving unit is configured to receive the cascaded signal of the upper stage, and generate the cascaded driving signal and the reset signal according to the cascaded signal.
  • the second output unit is configured to generate a scan driving signal of the current stage and a cascade signal of the current stage by using the cascade driving signal and the clock signal of the second state to pass through the transmission gate.
  • the second reset unit is configured to cancel the scan driving signal of the current stage according to the reset signal.
  • the clock signal of the first state and the clock signal of the second state are opposite.
  • the specific working principle of the liquid crystal display panel of the present invention is the same as or similar to that described in the preferred embodiment of the GOA circuit described above. For details, refer to the related description in the preferred embodiment of the GOA circuit described above.
  • the GOA circuit and the liquid crystal display panel of the invention share the clock signal by setting the first driving module and the second driving module, thereby reducing the occupied space of the GOA circuit and facilitating the narrow bezel design of the liquid crystal display panel; and solving the existing liquid crystal display panel
  • the GOA circuit occupies a large space, which is not conducive to the technical problem of the narrow bezel design of the liquid crystal display panel.

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Abstract

一种GOA电路，包括第一驱动模块（11）以及第二驱动模块（12）。第一驱动模块（11）包括第一驱动单元（111）、第一输出单元（112）以及第一复位单元（113）；第二驱动模块（12）包括第二驱动单元（121）、第二输出单元（122）以及第二复位单元（123）；其中第一输出单元（112）用于生成本级的扫描驱动信号以及本级的级联信号；第二输出单元（122）用于生成本级的扫描驱动信号以及本级的级联信号。

Description

GOA电路及液晶显示面板 技术领域
本发明涉及显示屏驱动领域，特别是涉及一种GOA电路及液晶显示面板。
 背景技术
Gate Driver On Array，简称GOA电路，也就是利用现有薄膜晶体管液晶显示器的阵列基板制程将扫描线驱动电路制作在阵列基板上，从而实现对扫描线的逐行扫描。
目前的GOA电路包括级联信号锁存模块、栅极驱动信号生成模块以及栅极驱动信号输出模块。上述模块中均具有多个薄膜晶体管，但是由于现有的GOA电路的各个模块中具有较多的薄膜晶体管，导致GOA电路的占据空间较大，不利于相应的液晶显示面板的窄边框设计。
故，有必要提供一种GOA电路及液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种可较好的实现液晶显示面板的窄边框设计的GOA电路及液晶显示面板，以解决现有的液晶显示面板中的GOA电路的占据空间较大，不利于液晶显示面板的窄边框设计的技术问题。
 技术解决方案
本发明实施例提供一种GOA电路，其包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
其中所述第一驱动模块包括：
第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
所述第二驱动模块包括：
第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反；
其中所述时钟信号以所述级联信号的传输周期进行状态变化；当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。本发明实施例提供一种GOA电路，其包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
其中所述第一驱动模块包括：
第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
所述第二驱动模块包括：
第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反。
在本发明所述的GOA电路中，所述第一驱动单元包括第一PMOS晶体管、第一NMOS晶体管以及第一反相放大器；
所述第一PMOS晶体管的控制端连接复位信号源，所述第一PMOS晶体管的输入端连接高电平信号源，所述第一PMOS晶体管的输出端分别与所述第一反相放大器的输入端以及所述第一NMOS晶体管的输出端连接；
所述第一NMOS晶体管的控制端输入所述上一级的级联信号，所述第一NMOS晶体管的输入端连接低电平信号源。
在本发明所述的GOA电路中，所述第一输出单元包括时钟反相器、第二反相放大器、第三反相放大器以及第四反相放大器；
所述时钟反相器的控制端与所述第一驱动单元的输出连接，所述时钟反相器的输入端输入所述第一状态的时钟信号，所述时钟反相器的输出端与所述第二反相放大器的输入端连接；
所述第二反相放大器的输出端与所述第三反相放大器的输入端连接，所述第三反相放大器的输出端与所述第四反相放大器的输入端连接，所述第四反相放大器的输出端输出所述本级的扫描驱动信号；所述第二反相放大器的输出端输出所述本级的级联信号。
在本发明所述的GOA电路中，所述第一复位单元包括第二PMOS晶体管、第三PMOS晶体管以及第四PMOS晶体管；
所述第二PMOS晶体管的输出端与所述第一PMOS晶体管的输出端连接，所述第二PMOS晶体管的控制端输入所述上一级的级联信号，所述第二PMOS晶体管的输入端与所述第三PMOS晶体管的输出端连接；
所述第三PMOS晶体管的控制端输入所述本级的级联信号；所述第三PMOS晶体管的输入端连接所述高电平信号源；
所述第四PMOS晶体管的输入端连接所述高电平信号源，所述第四PMOS晶体管的输出端与所述时钟反相器的输出端连接，所述第四PMOS晶体管的控制端与所述第一反相放大器的输出端连接。
在本发明所述的GOA电路中，所述第二驱动单元包括第五PMOS晶体管、第二NMOS晶体管以及第五反相放大器；
所述第五PMOS晶体管的控制端连接复位信号源，所述第五PMOS晶体管的输入端连接高电平信号源，所述第五PMOS晶体管的输出端分别与所述第五反相放大器的输入端以及所述第二NMOS晶体管的输出端连接；
所述第二NMOS晶体管的控制端输入所述上一级的级联信号，所述第二NMOS晶体管的输入端连接低电平信号源。
在本发明所述的GOA电路中，所述第二输出单元包括传输门、第六反相放大器、第七反相放大器以及第八反相放大器；
所述传输门的控制端与所述第二驱动单元的输出连接，所述传输门的输入端输入所述第一状态的时钟信号，所述传输门的输出端与所述第六反相放大器的输入端连接；
所述第六反相放大器的输出端与所述第七反相放大器的输入端连接，所述第七反相放大器的输出端与所述第八反相放大器的输入端连接，所述第八反相放大器的输出端输出所述本级的扫描驱动信号；所述第六反相放大器的输出端输出所述本级的级联信号。
在本发明所述的GOA电路中，所述第二复位单元包括第六PMOS晶体管、第七PMOS晶体管以及第八PMOS晶体管；
所述第六PMOS晶体管的输出端与所述第五PMOS晶体管的输出端连接，所述第六PMOS晶体管的控制端输入所述上一级的级联信号，所述第六PMOS晶体管的输入端与所述第七PMOS晶体管的输出端连接；
所述第七PMOS晶体管的控制端输入所述本级的级联信号；所述第七PMOS晶体管的输入端连接所述高电平信号源；
所述第八PMOS晶体管的输入端连接所述高电平信号源，所述第八PMOS晶体管的输出端与所述传输门的输出端连接，所述第八PMOS晶体管的控制端与所述第五反相放大器的输出端连接。
在本发明所述的GOA电路中，所述时钟信号以所述级联信号的传输周期进行状态变化。
在本发明所述的GOA电路中，当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。
本发明实施例还提供一种液晶显示面板，其包括GOA电路，其中所述GOA电路包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
其中所述第一驱动模块包括：
第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
所述第二驱动模块包括：
第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反。
在本发明所述的液晶显示面板中，所述第一驱动单元包括第一PMOS晶体管、第一NMOS晶体管以及第一反相放大器；
所述第一PMOS晶体管的控制端连接复位信号源，所述第一PMOS晶体管的输入端连接高电平信号源，所述第一PMOS晶体管的输出端分别与所述第一反相放大器的输入端以及所述第一NMOS晶体管的输出端连接；
所述第一NMOS晶体管的控制端输入所述上一级的级联信号，所述第一NMOS晶体管的输入端连接低电平信号源。
在本发明所述的液晶显示面板中，所述第一输出单元包括时钟反相器、第二反相放大器、第三反相放大器以及第四反相放大器；
所述时钟反相器的控制端与所述第一驱动单元的输出连接，所述时钟反相器的输入端输入所述第一状态的时钟信号，所述时钟反相器的输出端与所述第二反相放大器的输入端连接；
所述第二反相放大器的输出端与所述第三反相放大器的输入端连接，所述第三反相放大器的输出端与所述第四反相放大器的输入端连接，所述第四反相放大器的输出端输出所述本级的扫描驱动信号；所述第二反相放大器的输出端输出所述本级的级联信号。
在本发明所述的液晶显示面板中，所述第一复位单元包括第二PMOS晶体管、第三PMOS晶体管以及第四PMOS晶体管；
所述第二PMOS晶体管的输出端与所述第一PMOS晶体管的输出端连接，所述第二PMOS晶体管的控制端输入所述上一级的级联信号，所述第二PMOS晶体管的输入端与所述第三PMOS晶体管的输出端连接；
所述第三PMOS晶体管的控制端输入所述本级的级联信号；所述第三PMOS晶体管的输入端连接所述高电平信号源；
所述第四PMOS晶体管的输入端连接所述高电平信号源，所述第四PMOS晶体管的输出端与所述时钟反相器的输出端连接，所述第四PMOS晶体管的控制端与所述第一反相放大器的输出端连接。
在本发明所述的液晶显示面板中，所述第二驱动单元包括第五PMOS晶体管、第二NMOS晶体管以及第五反相放大器；
所述第五PMOS晶体管的控制端连接复位信号源，所述第五PMOS晶体管的输入端连接高电平信号源，所述第五PMOS晶体管的输出端分别与所述第五反相放大器的输入端以及所述第二NMOS晶体管的输出端连接；
所述第二NMOS晶体管的控制端输入所述上一级的级联信号，所述第二NMOS晶体管的输入端连接低电平信号源。
在本发明所述的液晶显示面板中，所述第二输出单元包括传输门、第六反相放大器、第七反相放大器以及第八反相放大器；
所述传输门的控制端与所述第二驱动单元的输出连接，所述传输门的输入端输入所述第一状态的时钟信号，所述传输门的输出端与所述第六反相放大器的输入端连接；
所述第六反相放大器的输出端与所述第七反相放大器的输入端连接，所述第七反相放大器的输出端与所述第八反相放大器的输入端连接，所述第八反相放大器的输出端输出所述本级的扫描驱动信号；所述第六反相放大器的输出端输出所述本级的级联信号。
在本发明所述的液晶显示面板中，所述第二复位单元包括第六PMOS晶体管、第七PMOS晶体管以及第八PMOS晶体管；
所述第六PMOS晶体管的输出端与所述第五PMOS晶体管的输出端连接，所述第六PMOS晶体管的控制端输入所述上一级的级联信号，所述第六PMOS晶体管的输入端与所述第七PMOS晶体管的输出端连接；
所述第七PMOS晶体管的控制端输入所述本级的级联信号；所述第七PMOS晶体管的输入端连接所述高电平信号源；
所述第八PMOS晶体管的输入端连接所述高电平信号源，所述第八PMOS晶体管的输出端与所述传输门的输出端连接，所述第八PMOS晶体管的控制端与所述第五反相放大器的输出端连接。
在本发明所述的液晶显示面板中，所述时钟信号以所述级联信号的传输周期进行状态变化。
在本发明所述的液晶显示面板中，当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。
 有益效果
相较于现有的GOA电路及液晶显示面板，本发明的GOA电路及液晶显示面板通过设置第一驱动模块和第二驱动模块共用时钟信号，从而缩小GOA电路的占据空间，便于液晶显示面板的窄边框设计；解决了现有的液晶显示面板中的GOA电路的占据空间较大，不利于液晶显示面板的窄边框设计的技术问题。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为本发明的GOA电路的优选实施例的结构示意图；
图2为本发明的GOA电路的优选实施例的一第一驱动模块和一第二驱动模块的具体电路图；
图3本发明的GOA电路的优选实施例的各信号的控制时序图；
图4为本发明的GOA电路的优选实施例的多个第一驱动模块以及多个第二驱动模块的具体电路图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的GOA电路的优选实施例的结构示意图。本优选实施例的GOA电路用于对相应的液晶显示面板进行扫描线的驱动，该GOA电路10包括用于对奇数行像素单元进行驱动的第一驱动模块11以及对偶数行像素单元进行驱动的第二驱动模块12。
其中第一驱动模块11包括第一驱动单元111、第一输出单元112以及第一复位单元113。第二驱动模块12包括第二驱动单元121、第二输出单元122以及第二复位单元123。
第一驱动单元111用于接收上一级的级联信号，并根据级联信号生成级联驱动信号以及复位信号。第一输出单元112用于使用级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号。第一复位单元113用于根据复位信号，消除本级的扫描驱动信号。
第二驱动单元121用于接收上一级的级联信号，并根据级联信号生成级联驱动信号以及复位信号。第二输出单元122用于使用级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号。第二复位单元123用于根据复位信号，消除本级的扫描驱动信号。
其中第一状态的时钟信号以及第二状态的时钟信号的点位相反。
请参照图2，图2为本发明的GOA电路的优选实施例的一第一驱动模块和一第二驱动模块的具体电路图。第一驱动模块11的第一驱动单元111包括第一PMOS晶体管T11、第一NMOS晶体管T21以及第一反放大器D1。
第一PMOS晶体管T11的控制端连接复位信号源RST，第一PMOS晶体管T11的输入端连接高电平信号源VGH，第一PMOS晶体管T11的输出端分别与第一反相放大器D1的输入端以及第一NMOS晶体管T21的输出端连接；第一NMOS晶体管T21的控制端输入上一级的级联信号STN-1，第一NMOS晶体管T21的输入端连接低电平信号源VGL。
第一输出单元112包括时钟反相器DC1、第二反相放大器D2、第三反相放大器D3以及第四反相放大器D4。
时钟反相器DC1的控制端与第一驱动单元111的输出连接，时钟反相器DC1的输入端输入第一状态的时钟信号，时钟反相器DC1的输出端与第二反相放大器D2的输入端连接。第二反相放大器D2的输出端与第三反相放大器D3的输入端连接，第三反相放大器D3的输出端与第四反相放大器D4的输入端连接，第四反相放大器D4的输出端输出本级的扫描驱动信号GoutN，第二反相放大器D2的输出端输出本级的级联信号STN。
第一复位单元113包括第二PMOS晶体管T12、第三PMOS晶体管T13以及第四PMOS晶体管T14。
第二PMOS晶体管T12的输出端与第一PMOS晶体管T11的输出端连接，第二PMOS晶体管T12的控制端输入上一级的级联信号STN-1，第二PMOS晶体管T12的输入端与第三PMOS晶体管T13的输出端连接。第三PMOS晶体管T13的控制端输入本级的级联信号STN，第三PMOS晶体管T13的输入端连接高电平信号源VGH。第四PMOS晶体管T14的输入端连接高电平信号源VGH，第四PMOS晶体管T14的输入端连接高电平信号源VGH，第四PMOS晶体管T14的输出端与时钟反相器DC1的输出端连接，第四PMOS晶体管T14的控制端与第一反相放大器D1的输出端连接。
第二驱动模块12为第一驱动模块11的下一级驱动电路，即第一驱动模块11的本级的级联信号STN为第二驱动模块12的上一级的级联信号STN。
第二驱动模块12的第二驱动单元121包括第五PMOS晶体管T15、第二NMOS晶体管T22以及第五反相放大器D5。
第五PMOS晶体管T15的控制端连接复位信号源RST，第五PMOS晶体管T15的输入端连接高电平信号源VGH，第五PMOS晶体管T15的输出端分别与第五反相放大器D5的输入端以及第二NMOS晶体管T22的输出端连接；第二NMOS晶体管T22的控制端输入上一级的级联信号STN，第二NMOS晶体管T22的输入端连接低电平信号源VGL。
第二输出单元122包括传输门DC2、第六反相放大器D6、第七反相放大器D7以及第八反相放大器D8。
传输门DC2的控制端与第二驱动单元121的输出连接，传输门DC2的输入端输入第一状态的时钟信号，传输门DC2的输出端与第六反响放大器D6的输入端连接；第六反相放大器D6的输出端与第七反相放大器D7的输入端连接，第七反相放大器D7的输出端与第八反相放大器D8的输入端连接，第八反相放大器D8的输出端输出本级的扫描驱动信号GoutN+1，第六反响放大器D6的输出端输出本级的级联信号STN+1。
第二复位单元123包括第六PMOS晶体管T16、第七PMOS晶体管T17以及第八PMOS晶体管T18。
第六PMOS晶体管T16的输出端与第五PMOS晶体管T15的输出端连接，第六PMOS晶体管T16的控制端输入上一级的级联信号STN，第六PMOS晶体管T16的输入端与第七PMOS晶体管T17的输出端连接。第七PMOS晶体管T17的控制端输入本级的级联信号STN+1，第七PMOS晶体管T17的输入端连接高电平信号源VGH。第八PMOS晶体管T18的输入端连接高电平信号源VGH，第八PMOS晶体管T18的输出端与传输门DC2的输出端连接，第八PMOS晶体管T18的控制端与第五反相放大器D5的输出端连接。
本优选实施例的GOA电路使用时，请参照图3，图3本发明的GOA电路的优选实施例的各信号的控制时序图。当STN-1为高电平，RST也为高电平，第一NMOS晶体管T21导通，第一PMOS晶体管 T11断开，低电平信号源VGL通过第一PMOS晶体管T11传输至第一反相放大器D1，第一反相放大器D1输出放大后的高电平信号至时钟反相器DC1。
时钟反相器DC1在高电平信号的控制下，对第一状态的时钟信号CK1（高电平状态）进行反相操作，输出低电平信号至第二反相放大器D2，第二反相放大器D2输出第一驱动模块11的高电平的本级级联信号STN，这时第四反相放大器D4输出第一驱动模块11的高电平的本级的扫描驱动信号GoutN。
随后高电平的本级级联信号STN传输至第二驱动模块12的第二驱动单元121，当STN为高电平，RST也为高电平，第二NMOS晶体管T22导通，第五PMOS晶体管 T15断开，低电平信号源VGL通过第一PMOS晶体管传输T15至第五反相放大器D5，第五反相放大器D5输出放大后的高电平信号至传输门DC2。
传输门DC2在高电平信号的控制下，对第二状态的时钟信号CK1（低电平状态）进行正相传输操作，输出低电平信号至第六反相放大器D6，第六反相放大器D6输出第二驱动模块12的高电平的本级级联信号STN+1，这时第八反相放大器D8输出第二驱动模块12的高电平的本级的扫描驱动信号GoutN+1。
同时第一驱动模块11中的时钟信号也转换为第二状态，这时时钟反相器DC1在高电平信号的控制下，对第二状态的时钟信号CK1（低电平状态）进行反相操作，输出高电平信号至第二反相放大器D2，第二反相放大器D2将第一驱动模块11的高电平的本级级联信号STN拉至低电平，这时第四反相放大器D4将第一驱动模块11的高电平的本级的扫描驱动信号GoutN也拉至低电平。
由于第一驱动模块11的本级级联信号STN为低电平且第一驱动模块11的上一级的级联信号STN-1也为低电平，第三PMOS晶体管T13以及第二PMOS晶体管T12均导通，第一NMOS晶体管T21断开，从而高电平信号源VGH通过第三PMOS晶体管T13以及第二PMOS晶体管T12对Qn进行充电，使得Qn回复到高电平状态。同时第五PMOS晶体管T15也导通，高电平信号源VGH通过第五PMOS晶体管T15同时保证了第二反相放大器D2的输入端也为高电平状态。这样即完成了第一驱动模块11的本级扫描驱动信号GoutN的产生过程。
随后第二驱动模块12中的时钟信号也转换为第一状态，这时传输门DC2在高电平信号的控制下，对第一状态的时钟信号CK1（高电平状态）进行正相传输操作，输出高电平信号至第六反相放大器D6，第六反相放大器D6将第二驱动模块12的高电平的本级级联信号STN+1拉至低电平，这时第八反相放大器D8将第二驱动模块的高电平的本级的扫描驱动信号GoutN+1也拉至低电平。
由于第二驱动模块12的本级级联信号STN+1为低电平且第二驱动模块12的上一级的级联信号STN也为低电平，第七PMOS晶体管T17以及第六PMOS晶体管T16均导通，第二NMOS晶体管T22断开，从而高电平信号源VGH通过第七PMOS晶体管T17以及第六PMOS晶体管T16对Qn+1进行充电，使得Qn+1回复到高电平状态。同时第八PMOS晶体管T18也导通，高电平信号源VGH通过第八PMOS晶体管T18同时保证了第六反相放大器D6的输入端也为高电平状态。这样即完成了第二驱动模块12的本级扫描驱动信号GoutN+1的产生过程。
请参照图4，图4为本发明的GOA电路的优选实施例的多个第一驱动模块以及多个第二驱动模块的具体电路图。该GOA电路的一第一驱动模块和一第二驱动模块形成一个驱动单元，如图4中的驱动单元41、驱动单元42以及驱动单元43，其中驱动单元41的输入信号为复位信号RST、时钟信号CK1以及级联信号STV，其中级联信号STV形成驱动单元41的第一驱动模块的上级级联信号STN-1。驱动单元41的输出信号为第一驱动模块的扫描驱动信号Gout1、第二驱动模块的扫描驱动信号Gout2以及第二驱动模块生成的下一级级联信号STN+1，即级联信号ST2。
驱动单元42的输入信号为复位信号RST、时钟信号CK1以及级联信号ST2，其中级联信号ST2形成驱动单元42的第一驱动模块的上级级联信号STN-1。驱动单元42的输出信号为第一驱动模块的扫描驱动信号Gout3、第二驱动模块的扫描驱动信号Gout4以及第二驱动模块生成的下一级级联信号STN+1，即级联信号ST4。
驱动单元43的输入信号为复位信号RST、时钟信号CK1以及级联信号ST4，其中级联信号ST4形成驱动单元43的第一驱动模块的上级级联信号STN-1。驱动单元43的输出信号为第一驱动模块的扫描驱动信号Gout5、第二驱动模块的扫描驱动信号Gout6以及第二驱动模块生成的下一级级联信号STN+1，即级联信号ST6。
这样即完成了多个驱动单元的级联驱动过程。
本发明还提供一种液晶显示面板，该液晶显示面板包括数据线、扫描线、由数据线和扫描线组成的像素单元以及相应的GOA电路。
该GOA电路包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块。
其中第一驱动模块包括第一驱动单元、第一输出单元以及第一复位单元。第二驱动模块包括第二驱动单元、第二输出单元以及第二复位单元。
第一驱动单元用于接收上一级的级联信号，并根据级联信号生成级联驱动信号以及复位信号。第一输出单元用于使用级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号。第一复位单元用于根据复位信号，消除本级的扫描驱动信号。
第二驱动单元用于接收上一级的级联信号，并根据级联信号生成级联驱动信号以及复位信号。第二输出单元用于使用级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号。第二复位单元用于根据复位信号，消除本级的扫描驱动信号。
其中第一状态的时钟信号以及第二状态的时钟信号的点位相反。
本发明的液晶显示面板的具体工作原理与上述的GOA电路的优选实施例中的描述相同或相似，具体请参见上述GOA电路的优选实施例中的相关描述。
本发明的GOA电路及液晶显示面板通过设置第一驱动模块和第二驱动模块共用时钟信号，从而缩小GOA电路的占据空间，便于液晶显示面板的窄边框设计；解决了现有的液晶显示面板中的GOA电路的占据空间较大，不利于液晶显示面板的窄边框设计的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种GOA电路，其包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
    其中所述第一驱动模块包括：
    第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
    第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    所述第二驱动模块包括：
    第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
    第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反；
    其中所述时钟信号以所述级联信号的传输周期进行状态变化；当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。
  2. 一种GOA电路，其包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
    其中所述第一驱动模块包括：
    第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
    第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    所述第二驱动模块包括：
    第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
    第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反。
  3. 根据权利要求2所述的GOA电路，其中所述第一驱动单元包括第一PMOS晶体管、第一NMOS晶体管以及第一反相放大器；
    所述第一PMOS晶体管的控制端连接复位信号源，所述第一PMOS晶体管的输入端连接高电平信号源，所述第一PMOS晶体管的输出端分别与所述第一反相放大器的输入端以及所述第一NMOS晶体管的输出端连接；
    所述第一NMOS晶体管的控制端输入所述上一级的级联信号，所述第一NMOS晶体管的输入端连接低电平信号源。
  4. 根据权利要求3所述的GOA电路，其中所述第一输出单元包括时钟反相器、第二反相放大器、第三反相放大器以及第四反相放大器；
    所述时钟反相器的控制端与所述第一驱动单元的输出连接，所述时钟反相器的输入端输入所述第一状态的时钟信号，所述时钟反相器的输出端与所述第二反相放大器的输入端连接；
    所述第二反相放大器的输出端与所述第三反相放大器的输入端连接，所述第三反相放大器的输出端与所述第四反相放大器的输入端连接，所述第四反相放大器的输出端输出所述本级的扫描驱动信号；所述第二反相放大器的输出端输出所述本级的级联信号。
  5. 根据权利要求4所述的GOA电路，其中所述第一复位单元包括第二PMOS晶体管、第三PMOS晶体管以及第四PMOS晶体管；
    所述第二PMOS晶体管的输出端与所述第一PMOS晶体管的输出端连接，所述第二PMOS晶体管的控制端输入所述上一级的级联信号，所述第二PMOS晶体管的输入端与所述第三PMOS晶体管的输出端连接；
    所述第三PMOS晶体管的控制端输入所述本级的级联信号；所述第三PMOS晶体管的输入端连接所述高电平信号源；
    所述第四PMOS晶体管的输入端连接所述高电平信号源，所述第四PMOS晶体管的输出端与所述时钟反相器的输出端连接，所述第四PMOS晶体管的控制端与所述第一反相放大器的输出端连接。
  6. 根据权利要求2所述的GOA电路，其中所述第二驱动单元包括第五PMOS晶体管、第二NMOS晶体管以及第五反相放大器；
    所述第五PMOS晶体管的控制端连接复位信号源，所述第五PMOS晶体管的输入端连接高电平信号源，所述第五PMOS晶体管的输出端分别与所述第五反相放大器的输入端以及所述第二NMOS晶体管的输出端连接；
    所述第二NMOS晶体管的控制端输入所述上一级的级联信号，所述第二NMOS晶体管的输入端连接低电平信号源。
  7. 根据权利要求6所述的GOA电路，其中所述第二输出单元包括传输门、第六反相放大器、第七反相放大器以及第八反相放大器；
    所述传输门的控制端与所述第二驱动单元的输出连接，所述传输门的输入端输入所述第一状态的时钟信号，所述传输门的输出端与所述第六反相放大器的输入端连接；
    所述第六反相放大器的输出端与所述第七反相放大器的输入端连接，所述第七反相放大器的输出端与所述第八反相放大器的输入端连接，所述第八反相放大器的输出端输出所述本级的扫描驱动信号；所述第六反相放大器的输出端输出所述本级的级联信号。
  8. 根据权利要求7所述的GOA电路，其中所述第二复位单元包括第六PMOS晶体管、第七PMOS晶体管以及第八PMOS晶体管；
    所述第六PMOS晶体管的输出端与所述第五PMOS晶体管的输出端连接，所述第六PMOS晶体管的控制端输入所述上一级的级联信号，所述第六PMOS晶体管的输入端与所述第七PMOS晶体管的输出端连接；
    所述第七PMOS晶体管的控制端输入所述本级的级联信号；所述第七PMOS晶体管的输入端连接所述高电平信号源；
    所述第八PMOS晶体管的输入端连接所述高电平信号源，所述第八PMOS晶体管的输出端与所述传输门的输出端连接，所述第八PMOS晶体管的控制端与所述第五反相放大器的输出端连接。
  9. 根据权利要求2所述的GOA电路，其中所述时钟信号以所述级联信号的传输周期进行状态变化。
  10. 根据权利要求2所述的GOA电路，其中当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。
  11. 一种液晶显示面板，其包括GOA电路，其中所述GOA电路包括用于对奇数行像素单元进行驱动的第一驱动模块以及对偶数行像素单元进行驱动的第二驱动模块；
    其中所述第一驱动模块包括：
    第一驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第一输出单元，用于使用所述级联驱动信号以及第一状态的时钟信号通过时钟反相器，生成本级的扫描驱动信号以及本级的级联信号；以及
    第一复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    所述第二驱动模块包括：
    第二驱动单元，用于接收上一级的级联信号，并根据所述级联信号生成级联驱动信号以及复位信号；
    第二输出单元，用于使用所述级联驱动信号以及第二状态的时钟信号通过传输门，生成本级的扫描驱动信号以及本级的级联信号；以及
    第二复位单元，用于根据所述复位信号，消除所述本级的扫描驱动信号；
    其中所述第一状态的时钟信号和所述第二状态的时钟信号的电位相反。
  12. 根据权利要求11所述的液晶显示面板，其中所述第一驱动单元包括第一PMOS晶体管、第一NMOS晶体管以及第一反相放大器；
    所述第一PMOS晶体管的控制端连接复位信号源，所述第一PMOS晶体管的输入端连接高电平信号源，所述第一PMOS晶体管的输出端分别与所述第一反相放大器的输入端以及所述第一NMOS晶体管的输出端连接；
    所述第一NMOS晶体管的控制端输入所述上一级的级联信号，所述第一NMOS晶体管的输入端连接低电平信号源。
  13. 根据权利要求12所述的液晶显示面板，其中所述第一输出单元包括时钟反相器、第二反相放大器、第三反相放大器以及第四反相放大器；
    所述时钟反相器的控制端与所述第一驱动单元的输出连接，所述时钟反相器的输入端输入所述第一状态的时钟信号，所述时钟反相器的输出端与所述第二反相放大器的输入端连接；
    所述第二反相放大器的输出端与所述第三反相放大器的输入端连接，所述第三反相放大器的输出端与所述第四反相放大器的输入端连接，所述第四反相放大器的输出端输出所述本级的扫描驱动信号；所述第二反相放大器的输出端输出所述本级的级联信号。
  14. 根据权利要求13所述的液晶显示面板，其中所述第一复位单元包括第二PMOS晶体管、第三PMOS晶体管以及第四PMOS晶体管；
    所述第二PMOS晶体管的输出端与所述第一PMOS晶体管的输出端连接，所述第二PMOS晶体管的控制端输入所述上一级的级联信号，所述第二PMOS晶体管的输入端与所述第三PMOS晶体管的输出端连接；
    所述第三PMOS晶体管的控制端输入所述本级的级联信号；所述第三PMOS晶体管的输入端连接所述高电平信号源；
    所述第四PMOS晶体管的输入端连接所述高电平信号源，所述第四PMOS晶体管的输出端与所述时钟反相器的输出端连接，所述第四PMOS晶体管的控制端与所述第一反相放大器的输出端连接。
  15. 根据权利要求11所述的液晶显示面板，其中所述第二驱动单元包括第五PMOS晶体管、第二NMOS晶体管以及第五反相放大器；
    所述第五PMOS晶体管的控制端连接复位信号源，所述第五PMOS晶体管的输入端连接高电平信号源，所述第五PMOS晶体管的输出端分别与所述第五反相放大器的输入端以及所述第二NMOS晶体管的输出端连接；
    所述第二NMOS晶体管的控制端输入所述上一级的级联信号，所述第二NMOS晶体管的输入端连接低电平信号源。
  16. 根据权利要求15所述的液晶显示面板，其中所述第二输出单元包括传输门、第六反相放大器、第七反相放大器以及第八反相放大器；
    所述传输门的控制端与所述第二驱动单元的输出连接，所述传输门的输入端输入所述第一状态的时钟信号，所述传输门的输出端与所述第六反相放大器的输入端连接；
    所述第六反相放大器的输出端与所述第七反相放大器的输入端连接，所述第七反相放大器的输出端与所述第八反相放大器的输入端连接，所述第八反相放大器的输出端输出所述本级的扫描驱动信号；所述第六反相放大器的输出端输出所述本级的级联信号。
  17. 根据权利要求16所述的液晶显示面板，其中所述第二复位单元包括第六PMOS晶体管、第七PMOS晶体管以及第八PMOS晶体管；
    所述第六PMOS晶体管的输出端与所述第五PMOS晶体管的输出端连接，所述第六PMOS晶体管的控制端输入所述上一级的级联信号，所述第六PMOS晶体管的输入端与所述第七PMOS晶体管的输出端连接；
    所述第七PMOS晶体管的控制端输入所述本级的级联信号；所述第七PMOS晶体管的输入端连接所述高电平信号源；
    所述第八PMOS晶体管的输入端连接所述高电平信号源，所述第八PMOS晶体管的输出端与所述传输门的输出端连接，所述第八PMOS晶体管的控制端与所述第五反相放大器的输出端连接。
  18. 根据权利要求11所述的液晶显示面板，其中所述时钟信号以所述级联信号的传输周期进行状态变化。
  19. 根据权利要求11所述的液晶显示面板，其中当所述复位信号为低电平时，对相应的所述第一驱动模块或相应的所述第二驱动模块进行复位操作。
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