WO2018018353A1 - 阵列基板及阵列基板的制造方法 - Google Patents

阵列基板及阵列基板的制造方法 Download PDF

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Publication number
WO2018018353A1
WO2018018353A1 PCT/CN2016/091528 CN2016091528W WO2018018353A1 WO 2018018353 A1 WO2018018353 A1 WO 2018018353A1 CN 2016091528 W CN2016091528 W CN 2016091528W WO 2018018353 A1 WO2018018353 A1 WO 2018018353A1
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Prior art keywords
layer
array substrate
hole
transmission line
signal transmission
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Ceased
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PCT/CN2016/091528
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English (en)
French (fr)
Inventor
袁泽
余晓军
古普塔阿米特
赵继刚
魏鹏
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to KR1020197003074A priority Critical patent/KR102221442B1/ko
Priority to CN201680015886.4A priority patent/CN107454981A/zh
Priority to PCT/CN2016/091528 priority patent/WO2018018353A1/zh
Priority to JP2019503520A priority patent/JP6752354B2/ja
Publication of WO2018018353A1 publication Critical patent/WO2018018353A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to an array substrate and a method of fabricating the array substrate.
  • a thin film transistor As a switching element, a thin film transistor (TFT) is widely used in electronic display devices such as liquid crystal display (LCD) and organic light-emitting diode (OLED).
  • a thin film transistor generally includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, etc., wherein a high quality gate insulating layer is an important parameter for realizing good electrical stability and small leakage current of the thin film transistor. key.
  • the gate insulating layer is mainly prepared by a plasma chemical vapor deposition method using an inorganic non-metal material (for example, SiO x , SiN x , etc.).
  • the gate insulating layer Due to the characteristics of the gate insulating layer and the limitation of the preparation conditions, the gate insulating layer usually has internal stress, and the gate insulating layer prepared by brittle SiO x , SiN x or the like is easily broken by internal stress; in particular, In a flexible display, the presence of internal stress also causes deformation of a layer structure of a flexible substrate, a gate insulating layer, and the like in a thin film transistor.
  • the present invention provides an array substrate, the array substrate comprising: a substrate, a signal transmission line and a gate disposed on the substrate, an insulating layer covering the signal transmission line and the gate, and An active layer on the insulating layer and a first metal layer, wherein a gap is formed between the gate and the signal transmission line; an isolation trench and a via hole are formed in the insulating layer, and the first metal layer
  • the signal transmission line is electrically connected through the through hole, and the isolation groove is disposed between the signal transmission line and the gate.
  • the array substrate further includes an organic layer disposed on the insulating layer and filling the isolation trench.
  • the array substrate further includes a second metal layer, the second metal layer being electrically connected to both ends of the active layer to form a source Pole and drain.
  • the first metal layer and the second metal layer are in a unitary structure.
  • the array substrate further includes an inorganic layer, the inorganic layer covering the active layer and the insulating layer; a first through hole, a second through hole, a third through hole and a fourth through hole; the first through hole is in communication with the through hole for conducting the signal transmission line and the first metal layer; The second through hole is in communication with the isolation groove; the third through hole and the fourth through hole are respectively disposed corresponding to both ends of the active layer for conducting the active layer and the source a pole and the drain.
  • the organic layer covers the inorganic layer; the organic layer defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein The fifth through hole is disposed corresponding to the first through hole and communicates with the first through hole for conducting the signal transmission line and the first metal layer; the sixth through hole corresponds to the a third through hole is disposed and communicates with the third through hole; the seventh through hole is disposed corresponding to the fourth through hole and communicates with the fourth through hole; the sixth through hole and the seventh through hole A via hole is used to turn on the active layer and the source and the drain.
  • the surface of the organic layer facing away from the substrate is flush with the end surface of the insulating layer facing away from the substrate.
  • the array substrate further includes a protective layer and a pixel electrode, the protective layer covering the first metal layer and the second metal And forming a second via hole; the second via hole is disposed corresponding to the source; the pixel electrode covers the protective layer, and is electrically connected to the source through the second via hole.
  • the array substrate further includes an inorganic layer and a pixel electrode, the inorganic layer covering the first metal layer and the second metal layer And an eighth through hole corresponding to the source; the organic layer covers the inorganic layer, and a third through hole is opened corresponding to the eighth through hole; the pixel electrode covers the organic layer, and passes through The eighth through hole and the third through hole are electrically connected to the source.
  • the inorganic layer further defines a ninth through hole corresponding to the isolation groove, and the ninth through hole communicates with the isolation groove.
  • the array substrate further includes a buffer layer covering the substrate, the signal transmission line and the The gate is disposed on the buffer layer.
  • the buffer layer corresponds to The isolation groove defines a groove, and the groove communicates with the isolation groove, and the height of the groove is less than or equal to a thickness of the buffer layer.
  • the isolation trench is parallel to a warp axis of the array substrate.
  • the array substrate of the present invention can provide an isolation trench on the insulating layer, and the isolation trench can release the internal stress in the insulating layer, thereby preventing the brittle insulating layer from being broken by the internal stress and reducing the thin film transistor.
  • the deformation of the layer structure of the flexible substrate and the insulating layer improves the flexibility of the array substrate.
  • the insulating layer of the array substrate may further include an organic layer filling the isolation trench, the structure of the array substrate may be planarized, and the flexibility of the array substrate may be improved; the array substrate may further include an inorganic layer covering the active layer, and Protecting the active layer from contact with the plasma during plasma etching to form the via hole and the isolation trench; the array substrate may further include a protective layer that blocks oxygen in the external air to prevent The first metal layer and the second metal layer are oxidized and serve to support the structure of the array substrate.
  • the present invention also provides a method of fabricating an array substrate, the method comprising:
  • An organic layer in the via hole is removed, and a first metal layer is deposited in the via hole to conduct the signal transmission line.
  • the covering the organic layer on the insulating layer further includes:
  • the removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes:
  • Removing a portion of the organic layer on the active layer to expose the active layer, the organic layer and the A second metal layer is deposited on the active layer to form a source and a drain.
  • the method further includes:
  • the etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose a portion of the data line further comprises: etching the inorganic layer;
  • the removing a portion of the organic layer on the active layer to expose the active layer further includes removing a portion of the inorganic layer on the active layer.
  • the method further includes:
  • a conductive layer is deposited on the protective layer, the source, and the drain to form a pixel electrode, and the drain is electrically connected to the pixel electrode.
  • the method further includes:
  • a conductive layer is deposited on the organic layer to form a pixel electrode, and the source or drain is electrically connected to the pixel electrode.
  • the method further includes:
  • the removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes: depositing a second on the organic layer and the active layer The metal layer forms a source and a drain.
  • the method further includes:
  • a conductive layer is deposited on the source and the protective layer to form a pixel electrode, and the source is electrically connected to the pixel electrode.
  • the forming the signal transmission line and the gate on the substrate includes:
  • a buffer layer is deposited on the substrate, and the signal transmission line and the gate are formed on the buffer layer.
  • the etching the insulating layer to form the isolation trench further includes: partially etching the buffer layer corresponding to the isolation trench.
  • the method for fabricating an array substrate comprises forming a signal transmission line and a gate on a substrate, a gap is provided between the signal transmission line and the gate; and the signal transmission line and the gate are Forming an insulating layer on the electrode; forming an active layer on the insulating layer, etching the insulating layer to form an isolation trench, and etching the insulating layer to form a via hole to expose the signal transmission line; covering the insulating layer with an organic layer Wherein the organic layer fills the isolation trench and the via, and removes an organic layer in the via, and deposits a first metal layer in the via to turn on the signal transmission line.
  • the isolation trench and the via hole for connecting the signal transmission line may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and forming the isolation trench to release internal stress in the insulating layer, thereby preventing brittleness.
  • the insulating layer is broken by the internal stress, and the deformation of the layer structure of the flexible substrate and the insulating layer in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the organic layer may further planarize the structure of the array substrate; and the inorganic layer covering the active layer may protect the through hole and the isolation trench during plasma etching
  • the active layer prevents the active layer from contacting the plasma and improves the electrical performance of the array substrate;
  • the array substrate may further include an organic layer to block oxygen in the environment, prevent oxidation of each electrode inside the array substrate, and may serve as a support. Stabilizing the structure of the array substrate.
  • FIG. 1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of an array substrate in a second state according to a preferred embodiment of the present invention
  • FIG. 3 is a cross-sectional structural view of an array substrate in a third state according to a preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional structural view of an array substrate in a fourth state according to a preferred embodiment of the present invention.
  • FIG. 5 is a cross-sectional structural view of an array substrate in a fifth state according to a preferred embodiment of the present invention.
  • FIG. 6 is a cross-sectional structural view of an array substrate in a sixth state according to a preferred embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention.
  • FIG. 8 is a cross-sectional structural view of an array substrate in an eighth state according to a preferred embodiment of the present invention.
  • FIG. 9 is a cross-sectional structural view of an array substrate in a ninth state according to a preferred embodiment of the present invention.
  • FIG. 10 is a cross-sectional structural view of an array substrate in a tenth state according to a preferred embodiment of the present invention.
  • FIG. 11 is a schematic structural view showing the distribution of isolation trenches in an array substrate according to a preferred embodiment of the present invention.
  • FIG. 12 is a flow chart showing a method of fabricating an array substrate according to a first preferred embodiment of the present invention
  • FIGS. 13A to 13G are schematic views showing respective preparation steps in a method for preparing an array substrate according to a first preferred embodiment of the present invention
  • FIG. 14 is a flow chart showing a method of fabricating an array substrate according to a second preferred embodiment of the present invention.
  • 15A to 15H are schematic views showing respective preparation steps in a method for preparing an array substrate according to a second preferred embodiment of the present invention.
  • 16 is a flow chart showing a method of fabricating an array substrate according to a third preferred embodiment of the present invention.
  • 17A to 17H are schematic views showing respective preparation steps in a method of fabricating an array substrate according to a third preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention.
  • the array substrate includes:
  • a substrate 110 a signal transmission line 120 and a gate 130 disposed on the substrate 110, an insulating layer 140 covering the signal transmission line 120 and the gate 130, an active layer 150 disposed on the insulating layer 140, and a first metal layer 160, wherein a gap is formed between the gate 130 and the signal transmission line 120; an isolation trench 1401 and a via hole 1402 are defined in the insulating layer 140, and the first metal layer 160 passes through the The via hole 1402 is electrically connected to the signal transmission line 120, and the isolation trench 1401 is disposed between the signal transmission line 120 and the gate 130.
  • the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress.
  • the rupture reduces the deformation of the layer structure of the flexible substrate 110 and the insulating layer 140 in the thin film transistor, and improves the flexibility of the array substrate.
  • FIG. 2 is a cross-sectional structural diagram of an array substrate in a second state according to a preferred embodiment of the present invention.
  • the array substrate further includes an organic layer 170 disposed on the insulating layer 140 and filling the isolation trench 1401.
  • the isolation trench 1401 is filled with a flexible insulating material, which may be a polymer material, the flexible insulating material does not affect the flexibility of the array substrate, and may serve as a support;
  • the organic layer 170 can planarize the structure of the array substrate, so that the arrangement of the isolation trenches does not bring about an increase in the step structure in the array substrate structure, and the organic layer 170 can make the structure of the entire array substrate more stable and improve the bending flexibility of the array substrate. .
  • FIG. 3 is a cross-sectional structural view of the array substrate in a third state according to a preferred embodiment of the present invention.
  • the array substrate further includes a second metal layer, and the second metal layer is electrically connected to both ends of the active layer 150 to form a source 1601 and a drain 1602.
  • the first metal layer 160 and the second metal layer are integrated structures to reduce the arrangement of the outer pins in the array substrate.
  • the array substrate further includes an inorganic layer 180.
  • FIG. 4 is a cross-sectional structural view of the array substrate in a fourth state according to a preferred embodiment of the present invention.
  • the inorganic layer 180 covers the active layer 150 and the insulating layer 140; the inorganic layer 180 is provided with a first through hole, a second through hole, a third through hole and a fourth through hole; a through hole communicating with the through hole 1402 for conducting the signal transmission line 120 and the first metal layer 160; the second through hole communicating with the isolation groove 1401; the third through hole and the The fourth through holes are respectively disposed corresponding to both ends of the active layer 150 for conducting the active layer 150 and the source 1601 and the drain 1602.
  • the organic layer 170 covers the inorganic layer 180; the organic layer 170 defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein the fifth through hole corresponds to the first a through hole is disposed in communication with the first through hole for conducting the signal transmission line 120 and the first metal layer 160; the sixth through hole is disposed corresponding to the third through hole and is opposite to the first through hole
  • the three through holes are connected to the fourth through holes and are in communication with the fourth through holes; the sixth through holes and the seventh through holes are used to conduct the active Layer 150 is coupled to source 1601 and drain 1602.
  • the material of the inorganic layer 180 may be that when the through hole 1402 and the isolation trench 1401 are formed by plasma etching, the active layer 150 is protected from contacting the active layer 150 with the plasma.
  • FIG. 5 is a cross-sectional structural view of the array substrate in a fifth state according to a preferred embodiment of the present invention.
  • the surface of the organic layer 170 facing away from the substrate 110 is flush with the end surface of the insulating layer 140 facing away from the substrate 110.
  • the array substrate further includes a protective layer 190 and a pixel electrode.
  • FIG. 6 is a cross-sectional structural view of the array substrate in a sixth state according to a preferred embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention.
  • the protective layer 190 covers the first metal layer 160 and the second metal layer, and defines a second via hole 1402; the second via hole 1402 is disposed corresponding to the source 1601;
  • the protective layer 190 is electrically connected to the source 1601 through the second via 1402.
  • the protective layer 190 may be a material of the organic insulating layer 140, such as a resin or a polymer material, and the pixel electrode 200 is a transparent conductive film such as an indium tin oxide film (ITO film).
  • ITO film indium tin oxide film
  • FIG. 8 is a cross-sectional structural view of the array substrate in an eighth state according to a preferred embodiment of the present invention.
  • the array substrate further includes an inorganic layer 180 and a pixel electrode, the inorganic layer 180 covers the first metal layer 160 and the second metal layer, and an eighth is opened corresponding to the source 1601. a through hole; the organic layer 170 covers the inorganic layer 180, and a third through hole 1402 is defined corresponding to the eighth through hole; the pixel electrode covers the organic layer 170, and passes through the eighth through hole And the third via hole 1402 is electrically connected to the source 1601.
  • the material of the inorganic layer 180 in the embodiment may be an inorganic insulating material, such as any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , Si 3 N 4 , and the like. Each electrode covered by the inorganic layer 180 can be protected.
  • FIG. 9 is a cross-sectional structural view of the array substrate in a ninth state according to a preferred embodiment of the present invention.
  • the inorganic layer 180 further defines a ninth through hole corresponding to the isolation trench 1401.
  • the ninth through hole is in communication with the isolation groove 1401.
  • the array substrate further includes a buffer layer 210 covering the substrate 110 , and the signal transmission line 120 and the gate 130 are disposed on the buffer layer 210 .
  • FIG. 10 is a cross-sectional structural view of the array substrate in a tenth state according to a preferred embodiment of the present invention.
  • the buffer layer 210 defines a recess corresponding to the isolation trench 1401, and the recess communicates with the isolation trench 1401, and the height of the recess is less than or equal to the thickness of the buffer layer 210.
  • the isolation trench 1401 is parallel to the winding axis of the array substrate. Thereby, the flexibility of the array substrate is improved, so that the array substrate can obtain greater curvature.
  • the isolation trench can be a rectangular parallelepiped structure, a trapezoidal structure, a semi-cylindrical structure, etc., and the isolation trenches can be located in each pixel unit in the array substrate, or can be distributed in some pixel units according to a preset pattern.
  • the isolation trench is parallel to the winding axis of the array substrate.
  • FIG. 11 is a schematic structural view showing the distribution of the isolation trenches in the array substrate according to a preferred embodiment of the present invention, and FIG. 11 is a surface of the deposited thin film from the array substrate. Schematic diagram of the distribution of the isolation trenches in the array substrate when viewed from above. As shown in FIG.
  • the array substrate may include a plurality of pixel units, such as a first pixel unit 1101, a second pixel unit 1102, a third pixel unit 1103, and a fourth.
  • a pixel unit 1104 or the like each of the pixel units includes a thin film transistor that controls a switching state of the pixel unit, and each of the thin film transistors in the array substrate can
  • the structure of the array substrate is as shown in FIG. 1-10.
  • the isolation trench 1105 can be a rectangular parallelepiped structure.
  • the curling axis of the array substrate is parallel to the long side of the isolation trench 1105.
  • the isolation trench 1105 can also be disposed on the edge of the array substrate.
  • the intermediate isolation grooves 1105 of the respective pixel units in the winding axis direction may be connected or may be spaced apart.
  • the substrate 110 may be a glass substrate or a flexible substrate prepared from a polymer material;
  • the signal transmission line 120 may be a data line or a voltage line; in the present invention, the signal transmission line 120 and the gate 130
  • the material includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, etc.;
  • the material of the insulating layer 140 may be HfO 2 , Any one or more of materials such as ZrO 2 , Al 2 O 3 , SiO 2 , Si 3 N 4 , etc.;
  • the active layer 150 includes a channel layer, a first doped region, and a second doped region.
  • the first doped region and the second doped region are both in contact with the channel layer, and the first doped region and the second doped region are spaced apart.
  • the material of the first metal layer 160 or the second metal layer may include any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like.
  • the first electrode 150 may be electrically connected to the second electrode 160 or the third electrode 170 through an outer lead, and the first metal layer 160 and the second metal layer may also be a unitary structure.
  • the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress.
  • the rupture reduces deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.
  • the insulating layer 140 of the array substrate may further include an organic layer 150 filling the isolation trenches, which can planarize the structure of the array substrate and improve the flexibility of the array substrate; the array substrate may further include an inorganic layer covering the active layer 150.
  • the layer 180 may protect the active layer 150 from contact with the plasma when the via hole 1402 and the isolation trench 1401 are formed by plasma etching; the array substrate may further include a protective layer 190, the protective layer The 190 can block oxygen in the external air, prevent oxidation of the first metal layer 160 and the second metal layer, and can serve as a support to stabilize the structure of the array substrate.
  • FIG. 12 is a flowchart of a method for fabricating an array substrate according to a first preferred embodiment of the present invention.
  • the method for preparing the array substrate includes:
  • Step S1210 Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. See Figure 13A.
  • a metal layer such as a gold (Au) layer may be deposited on the substrate 110 by a physical vapor deposition method, and the metal layer is patterned by a photomask and an etching process to form a signal transmission line 120 and a gate electrode 130.
  • Au gold
  • the method further includes: forming a buffer layer 210, the buffer layer 210 is disposed on the first surface of the substrate 110, and the signal transmission line 120 is disposed on the buffer layer
  • the surface of the substrate 110 is away from the surface of the substrate 110; the gate electrode 130 is disposed on a surface of the buffer layer 210 facing away from the substrate 110.
  • the buffer layer 210 may be an inorganic insulating material or a polymer insulating material.
  • the method of forming the buffer layer 210 may be a method such as chemical vapor deposition or physical vapor deposition.
  • the material of the signal transmission line 120 and the gate electrode 130 may be any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like. .
  • Step S1220 forming an insulating layer 140 on the signal transmission line 120 and the gate 130.
  • an insulating layer 140 may be deposited on the signal transmission line 120 and the gate 130 by a physical vapor deposition method.
  • the material of the insulating layer 140 may be HfO 2 , ZrO 2 , Al. Any one or more of 2 O 3 , SiO 2 , Si 3 N 4 and the like.
  • Step S1230 forming an active layer 150 on the insulating layer 140. See Figure 13C.
  • the active layer 150 is a semiconductor material, and the active layer 150 includes a channel layer, a first doped region, and a second doped region, and the first doped region and the second doped region are both Contacting the channel layer, and the first doped region is spaced apart from the second doped region.
  • the preparation technique of the active layer 150 is prior art, and the present invention is not described herein.
  • Step S1240 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120.
  • the insulating layer 140 may be patterned by a photomask and an etching process to form isolation trenches 1401 and vias 1402.
  • a photoresist layer is coated on the surface of the insulating layer 140 facing away from the substrate; the photoresist layer is patterned, and a portion of the photoresist layer covering the insulating layer 140 is removed;
  • the photoresist layer is plasma etched by the photoresist layer as a mask to form the isolation trench 1401 and the via hole 1402 as shown in FIG. 13D.
  • the remaining photoresist layer is stripped.
  • the remaining photoresist layer may be peeled off with an organic solvent such as acetone.
  • Step S1250 covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, see FIG. 13E.
  • the insulating layer 140 may be covered with an organic layer 170 by physical vapor deposition, chemical vapor deposition, or spin coating.
  • the organic layer 170 may be made of a polymer material.
  • Step S1260 removing the organic layer 170 in the via hole 1402.
  • a first metal layer 160 is deposited in the via hole 1402 to turn on the signal transmission line 120. See the array shown in FIG. 13G. Substrate.
  • the organic layer 170 may be wet etched by a photomask and an etching process to remove the organic layer 170 in the via hole 1402; when the organic layer 170 is a photosensitive organic material, the organic layer 170 may also be masked. Partial exposure removes the organic layer 170 in the via 1402 to form a patterned organic layer 170.
  • the first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120 by physical vapor deposition.
  • step S1260 may further include: removing a portion of the organic layer 170 on the active layer 150 to expose the active layer 150, depositing a layer on the organic layer 170 and the active layer 150.
  • the two metal layers form a source 1601 and a drain 1602. See the array substrate shown in FIG.
  • the organic layer 170 on the active layer 150 may be wet etched by a mask and an etching process to remove a portion of the organic layer 170 to expose the active layer 150; when the organic layer 170 is a photosensitive organic material, The organic layer 170 may also be partially exposed by a photomask to remove the organic layer 170 in the via 1402 to expose the active layer 150 to form a patterned organic layer 170.
  • both ends of the active layer 150 are etched or exposed, and the first doped region and the second doped region of the active layer 150 are leaked out.
  • a second metal layer may be formed on a surface of the active layer 150 or a surface of the organic layer 170, and then the second metal layer is patterned by a photomask and an etching process to form a source 1601 and a drain 1602. . See the array substrate described in FIG.
  • the first metal layer 160 and the second metal layer may be integrally formed, wherein the first metal layer 160 may turn on the source 1601. See the array substrate described in FIG. Specifically, a first metal layer 160 may be deposited in the via hole 1402, and the first metal layer 160 is patterned to form the source 1601 and The drain 1602, wherein the source 1601 turns on the signal transmission line 120.
  • the method of manufacturing the array substrate may further include: forming an inorganic layer 180 on the active layer 150 and the insulating layer 140; step S1240 further includes: etching The inorganic layer 180 causes the via hole 1402 to penetrate the inorganic layer 180.
  • Step S1260 further includes: removing a portion of the inorganic layer 180 on the active layer 150 to expose the first doped region and the second doped region of the active layer 150, as shown in FIG. 4 The array substrate shown.
  • the inorganic layer 180 may be any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , and Si 3 N 4 .
  • the method for manufacturing the array substrate may further include: forming a protective layer 190 on the first metal layer 160 and the second metal layer; patterning the protective layer 190 to form a via hole The drain 1602 is exposed; a conductive layer 200 is deposited on the protective layer 190, the source 1601, and the drain 1602 to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode. See the array substrate shown in Figure 6 or Figure 8.
  • the protective layer 190 may be a material such as a polymer or a rubber.
  • the protective layer 190 can be patterned using a mask and a wet etch process to form vias to expose the drain 1602.
  • a conductive layer 200 may be deposited on the protective layer 190, the source 1601, and the drain 1602 by physical vapor deposition to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode, wherein
  • the conductive layer 200 is a transparent conductive film such as tin-doped indium trioxide (ITO), aluminum-doped zinc oxide (AZO), or the like.
  • the etching in the present invention may include dry etching and wet etching, and the dry etching gas may be CF4, SF6 or a mixed gas of CL2 and O2, and the wet etching liquid may be oxalic acid or sulfuric acid. , hydrochloric acid, or a mixture of oxalic acid, sulfuric acid and hydrochloric acid.
  • the patterning refers to a patterning process, which may include a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, and the like for forming a predetermined pattern.
  • the lithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the display device formed by the method for manufacturing the array substrate of the embodiment of the invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital photo frame, Mobile phones, etc.
  • the method for fabricating the array substrate forms a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130;
  • An insulating layer 140 is formed on the transmission line 120 and the gate 130;
  • an active layer 150 is formed on the insulating layer 140, the insulating layer 140 is etched to form an isolation trench 1401, and the insulating layer 140 is etched to form a via hole 1402 to be exposed.
  • the signal transmission line 120 covering the insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, and removes the organic layer 170 in the via hole 1402, and A first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release the internal stress in the insulating layer 140. Therefore, the brittle insulating layer 140 is prevented from being broken by the internal stress, and the deformation of the layer structure of the flexible substrate 110, the insulating layer 140, and the like in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the organic layer 170 may also planarize the structure of the array substrate; the inorganic layer 180 covering the active layer 150 may form the via hole 1402 and the isolation trench 1401 by plasma etching.
  • the active layer 150 is protected from contact with the plasma to improve the electrical performance of the array substrate.
  • the array substrate may further include an organic layer 170 to block oxygen in the environment and prevent internal electrodes of the array substrate. Oxidized and supported to stabilize the structure of the array substrate.
  • FIG. 14 is a flowchart of a method for fabricating an array substrate according to a second preferred embodiment of the present invention.
  • the method for fabricating the array substrate includes:
  • step S1410 a signal transmission line 120 and a gate 130 are formed on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 15A.
  • Step S1420 forming an insulating layer 140 on the signal transmission line 120 and the gate 130. Please refer to FIG. 15B.
  • Step S1430 forming an active layer 150 on the insulating layer 140. Please refer to FIG. 15C.
  • Step S1440 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 15D.
  • Step S1450 depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120, and depositing a second metal layer on the active layer 150, and patterning the second metal layer to form Source 1601 and drain 1602. Please refer to Figure 15E.
  • Step S1460 covering the first metal layer 160 and the second metal layer insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401, please refer to FIG. 15F.
  • the method may further include: etching the organic layer 170 to expose the source 1601, see FIG. 15G; depositing a conductive layer on the source 1601 and the organic layer 170 200, forming a pixel electrode, the source 1601 or the drain 1602 being electrically connected to the pixel electrode, please refer to FIG. 15H.
  • the method further includes: covering the first metal layer 160 and the second metal layer with the inorganic layer 180. Please refer to Figure 9.
  • the method for fabricating the array substrate forms an insulating layer 140 on the signal transmission line 120 and the gate 130 by forming spaced-apart signal transmission lines 120 and a gate 130 on the substrate 110.
  • the active layer 150 is formed by etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed together by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 may release the insulating layer 140.
  • the internal stress thereby preventing the brittle insulating layer 140 from being broken by the internal stress, reduces the deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.
  • the method for fabricating the array substrate provided by the present invention may include covering the first metal layer 160 and the inorganic layer 180 of the second metal to prevent oxidation of the metal.
  • FIG. 16 is a method for preparing an array substrate according to a third preferred embodiment of the present invention.
  • the preparation method of the array substrate described with reference to FIGS. 17A to 17H including:
  • Step S1610 Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 17A.
  • Step S1620 forming an insulating layer 140 on the signal transmission line 120 and the gate 130, please refer to FIG. 17B.
  • Step S1630 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 17C.
  • Step S1640 covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, please refer to FIG. 17D.
  • Step S1650 removing the organic layer 170 on a portion of the insulating layer 140 to expose the insulating layer 140. Please refer to FIG. 17E.
  • Step S1660 forming an active layer 150 on the insulating layer 140; please refer to FIG. 17F.
  • Step S1670 removing the organic layer 170 in the via hole 1402, and depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120.
  • the organic layer 170 in the via hole 1402 is removed to leak out the signal transmission line 120. Please refer to FIG. 17G.
  • a second metal layer is formed on the organic layer 170 and the active layer 150 to form a source 1601 and a drain 1602. Please refer to Figure 17H.
  • a protective layer 190 is formed on the first metal layer 160, the organic layer 170, and the second metal layer; the protective layer 190 is etched to expose the source 1601; The conductive layer 200 is deposited on the source electrode 1601 and the protective layer 190 to form a pixel electrode, and the source electrode 1601 is electrically connected to the pixel electrode.
  • a signal transmission line 120 and a gate electrode 130 are formed on the substrate 110, and an insulating layer 140 is formed on the signal transmission line 120 and the gate electrode 130.
  • the insulating layer 140 is etched to form the isolation trench 1401 and the insulating layer is etched.
  • the through hole 1402 is formed to expose the signal transmission line 120, and the organic layer 170 is covered on the insulating layer 140, wherein the organic layer 170 fills the isolation trench 1401 And the via hole 1402, removing the organic layer 170 on a part of the insulating layer 140 to expose the insulating layer 140, forming a planarized organic layer 170, which can serve as a support and form on the insulating layer 140.
  • the active layer 150 removes the organic layer 170 in the via hole 1402 and deposits a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 can be simultaneously formed by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing brittleness.
  • the insulating layer 140 is broken by the internal stress, and the deformation of the layer structure of the substrate 110, the insulating layer 140 of the gate electrode 130 in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the protective layer 190 can block oxygen in the environment, prevent oxidation of the respective electrodes inside the array substrate, and can serve as a support to stabilize the structure of the array substrate.

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Abstract

一种阵列基板以及阵列基板的制造方法，所述阵列基板包括基板（110）、信号传输线（120）、栅极（130）、第一绝缘层（140）、有源层（150）、第一电极（1601）、第二电极（1602）以及第三电极（200），其中，第一绝缘层（140）包括第一绝缘部和第二绝缘部，覆盖所述信号传输线（120）的所述第一绝缘部与覆盖所述栅极（130）的所述第二绝缘部之间设有隔离槽（1401），所述隔离槽（1401）可以释放第一绝缘层（140）中的内应力，从而防止脆性的第一绝缘层（140）在内应力的作用下容易破裂，减少薄膜晶体管中柔性基板（110）、第一绝缘层（140）等层结构的变形，提高阵列基板的柔韧性。其中，隔离槽（1401）和用于连接第一电极（1601）和信号传输线（120）的第一通孔（1402）可以经过一次光罩和刻蚀工艺一起形成，简化阵列基板的工艺步骤，降低生产成本。

Description

阵列基板及阵列基板的制造方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种阵列基板及阵列基板的制造方法。
背景技术
随着薄膜晶体管(thin film transistor，TFT)作为一种开关元件广泛应用于液晶显示(Liquid Crystal Display，LCD)、有机电激光显示(Organic Light-Emitting Diode，OLED)等电子显示器件中。薄膜晶体管一般包含栅极、栅极绝缘层、有源层、源漏极等部分，其中，高质量的栅极绝缘层是实现薄膜晶体管的好的电稳定性、较小的漏电流等重要参数的关键。栅极绝缘层主要通过无机非金属材料，(例如，SiOx、SiNx等)采用等离子体化学气相沉积的方法制备。由于栅极绝缘层本身特性以及制备条件的限制，通常栅极绝缘层内部具有内应力，脆性的SiOx、SiNx等材料制备的栅极绝缘层在内应力的作用下容易破裂；尤其，在柔性显示器中，内应力的存在也会导致薄膜晶体管中柔性基板、栅极绝缘层等层结构的变形。
发明内容
第一方面，本发明提供了一种阵列基板，所述阵列基板包括：基板、设于所述基板上的信号传输线和栅极、覆盖所述信号传输线和所述栅极的绝缘层、设于所述绝缘层上的有源层以及第一金属层，其中，所述栅极与所述信号传输线之间设有间隙；所述绝缘层上开设隔离槽和通孔，所述第一金属层通过所述通孔与所述信号传输线导通，所述隔离槽设于所述信号传输线与所述栅极之间。
结合第一方面，在第一方面第一种实现中，所述阵列基板还包括有机层，所述有机层设于所述绝缘层上，且填充所述隔离槽。
结合第一方面第一种实现，在第一方面第二种实现中，所述阵列基板还包括第二金属层，所述第二金属层与所述有源层的两端导通，形成源极和漏极。
结合第一方面第二种实现，在第一方面第三种实现中，所述第一金属层和所述第二金属层为一体结构。
结合第一方面第三种实现，在第一方面第四种实现中，所述阵列基板还包括无机层，所述无机层覆盖所述有源层和所述绝缘层；所述无机层开设有第一贯孔、第二贯孔、第三贯孔及第四贯孔；所述第一贯孔与所述通孔连通，用于导通所述信号传输线与所述第一金属层；所述第二贯孔与所述隔离槽连通；所述第三贯孔及所述第四贯孔分别对应所述有源层的两端设置，用于导通所述有源层与所述源极和所述漏极。
结合第一方面第四种实现，在第一方面第五种实现中，所述有机层覆盖所述无机层；所述有机层开设第五贯孔、第六贯孔以及第七贯孔，其中，所述第五贯孔对应所述第一贯孔设置且与所述第一贯孔连通，用于导通所述信号传输线与所述第一金属层；所述第六贯孔对应所述第三贯孔设置且与所述第三贯孔连通；所述第七贯孔对应所述第四贯孔设置且与所述第四贯孔连通；所述第六贯孔和所述第七贯孔用于导通所述有源层与所述源极和所述漏极。
结合第一方面第二种实现，在第一方面第六种实现中，所述有机层背离所述基板的表面与所述绝缘层背离所述基板的端面齐平。
结合第一方面第二至六种实现，在第一方面第七种实现中，所述阵列基板还包括保护层以及像素电极，所述保护层覆盖所述第一金属层和所述第二金属层，并开设第二通孔；所述第二通孔对应所述源极设置；所述像素电极覆盖所述保护层，并通过所述第二通孔与所述源极导通。
结合第一方面第二种实现，在第一方面第八种实现中，所述阵列基板还包括无无机层和像素电极，所述无机层覆盖所述第一金属层和所述第二金属层，且对应所述源极开设第八贯孔；所述有机层覆盖所述无机层，且对应所述第八贯孔开设有第三通孔；所述像素电极覆盖所述有机层，且通过所述第八贯孔和所述第三通孔与所述源极导通。
结合第一方面第把种实现，在第一方面第九种实现中，所述无机层还对应所述隔离槽开设第九贯孔，所述第九贯孔与所述隔离槽连通。
结合第一方面，以及第一方面第一至九种实现，在第一方面第十种实现中，所述阵列基板还包括缓冲层，所述缓冲层覆盖所述基板，所述信号传输线和所述栅极设置在所述缓冲层上。
结合第一方面第十种实现，在第一方面第十一种实现中，所述缓冲层对应 所述隔离槽开设凹槽，所述凹槽与所述隔离槽连通，所述凹槽的高度小于或等于所述缓冲层的厚度。
结合第一方面，在第一方面第十二种实现中，所述隔离槽平行于所述阵列基板的卷曲轴。
相较于现有技术，本发明的阵列基板通过在绝缘层上设置隔离槽，该隔离槽可以释放绝缘层中的内应力，从而防止脆性的绝缘层在内应力的作用下破裂，减少薄膜晶体管中柔性基板、绝缘层等层结构的变形，提高阵列基板的柔韧性。
而且，该阵列基板的绝缘层上还可以包括填充隔离槽的有机层，可以平坦化阵列基板的结构，提高阵列基板的柔韧性；阵列基板还可以包括覆盖所述有源层的无机层，可以在等离子蚀刻形成所述通孔和隔离槽时，保护所述有源层避免所述有源层与等离子体接触；阵列基板还可以包括保护层，该保护层可以阻隔外接空气中的氧气，防止第一金属层和第二金属层的氧化，且可起支撑作用，稳固所述阵列基板的结构。
第二方面，本发明还提供了一种阵列基板的制造方法，所述方法包括：
在基板上形成信号传输线和栅极，所述信号传输线和所述栅极之间设有间隙；
在所述信号传输线和所述栅极上形成绝缘层；
蚀刻所述绝缘层形成隔离槽以及蚀刻所述绝缘层形成通孔以显露所述信号传输线；
在所述绝缘层上覆盖有机层，其中所述有机层填充所述隔离槽和通孔；以及
去除所述通孔中的有机层，并在所述通孔中沉积第一金属层导通所述信号传输线。
结合第二方面，在第二方面的第一种实现中，所述在所述绝缘层上覆盖有机层之前还包括：
在所述绝缘层上形成有源层；
所述去除所述通孔中的所述有机层，并在所述通孔中沉积第一金属层导通所述信号传输线还包括：
去除所述有源层上的部分有机层以显露所述有源层，在所述有机层和所述 有源层上沉积第二金属层形成源极和漏极。
结合第二方面第一种实现，在第二方面的第二种实现中，所述方法还包括：
在所述有源层和所述绝缘层上形成无机层；
所述蚀刻所述绝缘层形成隔离槽以及蚀刻所述绝缘层形成通孔以显露部分所述数据线还包括：刻蚀所述无机层；
所述去除所述有源层上的部分所述有机层以显露所述有源层还包括：去除所述有源层上的部分所述无机层。
结合第二方面第二种实现，在第二方面的第三种实现中，所述第一金属层导通所述源极，所述方法还包括：
在所述第一金属层和所述第二金属层上形成保护层；
图案化所述保护层显露所述漏极；以及
在所述保护层、所述源极和所述漏极上沉积导电层，形成像素电极，所述漏极与所述像素电极导通。
结合第二方面第一种实现，在第二方面的第四种实现中，所述方法还包括：
刻蚀所述有机层显露所述源极或漏极；以及
在所述有机层上沉积导电层，形成像素电极，所述源极或漏极与所述像素电极导通。
结合第二方面，在第二方面的第五种实现中，所述在所述绝缘层上覆盖有机层之后，所述方法还包括：
去除部分所述的绝缘层上的所述有机层以显露所述绝缘层；
在所述绝缘层上形成有源层；
所述去除所述通孔中的所述有机层，并在所述通孔中沉积第一金属层导通所述信号传输线还包括：在所述有机层和所述有源层上沉积第二金属层形成源极和漏极。
结合第二方面第五种实现，在第二方面的第六种实现中，所述方法还包括：
在所述第一金属层、所述有机层和所述第二金属层上形成保护层；
刻蚀所述保护层显露所述源极；以及
在所述源极和保护层上沉积导电层，形成像素电极，所述源极与所述像素电极导通。
结合第二方面，以及第二方面第一至六种实现，在第二方面的第七种实现中，所述在基板上形成信号传输线和栅极包括：
在基板上沉积缓冲层，在所述缓冲层上形成所述信号传输线和所述栅极。
结合第二方面第七种实现，在第二方面的第八种实现中，所述蚀刻所述绝缘层形成隔离槽还包括：部分刻蚀对应所述隔离槽的所述缓冲层。
相对于现有技术，本发明提供的阵列基板的制备方法通过在基板上形成信号传输线和栅极，所述信号传输线和所述栅极之间设有间隙；在所述信号传输线和所述栅极上形成绝缘层；在所述绝缘层上形成有源层，蚀刻所述绝缘层形成隔离槽以及蚀刻所述绝缘层形成通孔以显露所述信号传输线；在所述绝缘层上覆盖有机层，其中所述有机层填充所述隔离槽和通孔，以及去除所述通孔中的有机层，并在所述通孔中沉积第一金属层导通所述信号传输线。其中，隔离槽和用于连接信号传输线的通孔可以经过一次光罩和刻蚀工艺一起形成，简化阵列基板的工艺步骤，且形成的隔离槽可以释放绝缘层中的内应力，从而防止脆性的绝缘层在内应力的作用下破裂，减少薄膜晶体管中柔性基板、绝缘层等层结构的变形，提高阵列基板的柔韧性。
而且，本发明提供的阵列基板的制备方法中，有机层还可以平坦化阵列基板的结构；覆盖所述有源层的无机层可以在等离子蚀刻形成所述通孔和隔离槽时，保护所述有源层避免所述有源层与等离子体接触，提高阵列基板的电学性能；阵列基板还可以包括有机层可阻隔环境中的氧气，防止阵列基板内部各个电极的氧化，且可起支撑作用，稳固所述阵列基板的结构。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板在第一状态下的剖面结构示意图；
图2为本发明一较佳实施方式的阵列基板在第二状态下的剖面结构示意 图；
图3为本发明一较佳实施方式的阵列基板在第三状态下的剖面结构示意图；
图4为本发明一较佳实施方式的阵列基板在第四状态下的剖面结构示意图；
图5为本发明一较佳实施方式的阵列基板在第五状态下的剖面结构示意图；
图6为本发明一较佳实施方式的阵列基板在第六状态下的剖面结构示意图；
图7为本发明一较佳实施方式的阵列基板在第七状态下的剖面结构示意图；
图8为本发明一较佳实施方式的阵列基板在第八状态下的剖面结构示意图；
图9为本发明一较佳实施方式的阵列基板在第九状态下的剖面结构示意图；
图10为本发明一较佳实施方式的阵列基板在第十状态下的剖面结构示意图；
图11是本发明一较佳实施方式的阵列基板中隔离槽分布的结构示意图；
图12为本发明第一种较佳实施方式的阵列基板的制备方法的流程图；
图13A～图13G为本发明第一种较佳实施方式的阵列基板的制备方法中各制备步骤的示意图；
图14为本发明第二种较佳实施方式的阵列基板的制备方法的流程图；
图15A～图15H为本发明第二种较佳实施方式的阵列基板的制备方法中各制备步骤的示意图；
图16为本发明第三种较佳实施方式的阵列基板的制备方法的流程图。
图17A～图17H为本发明第三种较佳实施方式的阵列基板的制备方法中各制备步骤的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1，图1为本发明一较佳实施方式的阵列基板在第一状态下的剖面结构示意图，所述阵列基板包括：
基板110、设于所述基板110上的信号传输线120和栅极130、覆盖所述信号传输线120和所述栅极130的绝缘层140、设于所述绝缘层140上的有源层150以及第一金属层160，其中，所述栅极130与所述信号传输线120之间设有间隙；所述绝缘层140上开设隔离槽1401和通孔1402，所述第一金属层160通过所述通孔1402与所述信号传输线120导通，所述隔离槽1401设于所述信号传输线120与所述栅极130之间。
相较于现有技术，本发明的阵列基板通过在绝缘层140上设置隔离槽1401，该隔离槽1401可以释放绝缘层140中的内应力，从而防止脆性的绝缘层140在内应力的作用下破裂，减少薄膜晶体管中柔性基板110、绝缘层140等层结构的变形，提高阵列基板的柔韧性。
请参见图2，图2为本发明一较佳实施方式的阵列基板在第二状态下的剖面结构示意图。本发明实施例中，所述阵列基板还包括有机层170，所述有机层170设于所述绝缘层140上，且填充所述隔离槽1401。
在本实施方式中，所述隔离槽1401内填充柔性绝缘材料，该绝缘柔性材料可以是高分子材料，所述柔性绝缘材料不影响所述阵列基板的柔韧性，且可以起支撑作用；而且，有机层170可以平坦化阵列基板的结构，使得隔离槽的设置，不带来阵列基板结构中台阶结构的增加，且有机层170可以使得整个阵列基板的结构更加稳固，提高阵列基板弯曲柔性的性能。
请参见图3，图3为本发明一较佳实施方式的阵列基板在第三状态下的剖面结构示意图。本发明实施例中，所述阵列基板还包括第二金属层，所述第二金属层与所述有源层150的两端导通，形成源极1601和漏极1602。
可选地，所述第一金属层160和所述第二金属层为一体结构，减少所述阵列基板中外引脚的设置。
可选地，所述阵列基板还包括无机层180，请参阅图4，图4为本发明一较佳实施方式的阵列基板在第四状态下的剖面结构示意图。所述无机层180覆盖所述有源层150和所述绝缘层140；所述无机层180开设有第一贯孔、第二贯孔、第三贯孔及第四贯孔；所述第一贯孔与所述通孔1402连通，用于导通所述信号传输线120与所述第一金属层160；所述第二贯孔与所述隔离槽1401连通；所述第三贯孔及所述第四贯孔分别对应所述有源层150的两端设置，用于导通所述有源层150与所述源极1601和所述漏极1602。
可选地，所述有机层170覆盖所述无机层180；所述有机层170开设第五贯孔、第六贯孔以及第七贯孔，其中，所述第五贯孔对应所述第一贯孔设置且与所述第一贯孔连通，用于导通所述信号传输线120与所述第一金属层160；所述第六贯孔对应所述第三贯孔设置且与所述第三贯孔连通；所述第七贯孔对应所述第四贯孔设置且与所述第四贯孔连通；所述第六贯孔和所述第七贯孔用于导通所述有源层150与所述源极1601和所述漏极1602。
其中，无机层180的材料可以是在等离子蚀刻形成所述通孔1402和隔离槽1401时，保护所述有源层150避免所述有源层150与等离子体接触。
请参阅5，图5为本发明一较佳实施方式的阵列基板在第五状态下的剖面结构示意图。所述有机层170背离所述基板110的表面与所述绝缘层140背离所述基板110的端面齐平。
在本实施方式中，所述阵列基板还包括保护层190以及像素电极，请参阅图6以及图7，图6为本发明一较佳实施方式的阵列基板在第六状态下的剖面结构示意图。图7为本发明一较佳实施方式的阵列基板在第七状态下的剖面结构示意图。所述保护层190覆盖所述第一金属层160和所述第二金属层，并开设第二通孔1402；所述第二通孔1402对应所述源极1601设置；所述像素电极覆盖所述保护层190，并通过所述第二通孔1402与所述源极1601导通。
可以理解，本发明中，保护层190可以是有机绝缘层140材料，如树脂、高分子材料等，所述像素电极200为透明导电膜，如氧化铟锡膜(ITO膜)等。
请参阅8，图8为本发明一较佳实施方式的阵列基板在第八状态下的剖面结构示意图。本发明实施例中，所述阵列基板还包括无机层180和像素电极，所述无机层180覆盖所述第一金属层160和所述第二金属层，且对应所述源极1601开设第八贯孔；所述有机层170覆盖所述无机层180，且对应所述第八贯孔开设有第三通孔1402；所述像素电极覆盖所述有机层170，且通过所述第八贯孔和所述第三通孔1402与所述源极1601导通。
可以理解，本实施方式中所述无机层180的材料可以是无机绝缘材料，如：HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种，可以保护被无机层180覆盖的各个电极。
可选地，请参阅9，图9为本发明一较佳实施方式的阵列基板在第九状态下的剖面结构示意图，所述无机层180还对应所述隔离槽1401开设第九贯孔，所述第九贯孔与所述隔离槽1401连通。
在本实施方式中，所述阵列基板还包括缓冲层210，所述缓冲层210覆盖所述基板110，所述信号传输线120和所述栅极130设置在所述缓冲层210上。请参阅10，图10为本发明一较佳实施方式的阵列基板在第十状态下的剖面结构示意图。
可选地，所述缓冲层210对应所述隔离槽1401开设凹槽，所述凹槽与所述隔离槽1401连通，所述凹槽的高度小于或等于所述缓冲层210的厚度。
在本实施方式中，所述隔离槽1401平行于所述阵列基板的卷曲轴。从而提高阵列基板的柔韧性，使得阵列基板可获得更大的弯曲度。
可以理解，隔离槽可以是长方体结构，梯形体结构、半圆柱体结构等，隔离槽的可以位于阵列基板中各个像素单元中，也可以按预设规律分布于某些像素单元中。优选地，隔离槽平行于阵列基板的卷曲轴，请参阅图11，图11是本发明一较佳实施方式的阵列基板中隔离槽分布的结构示意图，图11为从阵列基板沉积薄膜的表面的俯视时，阵列基板中隔离槽的分布的结构示意图，图11所示的，阵列基板可以包括多个像素单元，比如第一像素单元1101、第二像素单元1102、第三像素单元1103、第四像素单元1104等，每一个像素单元包含控制该像素单元开关状态的薄膜晶体管，阵列基板中各个薄膜晶体管可以 是如图1-10所示的阵列基板的结构单元，隔离槽1105可以是长方体结构，阵列基板的卷曲轴平行于隔离槽1105的长边，隔离槽1105也可以设置于阵列基板的边缘，沿卷取轴方向上的各个像素单元的中隔离槽1105可以连通，也可以间隔设置。
可以理解，本发明中，基板110可以是玻璃基板，也可以是高分子材料制备的柔性基板；信号传输线120可以是数据线，也可以是电压线；本发明中信号传输线120和栅极130的材料包括Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni、Mo、Al、ITO等材料中的任意一种或者多种；所述绝缘层140的材料可以是HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种；所述有源层150包括沟道层、第一掺杂区及第二掺杂区，所述第一掺杂区及所述第二掺杂区均与所述沟道层接触，且所述第一掺杂区与所述第二掺杂区间隔设置。所述第一金属层160或第二金属层的材料可以包括Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni、Mo、Al、ITO等材料中的任意一种或者多种，所述第一电极150可以与所述第二电极160或所述第三电极170通过外引脚电连接，所述第一金属层160和所述第二金属层也可以是一体结构。
相较于现有技术，本发明的阵列基板通过在绝缘层140上设置隔离槽1401，该隔离槽1401可以释放绝缘层140中的内应力，从而防止脆性的绝缘层140在内应力的作用下破裂，减少薄膜晶体管中基板110、绝缘层140等层结构的变形，提高阵列基板的柔韧性。
而且，该阵列基板的绝缘层140上还可以包括填充隔离槽的有机层150，可以平坦化阵列基板的结构，提高阵列基板的柔韧性；阵列基板还可以包括覆盖所述有源层150的无机层180，可以在等离子蚀刻形成所述通孔1402和隔离槽1401时，保护所述有源层150避免所述有源层150与等离子体接触；阵列基板还可以包括保护层190，该保护层190可以阻隔外接空气中的氧气，防止第一金属层160和第二金属层的氧化，且可起支撑作用，稳固所述阵列基板的结构。
请参阅图12，图12为本发明第一种较佳实施方式的阵列基板的制备方法的流程图，请一并参见图13A～13G，所述阵列基板的制备方法包括：
步骤S1210：在基板110上形成信号传输线120和栅极130，所述信号传输线120和所述栅极130之间设有间隙。可参见图13A。
具体地，可以通过物理气相沉积的方法在基板110上沉积金属层，如金(Au)层，通过光罩及蚀刻工艺，图案化该金属层，形成信号传输线120和栅极130。
在本实施方式中，所述步骤S120之后，所述方法还包括：形成缓冲层210，所述缓冲层210设置在所述基板110的第一表面，所述信号传输线120设置在所述缓冲层210背离所述基板110的表面；所述栅极130设置在所述缓冲层210背离所述基板110的表面。
可以理解，所述缓冲层210可以是无机绝缘材料也可以是高分子绝缘材料。形成缓冲层210的方法可以是化学气相沉积或物理气相沉积等方法。
可以理解，信号传输线120和栅极130的材质可以是，Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni、Mo、Al、ITO等材料中的任意一种或者多种。
步骤S1220：在所述信号传输线120和所述栅极130上形成绝缘层140。
具体地，可参见图13B，可以通过物理气相沉积的方法在所述信号传输线120和所述栅极130上沉积一层绝缘层140，该绝缘层140的材料可以是HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种。
步骤S1230：在所述绝缘层140上形成有源层150。可参见图13C。
具体地，有源层150为半导体材料，所述有源层150包括沟道层、第一掺杂区及第二掺杂区，所述第一掺杂区及所述第二掺杂区均与所述沟道层接触，且所述第一掺杂区与所述第二掺杂区间隔。所述有源层150的制备技术为现有技术，本发明不在赘述。
步骤S1240：蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120。可参见图13D，具体地，可以通过光罩以及蚀刻工艺图案化所述绝缘层140，形成隔离槽1401和通孔1402。
具体地，在所述绝缘层140背离所述衬底的表面涂布光刻胶层；图案化所述光刻胶层，移除覆盖所述绝缘层140的部分光刻胶层；以剩余的光刻胶层为掩膜对所述绝缘层140进行等离子蚀刻，形成如图13D所示的隔离槽1401和通孔1402。剥离剩余的所述光刻胶层。在本实施方式中，可以用丙酮等有机溶剂来剥离剩余的所述光刻胶层。
步骤S1250：在所述绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401和通孔1402，可参见图13E。
具体地，可以通过物理气相沉积、化学气相沉积或旋涂等方法在所述绝缘层140上覆盖一层有机层170，该有机层170的材质可以是高分子材料。
步骤S1260：去除所述通孔1402中的有机层170，可参见图13F，并在所述通孔1402中沉积第一金属层160导通所述信号传输线120，可参见图13G所述的阵列基板。
具体地，可以通过光罩及蚀刻工艺，对该有机层170进行湿法蚀刻，去除通孔1402中的有机层170；当有机层170为光敏有机材料时，也可以光罩对该有机层170部分曝光，去除通孔1402中的有机层170，形成图形化的有机层170。再通过物理气相沉积法，在通孔1402中沉积第一金属层160导通所述信号传输线120。
在本实施方式中，步骤S1260还可以包括：去除所述有源层150上的部分有机层170以显露所述有源层150，在所述有机层170和所述有源层150上沉积第二金属层形成源极1601和漏极1602。可参见图3所示的阵列基板。具体地，可以通过光罩及蚀刻工艺，对有源层150上的有机层170使用湿法蚀刻，去除部分有机层170以显露所述有源层150；当有机层170为光敏有机材料时，也可以光罩对该有机层170部分曝光，去除通孔1402中的有机层170以显露所述有源层150，形成图形化的有机层170。优选地，对应有源层150的两端进行刻蚀或曝光处理，漏出所述有源层150的所述第一掺杂区及所述第二掺杂区。
具体地，可以在所述有源层150的表面或有机层170的表面，形成第二金属层，再通过光罩以及蚀刻工艺图案化所述第二金属层，形成源极1601和漏极1602。可参见图5所述的阵列基板。
其中的，第一金属层160和第二金属层可以一体成型，其中，第一金属层160可以导通源极1601。可参见图3所述的阵列基板。具体地，可以在所述通孔1402中沉积第一金属层160，图案化第一金属层160形成所述源极1601和 所述漏极1602，其中，所述源极1601导通所述信号传输线120。
在本实施方式中，步骤S1230或步骤S1240之后，该阵列基板的制造方法还可以包括：在所述有源层150和所述绝缘层140上形成无机层180；步骤S1240还包括：刻蚀所述无机层180使得通孔1402贯穿无机层180。步骤S1260还包括：去除所述有源层150上的部分所述无机层180，以露出所述有源层150的所述第一掺杂区及所述第二掺杂区，可参见图4所示的阵列基板。
需要说明的是，该无机层180可以是HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种。
可选地，步骤S1260之后，该阵列基板的制造方法还可以包括：在所述第一金属层160和所述第二金属层上形成保护层190；图案化所述保护层190，形成过孔，显露所述漏极1602；在所述保护层190、所述源极1601和所述漏极1602上沉积导电层200，形成像素电极，所述漏极1602与所述像素电极导通。可参见图6或图8所示的阵列基板。
需要说明的是，该保护层190可以是高分子、橡胶等材料。可以利用光罩及湿法蚀刻工艺图案化该保护层190，形成过孔，显露所述漏极1602。可以通过物理气相沉积法在所述保护层190、所述源极1601和所述漏极1602上沉积导电层200，形成像素电极，所述漏极1602与所述像素电极导通，其中，所述导电层200为透明导电薄膜，如，锡掺杂三氧化铟(ITO)、铝掺杂氧化锌(AZO)等。
应当理解，本发明中刻蚀可以包括干刻蚀以及湿刻蚀，所述干蚀刻的气体可以是为CF4，SF6或CL2和O2的混合气体，所示湿蚀刻的液体可以是为草酸，硫酸，盐酸，或草酸、硫酸及盐酸的混合液。
应该理解，在本发明中，所述图案化即是指构图工艺，可包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影，等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
通过本发明实施例阵列基板的制造方法形成的显示器件，可以为：液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、 手机等。
相对于现有技术，本发明提供的阵列基板的制备方法通过在基板110上形成信号传输线120和栅极130，所述信号传输线120和所述栅极130之间设有间隙；在所述信号传输线120和所述栅极130上形成绝缘层140；在所述绝缘层140上形成有源层150，蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120；在所述绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401和通孔1402，以及去除所述通孔1402中的有机层170，并在所述通孔1402中沉积第一金属层160导通所述信号传输线120。其中，隔离槽1401和用于连接信号传输线120的通孔1402可以经过一次光罩和刻蚀工艺一起形成，简化阵列基板的工艺步骤，且形成的隔离槽1401可以释放绝缘层140中的内应力，从而防止脆性的绝缘层140在内应力的作用下破裂，减少薄膜晶体管中柔性基板110、绝缘层140等层结构的变形，提高阵列基板的柔韧性。
而且，本发明提供的阵列基板的制备方法中，有机层170还可以平坦化阵列基板的结构；覆盖所述有源层150的无机层180可以在等离子蚀刻形成所述通孔1402和隔离槽1401时，保护所述有源层150避免所述有源层150与等离子体接触，提高阵列基板的电学性能；阵列基板还可以包括有机层170可阻隔环境中的氧气，防止阵列基板内部各个电极的氧化，且可起支撑作用，稳固所述阵列基板的结构。
请参阅图14，图14为本发明第二种较佳实施方式的阵列基板的制备方法的流程图，请一并参阅图15A～15H，所述阵列基板的制备方法包括：
步骤S1410，在基板110上形成信号传输线120和栅极130，所述信号传输线120和所述栅极130之间设有间隙。请参照图15A。
步骤S1420：在所述信号传输线120和所述栅极130上形成绝缘层140。请参照图15B。
步骤S1430：在所述绝缘层140上形成有源层150。请参照图15C。
步骤S1440：蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120，请参照图15D。
步骤S1450：在所述通孔1402中沉积第一金属层160导通所述信号传输线120，以及在所述有源层150上沉积第二金属层，并图案化所述第二金属层，形成源极1601和漏极1602。请参阅图15E。
步骤S1460：在所述第一金属层160以及所述第二金属层绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401，请参阅图15F。
本实施方式中，步骤S1460之后，该方法还可以包括：刻蚀所述有机层170显露所述源极1601，请参阅图15G；在所述源极1601和所述有机层170上沉积导电层200，形成像素电极，所述源极1601或漏极1602与所述像素电极导通，请参阅图15H。
本实施方式中，步骤S1450之后，还可以包括：在第一金属层160和第二金属层上覆盖无机层180。请参阅图9。
可以理解，图14所述的阵列基板的制造方法中各个膜层的制备可以参考图12所述的阵列基板的制造方法，本发明不在赘述。
相对于现有技术，本发明提供的阵列基板的制备方法通过在基板110上形成间隔设置的信号传输线120和栅极130，在所述信号传输线120和所述栅极130上形成绝缘层140、有源层150，蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120；在所述通孔1402中沉积第一金属层160导通所述信号传输线120，以及在所述有源层150上沉积第二金属层，并图案化所述第二金属层，形成源极1601和漏极1602，在所述第一金属层160以及所述第二金属层绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401。该方法中，隔离槽1401和用于连接信号传输线120的通孔1402可以经过一次光罩和刻蚀工艺一起形成，简化阵列基板的工艺步骤，且形成的隔离槽1401可以释放绝缘层140中的内应力，从而防止脆性的绝缘层140在内应力的作用下破裂，减少薄膜晶体管中基板110、绝缘层140等层结构的变形，提高阵列基板的柔韧性。
而且，本发明提供的阵列基板的制备方法，可以包括覆盖所述第一金属层160和第二金属的无机层180，防止金属的氧化。
请参阅图16，图16为本发明第三种较佳实施方式的阵列基板的制备方法 的流程图，请一并参考图17A～17H所述阵列基板的制备方法包括：
步骤S1610：在基板110上形成信号传输线120和栅极130，所述信号传输线120和所述栅极130之间设有间隙。请参照图17A。
步骤S1620：在所述信号传输线120和所述栅极130上形成绝缘层140，请参照图17B。
步骤S1630：蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120，请参照图17C。
步骤S1640：在所述绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401和通孔1402，请参照图17D。
步骤S1650：去除部分所述的绝缘层140上的所述有机层170以显露所述绝缘层140，请参照图17E。
步骤S1660：在所述绝缘层140上形成有源层150；请参照图17F。
步骤S1670：去除所述通孔1402中的有机层170，并在所述通孔1402中沉积第一金属层160导通所述信号传输线120。
具体地，去除通孔1402中的有机层170，以漏出信号传输线120。请参照图17G。
本实施方式中，在所述有机层170和所述有源层150上沉积第二金属层形成源极1601和漏极1602。请参照图17H。
本实施方式中，在所述第一金属层160、所述有机层170和所述第二金属层上形成保护层190；刻蚀所述保护层190显露所述源极1601；以及，在所述源极1601和保护层190上沉积导电层200，形成像素电极，所述源极1601与所述像素电极导通。请参照图7。
可以理解，图16所述的阵列基板的制造方法中各个膜层的制备可以参考图12所述的阵列基板的制造方法，本发明不在赘述。
相较于现有技术，本发明的阵列基板的制造方法中通过
在基板110上形成间隔设置的信号传输线120和栅极130，在所述信号传输线120和所述栅极130上形成绝缘层140，蚀刻所述绝缘层140形成隔离槽1401以及蚀刻所述绝缘层140形成通孔1402以显露所述信号传输线120，在所述绝缘层140上覆盖有机层170，其中所述有机层170填充所述隔离槽1401 和通孔1402，去除部分所述的绝缘层140上的所述有机层170以显露所述绝缘层140，形成平坦化的有机层170，可以起到支撑作用，在所述绝缘层140上形成有源层150，去除所述通孔1402中的有机层170，并在所述通孔1402中沉积第一金属层160导通所述信号传输线120。其中，用于隔离槽1401和通孔1402可以经过一次光罩和刻蚀工艺同时形成，简化阵列基板的工艺步骤，且形成的隔离槽1401可以释放绝缘层140中的内应力，从而防止脆性的绝缘层140在内应力的作用下破裂，减少薄膜晶体管中基板110、栅极130绝缘层140等层结构的变形，提高阵列基板的柔韧性。
而且，保护层190可阻隔环境中的氧气，防止阵列基板内部各个电极的氧化，且可起支撑作用，稳固所述阵列基板的结构。
本发明实施例中所使用的技术术语仅用于说明特定实施例而并不旨在限定本发明。在本文中，单数形式“一”、“该”及“所述”用于同时包括复数形式，除非上下文中明确另行说明。进一步地，在说明书中所使用的用于“包括”和/或“包含”是指存在所述特征、整体、步骤、操作、元件和/或构件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、元件和/或构件。
在所附权利要求中对应结构、材料、动作以及所有装置或者步骤以及功能元件的等同形式(如果存在的话)旨在包括结合其他明确要求的元件用于执行该功能的任何结构、材料或动作。本发明的描述出于实施例和描述的目的被给出，但并不旨在是穷举的或者将被发明限制在所公开的形式。在不偏离本发明的范围和精神的情况下，多种修改和变形对于本领域的一般技术人员而言是显而易见的。本发明中所描述的实施例能够更好地揭示本发明的原理与实际应用，并使本领域的一般技术人员可了解本发明。
本发明中所描述的流程图仅仅为一个实施例，在不偏离本发明的精神的情况下对此图示或者本发明中的步骤可以有多种修改变化。比如，可以不同次序的执行这些步骤，或者可以增加、删除或者修改某些步骤。本领域的一般技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (22)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：基板、设于所述基板上的信号传输线和栅极、覆盖所述信号传输线和所述栅极的绝缘层、设于所述绝缘层上的有源层以及第一金属层，其中，所述栅极与所述信号传输线之间设有间隙；所述绝缘层上开设隔离槽和通孔，所述第一金属层通过所述通孔与所述信号传输线导通，所述隔离槽设于所述信号传输线与所述栅极之间。
  2. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括有机层，所述有机层设于所述绝缘层上，且填充所述隔离槽。
  3. 如权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括第二金属层，所述第二金属层与所述有源层的两端导通，形成源极和漏极。
  4. 如权利要求3所述的阵列基板，其特征在于，所述第一金属层和所述第二金属层为一体结构。
  5. 如权利要求4所述的阵列基板，其特征在于，所述阵列基板还包括无机层，所述无机层覆盖所述有源层和所述绝缘层；所述无机层开设有第一贯孔、第二贯孔、第三贯孔及第四贯孔；所述第一贯孔与所述通孔连通，用于导通所述信号传输线与所述第一金属层；所述第二贯孔与所述隔离槽连通；所述第三贯孔及所述第四贯孔分别对应所述有源层的两端设置，用于导通所述有源层与所述源极和所述漏极。
  6. 如权利要求5所述的阵列基板，其特征在于，所述有机层覆盖所述无机层；所述有机层开设第五贯孔、第六贯孔以及第七贯孔，其中，所述第五贯孔对应所述第一贯孔设置且与所述第一贯孔连通，用于导通所述信号传输线与所述第一金属层；所述第六贯孔对应所述第三贯孔设置且与所述第三贯孔连通； 所述第七贯孔对应所述第四贯孔设置且与所述第四贯孔连通；所述第六贯孔和所述第七贯孔用于导通所述有源层与所述源极和所述漏极。
  7. 如权利要求3所述的阵列基板，其特征在于，所述有机层背离所述基板的表面与所述绝缘层背离所述基板的端面齐平。
  8. 如权利要求3-7所述的任一一项阵列基板，其特征在于，所述阵列基板还包括保护层以及像素电极，所述保护层覆盖所述第一金属层和所述第二金属层，并开设第二通孔；所述第二通孔对应所述源极设置；所述像素电极覆盖所述保护层，并通过所述第二通孔与所述源极导通。
  9. 如权利要求3所述的阵列基板，其特征在于，所述阵列基板还包括无无机层和像素电极，所述无机层覆盖所述第一金属层和所述第二金属层，且对应所述源极开设第八贯孔；所述有机层覆盖所述无机层，且对应所述第八贯孔开设有第三通孔；所述像素电极覆盖所述有机层，且通过所述第八贯孔和所述第三通孔与所述源极导通。
  10. 如权利要求9所述的阵列基板，其特征在于，所述无机层还对应所述隔离槽开设第九贯孔，所述第九贯孔与所述隔离槽连通。
  11. 如权利要求1-9所述的任一一项阵列基板，其特征在于，所述阵列基板还包括缓冲层，所述缓冲层覆盖所述基板，所述信号传输线和所述栅极设置在所述缓冲层上。
  12. 如权利要求11所述的阵列基板，其特征在于，所述缓冲层对应所述隔离槽开设凹槽，所述凹槽与所述隔离槽连通，所述凹槽的高度小于或等于所述缓冲层的厚度。
  13. 如权利要求1所述的阵列基板，其特征在于，所述隔离槽平行于所述 阵列基板的卷曲轴。
  14. 一种阵列基板的制造方法，其特征在于，所述方法包括，
    在基板上形成信号传输线和栅极，所述信号传输线和所述栅极之间设有间隙；
    在所述信号传输线和所述栅极上形成绝缘层；
    蚀刻所述绝缘层形成隔离槽以及蚀刻所述绝缘层形成通孔以显露所述信号传输线；
    在所述绝缘层上覆盖有机层，其中所述有机层填充所述隔离槽和通孔；以及
    去除所述通孔中的有机层，并在所述通孔中沉积第一金属层导通所述信号传输线。
  15. 如权利要求14所述的阵列基板的制造方法，其特征在于，所述在所述绝缘层上覆盖有机层之前还包括：
    在所述绝缘层上形成有源层；
    所述去除所述通孔中的所述有机层，并在所述通孔中沉积第一金属层导通所述信号传输线还包括：
    去除所述有源层上的部分有机层以显露所述有源层，在所述有机层和所述有源层上沉积第二金属层形成源极和漏极。
  16. 如权利要求15所述的阵列基板的制造方法，其特征在于，所述方法还包括：
    在所述有源层和所述绝缘层上形成无机层；
    所述蚀刻所述绝缘层形成隔离槽以及蚀刻所述绝缘层形成通孔以显露部分所述数据线还包括：刻蚀所述无机层；
    所述去除所述有源层上的部分所述有机层以显露所述有源层还包括：去除所述有源层上的部分所述无机层。
  17. 如权利要求16所述的阵列基板的制造方法，其特征在于，所述第一金属层导通所述源极，所述方法还包括：
    在所述第一金属层和所述第二金属层上形成保护层；
    图案化所述保护层显露所述漏极；以及
    在所述保护层、所述源极和所述漏极上沉积导电层，形成像素电极，所述漏极与所述像素电极导通。
  18. 如权利要求15所述的阵列基板的制造方法，其特征在于，所述方法还包括：
    刻蚀所述有机层显露所述源极或漏极；以及
    在所述有机层上沉积导电层，形成像素电极，所述源极或漏极与所述像素电极导通。
  19. 如权利要求14所述的阵列基板的制造方法，其特征在于，所述在所述绝缘层上覆盖有机层之后，所述方法还包括：
    去除部分所述的绝缘层上的所述有机层以显露所述绝缘层；
    在所述绝缘层上形成有源层；
    所述去除所述通孔中的所述有机层，并在所述通孔中沉积第一金属层导通所述信号传输线还包括：在所述有机层和所述有源层上沉积第二金属层形成源极和漏极。
  20. 如权利要求19所述的阵列基板的制造方法，其特征在于，所述方法还包括：
    在所述第一金属层、所述有机层和所述第二金属层上形成保护层；
    刻蚀所述保护层显露所述源极；以及
    在所述源极和保护层上沉积导电层，形成像素电极，所述源极与所述像素电极导通。
  21. 如权利要求14-19所述的任一一项阵列基板的制造方法，其特征在于， 所述在基板上形成信号传输线和栅极包括：
    在基板上沉积缓冲层，在所述缓冲层上形成所述信号传输线和所述栅极。
  22. 如权利要求21所述阵列基板的制造方法，其特征在于，所述蚀刻所述绝缘层形成隔离槽还包括：部分刻蚀对应所述隔离槽的所述缓冲层。
PCT/CN2016/091528 2016-07-25 2016-07-25 阵列基板及阵列基板的制造方法 Ceased WO2018018353A1 (zh)

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