WO2017206523A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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WO2017206523A1
WO2017206523A1 PCT/CN2017/071415 CN2017071415W WO2017206523A1 WO 2017206523 A1 WO2017206523 A1 WO 2017206523A1 CN 2017071415 W CN2017071415 W CN 2017071415W WO 2017206523 A1 WO2017206523 A1 WO 2017206523A1
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substrate
common electrode
pixel electrode
array substrate
pixel
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PCT/CN2017/071415
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English (en)
French (fr)
Inventor
肖丽
何晓龙
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京东方科技集团股份有限公司
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Priority to US15/556,507 priority Critical patent/US20180166000A1/en
Publication of WO2017206523A1 publication Critical patent/WO2017206523A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/12—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using electroluminescent elements
    • G09G3/14—Semiconductor devices, e.g. diodes
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136295—Materials; Compositions; Manufacture processes
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
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    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • a thin film transistor liquid crystal display is a liquid crystal display device in which a thin film transistor (TFT) is used as a switching control element of a pixel unit.
  • TFT thin film transistor
  • the electrical characteristics, optical characteristics and display mode of the liquid crystal directly affect the display effect of the liquid crystal display device.
  • common liquid crystal display modes include TN (twisted nematic) display mode, IPS (planar conversion) display mode, and ADS (advanced super-dimensional field conversion) display mode.
  • the IPS display mode has the advantages of large viewing angle, high dynamic resolution and good color reproduction effect. It has a wide range of applications in aerospace, medical, design and other fields with high technology content.
  • the two electrodes are disposed in the same plane, and the liquid crystal molecules rotate in the plane, thereby achieving brightness control.
  • the liquid crystal molecules are always parallel to the display panel, and uneven arrangement of the liquid crystal molecules reduces the aperture ratio and reduces the light transmittance, thereby reducing the brightness.
  • At least one embodiment of the present invention provides an array substrate including: a substrate substrate; a gate line and a data line disposed on the base substrate, the gate line and the data line intersect to define a pixel area; a pixel electrode and a common electrode in the pixel region; wherein the pixel electrode and the common electrode are both convexly disposed on the substrate substrate perpendicular to the substrate substrate, thereby being disposed opposite to each other; After a voltage is applied to the pixel electrode and the common electrode, an electric field parallel to the substrate may be generated between the opposite faces of the pixel electrode and the common electrode.
  • materials of the pixel electrode and the common electrode are conductive resin materials.
  • the conductive resin material includes Resin matrix and conductive incorporation.
  • the resin substrate includes an epoxy resin, an acrylic resin, a polyurethane, or the like.
  • the conductive inclusions include metal particles or fibers, carbon particles or fibers, or graphene.
  • the array substrate includes a thin film transistor including: a gate connected to the gate line, an active layer, connected to the data line, and a source contacted by the active layer, a drain disposed opposite to the source and in contact with the active layer, a gate insulating layer between the gate and the active layer, and The drain is also electrically connected to the pixel electrode.
  • the thin film transistor is provided with a passivation layer and a via structure penetrating the passivation layer.
  • the pixel electrode is electrically connected to the drain through the via structure.
  • the thin film transistor may be a bottom gate type or a top gate type thin film transistor.
  • the pixel electrode and the common electrode are elongated and thus opposed to each other.
  • each of the pixel regions includes at least one of the pixel electrodes or at least one of the common electrodes.
  • the array substrate provided in an embodiment of the present invention further includes a common electrode line, and the common electrode is electrically connected to the common electrode line.
  • At least one embodiment of the present invention further provides a display panel including any one of the thin film transistor array substrates described above, a counter substrate disposed in parallel with the substrate substrate, and a substrate disposed on the array substrate and the opposite substrate Liquid crystal molecules.
  • a thickness of the pixel electrode and the common electrode on a substrate perpendicular to the substrate is a thickness of the liquid crystal molecules.
  • the pixel electrode and the common electrode are both perpendicular to the opposite substrate and support the opposite substrate.
  • the opposite substrate is a color filter substrate.
  • At least one embodiment of the present invention also provides a display device including any of the above display panels.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, comprising: forming a gate line, a data line, and a pixel region defined by the intersection of the gate line and the data line on a base substrate; Forming a pixel electrode and a common electrode in the region; wherein the pixel electrode and the common electrode are both convexly disposed on the substrate substrate perpendicular to the substrate substrate, thereby being disposed opposite to each other; After a voltage is applied to the pixel electrode and the common electrode, an electric field parallel to the substrate may be generated between the opposite faces of the pixel electrode and the common electrode.
  • the materials of the pixel electrode and the common electrode are all conductive resin materials.
  • the conductive resin material includes a resin matrix and a conductive incorporation.
  • the resin matrix includes an epoxy resin, an acrylic resin, a polyurethane, or the like.
  • the conductive incorporation includes metal particles or fibers, carbon particles or fibers, or graphene or the like.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • Figure 2 is a cross-sectional view of the array substrate of Figure 1 taken along line A-B;
  • FIG. 3 is a schematic cross-sectional structural view of a top gate thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the invention.
  • the pixel electrode and the common electrode are made of a transparent conductive material or a metal material. If the above electrode is made of a transparent conductive material or a metal material, a method of depositing a film is generally employed. The thickness of the electrode formed by depositing the thin film is relatively thin, and after the voltage signal is applied, an arc-shaped electric field line is formed between the pixel electrode and the upper surface of the common electrode, and the liquid crystal molecules are arranged along the arc electric field line. This causes a decrease in the transmittance of light of the liquid crystal panel.
  • both electrodes can be convexly disposed on the base substrate perpendicular to the base substrate.
  • the pixel electrode and the common electrode are disposed opposite to each other, whereby a horizontal electric field parallel to the substrate substrate can be generated between the opposite faces of the pixel electrode and the common electrode after the voltage signal is applied, so that the liquid crystal molecules can be uniformly arranged.
  • the switching speed of the liquid crystal molecules can be improved, thereby improving the display response speed of the liquid crystal panel, and also improving the light transmittance of the liquid crystal panel and improving the display effect.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, a display panel, and a display device.
  • the array substrate includes: a substrate substrate; a gate line and a data line disposed on the base substrate, the gate line and the data line intersect to define a pixel area; a pixel electrode and a common electrode disposed in the pixel area; wherein, the pixel electrode And the common electrode is perpendicular to the base substrate and is convexly disposed on the lining On the base substrate, thereby being disposed opposite to each other; after a voltage is applied to the pixel electrode and the common electrode, an electric field parallel to the substrate can be generated between the faces of the pixel electrode and the common electrode.
  • Applying the pixel electrode and the common electrode of the structure to the IPS display mode can make the distribution of the parallel electric fields generated by the two devices more uniform after being energized, which is beneficial to increase the switching speed of the liquid crystal, improve the transmittance of the light, and improve the display panel.
  • the speed of response the pixel electrode and the common electrode of the structure are applied to the display panel, and the spacer (PS) disposed between the array substrate and the opposite substrate may be at least partially replaced to support the opposite substrate. The effect is to improve the pressure resistance of the liquid crystal panel.
  • Embodiments of the present invention provide an array substrate, and the switching elements on the array substrate may be thin film transistors or other switching elements.
  • the array substrate may be a thin film transistor array substrate, and the thin film transistor array substrate is exemplified below.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line A-B.
  • the array substrate 100 includes: a substrate substrate 101; a gate line 102 and a data line 103 disposed on the base substrate 101, the gate line 102 and the data line 103 intersect to define a pixel region 104; a thin film transistor 105, a pixel electrode 106, and a common electrode 107 in the pixel region 104; wherein the pixel electrode 106 and the common electrode 107 are both convexly disposed on the base substrate 101 perpendicular to the base substrate 101, thereby being disposed opposite to each other
  • an electric field parallel to the base substrate 101 may be generated between the opposite faces of the pixel electrode 106 and the common electrode 107 without forming an arc at the top of the pixel electrode and the common electrode. Electric field line.
  • both the pixel electrode 106 and the common electrode 107 can be made thick (high) and disposed oppositely, whereby the portions facing each other define a space for accommodating the liquid crystal, and thus both are applied with electricity
  • a uniform horizontal electric field is formed in the space after the signal (energization), the horizontal electric field line being perpendicular to the face of the pixel electrode 106 and the common electrode 107.
  • the electric field acts on the liquid crystal contained between the two to control the arrangement of the liquid crystal molecules.
  • protrusively disposed means extending in a direction perpendicular to the base substrate 101, and the thickness (height) of the pixel electrode 106 and the common electrode 107 coincides with the thickness (height) of the liquid crystal layer therebetween.
  • the liquid crystal molecules can be uniformly arranged along parallel electric field lines between the pixel electrode 106 and the common electrode 107.
  • the base substrate 101 is a transparent insulating substrate, and the material thereof may be glass, quartz, or other suitable material.
  • gate lines 102 and two data lines 103 are arranged to define a pixel area 104. Only two gate lines 102 and two data lines 103 are shown in FIG. 1, and a plurality of gate lines 102 and a plurality of data lines 103 may be disposed on the base substrate 101.
  • Materials that can be used for gate line 102 and data line 103 include copper, copper alloys, aluminum, aluminum alloys, molybdenum, molybdenum alloys, or other suitable materials.
  • Gate line 102 includes a plurality of gates 108 that are bifurcated therefrom, with gate signals being applied to gates 108 through gate lines 102.
  • the common electrode line 113 is disposed on the base substrate 101, which is substantially parallel to the gate line 102. Only one common electrode line 113 is shown in FIG. 1, and a plurality of common electrode lines 113 may be disposed on the base substrate 101.
  • Materials that can be used for the common electrode line 113 include copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, conductive resin, or other suitable materials.
  • the common electrode lines may be disposed in the same layer as the gate lines or in different layers.
  • the thin film transistor 105 includes a gate electrode 108 connected to the gate line 102, an active layer 109, a source 110 connected to the data line 103 and in contact with the active layer 109, and opposite to the source electrode 110.
  • a drain electrode 111 disposed in contact with the active layer 109, a gate insulating layer 112 between the gate electrode 108 and the active layer 109, and a drain electrode 111 are also electrically connected to the pixel electrode 106.
  • the gate insulating layer 112 covers the gate line 102, the gate electrode 108, the common electrode line 113, and the common electrode 107.
  • the material of the gate insulating layer 112 includes silicon oxide and silicon nitride.
  • the active layer 109 is disposed on the gate insulating layer 112, corresponding to the gate electrode 108, and the material for the active layer 109 includes amorphous silicon, a metal oxide semiconductor, an organic semiconductor, or the like.
  • the material for source 110 and drain 111 may be copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, or other suitable material.
  • the passivation layer 115 covers the data line 103, the active layer 109, the source 110, and the drain 111.
  • Passivation layer 115 includes a via structure 114 that exposes a portion of drain 111.
  • Materials for passivation layer 115 include silicon oxide, silicon nitride, or other suitable materials.
  • a flat layer 116 may be disposed on the passivation layer 115, and the flat layer 116 is thicker. Except for the flat layer 116 being uneven at the via structure 114, the other portions of the surface of the flat layer are flat.
  • the material of the flat layer 116 may be an inorganic material such as silicon oxide or silicon nitride or an organic material such as an epoxy resin, an acrylic resin, or a polyurethane.
  • the pixel electrode 106 is disposed on the flat layer 116, which is electrically connected to the drain 111 through the via structure 114, whereby a data signal (voltage) can be applied to the pixel electrode through the data line and the thin film transistor. 106 on.
  • the material for the pixel electrode 106 is a conductive resin material.
  • the common electrode 107 is disposed on the flat layer 116, which is electrically connected to the common electrode line 113 through a via structure (not shown). The common voltage is applied to the common electrode 107 through the common electrode line 113.
  • the material for the common electrode 107 is a conductive resin material. Although only three common electrodes 107 of a strip-like structure in one pixel region are shown in FIG. 1, each pixel region may further include more elongated structures. Common electrode 107.
  • the pixel electrode 106 and the common electrode 107 are each elongated, whereby the pixel electrode 106 and the common electrode 107 are opposed to each other, so that a uniform horizontal electric field can be formed therebetween.
  • each pixel region 104 includes at least one pixel electrode 106 or at least one common electrode 107.
  • each of the pixel electrodes 106 is disposed adjacent to the common electrode 107
  • each of the common electrodes 107 is disposed adjacent to the pixel electrode 106.
  • the conductive resin material includes a resin matrix and a conductive incorporation, and the conductive matrix is modified in the resin matrix to modify the resin matrix to impart electrical conductivity to the entire resin matrix.
  • the resin matrix includes an epoxy resin, an acrylic resin, or a polyurethane.
  • the resin matrix may further include a phenol resin, an alkyd resin, a synthetic fatty acid resin, or the like.
  • the conductive incorporation includes metal particles or fibers, carbon particles or fibers, or graphene.
  • the metal particles or fibers include silver nanoparticles or fibers, nickel nanoparticles or fibers, etc.
  • the carbon particles include hollow carbon particles, solid carbon spheres, core-shell structured carbon spheres, and colloidal carbon spheres
  • carbon fibers include acrylonitrile-based carbon fibers, asphalt.
  • Base carbon fiber may also include seamless, hollow, electrically conductive carbon nanotubes rolled from a graphene sheet layer, including single-walled carbon nanotubes, double-walled carbon nanotubes, and multi-walled carbon nanotubes.
  • the conductive resin material may have a certain hardness, as shown in FIG. 2, which satisfies the requirement that the pixel electrode 106 and the common electrode 107 are manufactured to have a relatively large thickness (height), that is, to satisfy the pixel electrode 106 and the common electrode.
  • 107 is convexly disposed on the base substrate 101 perpendicular to the base substrate 101, and an electric field parallel to the base substrate 101 may be generated between the opposite faces.
  • the resin matrix also has good light transmittance at the same time, so that the aperture ratio is not lowered.
  • the thin film transistor 105 may be a bottom gate type or a top gate type thin film transistor.
  • 1 and 2 illustrate a thin film transistor of a bottom gate type structure as an example.
  • FIG. 3 is a schematic cross-sectional view of a top gate thin film transistor according to an embodiment of the present invention.
  • the gate 108 is disposed in Above the source layer 109, the source 110, and the drain 111, a gate insulating layer 112 is disposed under the gate 108, thereby isolating the gate 108 and the active layer 109.
  • Other structural settings and materials of the respective layers are identical to those described in the above-described bottom gate type thin film transistor, and will not be described herein.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • the display panel 200 includes any of the above-described thin film transistor array substrate 100, a counter substrate 117 disposed in parallel with the base substrate 101, and liquid crystal molecules disposed between the array substrate 100 and the opposite substrate 117. 118.
  • the thickness (height) of the pixel electrode and the common electrode in the direction perpendicular to the substrate 101 is the thickness (height) of the liquid crystal molecules 118, where the pixel electrode and the common electrode are perpendicular to the substrate.
  • the thickness (height) in the direction of the substrate 101 is the height of the flat layer 116 to the side opposite to the base substrate 101 of the counter substrate 117. It should be noted that the pixel electrode 106 and the common electrode 107 are perpendicular to the substrate 101.
  • the thickness (height) on the upper side is also not the thickness (height) of the liquid crystal molecules 118 in a strict sense.
  • the pixel electrode 106 and the common electrode 107 are both perpendicular to the opposite substrate 117 and support the opposite substrate 117.
  • the pixel electrode 106 and the common electrode 107 of this structure are applied to the IPS display mode, and after the voltage is applied to the pixel electrode 106 and the common electrode 107, the distribution of the parallel electric field formed between the pixel electrode 106 and the common electrode 107 can be made more.
  • the liquid crystal molecules 118 are uniformly arranged in the direction of the electric field lines between the two electrodes, thereby improving the transmittance of light.
  • the pixel electrode 106 and the common electrode 107 not only have the function of conducting electricity, but also at least partially replace the spacer (PS) disposed between the array substrate 101 and the opposite substrate 117 to support the opposite substrate 117. This saves process steps.
  • PS spacer
  • the opposite substrate 117 is a color filter substrate.
  • the pixel electrode 106 and the common electrode 107 are both perpendicular to the substrate substrate and support the color filter substrate, and the spacer (PS) disposed between the array substrate 101 and the color filter substrate can be at least partially replaced, which simplifies the process steps.
  • Embodiments of the present invention also provide a display device including any of the above display panels 200.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, or the like including the display device. Any product or component that has a display function, such as a navigator.
  • a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, or the like including the display device.
  • Any product or component that has a display function such as a navigator.
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the method includes: Forming a gate line, a data line, and a pixel region defined by the intersection of the gate line and the data line; forming a pixel electrode and a common electrode in the pixel region; wherein the pixel electrode and the common electrode are both perpendicular to the substrate substrate and protruding
  • the ground substrate is disposed on the substrate, thereby being disposed opposite to each other; after a voltage is applied to the pixel electrode and the common electrode, an electric field parallel to the substrate can be generated between the opposite faces of the pixel electrode and the common electrode.
  • both the pixel electrode and the common electrode are made thick (high) and are disposed opposite each other.
  • “protrusively disposed” means that the thickness (height) of the pixel electrode and the common electrode coincides with the thickness (height) of the liquid crystal layer to be packaged in a direction perpendicular to the substrate.
  • the liquid crystal molecules can be uniformly arranged along parallel electric field lines between the pixel electrode and the common electrode.
  • the material of the pixel electrode and the common electrode are both conductive resin materials.
  • the conductive resin material includes a resin matrix and a conductive incorporation.
  • the pixel electrode and the common electrode which are convexly disposed can be prepared on the base substrate by photolithography.
  • a method of preparing a thin film transistor array substrate will be described as an example.
  • a conductive resin material layer is formed (for example, coated) on a base substrate on which a structure including a thin film transistor, a gate line, a data line, and the like, and a passivation layer is prepared; then, light is formed on the conductive resin material layer a photoresist layer, exposing and developing the photoresist layer to obtain a photoresist pattern; next, etching the conductive resin material layer using the photoresist pattern to obtain a pixel electrode and a common electrode; and finally, removing the remaining photolithography Glue pattern.
  • the conductive resin material itself has photosensitive properties
  • the pixel electrode and the common electrode can be obtained by directly exposing and developing the formed conductive resin material layer.
  • Structures such as a thin film transistor, a gate line, a data line, and the like on the base substrate, and a passivation layer can be prepared by a usual method.
  • the resin matrix includes an epoxy resin, an acrylic resin or a polyurethane.
  • the resin matrix may further include a phenol resin, an alkyd resin, a synthetic fatty acid resin, or the like.
  • the conductive incorporation includes metal particles or fibers, carbon particles or fibers, or graphene.
  • the metal particles or fibers include silver nanoparticles or fibers, nickel nanoparticles or fibers, etc.
  • the carbon particles include hollow carbon particles, solid carbon spheres, core-shell structured carbon spheres, and colloidal carbon spheres
  • the carbon fibers include acrylonitrile carbon fibers and pitch carbon fibers.
  • the conductive incorporation may also include seamless, hollow carbon nanotubes rolled from layers of graphene, including single-walled carbon nanotubes, double-walled carbon nanotubes, and multi-walled carbon nanotubes.
  • the conductive resin material has a certain hardness and can be prepared to have a relatively large size.
  • the thickness (height) requirement is provided so as to be convexly disposed on the base substrate 101 perpendicular to the base substrate 101, and the resin substrate has good light transmittance at the same time, so that the aperture ratio is not lowered.
  • Embodiments of the present invention provide a thin film transistor array substrate, a method of fabricating the same, a display panel, and a display device, which have at least one of the following beneficial effects:
  • the pixel electrode and the common electrode of the structure are applied to the display panel, and the spacer (PS) provided between the array substrate and the opposite substrate can be at least partially replaced to function as a supporting counter substrate.

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Abstract

一种阵列基板及其制备方法、显示面板和显示装置。该阵列基板包括：衬底基板(101)；设置在衬底基板(101)上的栅线(102)和数据线(103)，栅线(102)和数据线(103)交叉以限定像素区域(104)；设置在像素区域(104)内的像素电极(106)和公共电极(107)；像素电极(106)和公共电极(107)均垂直于衬底基板(101)而凸出地设置在衬底基板(101)上，由此彼此相对设置；在给像素电极(106)和公共电极(107)施加电压后，像素电极(106)和公共电极(107)相对的面之间可以产生平行于衬底基板(101)的电场。将该结构的像素电极和公共电极应用于平面转换显示模式中，可使平行电场的分布更均匀，可以提高光线的透过率，改善显示面板的响应速度。

Description

阵列基板及其制备方法、显示面板和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)是薄膜晶体管(TFT)作为像素单元的开关控制元件的液晶显示装置。液晶的电学特性、光学特性和显示模式都直接影响到液晶显示装置的显示效果。在TFT-LCD领域，常见的液晶显示模式有TN(扭曲向列型)显示模式、IPS(平面转换)显示模式和ADS(高级超维场转换)显示模式等。
IPS显示模式具有可视角度大、动态清晰度高和色彩还原效果好的优点，其在科技含量较高的航天、医疗、设计等领域具有广泛的应用。在IPS显示模式中，两个电极设置在同一个平面内，液晶分子在平面内转动，从而实现亮度的控制。但是，不管在何种状态下，IPS显示模式中都希望液晶分子始终都与显示面板平行，液晶分子排布不均匀会降低开口率，降低透光率，从而减弱亮度。
发明内容
本发明至少一个实施例提供一种阵列基板，包括：衬底基板；设置在所述衬底基板上的栅线和数据线，所述栅线和所述数据线交叉以限定像素区域；设置在所述像素区域内的像素电极和公共电极；其中，所述像素电极和所述公共电极均垂直于所述衬底基板而凸出地设置在所述衬底基板上，由此彼此相对设置；在给所述像素电极和所述公共电极施加电压后，所述像素电极和所述公共电极相对的面之间可以产生平行于所述衬底基板的电场。
例如，在本发明一实施例提供的阵列基板中，所述像素电极和所述公共电极的材料均为导电树脂材料。
例如，在本发明一实施例提供的阵列基板中，所述导电树脂材料包括 树脂基体和导电掺入物。
例如，在本发明一实施例提供的阵列基板中，所述树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯等。
例如，在本发明一实施例提供的阵列基板中，所述导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯等。
例如，在本发明一实施例提供的阵列基板中，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括：连接到所述栅线的栅极、有源层、连接到所述数据线并与所述有源层接触的源极、与所述源极相对设置并与所述有源层接触的漏极、位于所述栅极和所述有源层之间的栅绝缘层，并且所述漏极还与所述像素电极电连接。
例如，在本发明一实施例提供的阵列基板中，所述薄膜晶体管上设置有钝化层和贯穿所述钝化层的过孔结构。
例如，在本发明一实施例提供的阵列基板中，所述像素电极通过所述过孔结构与所述漏极电连接。
例如，在本发明一实施例提供的阵列基板中，所述薄膜晶体管可以是底栅型或顶栅型的薄膜晶体管。
例如，在本发明一实施例提供的阵列基板中，所述像素电极和所述公共电极呈长条状，由此彼此相对。
例如，在本发明一实施例提供的阵列基板中，每个所述像素区域包括至少一个所述像素电极或至少一个所述公共电极。
例如，在本发明一实施例提供的阵列基板，还包括公共电极线，所述公共电极与所述公共电极线电连接。
本发明至少一个实施例还提供一种显示面板，包括上述任一所述薄膜晶体管阵列基板、与所述衬底基板平行设置的对置基板和设置于所述阵列基板和所述对置基板之间的液晶分子。
例如，在本发明一实施例提供的显示面板中，所述像素电极和所述公共电极在垂直于所述衬底基板上的厚度为所述液晶分子的厚度。
例如，在本发明一实施例提供的显示面板中，所述像素电极和所述公共电极均垂直于所述对置基板且支撑所述对置基板。
例如，在本发明一实施例提供的显示面板中，所述对置基板是彩膜基板。
本发明至少一个实施例还提供一种显示装置，包括上述任一显示面板。
本发明至少一个实施例还提供一种阵列基板的制备方法，包括：在衬底基板上形成栅线、数据线和由所述栅线和所述数据线交叉限定的像素区域；在所述像素区域内形成像素电极和公共电极；其中，所述像素电极和所述公共电极均垂直于所述衬底基板而凸出地设置在所述衬底基板上，由此彼此相对设置；在给所述像素电极和所述公共电极施加电压后，所述像素电极和所述公共电极相对的面之间可以产生平行于所述衬底基板的电场。
例如，在本发明一实施例提供的制备方法中，所述像素电极和所述公共电极的材料均为导电树脂材料。
例如，在本发明一实施例提供的制备方法中，所述导电树脂材料包括树脂基体和导电掺入物。
例如，在本发明一实施例提供的制备方法中，所述树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯等。
例如，在本发明一实施例提供的制备方法中，所述导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯等。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种阵列基板的结构示意图；
图2为图1中阵列基板沿A-B线的剖视截面图；
图3为本发明一实施例提供的顶栅型薄膜晶体管的截面结构示意图；
图4为本发明一实施例提供的显示面板的结构示意图；
图5为本发明一实施例提供的一种阵列基板的制作方法流程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。 显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常在IPS模式的液晶面板中，像素电极和公共电极用透明导电材料或金属材料制作。如果采用透明导电材料或金属材料制作上述电极，则一般采用沉积薄膜的方式。采用沉积薄膜的方式形成的电极的厚度比较薄，则施加了电压信号之后在像素电极和公共电极的上表面之间会形成弧状的电场线，液晶分子会随着该弧状电场线排布，由此导致液晶面板的光线的透过率降低。即使使用多次沉积的方式来加厚(高)像素电极和公共电极，也会因为多层导电层之间粘结力弱而带来透明导电层或金属层易剥落的问题，且工序繁琐，成本高。
在研究中，本公开的发明人注意到，如果采用具有一定硬度的导电树脂材料制作像素电极和公共电极，则可以让两电极均垂直于衬底基板而凸出地设置在衬底基板上，且该像素电极和公共电极彼此相对设置，由此在施加了电压信号之后可在像素电极和公共电极相对的面之间产生平行于衬底基板的水平电场，使液晶分子可以均匀的排布，从而可以提高液晶分子切换的速度由此改善液晶面板的显示响应速度，还可以提升液晶面板的光线的透过率和改善显示效果。
本发明至少一实施例提供一种阵列基板及其制备方法、显示面板和显示装置。该阵列基板包括：衬底基板；设置在衬底基板上的栅线和数据线，该栅线和数据线交叉以限定像素区域；设置在像素区域内的像素电极和公共电极；其中，像素电极和公共电极均垂直于衬底基板而凸出地设置在衬 底基板上，由此彼此相对设置；在给像素电极和公共电极施加电压后，像素电极和公共电极相对的面之间可以产生平行于衬底基板的电场。
将该种结构的像素电极和公共电极应用于IPS显示模式中，可使二者在通电后产生的平行电场的分布更均匀，有利于增加液晶切换速度、提高光线的透过率和改善显示面板的响应速度。除此之外，将该结构的像素电极和公共电极应用于显示面板中，还可以至少部分取代设置在阵列基板和对置基板之间的隔垫物(PS)，起到支撑对置基板的作用，从而改善了液晶面板的抗压性能。
本发明的实施例提供一种阵列基板，该阵列基板上的开关元件可以是薄膜晶体管或其他开关元件。例如，该阵列基板可为薄膜晶体管阵列基板，以下均以薄膜晶体管阵列基板为例加以说明。
例如，图1为本发明一实施例提供的一种薄膜晶体管阵列基板的结构示意图，图2为图1中薄膜晶体管阵列基板沿A-B线的剖视截面图。参见图1和图2，该阵列基板100包括：衬底基板101；设置在衬底基板101上的栅线102和数据线103，栅线102和数据线103交叉以限定像素区域104；设置在像素区域104内的薄膜晶体管105、像素电极106和公共电极107；其中，像素电极106和公共电极107均垂直于衬底基板101而凸出地设置在衬底基板101上，由此彼此相对设置，在给像素电极106和公共电极107施加电压后，像素电极106和公共电极107相对的面之间可以产生平行于衬底基板101的电场，而不会在像素电极和公共电极的顶部形成弧状的电场线。
例如，像素电极106和公共电极107均可以被制作得很厚(高)，且相对设置，由此二者彼此正对的部分限定了容纳液晶的空间，且由此二者在被施加了电信号(通电)后在该空间中形成均匀的水平电场，该水平电场线垂直于像素电极106和公共电极107相对的面。该电场作用在二者之间容纳的液晶上以控制液晶分子的排布。这里，“凸出地设置”是指沿垂直于衬底基板101的方向延伸，像素电极106和公共电极107的厚度(高度)和其间的液晶层的厚度(高度)一致。液晶分子可以沿像素电极106和公共电极107之间的平行电场线均匀地排布。
例如，衬底基板101是透明绝缘基板，其材料可以是玻璃、石英或其他适合的材料。
例如，如图1所示，两条栅线102和两条数据线103交叉设置限定像素区域104。图1中只示出了两条栅线102和两条数据线103，可以在衬底基板101上设置多条栅线102和多条数据线103。可用于栅线102和数据线103的材料包括铜、铜合金、铝、铝合金、钼、钼合金或其他适合的材料。栅线102包括从其上分叉的多个栅极108，栅信号通过栅线102被施加到栅极108上。
例如，如图1所示，公共电极线113被设置在衬底基板101上，其基本平行于栅线102。图1中只示出了一条公共电极线113，可以在衬底基板101上设置多条公共电极线113。可用于公共电极线113的材料包括铜、铜合金、铝、铝合金、钼、钼合金、导电树脂或其他适合的材料。例如，公共电极线可以与栅线同层设置或不同层设置。
例如，如图1所示，薄膜晶体管105包括：连接到栅线102的栅极108、有源层109、连接到数据线103并与有源层109接触的源极110、与源极110相对设置并与有源层109接触的漏极111、位于栅极108和有源层109之间的栅绝缘层112，并且漏极111还与像素电极106电连接。
例如，如图2所示，栅绝缘层112覆盖栅线102、栅极108、公共电极线113和公共电极107。栅绝缘层112的材料包括氧化硅、氮化硅。
例如，有源层109设置在栅绝缘层112上，与栅极108相对应，用于有源层109的材料包括非晶硅、金属氧化物半导体、有机物半导体等。
例如，用于源极110和漏极111的材料可以为铜、铜合金、铝、铝合金、钼、钼合金或其他适合的材料。
例如，钝化层115覆盖数据线103、有源层109、源极110和漏极111。钝化层115包括暴露一部分漏极111的过孔结构114。用于钝化层115的材料包括氧化硅、氮化硅或其他适合的材料。
例如，在钝化层115上还可以设置有平坦层116，平坦层116的厚度较厚。除了在过孔结构114处平坦层116会不平整外，平坦层表面的其他部分都是平整的。例如，平坦层116的材料可以是氧化硅、氮化硅等无机材料或环氧树脂、丙烯酸树脂、聚氨酯等有机材料。
例如，如图2所示，像素电极106设置在平坦层116上，其通过过孔结构114与漏极111电连接，由此数据信号(电压)可以通过数据线和薄膜晶体管施加到该像素电极106上。用于像素电极106的材料为导电树脂 材料。虽然图1中只示出了一个像素区域中的三条长条状结构的像素电极106，但是该阵列基板还可以包括更多的像素区域，以及每个像素区域还可以包括更多的长条状结构的像素电极106。
例如，公共电极107设置在平坦层116上，其通过过孔结构(图中未示出)与公共电极线113电连接。公共电压通过公共电极线113施加到公共电极107。用于公共电极107的材料为导电树脂材料，虽然图1中只示出了一个像素区域中的三条长条状结构的公共电极107，但是每个像素区域还可以包括更多长条状结构的公共电极107。
像素电极106和公共电极107均呈长条状，由此像素电极106和公共电极107彼此相对，从而可以在它们之间形成均匀的水平电场。
例如，每个像素区域104包括至少一个像素电极106或至少一个公共电极107。例如，每个像素电极106均与公共电极107相邻设置，每个公共电极107均与像素电极106相邻设置。
例如，导电树脂材料包括树脂基体和导电掺入物，导电颗粒掺入树脂基体中后对所述树脂基体进行了改性，使整个树脂基体具有了导电性。
例如，树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯。例如，该树脂基体还可以包括酚醛树脂、醇酸树脂、合成脂肪酸树脂等。
例如，导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯。例如，金属颗粒或纤维包括银纳米颗粒或纤维、镍纳米颗粒或纤维等；碳颗粒包括空心碳颗粒、实心碳球、核壳结构碳球和胶状碳球，碳纤维包括丙烯腈基碳纤维、沥青基碳纤维。例如，导电掺入物还可以包括由石墨烯片层卷成的无缝、中空的导电性的碳纳米管，包括单壁碳纳米管、双壁碳纳米管和多壁碳纳米管。
例如，该导电树脂材料可以具有一定的硬度，如图2所示，可以满足像素电极106和公共电极107被制造成具有比较大的厚度(高度)的要求，即可以满足像素电极106和公共电极107垂直于衬底基板101而凸出地设置在衬底基板101上，并且在二者相对的面之间可以产生平行于衬底基板101的电场。该树脂基体同时具有很好的透光性，所以不会降低开口率。
例如，薄膜晶体管105可以是底栅型或顶栅型的薄膜晶体管。图1和图2是以底栅型结构的薄膜晶体管为例加以说明的。例如，图3为本发明一实施例提供的顶栅型薄膜晶体管的截面结构示意图。栅极108设置在有 源层109、源极110、漏极111的上方，栅绝缘层112设置在栅极108的下方，从而隔绝栅极108和有源层109。其他的结构设置、各层的材料均和上述底栅型薄膜晶体管中描述的内容一致，在此不再赘述。
本发明的实施例还提供一种显示面板，例如，图4为本发明一实施例提供的显示面板的结构示意图。例如，如图4所示，该显示面板200包括上述任一薄膜晶体管阵列基板100、与衬底基板101平行设置的对置基板117和设置于阵列基板100和对置基板117之间的液晶分子118。
例如，如图4所示，该像素电极和公共电极在垂直于衬底基板101方向上的厚度(高度)为液晶分子118的厚度(高度)，此处像素电极和公共电极在垂直于衬底基板101方向上的厚度(高度)为平坦层116至对置基板117的与衬底基板101相对一侧的高度，需要说明的是，像素电极106和公共电极107在垂直于衬底基板101方向上的厚度(高度)也并非严格意义上的液晶分子118的厚度(高度)。
例如，如图4所示，像素电极106和公共电极107均垂直于对置基板117且支撑对置基板117。将该种结构的像素电极106和公共电极107应用于IPS显示模式中，对像素电极106和公共电极107施加电压后，可以使在像素电极106和公共电极107之间形成的平行电场的分布更均匀，使液晶分子118在两个电极之间沿着电场线的方向均匀地排布，从而可提高光线的透过率。该像素电极106和公共电极107不仅具有导电的作用，同时，还可以至少部分取代设置在阵列基板101和对置基板117之间的隔垫物(PS)，起到支撑对置基板117的作用，这样可以节省工艺步骤。
例如，该对置基板117是彩膜基板。像素电极106和公共电极107均垂直于衬底基板且支撑着彩膜基板，可以至少部分取代设置在阵列基板101和彩膜基板之间的隔垫物(PS)，简化了工艺步骤。
本发明的实施例还提供一种显示装置，包括上述任一显示面板200。
例如，该显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
本发明的实施例还提供一种阵列基板的制备方法，例如，图5为本发明一实施例提供的一种阵列基板的制作方法流程示意图。该方法包括：在 衬底基板上形成栅线、数据线和由栅线和数据线交叉限定的像素区域；在像素区域内形成像素电极和公共电极；其中，像素电极和公共电极均垂直于衬底基板而凸出地设置在衬底基板上，由此彼此相对设置；在给像素电极和公共电极施加电压后，像素电极和公共电极相对的面之间可以产生平行于衬底基板的电场。
例如，像素电极和公共电极均被制作得很厚(高)，且相对设置。这里，“凸出地设置”是指沿垂直于衬底基板的方向，像素电极和公共电极的厚度(高度)和待封装的液晶层的厚度(高度)一致。液晶分子可以沿像素电极和公共电极之间的平行电场线均匀地排布。
例如，像素电极和公共电极的材料均为导电树脂材料。该导电树脂材料包括树脂基体和导电掺入物。
例如，可以通过光刻的方法在衬底基板上制备凸出地设置的像素电极和公共电极。例如，以薄膜晶体管阵列基板的制备方法为例加以说明。首先，在制备了包括薄膜晶体管、栅线、数据线等驱动电路以及钝化层等结构的衬底基板上形成(例如涂覆)导电树脂材料层；然后，在该导电树脂材料层上形成光刻胶层，将该光刻胶层曝光、显影得到光刻胶图案；接下来，使用该光刻胶图案对导电树脂材料层刻蚀以得到像素电极和公共电极；最后，去除剩余的光刻胶图案。或者，如果导电树脂材料本身具有感光性能，则可以直接通过对形成的导电树脂材料层曝光、显影得到像素电极和公共电极。
衬底基板上的薄膜晶体管、栅线、数据线等驱动电路以及钝化层等结构可以通过通常的方法制备得到。
例如，该树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯。例如，该树脂基体还可以包括酚醛树脂、醇酸树脂、合成脂肪酸树脂等。
例如，导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯。例如，金属颗粒或纤维包括银纳米颗粒或纤维、镍纳米颗粒或纤维等；碳颗粒包括空心碳颗粒、实心碳球、核壳结构碳球和胶状碳球，碳纤维包括丙烯腈碳纤维、沥青碳纤维。例如，导电掺入物还可以包括由石墨烯片层卷成的无缝、中空的碳纳米管，包括单壁碳纳米管、双壁碳纳米管和多壁碳纳米管。
例如，该导电树脂材料具有一定的硬度，可以满足制备成具有比较大 厚度(高度)的要求，即可以满足垂直于衬底基板101而凸出地设置在衬底基板101上，该树脂基体同时具有很好的透光性，所以不会降低开口率。
本发明的实施例提供一种薄膜晶体管阵列基板及其制备方法、显示面板和显示装置，具有以下至少一项有益效果：
(1)将该结构的像素电极和公共电极应用于IPS显示模式中，可在通电后形成均匀的平行电场，使液晶分子的排布更均匀，从而可提高光线的透过率；
(2)通电后形成的均匀的平行电场可以提高液晶分子切换的速度，由此改善液晶面板的显示响应速度；
(3)将该结构的像素电极和公共电极应用于显示面板中，可以至少部分取代设置在阵列基板和对置基板之间的隔垫物(PS)，起到支撑对置基板的作用。
有以下几点需要说明：
(1)本发明实施例附图只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年5月31日递交的中国专利申请第201610378261.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上的栅线和数据线，所述栅线和所述数据线交叉以限定像素区域；
    设置在所述像素区域内的像素电极和公共电极；
    其中，所述像素电极和所述公共电极均垂直于所述衬底基板而凸出地设置在所述衬底基板上，由此彼此相对设置；在给所述像素电极和所述公共电极施加电压后，所述像素电极和所述公共电极相对的面之间可以产生平行于所述衬底基板的电场。
  2. 根据权利要求1所述的阵列基板，其中，所述像素电极和所述公共电极的材料均为导电树脂材料。
  3. 根据权利要求2所述的阵列基板，其中，所述导电树脂材料包括树脂基体和导电掺入物。
  4. 根据权利要求3所述的阵列基板，其中，所述树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯。
  5. 根据权利要求3所述的阵列基板，其中，所述导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述阵列基板还包括薄膜晶体管，所述薄膜晶体管包括：连接到所述栅线的栅极、有源层、连接到所述数据线并与所述有源层接触的源极、与所述源极相对设置并与所述有源层接触的漏极、位于所述栅极和所述有源层之间的栅绝缘层，并且所述漏极还与所述像素电极电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述薄膜晶体管上设置有钝化层和贯穿所述钝化层的过孔结构。
  8. 根据权利要求7所述的阵列基板，其中，所述像素电极通过所述过孔结构与所述漏极电连接。
  9. 根据权利要求6-8中任一项所述的阵列基板，其中，所述薄膜晶体管可以是底栅型或顶栅型的薄膜晶体管。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中，所述像素电 极和所述公共电极呈长条状，由此彼此相对。
  11. 根据权利要求10所述的阵列基板，其中，每个所述像素区域包括至少一个所述像素电极或至少一个所述公共电极。
  12. 根据权利要求11所述的阵列基板，还包括公共电极线，所述公共电极与所述公共电极线电连接。
  13. 一种显示面板，包括权利要求1-12中任一项所述的阵列基板、与所述衬底基板平行设置的对置基板和设置于所述阵列基板和所述对置基板之间的液晶分子。
  14. 根据权利要求13所述的显示面板，其中，所述像素电极和所述公共电极在垂直于所述衬底基板方向上的厚度为所述液晶分子的厚度。
  15. 根据权利要求13所述的显示面板，其中，所述像素电极和所述公共电极均垂直于所述对置基板且支撑所述对置基板。
  16. 根据权利要求15所述的显示面板，其中，所述对置基板是彩膜基板。
  17. 一种显示装置，包括权利要求13-16中任一项所述的显示面板。
  18. 一种阵列基板的制备方法，包括：
    在衬底基板上形成栅线、数据线和由所述栅线和所述数据线交叉限定的像素区域；
    在所述像素区域内形成像素电极和公共电极；
    其中，所述像素电极和所述公共电极均垂直于所述衬底基板而凸出地设置在所述衬底基板上，由此彼此相对设置；在给所述像素电极和所述公共电极施加电压后，所述像素电极和所述公共电极相对的面之间可以产生平行于所述衬底基板的电场。
  19. 根据权利要求18所述的制备方法，其中，所述像素电极和所述公共电极的材料均为导电树脂材料。
  20. 根据权利要求19所述的制备方法，其中，所述导电树脂材料包括树脂基体和导电掺入物。
  21. 根据权利要求20所述的制备方法，其中，所述树脂基体包括环氧树脂、丙烯酸树脂或聚氨酯。
  22. 根据权利要求21所述的制备方法，其中，所述导电掺入物包括金属颗粒或纤维、碳颗粒或纤维、或石墨烯。
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Publication number Priority date Publication date Assignee Title
CN105977263A (zh) * 2016-05-31 2016-09-28 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置
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CN107515495A (zh) * 2017-09-19 2017-12-26 惠科股份有限公司 平面显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131552A1 (ja) * 2009-05-13 2010-11-18 シャープ株式会社 液晶表示装置
CN101995700A (zh) * 2009-08-10 2011-03-30 北京京东方光电科技有限公司 液晶面板及其制造方法
US20110141421A1 (en) * 2009-12-11 2011-06-16 Sang-Wook Lee Liquid crystal display device
CN104765207A (zh) * 2015-01-20 2015-07-08 深圳市华星光电技术有限公司 像素结构及具有该像素结构的液晶显示器
CN105278181A (zh) * 2015-11-05 2016-01-27 武汉华星光电技术有限公司 响应时间短的液晶面板及显示装置
CN105977263A (zh) * 2016-05-31 2016-09-28 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716551A (en) * 1996-02-09 1998-02-10 Tech Spray, Inc. Static dissipative composition and process for static disspative coatings
US8713420B2 (en) * 2011-06-30 2014-04-29 Cable Television Laboratories, Inc. Synchronization of web applications and media
CN102879958A (zh) * 2012-09-28 2013-01-16 京东方科技集团股份有限公司 一种阵列基板及其制造方法、液晶显示装置
CN103268178B (zh) * 2012-12-31 2017-06-16 上海天马微电子有限公司 水平电场驱动模式的阵列基板及触摸屏
TWI563332B (en) * 2016-03-02 2016-12-21 Au Optronics Corp Liquid crystal display panel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131552A1 (ja) * 2009-05-13 2010-11-18 シャープ株式会社 液晶表示装置
CN101995700A (zh) * 2009-08-10 2011-03-30 北京京东方光电科技有限公司 液晶面板及其制造方法
US20110141421A1 (en) * 2009-12-11 2011-06-16 Sang-Wook Lee Liquid crystal display device
CN104765207A (zh) * 2015-01-20 2015-07-08 深圳市华星光电技术有限公司 像素结构及具有该像素结构的液晶显示器
CN105278181A (zh) * 2015-11-05 2016-01-27 武汉华星光电技术有限公司 响应时间短的液晶面板及显示装置
CN105977263A (zh) * 2016-05-31 2016-09-28 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置

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