WO2017202123A1 - 一种基准电路 - Google Patents

一种基准电路 Download PDF

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Publication number
WO2017202123A1
WO2017202123A1 PCT/CN2017/077669 CN2017077669W WO2017202123A1 WO 2017202123 A1 WO2017202123 A1 WO 2017202123A1 CN 2017077669 W CN2017077669 W CN 2017077669W WO 2017202123 A1 WO2017202123 A1 WO 2017202123A1
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WO
WIPO (PCT)
Prior art keywords
transistor
voltage
resistor
control unit
reference circuit
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PCT/CN2017/077669
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English (en)
French (fr)
Inventor
王糖祥
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/566,121 priority Critical patent/US10509430B2/en
Publication of WO2017202123A1 publication Critical patent/WO2017202123A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • Embodiments of the present invention relate to the field of integrated circuit technologies, and in particular, to a reference circuit.
  • the power supply voltage is susceptible to the temperature of the external environment.
  • the power supply voltage changes as the temperature of the external environment changes, directly or indirectly affecting the performance of the entire integrated circuit.
  • the embodiment of the invention provides a reference circuit, including:
  • the first end of the current control unit is connected to the first level signal end, the second end is connected to the first end of the voltage control unit, and the third end is connected to the second end of the voltage control unit.
  • a fourth end connected to the first end of the voltage adjustment unit and an output of the reference circuit, the current control unit being configured to respectively adjust to the first end and the second end of the voltage control unit and the voltage
  • the first end of the unit outputs a current having a ratio of 1:1: n; wherein n is a positive number;
  • the third end of the voltage control unit is connected to the second end of the voltage adjustment unit, the fourth end is connected to the third end of the voltage adjustment unit, and the voltage control unit respectively goes to the voltage adjustment unit The second end and the third end output equal voltages;
  • the voltage adjustment unit is configured to adjust a voltage outputted by an output end of the reference circuit such that a voltage output by the output terminal is independent of temperature.
  • the voltage adjustment unit comprises: a first triode, a second triode, a first resistor, a second resistor and a third resistor;
  • One end of the first resistor and one end of the second resistor are respectively connected to the first node, the other end of the first resistor is connected to the emitter of the first transistor, and the other of the second resistor Grounded at one end;
  • One end of the third resistor is respectively connected to the fourth end of the current control unit and the output end, and the other end is grounded;
  • a base and a collector of the first transistor and a base and a collector of the second transistor are grounded, respectively, an emitter of the second transistor and a fourth end of the voltage control unit Connected.
  • the voltage adjustment unit further includes: a fourth resistor
  • One end of the fourth resistor is connected to the second node, and the other end is grounded.
  • the resistance value of the second resistor is equal to the resistance value of the fourth resistor.
  • the voltage control unit includes: a first transistor and a second transistor; wherein
  • a gate of the first transistor is respectively connected to a gate and a drain of the second transistor, a source of the first transistor is connected to the first node, a drain of the first transistor is The second end of the current adjustment unit is connected;
  • a source of the second transistor is coupled to the second node.
  • the first transistor and the second transistor are both N-type transistors.
  • the current control unit includes: a third transistor, a fourth transistor, and a fifth transistor; wherein
  • a gate and a drain of the third transistor, a gate of the fourth transistor, and a gate of the fifth transistor are respectively connected to a drain of the first transistor, a source of the third transistor, a source of the fourth transistor and a source of the fifth transistor are respectively connected to the first level signal end;
  • a drain of the fourth transistor is respectively connected to a gate and a drain of the second transistor and a gate of the first transistor;
  • the drain of the fifth transistor is connected to the output.
  • the third transistor, the fourth transistor and the fifth transistor are all P-type transistors.
  • the first end and the second end of the voltage control unit can make the voltage of the second end of the voltage adjusting unit equal to the third end of the voltage adjusting unit when receiving the equal current output by the current control unit.
  • Voltage. Therefore, the voltage adjusting unit can adjust the voltage outputted by the output end of the reference circuit to be independent of temperature when the voltage of the second terminal is equal to the voltage of the third terminal, so that the reference circuit can provide the integrated circuit with a voltage that is substantially independent of temperature. Thereby the performance of the entire integrated circuit can be optimized.
  • FIG. 1 is a schematic structural diagram of a reference circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing an example structure of a reference circuit according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing another example structure of a reference circuit in accordance with an embodiment of the present invention.
  • the embodiment of the invention provides a reference circuit, as shown in FIG. 1, comprising: a current control unit 1, a voltage control unit 2 and a voltage adjustment unit 3.
  • the first end 1a of the current control unit 1 is connected to the first level signal terminal Rer1, the second end 1b is connected to the first end 2a of the voltage control unit 2, and the third end 1c is connected to the second end 2b of the voltage control unit 2.
  • the fourth end 1d is connected to the first end 3a of the voltage adjusting unit 3 and the output end of the reference circuit, respectively.
  • the current control unit 1 is configured to output a current having a ratio of 1: 1:n to the first end 2a and the second end 2b of the voltage control unit 2 and the first end 3a of the voltage adjusting unit 3, respectively; wherein n is a positive number.
  • the third end 2c of the voltage control unit 2 is connected to the second end 3b of the voltage adjusting unit 3, and the fourth end 2d is connected to the third end 3c of the voltage adjusting unit 3.
  • the voltage control unit 2 is configured to output equal voltages to the second end 3b and the third end 3c of the voltage adjusting unit 3, respectively.
  • the voltage adjusting unit 3 is configured to adjust the voltage outputted by the output terminal so that the voltage outputted by the output terminal is independent of temperature.
  • the current control unit respectively outputs equal currents to the first end and the second end of the voltage control unit, and the first end and the second end of the voltage control unit receive the output of the current control unit
  • the voltage of the second end of the voltage adjusting unit can be equal to the voltage of the third end of the voltage adjusting unit.
  • the voltage adjusting unit can adjust the voltage outputted from the output end of the reference circuit to be independent of temperature when the voltage of the second terminal is equal to the voltage of the third terminal, so that the reference circuit can provide the integrated circuit with a voltage that is substantially independent of temperature, thereby optimizing Whole The performance of an integrated circuit.
  • the voltage of the first level signal terminal Ref1 may be a positive voltage.
  • the voltage adjusting unit 3 may include: a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3; wherein, one end of the first resistor R1 And one end of the second resistor R2 is respectively connected to the first node A, the other end of the first resistor R2 is connected to the emitter of the first transistor Q1, and the other end of the second resistor R2 is grounded; one end of the third resistor R3 is respectively Connected to the fourth end 1d of the current control unit 1 and the output terminal Output, the other end is grounded; the base and collector of the first transistor Q1 and the base and collector of the second transistor Q2 are grounded, respectively The emitter of the transistor Q2 is connected to the fourth terminal 2d of the voltage control unit 2.
  • the first resistor R1 is connected in series with the first transistor Q1.
  • a second transistor Q2 connected in parallel, the voltage V R1 across the first resistor R1 to the second transistor Q2 base - emitter junction voltage V BE2 of the first transistor Q1 is base - emitter junction voltage V
  • V t is the thermal voltage
  • V t kT/q
  • k is the Boltzmann constant
  • k 1.38 ⁇ 10-23J/K
  • T is the thermodynamic temperature, ie the absolute temperature, the normal temperature.
  • T 300K
  • q the charge amount of electrons
  • q 1.6 ⁇ 10-19C. Therefore, it can be derived that the voltage across the first resistor R1 Assuming that the area of the emitter of the second transistor Q2 is N times the area of the emitter of the first transistor Q1, the saturation current I S2 of the second transistor Q2 is the saturation current of the first transistor Q1.
  • the current on the first resistor R1 is A second resistor R2 and a second transistor Q2 connected in parallel across the second resistor R2 is equal to voltage V R2 of the second transistor Q2 base - emitter junction voltage V be2, the current to the second resistor R2
  • the current output by the current control unit 1 to the first terminal 2a of the voltage control unit 2 is the sum of the current on the first resistor R1 and the current on the second resistor R2, ie Since the ratio of the current output by the current control unit 1 to the first end 2a and the second end 2b of the voltage control unit 2 and the first end 3a of the voltage adjusting unit 3 is 1:1: n, the current control unit 1
  • the current outputted by the first terminal 3a of the voltage adjusting unit 3, that is, the current on the third resistor R3 is It can be seen that the voltage across the third resistor R3, that is, the output of the output terminal of the reference circuit is Where V t is positively correlated with temperature, and V
  • the output voltage of the output terminal of the reference circuit can be output. Basically unaffected by temperature. Further, it is calculated and simulated that the voltage outputted from the output terminal of the reference circuit can be controlled to about 0.6 V, and therefore, the above reference circuit according to an embodiment of the present invention can also realize a low voltage output.
  • the voltage adjusting unit 3 may further include: a fourth resistor R4; one end of the fourth resistor R4 is connected to the second node B, and the other end is grounded; thus, the first resistor R1 and the second resistor R2 may be designed.
  • the resistance values of the third resistor R3 and the fourth resistor R4 cause the voltage outputted from the output terminal of the reference circuit to be substantially unaffected by the temperature.
  • the second resistor R2 can be maintained.
  • the resistance value is equal to the resistance value R4 of the fourth resistor, so that the current on the second resistor R2 is equal to the current on the fourth resistor, thereby ensuring that the collector current of the first transistor Q1 is equal to the second transistor
  • the collector current of Q2, ie I C1 I C2 .
  • the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may be resistors having a fixed resistance, and the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor are properly designed.
  • the resistance of R4 is such that the voltage outputted by the output terminal Output of the above reference circuit provided by the embodiment of the present invention is substantially unaffected by temperature.
  • the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may also be resistors with adjustable resistance values, for example, variable resistors, by properly adjusting the first resistor R1 and the second resistor R2.
  • the resistance values of the third resistor R3 and the fourth resistor R4 are such that the voltage outputted by the output terminal Output of the reference circuit provided by the embodiment of the present invention is substantially unaffected by temperature;
  • the voltage control unit 2 may include: a first transistor T1 and a second transistor T2; wherein a gate of the first transistor T1 is respectively connected to a gate and a drain of the second transistor T2, and the first transistor T1
  • the source is connected to the first node A
  • the drain of the first transistor T1 is connected to the second terminal 1b of the current adjustment unit 1
  • the source of the second transistor T2 is connected to the second node B.
  • the current control unit 1 when the voltage control unit 2 includes the first transistor T1 and the second transistor T2, the current control unit 1 outputs equal currents, that is, currents, to the first terminal 2a and the second terminal 2b of the voltage control unit 2, respectively.
  • the control unit 1 outputs equal currents to the drain of the first transistor T1 and the drain of the second transistor T2, respectively, that is, the current of the first transistor T1 operating in the saturation region is equal to the current of the second transistor T2 operating in the saturation region;
  • the current in the saturation region satisfies the formula Where ⁇ n is the migration rate of electrons, and C ox is the capacitance of the active layer per unit area, Is the width to length ratio of the channel, V gs is the voltage between the gate and the source, and V th is the threshold voltage; therefore, the voltage V gs1 between the gate and the source of the first transistor T1 is equal to the first transistor T1 a voltage V gs2 between the gate and the source, so that the voltage of the first node A can be equal to the voltage of the second node B, that is, the voltage of the second terminal 3b of the voltage adjusting unit 3 is equal to the third of the voltage adjusting unit 3 The voltage at terminal 3c.
  • the voltage control unit 2 adopts the configuration of the above-mentioned clamp circuit, and can output equal voltages to the second end 3b and the third end 3c of the voltage adjusting unit 3 by using only two transistors, so that the reference can be simplified.
  • the structure of the circuit reduces the power consumption of the reference circuit, so that a low voltage input can be realized, and the voltage of the first level signal terminal Ref1 is controlled to about 1.8V.
  • the first transistor T1 and the second transistor T2 may both be N-type transistors.
  • the current control unit 1 may include: a third transistor T3, a fourth transistor T4, and a fifth transistor T5; wherein a gate and a drain of the third transistor T3 and a gate of the fourth transistor T4
  • the gates of the poles and the fifth transistor T5 are respectively connected to the drains of the first transistors T1, the sources of the third transistor T3, the source of the fourth transistor T4, and the source of the fifth transistor T5 are respectively associated with the first level signal.
  • the terminal Ref1 is connected; the drain of the fourth transistor T4 is respectively connected to the gate and the drain of the second transistor T2 and the gate of the first transistor T1; the drain of the fifth transistor T5 is connected to the output terminal Output.
  • the current control unit 1 includes the third transistor T3, the fourth transistor T4, and the fifth transistor T5, the structure of the mirror circuit is adopted, the aspect ratios of the third transistor T3 and the fourth transistor T4 are equal, and the third transistor T3 is When the aspect ratio of the fifth transistor T5 is 1:n, a current having a ratio of 1:1:1: can be output to the first end 2a and the second end 2b of the voltage control unit 2 and the first end 3a of the voltage adjusting unit 3 .
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may both be P-type transistors.
  • MOS Metal Oxide Scmiconductor

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Abstract

一种基准电路，包括：电流控制单元（1）、电压控制单元（2）和电压调整单元（3）；其中，电流控制单元（1）分别向电压控制单元（2）的第一端（2a）和第二端（2b）以及电压调整单元（3）的第一端（3a）输出比值为1:1:n的电流，电压控制单元（2）的第一端（2a）和第二端（2b）在接收到电流控制单元（1）输出的相等的电流时可以使电压调整单元（3）的第二端（3b）的电压等于电压调整单元（3）的第三端（3c）的电压，电压调整单元（3）在第二端（3b）的电压等于第三端（3c）的电压时可以调整基准电路的输出端（Output）输出的电压使其与温度无关。

Description

一种基准电路
本申请要求于2016年5月26日提交的、申请号为201610363419.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及集成电路技术领域，尤其涉及一种基准电路。
背景技术
在传统的集成电路中，电源电压容易受到外界环境的温度的影响。电源电压随外界环境的温度的改变而变化，会直接或间接地影响整个集成电路的性能。
因此，需要为一种基准电路为集成电路提供基本不受外界环境的温度的影响的电压。
发明内容
本发明实施例提供了一种基准电路，包括：
电流控制单元；
电压控制单元；以及
电压调整单元；
其中，所述电流控制单元的第一端与第一电平信号端相连，第二端与所述电压控制单元的第一端相连，第三端与所述电压控制单元的第二端相连，第四端与所述电压调整单元的第一端和所述基准电路的输出端相连，所述电流控制单元配置为分别向所述电压控制单元的第一端和第二端以及所述电压调整单元的第一端输出比值为1∶1∶n的电流；其中，n为正数；
其中，所述电压控制单元的第三端与所述电压调整单元的第二端相连，第四端与所述电压调整单元的第三端相连，所述电压控制单元分别向所述电压调整单元的第二端和第三端输出相等的电压；
其中，所述电压调整单元配置为调整所述基准电路的输出端输出的电压，使所述输出端输出的电压与温度无关。
根据本发明实施例，所述电压调整单元包括：第一三极管、第二三极管、第一电阻、 第二电阻和第三电阻；其中，
所述第一电阻的一端和所述第二电阻的一端分别与第一节点相连，所述第一电阻的另一端与所述第一三极管的发射极相连，所述第二电阻的另一端接地；
所述第三电阻的一端分别与所述电流控制单元的第四端和所述输出端相连，另一端接地；
所述第一三极管的基极和集电极以及所述第二三极管的基极和集电极分别接地，所述第二三极管的发射极与所述电压控制单元的第四端相连。
根据本发明实施例，所述电压调整单元还包括：第四电阻；
所述第四电阻的一端与第二节点相连，另一端接地。
根据本发明实施例，所述第二电阻的电阻值等于所述第四电阻的电阻值。
根据本发明实施例提供，所述电压控制单元包括：第一晶体管和第二晶体管；其中，
所述第一晶体管的栅极分别与所述第二晶体管的栅极和漏极相连，所述第一晶体管的源极与所述第一节点相连，所述第一晶体管的漏极与所述电流调整单元的第二端相连；
所述第二晶体管的源极与所述第二节点相连。
根据本发明实施例，所述第一晶体管和所述第二晶体管均为N型晶体管。
根据本发明实施例，所述电流控制单元包括：第三晶体管、第四晶体管和第五晶体管；其中，
所述第三晶体管的栅极和漏极、所述第四晶体管的栅极以及所述第五晶体管的栅极分别与所述第一晶体管的漏极相连，所述第三晶体管的源极、所述第四晶体管的源极和所述第五晶体管的源极分别与所述第一电平信号端相连；
所述第四晶体管的漏极分别与所述第二晶体管的栅极和漏极以及所述第一晶体管的栅极相连；
所述第五晶体管的漏极与所述输出端相连。
根据本发明实施例，所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
根据本发明实施例的上述基准电路，电压控制单元的第一端和第二端在接收到电流控制单元输出的相等电流时可以使电压调整单元的第二端的电压等于电压调整单元的第三端 的电压。由此，电压调整单元在第二端的电压等于第三端的电压时可以调整基准电路的输出端输出的电压使其与温度无关，这样，基准电路可以为集成电路提供基本不受温度影响的电压，从而可以优化整个集成电路的性能。
附图说明
图1为根据本发明实施例的基准电路的结构示意图；
图2为根据本发明实施例的基准电路的一个示例结构示意图；
图3为根据本发明实施例的基准电路的另一个示例结构示意图。
具体实施方式
下面结合附图，对根据本发明实施例的基准电路的具体实施方式进行详细地说明。
本发明实施例提供了一种基准电路，如图1所示，包括：电流控制单元1、电压控制单元2和电压调整单元3。电流控制单元1的第一端1a与第一电平信号端Rer1相连，第二端1b与电压控制单元2的第一端2a相连，第三端1c与电压控制单元2的第二端2b相连，第四端1d分别与电压调整单元3的第一端3a和基准电路的输出端Output相连。电流控制单元1配置为分别向电压控制单元2的第一端2a和第二端2b以及电压调整单元3的第一端3a输出比值为1∶1∶n的电流；其中，n为正数。
电压控制单元2的第三端2c与电压调整单元3的第二端3b相连，第四端2d与电压调整单元3的第三端3c相连。电压控制单元2配置为分别向电压调整单元3的第二端3b和第三端3c输出相等的电压。
电压调整单元3配置为调整输出端Output输出的电压，使输出端Output输出的电压与温度无关。
根据本发明实施例的上述基准电路，电流控制单元分别向电压控制单元的第一端和第二端输出相等的电流，电压控制单元的第一端和第二端在接收到电流控制单元输出的相等电流时可以使电压调整单元的第二端的电压等于电压调整单元的第三端的电压。电压调整单元可以在第二端的电压等于第三端的电压时调整基准电路的输出端输出的电压使其与温度无关，这样，基准电路可以为集成电路提供基本不受温度影响的电压，从而可以优化整 个集成电路的性能。
例如，第一电平信号端Ref1的电压可以为正电压。
如图2所示，电压调整单元3可以包括：第一三极管Q1、第二三极管Q2、第一电阻R1、第二电阻R2和第三电阻R3；其中，第一电阻R1的一端和第二电阻R2的一端分别与第一节点A相连，第一电阻R2的另一端与第一三极管Q1的发射极相连，第二电阻R2的另一端接地；第三电阻R3的一端分别与电流控制单元1的第四端1d和输出端Output相连，另一端接地；第一三极管Q1的基极和集电极以及第二三极管Q2的基极和集电极分别接地，第二三极管Q2的发射极与电压控制单元2的第四端2d相连。
电压调整单元3采用上述第一三极管Q1、第二三极管Q2、第一电阻R1、第二电阻R2和第三电阻R3时，第一电阻R1与第一三极管Q1串联后和第二三极管Q2并联，第一电阻R1两端的电压VR1为第二三极管Q2的基极-发射极结电压Vbe2与第一三极管Q1的基极-发射极结电压Vbe1之差，即VR1＝Vbe2-Vbe1；由于三极管满足公式IC＝IS×exp[Vbe/Vt]，其中，IC为集电极电流，IS为饱和电流，Vbe为基极-发射极结电压，Vt为热电压，Vt＝kT/q，k为波耳兹曼常数，k＝1.38×10-23J/K，T为热力学温度，即绝对温度，常温下，T＝300K，q为电子的电荷量，q＝1.6×10-19C。因此，可以推导出，第一电阻R1两端的电压
Figure PCTCN2017077669-appb-000001
假设第二三极管Q2的发射极的面积是第一三极管Q1的发射极的面积的N倍，则第二三极管Q2的饱和电流IS2是第一三极管Q1的饱和电流IS1的
Figure PCTCN2017077669-appb-000002
则上式可以简化为
Figure PCTCN2017077669-appb-000003
由此可知，第一电阻R1上的电流为
Figure PCTCN2017077669-appb-000004
第二电阻R2与第二三极管Q2并联，第二电阻R2两端的电压VR2等于第二三极管Q2的基极-发射极结电压Vbe2，第二电阻R2上的电流为
Figure PCTCN2017077669-appb-000005
电流控制单元1向电压控制单元2的第一端2a输出的电流为第一电阻R1上的电流与第二电阻R2上的电流之和，即
Figure PCTCN2017077669-appb-000006
由于电流控制单元1分别向电压控制单元2的第一端2a和第二端2b以及电压调整单元3的第一端3a输出的电流的比值为1∶1∶n，因此，电流控制单元1向电压调整单元3的第一端3a输出的电流即第三电阻R3上的电流为
Figure PCTCN2017077669-appb-000007
由此可知，第三电阻R3两端的电压即基准电路的输出端Output输出的电压为
Figure PCTCN2017077669-appb-000008
其中，Vt与温度呈正相关，Vbe2与温度呈负相关，因此，通过设计第一电阻R1、第二电阻R2和第三电阻R3的电阻值即可使基准电路的输出端Output输出的电压基本不受温度的影响。此外，通过计算和仿真得出，基准电路的输出端输出的电压可以控制在0.6V左右，因此，根据本发明实施例的上述基准电路还可以实现低电压输出。
如图3所示，电压调整单元3还可以包括：第四电阻R4；第四电阻R4的一端与第二节点B相连，另一端接地；这样，可以通过设计第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的电阻值使基准电路的输出端Output输出的电压基本不受温度的影响。
例如，在设计第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的电阻值使基准电路的输出端Output输出的电压基本不受温度的影响时，可以保持第二电阻R2的电阻值等于第四电阻的电阻值R4，这样，可以保证第二电阻R2上的电流等于第四电阻上的电流，从而可以保证第一三极管Q1的集电极电流等于第二三极管Q2的集电极电流，即IC1＝IC2。这样，可以将基准电路的输出端Output输出的电压简化为
Figure PCTCN2017077669-appb-000009
例如，第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4可以采用阻值固定的电阻，通过合理设计第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的阻值，使本发明实施例提供的上述基准电路的输出端Output输出的电压基本不受温度的影响。或者，第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4也可以采用阻值可调的电阻，例如，可变电阻器，通过合理调整第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的阻值，使本发明实施例提供的上述基准电路的输出端Output输出的电压基本不受温度的影响；在此不做限定。
如图3所示，电压控制单元2可以包括：第一晶体管T1和第二晶体管T2；其中，第一晶体管T1的栅极分别与第二晶体管T2的栅极和漏极相连，第一晶体管T1的源极与第一节点A相连，第一晶体管T1的漏极与电流调整单元1的第二端1b相连；第二晶体管T2的源极与第二节点B相连。
根据本发明实施例，当电压控制单元2包括第一晶体管T1和第二晶体管T2时，电流控制单元1分别向电压控制单元2的第一端2a和第二端2b输出相等的电流，即电流控制单元1分别向第一晶体管T1的漏极和第二晶体管T2的漏极输出相等的电流，即第一晶体管T1工作在饱和区的电流等于第二晶体管T2工作在饱和区的电流；晶体管工作在饱和区的电流满足公式
Figure PCTCN2017077669-appb-000010
其中，μn为电子的迁移速率，Cox为单位面积的有源层的电容，
Figure PCTCN2017077669-appb-000011
是沟道的宽长比，Vgs是栅极与源极之间的电压，Vth为阈值电压；因此，第一晶体管T1的栅极与源极之间的电压Vgs1等于第一晶体管T1的栅极与源极之间的电压Vgs2，从而可以使第一节点A的电压等于第二节点B的电压，即电压调整单元3的第二端3b的电压等于电压调整单元3的第三端3c的电压。根据本发明实施例电压控制单元2采用上述钳位电路的结构，仅利用两个晶体管即可实现向电压调整单元3的第二端3b和第三端3c输出相等的电压，这样，可以简化基准电路的结构，降低基准电路的功耗，从而可以实现低电压输入，将第一电平信号端Ref1的电压控制在1.8V左右。
如图2和图3所示，例如第一晶体管T1和第二晶体管T2可以均为N型晶体管。
如图2和图3所示，电流控制单元1可以包括：第三晶体管T3、第四晶体管T4和第五晶体管T5；其中，第三晶体管T3的栅极和漏极、第四晶体管T4的栅极以及第五晶体管T5的栅极分别与第一晶体管T1的漏极相连，第三晶体管T3的源极、第四晶体管T4的源极和第五晶体管T5的源极分别与第一电平信号端Ref1相连；第四晶体管T4的漏极分别与第二晶体管T2的栅极和漏极以及第一晶体管T1的栅极相连；第五晶体管T5的漏极与输出端Output相连。
当电流控制单元1包括第三晶体管T3、第四晶体管T4和第五晶体管T5时，采用镜像电路的结构，在第三晶体管T3和第四晶体管T4的宽长比相等，且第三晶体管T3与第五晶体管T5的宽长比为1∶n时，可以向电压控制单元2的第一端2a和第二端2b以及电压调整单元3的第一端3a输出比值为1∶1∶n的电流。
如图2和图3所示，例如第三晶体管T3、第四晶体管T4和第五晶体管T5可以均为P型晶体管。
需要说明的是，本发明实施例提供的上述基准电路中提到的晶体管可以是金属氧化物 半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (8)

  1. 一种基准电路，包括：
    电流控制单元；
    电压控制单元；和
    电压调整单元；
    其中，所述电流控制单元的第一端与第一电平信号端相连，第二端与所述电压控制单元的第一端相连，第三端与所述电压控制单元的第二端相连，第四端与所述电压调整单元的第一端和所述基准电路的输出端相连，所述电流控制单元配置为分别向所述电压控制单元的第一端和第二端以及所述电压调整单元的第一端输出比值为1∶1∶n的电流；其中，n为正数；
    其中，所述电压控制单元的第三端与所述电压调整单元的第二端相连，第四端与所述电压调整单元的第三端相连，所述电压控制单元配置为分别向所述电压调整单元的第二端和第三端输出相等的电压；
    其中，所述电压调整单元配置为调整所述输出端输出的电压，使所述输出端输出的电压与温度无关。
  2. 如权利要求1所述的基准电路，其特征在于，所述电压调整单元包括：第一三极管、第二三极管、第一电阻、第二电阻和第三电阻；其中，
    所述第一电阻的一端和所述第二电阻的一端分别与第一节点相连，所述第一电阻的另一端与所述第一三极管的发射极相连，所述第二电阻的另一端接地；
    所述第三电阻的一端分别与所述电流控制单元的第四端和所述输出端相连，另一端接地；
    所述第一三极管的基极和集电极以及所述第二三极管的基极和集电极分别接地，所述第二三极管的发射极与所述电压控制单元的第四端相连。
  3. 如权利要求2所述的基准电路，其特征在于，所述电压调整单元还包括：第四电阻；
    所述第四电阻的一端与第二节点相连，另一端接地。
  4. 如权利要求3所述的基准电路，其特征在于，所述第二电阻的电阻值等于所述第四电阻的电阻值。
  5. 如权利要求3所述的基准电路，其特征在于，所述电压控制单元包括：第一晶体管和第二晶体管；其中，
    所述第一晶体管的栅极分别与所述第二晶体管的栅极和漏极相连，所述第一晶体管的源极与所述第一节点相连，所述第一晶体管的漏极与所述电流调整单元的第二端相连；
    所述第二晶体管的源极与所述第二节点相连。
  6. 如权利要求5所述的基准电路，其特征在于，所述第一晶体管和所述第二晶体管均为N型晶体管。
  7. 如权利要求5所述的基准电路，其特征在于，所述电流控制单元包括：第三晶体管、第四晶体管和第五晶体管；其中，
    所述第三晶体管的栅极和漏极、所述第四晶体管的栅极以及所述第五晶体管的栅极分别与所述第一晶体管的漏极相连，所述第三晶体管的源极、所述第四晶体管的源极和所述第五晶体管的源极分别与所述第一电平信号端相连；
    所述第四晶体管的漏极分别与所述第二晶体管的栅极和漏极以及所述第一晶体管的栅极相连；
    所述第五晶体管的漏极与所述输出端相连。
  8. 如权利要求7所述的基准电路，其特征在于，所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200827978A (en) * 2006-12-29 2008-07-01 Mediatek Inc Bandgap reference circuits and start-up methods thereof
CN101763136A (zh) * 2009-11-09 2010-06-30 天津南大强芯半导体芯片设计有限公司 一种非对称带隙基准电路
CN101995898A (zh) * 2009-08-21 2011-03-30 深圳艾科创新微电子有限公司 一种高阶温度补偿电流基准源
CN102654780A (zh) * 2012-05-17 2012-09-05 无锡硅动力微电子股份有限公司 应用于集成电路的温度补偿电流基准电路
CN203870501U (zh) * 2014-04-30 2014-10-08 中国科学院声学研究所 一种与温度无关的集成电路电流基准源
CN105955388A (zh) * 2016-05-26 2016-09-21 京东方科技集团股份有限公司 一种基准电路

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849684A (en) * 1988-11-07 1989-07-18 American Telephone And Telegraph Company, At&T Bell Laaboratories CMOS bandgap voltage reference apparatus and method
US5936392A (en) * 1997-05-06 1999-08-10 Vlsi Technology, Inc. Current source, reference voltage generator, method of defining a PTAT current source, and method of providing a temperature compensated reference voltage
US6188270B1 (en) * 1998-09-04 2001-02-13 International Business Machines Corporation Low-voltage reference circuit
IT1319613B1 (it) * 2000-12-22 2003-10-20 St Microelectronics Srl Circuito generatore di una tensione di riferimento stabile intemperatura,in particolare per processi cmos
US6351111B1 (en) * 2001-04-13 2002-02-26 Ami Semiconductor, Inc. Circuits and methods for providing a current reference with a controlled temperature coefficient using a series composite resistor
US6522117B1 (en) * 2001-06-13 2003-02-18 Intersil Americas Inc. Reference current/voltage generator having reduced sensitivity to variations in power supply voltage and temperature
FR2832819B1 (fr) * 2001-11-26 2004-01-02 St Microelectronics Sa Source de courant compensee en temperature
US6943617B2 (en) * 2003-12-29 2005-09-13 Silicon Storage Technology, Inc. Low voltage CMOS bandgap reference
JP4780968B2 (ja) * 2005-01-25 2011-09-28 ルネサスエレクトロニクス株式会社 基準電圧回路
US7511567B2 (en) * 2005-10-06 2009-03-31 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Bandgap reference voltage circuit
TWI307211B (en) * 2006-03-06 2009-03-01 Novatek Microelectronics Corp Current source with adjustable temperature coefficient and method for generating current with specific temperature coefficient
KR100809716B1 (ko) * 2007-01-04 2008-03-06 삼성전자주식회사 레지스터를 추가하여 트리밍을 수행하는 밴드갭 기준 회로
US20090066313A1 (en) * 2007-09-07 2009-03-12 Nec Electronics Corporation Reference voltage circuit compensated for temprature non-linearity
KR100901769B1 (ko) * 2007-11-15 2009-06-11 한국전자통신연구원 저전압 고정밀도 밴드갭 기준전압 발생기
CN101470458B (zh) * 2007-12-26 2010-10-27 中国科学院微电子研究所 带隙基准电压参考电路
JP2009251877A (ja) * 2008-04-04 2009-10-29 Nec Electronics Corp 基準電圧回路
JP5326648B2 (ja) * 2009-02-24 2013-10-30 富士通株式会社 基準信号発生回路
TWI437406B (zh) * 2010-10-25 2014-05-11 Novatek Microelectronics Corp 低雜訊電流緩衝電路及電流電壓轉換器
JP5535154B2 (ja) * 2011-09-02 2014-07-02 株式会社東芝 基準信号発生回路
TWI457743B (zh) * 2012-09-20 2014-10-21 Novatek Microelectronics Corp 能帶隙參考電路及其雙輸出自我參考穩壓器
CN105022441B (zh) * 2014-04-30 2016-09-14 中国科学院声学研究所 一种与温度无关的集成电路电流基准源

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200827978A (en) * 2006-12-29 2008-07-01 Mediatek Inc Bandgap reference circuits and start-up methods thereof
CN101995898A (zh) * 2009-08-21 2011-03-30 深圳艾科创新微电子有限公司 一种高阶温度补偿电流基准源
CN101763136A (zh) * 2009-11-09 2010-06-30 天津南大强芯半导体芯片设计有限公司 一种非对称带隙基准电路
CN102654780A (zh) * 2012-05-17 2012-09-05 无锡硅动力微电子股份有限公司 应用于集成电路的温度补偿电流基准电路
CN203870501U (zh) * 2014-04-30 2014-10-08 中国科学院声学研究所 一种与温度无关的集成电路电流基准源
CN105955388A (zh) * 2016-05-26 2016-09-21 京东方科技集团股份有限公司 一种基准电路

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