WO2017201810A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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Publication number
WO2017201810A1
WO2017201810A1 PCT/CN2016/087799 CN2016087799W WO2017201810A1 WO 2017201810 A1 WO2017201810 A1 WO 2017201810A1 CN 2016087799 W CN2016087799 W CN 2016087799W WO 2017201810 A1 WO2017201810 A1 WO 2017201810A1
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Prior art keywords
electrically connected
thin film
film transistor
node
clock signal
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PCT/CN2016/087799
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/126,418 priority Critical patent/US10126621B2/en
Priority to GB1814495.6A priority patent/GB2564583B/en
Priority to EA201892812A priority patent/EA036256B1/ru
Priority to JP2018555631A priority patent/JP2019518982A/ja
Priority to KR1020187035664A priority patent/KR102177425B1/ko
Publication of WO2017201810A1 publication Critical patent/WO2017201810A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a GOA circuit based on an LTPS semiconductor thin film transistor which can improve the stability of a GOA circuit.
  • GOA Gate Driver on Array, line scan integrated on array substrate technology, utilizes existing TFT-LCD (Thin Film Transistor-Liquid Crystal) Display, thin film transistor liquid crystal display) Array process
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • Array process A technique in which the Gate line scan driving circuit is fabricated on an array substrate to realize the drive mode of Gate progressive scanning.
  • GOA technology can reduce external IC (Integrated Circuit, integrated circuit board (bonding) process, has the opportunity to increase production capacity and jump product cost, and can make LCD panel more suitable for making narrow border or borderless display products.
  • LTPS-TFT liquid crystal displays have the advantages of high resolution, fast response, high brightness and high aperture ratio.
  • the gate driver can be fabricated on the thin film transistor array substrate by using GOA technology to achieve the goal of system integration, space saving and cost of driving the IC.
  • the Q(n) point is the point for controlling the gate drive signal output; the P(n) point is used.
  • the relationship between the two nodes Q(n) and P(n) is mostly mutually restrained.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein n is a positive integer, and the nth-level GOA unit includes: a first thin film transistor T1 whose gate is electrically connected to the first clock signal CK1, and the source is electrically Connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, the drain is electrically connected to the third node H(n); the second thin film transistor T2 has its gate electrically connected to the a node Q(n), the source is electrically connected to the second clock signal CK2, the drain is electrically connected to the output terminal G(n), and the third thin film transistor T3 is electrically connected to the third clock signal CK3.
  • the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage, the drain is electrically connected to the third node H(n), and the fourth thin film transistor T4 has a gate thereof.
  • the source is electrically connected to the constant voltage low level VGL, the drain is electrically connected to the output terminal G(n), and the fifth thin film transistor T5 is electrically connected to the constant voltage high level VGH, and the source is electrically Connected to the third node H(n), the drain is electrically connected to the first node Q(n); the sixth thin film transistor T6 is electrically connected to the third node H(n), and the source is electrically Connected to the constant voltage low level VGL, the drain is electrically connected to the second node P(n); the seventh thin film transistor T7 has a gate electrically connected to the second node P(n) The source is electrically connected to the constant voltage low level VGL, the drain is electrically connected to the first node
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1.
  • the working process is: Phase 1, pre-charge: G(n-1) and CK1 provide high level at the same time, T1 is turned on, T5 gate is connected to constant voltage high level VGH, so T5 is always in guide In the on state, the third node H(n) is precharged to a high level, T6 is turned on; the third node H(n) is always the same level as the first node Q(n), and the first node Q(n) Precharged to a high level, the second node P(n) is pulled low, and T4, T7 are turned off.
  • the output terminal G(n) outputs a high level: G(n-1) and CK1 jump to a low level, and CK2 provides a high level; the first node Q(n) is stored due to the storage of the first capacitor C1. Keeping high level, T2 is turned on, the high level of CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and the first node Q(n) is raised to a higher level. Level.
  • the output G(n) outputs a low level: CK3 and G(n+1) Simultaneously providing a high level, the first node Q(n) It is held at a high level; CK2 jumps to a low level, and a low level of CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a low level.
  • the first node Q(n) is pulled low to a constant voltage low level VGL: CK1 provides a high level again, G(n-1) remains low, and T1 turns on the first node Q(n) To constant voltage low level VGL, T6 is cut off.
  • phase 5 the first node Q(n) and the output terminal G(n) are in a low-level sustain phase: CK2 transitions to a high level, T8 is turned on, and the second node P(n) is charged to a high level, T4, T7 is turned on, and continues to pull down the first node Q(n) and the output terminal G(n) to the constant voltage low level VGL, and the second node P(n) continues to remain high under the storage of the second capacitor C2.
  • the level, T4, T7 is always on for one frame time, keeping the low level of the first node Q(n) and the output terminal G(n).
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, characterized in that it comprises: a plurality of cascaded GOA units, each of which includes a scan control module, an output module, and a pull-down module.
  • the scan control module comprises: a first thin film transistor, a third thin film transistor, and a fifth a thin film transistor; the gate of the first thin film transistor is electrically connected to the first clock signal, and the source is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically Connected to the third node; the gate of the third thin film transistor is electrically connected to the third clock signal, and the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage The drain is electrically connected to the third node; the gate of the fifth thin film transistor is electrically connected to the constant voltage high level, the source is electrically connected to the third node, and the drain is electrically connected to the drain a first node; the output module includes: a second thin film crystal a gate and
  • the drain is electrically connected to the output terminal G(n); one end of the second bootstrap capacitor is electrically connected to the second node, and the other end is electrically connected to the constant voltage low level;
  • the node control module is electrically connected to the second clock signal and the second node, and is configured to control the second node to switch between high and low levels according to the second clock signal;
  • the pulses of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially output in turn, and do not overlap each other; during forward scanning, The first clock signal electrically connected to the first thin film transistor and the output terminal G(n-1) Simultaneously providing a high level; in the reverse scan, the third clock signal electrically connected to the third thin film transistor and the output terminal G(n+1) simultaneously provide a high level.
  • the present invention also provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage of the GOA unit including a scan control module, an output module, a pull-down module, and node control
  • the module is a positive integer, except for the first and last stage GOA units, in the nth stage GOA unit:
  • the scan control module includes: a first thin film transistor, a third thin film transistor, and a fifth thin film transistor;
  • the gate of the first thin film transistor is electrically connected to the first clock signal, and the source is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically connected to the drain a third node;
  • the gate of the third thin film transistor is electrically connected to the third clock signal, and the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage, and the drain Electrically connected to the third node;
  • An advantage of the present invention is that the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces a ninth thin film transistor to adjust the high and low levels of the voltage corresponding to the second node P(n).
  • the gate and the source of the ninth thin film transistor are electrically connected to the second node P(n), the drain is electrically connected to the second clock signal; or the gate of the ninth thin film transistor is electrically connected to the fourth a clock signal, the source is electrically connected to the second node P(n), and the drain is electrically connected to the second clock signal; and the second end of the output terminal G(n) can be pulled down at a certain frequency
  • the level of the node P(n) effectively avoids the second node P(n) being at a high level for a long time, preventing the threshold voltage shift caused by the fourth and seventh thin film transistor lengths T4 and T7 working, and improving
  • the stability of the GOA circuit is suitable for high resolution LCD panel design.
  • FIG. 1 is a schematic diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of an embodiment of a LTPS semiconductor thin film transistor-based GOA circuit according to the present invention.
  • FIG. 4 is a timing chart of forward scanning of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3;
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3;
  • FIG. 6 is a schematic diagram of another embodiment of a LTPS semiconductor thin film transistor-based GOA circuit according to the present invention.
  • FIG. 7 is a timing chart of forward scanning of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 6;
  • Fig. 8 is a timing chart showing the reverse scan of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in Fig. 6.
  • the GOA circuit includes: a plurality of cascaded GOA units, each of which includes a scan control module 32, an output module 34, a pull-down module 36, and a node control module 38.
  • the scan control module 32 includes: a first thin film transistor T1, a third thin film transistor T3, and a fifth thin film transistor
  • the output module 34 includes: a second thin film transistor T2 and a first bootstrap capacitor C1;
  • the pull-down module 36 includes: a fourth thin film transistor T4, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film.
  • the gate of the first thin film transistor T1 is electrically connected to the first clock signal CK1, and the source is electrically connected to the output terminal G of the upper n-1th GOA unit (n- 1), the drain is electrically connected to the third node H(n); the gate of the third thin film transistor T3 is electrically connected to the third clock signal CK3, and the source is electrically connected to the next n+1th GOA
  • the output terminal G(n+1) of the cell is electrically connected to the third node H(n); the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high level VGH, and the source is electrically connected to
  • the third node H(n) has a drain electrically connected to the first node Q(n).
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), the source is electrically connected to the second clock signal CK2, and the drain is electrically connected to the output terminal G ( n); one end of the first bootstrap capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output terminal G(n).
  • the gate of the fourth thin film transistor T4 is electrically connected to the second node P(n)
  • the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the output terminal G(n);
  • the gate of the sixth thin film transistor T6 is electrically connected to the third node H(n), and the source is electrically Connected to the constant voltage low level VGL, the drain is electrically connected to the second node P(n);
  • the gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), and the source is electrically connected a constant voltage low level VGL, the drain is electrically connected to the first node Q(n);
  • the gate and the source of the eighth thin film transistor T8 are electrically connected to the second clock signal CK2, and the drain is electrically connected to the first The second node P(n);
  • the gate of the tenth thin film transistor T10 is electrically connected to the fourth clock signal CK4, the source is electrically connected to the constant voltage low level VGL
  • the node control module 38 is electrically connected to the second clock signal CK2 and the second node P(n) for controlling the second node P(n) to switch between high and low levels according to the second clock signal CK2.
  • the node control module includes: a ninth thin film transistor T9, the gate and the source of the ninth thin film transistor T9 are electrically connected to the second node P(n), and the drain is electrically connected to the first Two clock signals CK2.
  • the level of the second node P(n) jumps to the same level as the second clock signal CK2 goes high, and the same high level jump occurs with The second clock signal CK2 jumps to a low level and falls to a low level.
  • each of the thin film transistors described in the present invention is a low temperature polysilicon semiconductor thin film transistor.
  • the four clock signals of the GOA circuit are: the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are sequentially rotated. Output, and do not overlap each other.
  • the source of the first thin film transistor T1 is electrically connected to the circuit start signal STV; at the final stage GOA In the cell, the source of the third thin film transistor T3 is electrically connected to the circuit start signal STV.
  • LTPS based on the present invention
  • the GOA circuit of the semiconductor thin film transistor can perform forward scanning step by step from the first stage to the last stage, or can perform reverse scanning from the last stage to the first stage step by step.
  • first to the first level GOA First thin film transistor T1 in the cell Providing a first clock signal (ie, CK1 is a high level) and a circuit start signal STV; that is, a first clock signal CK1 and a previous level electrically connected to the first thin film transistor T1 during forward scanning Output G(n-1) of n-1 level GOA unit Also provide a high level.
  • a first clock signal ie, CK1 is a high level
  • STV a circuit start signal
  • the GOA circuit of the semiconductor thin film transistor can pull down the level of the second node P(n) at a certain frequency whether in forward scanning or reverse scanning.
  • FIG. 4 it is a forward scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. In the forward scan, the working process is:
  • Phase 1, pre-charge the clock signal CK1 and the output terminal G(n-1) both provide a high level, the clock signals CK2, CK3, and CK4 both provide a low level, and the output terminal G(n+1) also provides a low level.
  • Phase 2 output G(n) outputs a high level: the clock signal CK1 and the output terminal G(n-1) both jump to a low level, the clock signal CK2 provides a high level, the clock signals CK3, CK4 and the output end G(n+1) still provides a low level; the first node Q(n) is due to the first bootstrap capacitor C1 The storage function remains high; the second thin film transistor T2 Turned on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and causes the first node Q(n) to be raised to a higher level, Six thin film transistor T6 Still conducting; the second node P(n) maintains a constant voltage low level VGL, and the fourth and seventh thin film transistors T4, T7 controlled by the second node P(n) are still turned off.
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK3 and the output terminal G(n+1) both provide a high level, the clock signals CK1, CK4 and the output end.
  • G(n-1) still provides a low level; the third thin film transistor T3 controlled by the clock signal CK3 Turning on; the first node Q(n) is kept at a high level, and the second and sixth thin film transistors T2 and T6 are still turned on; the second node P(n) is still maintained at a constant voltage low level VGL, and is subjected to the second node P.
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK1 is again supplied with a high level, and the clock signals CK2, CK3, CK4 and the output terminal G(n-1) are supplied with a low level; First thin film transistor T1 controlled by clock signal CK1 Turning on, pulling down the first node Q(n) to the constant voltage low level VGL, so that the second and sixth thin film transistors T2, T6 are turned off.
  • Phase 5 the first node Q (n) and the output terminal G (n) low-level maintenance phase: the clock signal CK1 jumps to a low level, the clock signal CK2 provides a high level, the clock signals CK3, CK4, and the output terminal G (n-1), G(n+1) provide a low level; the eighth thin film transistor T8 is turned on, the second node P(n) is charged to a high level, and the fourth and seventh thin film transistors T4, T7 Turning on, the first node Q(n) and the output terminal G(n) are kept at a low level; under the storage of the second bootstrap capacitor C2, the second node P(n) is continuously maintained at a high level; when the clock When the signal CK2 jumps from a high level to a low level, and at this time, since the second node P(n) is at a high level, the ninth thin film transistor T9 is in an on state, and the low level of the clock signal CK2 is constant.
  • the second node P(n) is pulled down to the extent. Due to the storage function of the second bootstrap capacitor C2, the second node P(n) will linearly fall to a low level after a delay of one end time when the clock signal CK2 transitions to a low level. That is, at the stage where the output terminal G(n) is kept low, the level of the second node P(n) jumps to the same level as the clock signal CK2 goes high, and the same high level jump occurs with the clock. Signal CK2 transitions to a low level and falls to a low level.
  • the second node P(n) maintains a high level for a long time
  • the fourth and seventh thin film transistors T4 and T7 The LTPS is provided based on the LTPS provided by the present invention.
  • the GOA circuit of the thin film transistor is pulled down at a certain frequency in phase 5, effectively avoiding the second node P(n) being at a high level for a long time, preventing the fourth and seventh thin film transistors T4
  • the problem of threshold voltage shift caused by long-term operation of T7 improves the stability of the GOA circuit.
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3, since the working processes of the forward and reverse scans are similar, the following describes the operation of the reverse scan.
  • the working process is:
  • Phase 1 pre-charge: both the clock signal CK3 and the output terminal G(n+1) provide a high level, the third thin film transistor T3 is turned on by the control of the clock signal CK3, and the third node H(n) is precharged to a high level.
  • the sixth thin film transistor T6 controlled by the third node H(n) is turned on; the fifth thin film transistor T5 Subject to constant voltage high level VGH The control is always on, so the level of the third node H(n) and the first node Q(n) are always the same, the first node Q(n) is precharged to a high level; the second node P(n) is Pull down to constant voltage low level VGL, fourth and seventh thin film transistors T4, T7 Deadline.
  • Phase 2 output G(n) outputs a high level: the clock signal CK2 provides a high level, and the first node Q(n) is due to the first bootstrap capacitor C1 The storage function remains high, the second thin film transistor T2 Turning on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and causes the first node Q(n) to be raised to a higher level.
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK1 and the output terminal G(n-1) both provide a high level, and the first node Q(n) remains When the level is high, the second thin film transistor T2 is still turned on, and the low level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a low level.
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK3 provides a high level again, the output terminal G(n+1) provides a low level; the third thin film transistor T3 is turned on, Pull down the first node Q(n) to the constant voltage low level VGL.
  • Phase 5 the first node Q(n) and the output terminal G(n) are maintained at a low level: the clock signal CK3 jumps to a low level, the clock signal CK2 provides a high level; and the eighth thin film transistor T8 is turned on, Two nodes P(n) are charged to a high level, fourth and seventh thin film transistors T4, T7 Turning on, the first node Q(n) and the output terminal G(n) are kept at a low level; under the storage of the second bootstrap capacitor C2, the second node P(n) is continuously maintained at a high level; when the clock When the signal CK2 jumps from a high level to a low level, and at this time, since the second node P(n) is at a high level, the ninth thin film transistor T9 is in an on state, and the low level of the clock signal CK2 is constant.
  • the second node P(n) is pulled down to the extent. Due to the storage function of the second bootstrap capacitor C2, the second node P(n) will linearly fall to a low level after a delay of one end time when the clock signal CK2 transitions to a low level. That is, at the stage where the output terminal G(n) is kept low, the level of the second node P(n) jumps to the same level as the clock signal CK2 goes high, and the same high level jump occurs with the clock. Signal CK2 transitions to a low level and falls to a low level.
  • the second node P(n) maintains a high level for a long time
  • the fourth and seventh thin film transistors T4 and T7 The LTPS is provided based on the LTPS provided by the present invention.
  • the GOA circuit of the thin film transistor is pulled down at a certain frequency in phase 5, effectively avoiding the second node P(n) being at a high level for a long time, preventing the fourth and seventh thin film transistors T4
  • the problem of threshold voltage shift caused by long-term operation of T7 improves the stability of the GOA circuit.
  • FIG. 6 a schematic diagram of another embodiment of a LTPS semiconductor thin film transistor-based GOA circuit according to the present invention is shown.
  • the difference from the embodiment shown in FIG. 3 is that, in the embodiment, in the node control module 38, the gate of the ninth thin film transistor T9 is electrically connected to the fourth clock signal CK4, and the source is electrically Connected to the second node P(n), the drain is electrically connected to the second clock signal CK2.
  • the level of the second node P(n) occurs the same high as the second clock signal CK2 jumps to a high level. The level jumps and a low level transition occurs as the fourth clock signal CK4 transitions to a high level.
  • FIG. 7 is Figure 6 A forward scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention is shown; the difference between FIG. 7 and FIG. 4 is that the second node P(n) is in a stage where the output terminal G(n) is kept at a low level.
  • the level of the third clock signal CK4 jumps to a high level and a low level jump occurs, but the connection of the ninth thin film transistor T9 in the GOA circuit unit disclosed in FIG. 3 and FIG. 6 can be performed by those skilled in the art. The relationship is known about the timing differences between the two, and will not be repeated here.
  • FIG. 8 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 6.
  • the difference between FIG. 8 and FIG. 5 is that the output terminal G(n) is kept at a low level, and the second The level of the node P(n) occurs with the fourth clock signal CK4 jumping to a high level, and a low level transition occurs, but those skilled in the art can refer to the ninth in the GOA circuit unit disclosed in FIG. 3 and FIG.
  • the connection relationship of the thin film transistor T9 is known for the timing difference between the two, and will not be further described herein.
  • the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces a ninth thin film transistor to adjust the high and low levels of the voltage corresponding to the second node P(n).
  • the gate and the source of the ninth thin film transistor are electrically connected to the second node P(n), the drain is electrically connected to the second clock signal; or the gate of the ninth thin film transistor is electrically connected to the fourth a clock signal, the source is electrically connected to the second node P(n), and the drain is electrically connected to the second clock signal; and the second end of the output terminal G(n) can be pulled down at a certain frequency
  • the level of the node P(n) effectively avoids the second node P(n) being at a high level for a long time, preventing the threshold voltage shift caused by the fourth and seventh thin film transistor lengths T4 and T7 working, and improving
  • the stability of the GOA circuit is suitable for high resolution LCD panel design.
  • the GOA circuit provided by the invention can be applied to the field of

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Abstract

提供一种基于LTPS半导体薄膜晶体管的GOA电路，引入了第九薄膜晶体管（T9）调整第二节点（P(n)）对应的电压的高低电平。采用第九薄膜晶体管（T9）的栅极和源极均电性连接于第二节点（P(n)），漏极电性连接于第二时钟信号（CK2）；或者采用第九薄膜晶体管（T9）的栅极电性连接于第四时钟信号（CK4），源极电性连接于第二节点（P(n)），漏极电性连接于第二时钟信号（CK2）；能够在输出端（G(n)）保持低电平的阶段，按一定频率拉低第二节点（P(n)）的电平，有效避免了第二节点（P(n)）长时间处于高电平，防止因第四薄膜晶体管（T4）与第七薄膜晶体管（T7）长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及液晶显示领域，尤其是涉及一种可以提升GOA电路稳定性的基于LTPS半导体薄膜晶体管的GOA电路。
 背景技术
GOA（Gate Driver on Array，集成在阵列基板上的行扫描）技术，是利用现有TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）阵列制程将Gate行扫描驱动电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式的一项技术。GOA技术能减少外接IC（Integrated Circuit，集成电路板）的焊接（bonding）工序，有机会提升产能并跳变产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅（Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。而且由于LTPS半导体本身具有超高载流子迁移率的特性，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。为了保证输出端G(n)点的稳定，都会引入Q(n)、P(n)两节点，Q(n)点为用于控制栅极驱动信号输出的点；P(n)点为用于维持Q(n)点及输出端G(n)点低电平的稳定点，而Q(n)、P(n)两节点之间多为相互牵制的关系。
参考图1，现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，其栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第二薄膜晶体管T2，其栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，其栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三节点H(n)；第四薄膜晶体管T4，其栅极电性连接于第二节点P(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第五薄膜晶体管T5，其栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，其栅极电性连接于第三节点H(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第七薄膜晶体管T7，其栅极电性连接于第二节点P(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于第一节点Q(n)；第八薄膜晶体管T8，其栅极与源极均电性连接于第二时钟信号CK2，漏极电性连接于第二节点P(n)；第十薄膜晶体管T10，其栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第一电容C1，其一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，其一端电性连接于第二节点P(n)，另一端电性连接于恒压低电平VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。结合图1与图2，以正向扫描为例进行说明，其中，图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：阶段1，预充电：G(n-1)与CK1同时提供高电平，T1导通，T5栅极接恒压高电平VGH因此T5一直处于导通的状态，第三节点H(n)被预充电至高电平，T6导通；第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平，第二节点P(n)被拉低，T4、T7截止。阶段2，输出端G(n)输出高电平：G(n-1)与CK1跳变为低电平，CK2提供高电平；第一节点Q(n)因第一电容C1的存储作用保持高电平，T2导通，CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平。阶段3，输出端G(n)输出低电平：CK3与G(n+1) 同时提供高电平，第一节点Q(n) 被保持在高电平；CK2跳变为低电平，CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。阶段4，第一节点Q(n)拉低到恒压低电平VGL：CK1再次提供高电平，G(n-1)保持低电平，T1导通拉低第一节点Q(n)至恒压低电平VGL，T6截止。阶段5，第一节点Q(n)及输出端G(n)低电平维持阶段：CK2跳变为高电平，T8导通，第二节点P(n)被充电至高电平，T4、T7导通，分别继续拉低第一节点Q(n)及输出端G(n)至恒压低电平VGL，在第二电容C2的存储作用下，第二节点P(n)持续保持高电平，T4、T7在一帧时间内一直导通，保持第一节点Q(n)及输出端G(n)的低电平。
在上述现有的GOA电路中，由于第二节点P(n)一直处于高电平的状态，也就是T4、T7一直处于导通的状态。T4、T7长时间工作，会造成T4、T7这两个关键薄膜晶体管发生阈值电压偏移（Vth Shift)，造成电路的稳定能力下降，从而引起GOA电路输出异常。
因此，亟需提供一种新的GOA电路，以提升GOA电路的稳定性。
 技术问题
本发明的目的在于，提供一种基于LTPS半导体薄膜晶体管的GOA电路，与现有的基于LTPS半导体薄膜晶体管的GOA电路相比，可以避免第二节点P(n)长时间处于高电平，防止因第四与第七薄膜晶体管长T4、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，提高液晶面板显示品质。
 技术解决方案
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，其特征在于，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及节点控制模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极和源极均电性连接于所述第二时钟信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述恒压低电平；以及所述节点控制模块电性连接所述第二时钟信号和所述第二节点，用于根据所述第二时钟信号控制所述第二节点在高低电平间转换；
其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠；正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
为实现上述目的，本发明还提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及节点控制模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极和源极均电性连接于所述第二时钟信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述恒压低电平；以及所述节点控制模块电性连接所述第二时钟信号和所述第二节点，用于根据所述第二时钟信号控制所述第二节点在高低电平间转换。
 有益效果
本发明的优点在于，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了第九薄膜晶体管调整第二节点P(n)对应的电压的高低电平。采用第九薄膜晶体管的栅极和源极均电性连接于第二节点P(n)，漏极电性连接于第二时钟信号；或者采用第九薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于第二节点P(n)，漏极电性连接于第二时钟信号；能够在输出端G(n)保持低电平的阶段，按一定频率拉低第二节点P(n)的电平，有效避免了第二节点P(n)长时间处于高电平，防止因第四与第七薄膜晶体管长T4、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，以适用高解析度的液晶面板设计。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
 附图说明
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路一实施例的示意图；
图4为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图5为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图；
图6，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路另一实施例的示意图；
图7为图6所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图8为图6所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图。
 本发明的最佳实施方式
下面结合附图对本发明提供的基于LTPS半导体薄膜晶体管的GOA电路做详细说明。
参考图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路一实施例的示意图。所述的GOA电路包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块32、输出模块34、下拉模块36以及节点控制模块38。
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块32包括：第一薄膜晶体管T1、第三薄膜晶体管T3以及第五薄膜晶体管T5；所述输出模块34包括：第二薄膜晶体管T2以及第一自举电容C1；所述下拉模块36包括：第四薄膜晶体管T4、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第十薄膜晶体管T10以及第二自举电容C2。
在所述扫描控制模块32中：第一薄膜晶体管T1的栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第三薄膜晶体管T3的栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三节点H(n)；第五薄膜晶体管T5的栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)。
在所述输出模块34中：第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第一自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)。
在所述下拉模块36中：第四薄膜晶体管T4的栅极电性连接于第二节点P(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第六薄膜晶体管T6的栅极电性连接于第三节点H(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第一节点Q(n)；第八薄膜晶体管T8的栅极和源极均电性连接于第二时钟信号CK2，漏极电性连接于第二节点P(n)；第十薄膜晶体管T10的栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第二自举电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电平VGL。
所述节点控制模块38电性连接第二时钟信号CK2和第二节点P(n)，用于根据第二时钟信号CK2控制第二节点P(n)在高低电平间转换。
在本实施例中，所述节点控制模块包括：第九薄膜晶体管T9，第九薄膜晶体管T9的栅极和源极均电性连接于第二节点P(n)，漏极电性连接于第二时钟信号CK2。在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着第二时钟信号CK2跳变成高电平而发生同样的高电平跳变，并随着第二时钟信号CK2跳变成低电平而下降至低电平。
具体的，本发明所述的各个薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
具体的，所述的GOA电路的四条时钟信号：所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4的脉冲是依序轮流输出，且互不重叠。
特别地，在第一级GOA 单元中，第一薄膜晶体管T1 的源极电性连接于电路起始信号STV；在最后一级GOA 单元中，第三薄膜晶体管T3 的源极电性连接于电路起始信号STV。本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描，也可以从最后一级向第一级逐级进行反向扫描。其中，在正向扫描时，首先向第一级GOA 单元中的第一薄膜晶体管T1 提供第一条时钟信号（即CK1为高电平）和电路起始信号STV；也即正向扫描时，与所述第一薄膜晶体管T1电性连接的第一时钟信号CK1和上一级第n-1级GOA单元的输出端G(n-1) 同时提供高电平。反向扫描时，首先向最后一级GOA 单元中的第三薄膜晶体管T3 提供第一条时钟信号（即CK3为高电平）和电路起始信号STV；也即反向扫描时，与所述第三薄膜晶体管电性连接的第三时钟信号CK3和下一级第n+1级GOA单元的输出端G(n+1)同时提供高电平。
本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路，无论是在正向扫描时还是反向扫描时，均能够按一定频率拉低第二节点P(n) 的电平。
参考图4，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK1与输出端G(n-1)均提供高电平，时钟信号CK2、CK3、CK4均提供低电平，输出端G(n+1)也提供低电平；第一薄膜晶体管T1 受时钟信号CK1的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7 截止。
阶段2、输出端G(n)输出高电平：时钟信号CK1与输出端G(n-1)均跳变为低电平，时钟信号CK2提供高电平，时钟信号CK3、CK4和输出端G(n+1)仍提供低电平；第一节点Q(n)因第一自举电容C1 的存储作用保持高电平；第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平，第六薄膜晶体管T6 仍导通；第二节点P(n)保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK3与输出端G(n+1)均提供高电平，时钟信号CK1、CK4及输出端G(n-1)仍提供低电平；受时钟信号CK3控制的第三薄膜晶体管T3 导通；第一节点Q(n)保持高电平，第二、第六薄膜晶体管T2、T6仍导通；第二节点P(n)仍保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止；由于第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK1再次提供高电平，时钟信号CK2、CK3、CK4和输出端G(n-1)提供低电平；受时钟信号CK1控制的第一薄膜晶体管T1 导通，拉低第一节点Q(n)至恒压低电平VGL，使得第二、第六薄膜晶体管T2、T6截止。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK1跳变为低电平，时钟信号CK2提供高电平，时钟信号CK3、CK4和输出端G(n-1)、G(n+1)提供低电平；第八薄膜晶体管T8导通，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7 导通，使得第一节点Q(n)及输出端G(n)保持低电平；在第二自举电容C2的存储作用下，第二节点P(n)持续保持高电平；当时钟信号CK2由高电平跳变成低电平时，而此时由于第二节点P(n)是高电平，第九薄膜晶体管T9会处于导通的状态，时钟信号CK2的低电平会一定程度上将第二节点P(n)拉低。由于第二自举电容C2的存储作用，第二节点P(n)会在时钟信号CK2跳变成低电平时延迟一端时间后呈直线下降至低电平。即在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着时钟信号CK2跳变成高电平而发生同样的高电平跳变，并随着时钟信号CK2跳变成低电平而下降至低电平。
相比于现有技术中第二节点P(n)长时间保持高电平，第四、第七薄膜晶体管T4、T7 在一帧时间内一直导通，本发明提供的基于LTPS 薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低，有效避免了第二节点P(n)长时间处于高电平，防止因第四、第七薄膜晶体管T4、T7长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
参考图5，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图，由于正、反向扫描的工作过程类似，以下简述反向扫描的工作过程。在反向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK3与输出端G(n+1)均提供高电平，第三薄膜晶体管T3受时钟信号CK3的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，第四、第七薄膜晶体管T4、T7 截止。
阶段2、输出端G(n)输出高电平：时钟信号CK2提供高电平，第一节点Q(n)因第一自举电容C1 的存储作用保持高电平，第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK1与输出端G(n-1)均提供高电平，第一节点Q(n)仍为高电平，第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK3再次提供高电平，输出端G(n+1)提供低电平；第三薄膜晶体管T3导通，拉低第一节点Q(n)至恒压低电平VGL。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK3跳变为低电平，时钟信号CK2提供高电平；第八薄膜晶体管T8导通，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7 导通，使得第一节点Q(n)及输出端G(n)保持低电平；在第二自举电容C2的存储作用下，第二节点P(n)持续保持高电平；当时钟信号CK2由高电平跳变成低电平时，而此时由于第二节点P(n)是高电平，第九薄膜晶体管T9会处于导通的状态，时钟信号CK2的低电平会一定程度上将第二节点P(n)拉低。由于第二自举电容C2的存储作用，第二节点P(n)会在时钟信号CK2跳变成低电平时延迟一端时间后呈直线下降至低电平。即在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着时钟信号CK2跳变成高电平而发生同样的高电平跳变，并随着时钟信号CK2跳变成低电平而下降至低电平。
相比于现有技术中第二节点P(n)长时间保持高电平，第四、第七薄膜晶体管T4、T7 在一帧时间内一直导通，本发明提供的基于LTPS 薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低，有效避免了第二节点P(n)长时间处于高电平，防止因第四、第七薄膜晶体管T4、T7长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
参考图6，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路另一实施例的示意图。与图3所示实施例的不同之处在于，在本实施例中，在所述节点控制模块38中，第九薄膜晶体管T9的栅极电性连接于第四时钟信号CK4，源极电性连接于第二节点P(n)，漏极电性连接于第二时钟信号CK2。在本实施例中，在所述输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着第二时钟信号CK2跳变成高电平而发生同样的高电平跳变，并随着第四时钟信号CK4跳变成高电平而发生低电平跳变。
图7是图6 所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；图7与图4的差异在于，在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着第四时钟信号CK4跳变成高电平而发生低电平跳变，但是本领域技术人员可依据图3、图6所揭示的GOA电路单元中第九薄膜晶体管T9的连接关系了解两者的时序差异，在此不另赘述。
图8是图6所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图；图8与图5的差异在于，在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着第四时钟信号CK4跳变成高电平而发生低电平跳变，但是本领域技术人员可依据图3、图6所揭示的GOA电路单元中第九薄膜晶体管T9的连接关系了解两者的时序差异，在此不另赘述。
综上所述，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了第九薄膜晶体管调整第二节点P(n)对应的电压的高低电平。采用第九薄膜晶体管的栅极和源极均电性连接于第二节点P(n)，漏极电性连接于第二时钟信号；或者采用第九薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于第二节点P(n)，漏极电性连接于第二时钟信号；能够在输出端G(n)保持低电平的阶段，按一定频率拉低第二节点P(n)的电平，有效避免了第二节点P(n)长时间处于高电平，防止因第四与第七薄膜晶体管长T4、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，以适用高解析度的液晶面板设计。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (14)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，其特征在于，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及节点控制模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极和源极均电性连接于所述第二时钟信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述恒压低电平；以及
    所述节点控制模块电性连接所述第二时钟信号和所述第二节点，用于根据所述第二时钟信号控制所述第二节点在高低电平间转换；
    其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠；正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  2. 如权利要求1所述的GOA电路，其特征在于，所述节点控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极和源极均电性连接于所述第二节点，漏极电性连接于所述第二时钟信号。
  3. 如权利要求2所述的GOA电路，其特征在于，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述第二时钟信号跳变成高电平而发生同样的高电平跳变，并随着所述第二时钟信号跳变成低电平而下降至低电平。
  4. 如权利要求1所述的GOA电路，其特征在于，所述节点控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于所述第四时钟信号，源极电性连接于所述第二节点，漏极电性连接于所述第二时钟信号。
  5. 如权利要求4所述的GOA电路，其特征在于，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述第二时钟信号跳变成高电平而发生同样的高电平跳变，并随着所述第四时钟信号跳变成高电平而发生低电平跳变。
  6. 如权利要求1所述的GOA电路，其特征在于，所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
  7. 一种基于LTPS半导体薄膜晶体管的GOA电路，其特征在于，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及节点控制模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极和源极均电性连接于所述第二时钟信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述恒压低电平；以及
    所述节点控制模块电性连接所述第二时钟信号和所述第二节点，用于根据所述第二时钟信号控制所述第二节点在高低电平间转换。
  8. 如权利要求7所述的GOA电路，其特征在于，所述节点控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极和源极均电性连接于所述第二节点，漏极电性连接于所述第二时钟信号。
  9. 如权利要求8所述的GOA电路，其特征在于，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述第二时钟信号跳变成高电平而发生同样的高电平跳变，并随着所述第二时钟信号跳变成低电平而下降至低电平。
  10. 如权利要求7所述的GOA电路，其特征在于，所述节点控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于所述第四时钟信号，源极电性连接于所述第二节点，漏极电性连接于所述第二时钟信号。
  11. 如权利要求10所述的GOA电路，其特征在于，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述第二时钟信号跳变成高电平而发生同样的高电平跳变，并随着所述第四时钟信号跳变成高电平而发生低电平跳变。
  12. 如权利要求7所述的GOA电路，其特征在于，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
  13. 如权利要求7所述的GOA电路，其特征在于，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  14. 如权利要求7所述的GOA电路，其特征在于，所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102707009B1 (ko) * 2016-12-19 2024-09-12 엘지디스플레이 주식회사 게이트 구동회로
KR102445577B1 (ko) 2017-10-27 2022-09-20 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함하는 표시 장치
CN108154856B (zh) * 2017-12-27 2020-10-02 南京中电熊猫液晶显示科技有限公司 栅极扫描驱动电路
WO2020061802A1 (zh) * 2018-09-26 2020-04-02 深圳市柔宇科技有限公司 Goa电路、阵列基板及显示装置
CN109830212A (zh) * 2019-03-15 2019-05-31 深圳市华星光电半导体显示技术有限公司 一种oled显示面板
CN111312177B (zh) * 2020-03-03 2021-04-02 武汉华星光电技术有限公司 Goa驱动电路、显示面板及显示装置
CN113643641A (zh) * 2021-08-03 2021-11-12 武汉华星光电技术有限公司 栅极驱动电路及显示面板
WO2023115401A1 (zh) * 2021-12-22 2023-06-29 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN117456874A (zh) * 2023-10-24 2024-01-26 深圳市华星光电半导体显示技术有限公司 栅极驱动电路及显示面板
CN118658398B (zh) * 2024-08-19 2024-11-08 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN105355187A (zh) * 2015-12-22 2016-02-24 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105489180A (zh) * 2016-01-04 2016-04-13 武汉华星光电技术有限公司 Goa电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393093B (zh) * 2004-06-30 2013-04-11 Samsung Display Co Ltd 移位暫存器，具有該移位暫存器之顯示裝置，及其驅動方法
US7203264B2 (en) * 2005-06-28 2007-04-10 Wintek Corporation High-stability shift circuit using amorphous silicon thin film transistors
JP2007242129A (ja) * 2006-03-08 2007-09-20 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
JP5116277B2 (ja) * 2006-09-29 2013-01-09 株式会社半導体エネルギー研究所 半導体装置、表示装置、液晶表示装置、表示モジュール及び電子機器
JP2009205706A (ja) * 2008-02-26 2009-09-10 Sony Corp シフトレジスタ回路および表示装置ならびに電子機器
JP5413870B2 (ja) * 2008-02-26 2014-02-12 株式会社ジャパンディスプレイ シフトレジスタ回路および表示装置ならびに電子機器
CN102651208B (zh) * 2012-03-14 2014-12-03 京东方科技集团股份有限公司 一种栅极驱动电路及显示器
KR102015396B1 (ko) * 2012-11-27 2019-08-28 엘지디스플레이 주식회사 쉬프트 레지스터와 이의 구동방법
CN104252853A (zh) * 2014-09-04 2014-12-31 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104766580B (zh) * 2015-04-23 2017-08-01 合肥京东方光电科技有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN105139820B (zh) * 2015-09-29 2017-11-10 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN105206243B (zh) 2015-10-28 2017-10-17 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN105185347B (zh) * 2015-10-29 2018-01-26 武汉华星光电技术有限公司 一种基于ltps的goa电路及显示面板
CN105390086B (zh) 2015-12-17 2018-03-02 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN105355187A (zh) * 2015-12-22 2016-02-24 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105489180A (zh) * 2016-01-04 2016-04-13 武汉华星光电技术有限公司 Goa电路

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