WO2020007019A1 - 数据驱动电路及其驱动方法、阵列基板和显示面板 - Google Patents

数据驱动电路及其驱动方法、阵列基板和显示面板 Download PDF

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Publication number
WO2020007019A1
WO2020007019A1 PCT/CN2019/070189 CN2019070189W WO2020007019A1 WO 2020007019 A1 WO2020007019 A1 WO 2020007019A1 CN 2019070189 W CN2019070189 W CN 2019070189W WO 2020007019 A1 WO2020007019 A1 WO 2020007019A1
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Prior art keywords
data
coupled
driving circuit
switch
circuit
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PCT/CN2019/070189
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English (en)
French (fr)
Inventor
王孝林
付鹏程
汪锐
朴正淏
马晓峰
袁剑峰
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/469,831 priority Critical patent/US11263941B2/en
Publication of WO2020007019A1 publication Critical patent/WO2020007019A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a data driving circuit for a display panel and a driving method thereof, an array substrate, and a display panel.
  • the data output lines can be multiplexed by a multiplexing circuit, thereby reducing the number of data output terminals, so as to achieve a narrow frame of the display panel.
  • the multiplexing circuit can be implemented using an oxide thin film transistor (TFT).
  • Embodiments of the present disclosure provide a data driving circuit, an array substrate, a display panel, and a method for driving the data driving circuit.
  • a data driving circuit includes a data driver, a multiplexing circuit, and a control circuit.
  • the data driver includes M data output terminals, and each data output terminal outputs data signals to corresponding L data lines via a multiplexing circuit.
  • the multiplexing circuit includes M ⁇ L switch groups, and each switch group includes N switch tubes and is coupled between a data line and a corresponding data output terminal. Each switch is coupled to one of the L ⁇ N strobe control terminals of the control circuit and is configured to output a data signal from a corresponding data output terminal according to a control signal from the coupled strobe control terminal To the corresponding data line.
  • Each of the gating control terminals is coupled to M switching tubes spaced (L ⁇ N-1) of the switching tubes from each other, and is configured to provide a control signal to a corresponding switching tube.
  • M is an integer
  • L and N are integers of 2 or more.
  • the switching transistor is an oxide thin film transistor.
  • the control electrode of the oxide thin film transistor is coupled to the corresponding gate control terminal, the first electrode is coupled to the corresponding data output terminal, and the second electrode is coupled to the corresponding data line.
  • the data output terminal of the odd-numbered bits and the data output terminal of the next even-numbered bits are alternately coupled to the adjacent 2L data lines through the multiplexing circuit.
  • each of the M data output terminals is coupled to an adjacent L data line through a multiplexing circuit.
  • N is 2, 3, or 4.
  • L is 2 or 3.
  • an array substrate includes a scan driving circuit, a data driving circuit according to the first aspect of the present disclosure, and a pixel circuit.
  • the scanning driving circuit is configured to provide a scanning signal to the pixel circuit through a scanning line.
  • the data driving circuit is configured to provide a data signal to the pixel circuit through a data line.
  • a display panel includes an array substrate according to a second aspect of the present disclosure.
  • a driving method for driving a data driving circuit in each of the N time periods, control signals are sequentially provided through L gate control terminals, so that one switch tube in each switch group works to output the corresponding data from The terminal's data signal is output to the corresponding data line.
  • the L strobe control terminals are different, and the switch tubes working in each switch group are different.
  • one or more scan periods are included in each time period.
  • FIG. 1 is a schematic circuit diagram of a data driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a timing diagram of signals used in the data driving circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of one example of a data driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic circuit diagram of a data driving circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of another example of a data driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a method for driving a data driving circuit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the sources and drains (emitters and collectors) of the transistors are symmetrical, and between the sources and drains (emitters and collectors) of the N-type and P-type transistors The direction of the on-time current is opposite. Therefore, in the embodiments of the present disclosure, the controlled intermediate terminal of the transistor is collectively referred to as the control pole, the signal input terminal is referred to as the first pole, and the signal output terminal is referred to as the second pole.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. In addition, terms such as "first" and "second” are only used to distinguish one component (or part of a component) from another component (or another part of a component).
  • the oxide transistor When a multiplexing circuit implemented by an oxide thin film transistor is applied in the field of display technology, the oxide transistor is in a high-frequency charging and discharging state for a long time. Due to the low reliability of the oxide thin film transistor, the threshold voltage of the oxide thin film transistor is shifted forward, which results in insufficient charging of the device coupled to the output line of the multiplexing circuit. For example, the pixel driving circuit is not fully charged, and the display panel cannot work normally. In addition, being in a high-frequency charging and discharging state for a long time will reduce the life of the transistor, thereby affecting the life of the multiplexing circuit and the display device.
  • FIG. 1 is a schematic circuit diagram of a data driving circuit 100 according to an embodiment of the present disclosure.
  • the data driving circuit 100 may include a data driver 101, a multiplexing circuit 102, and a control circuit 103.
  • the data driver 101 includes M data output terminals. Each data output terminal outputs a data signal to a corresponding L data line via the multiplexing circuit 102.
  • the multiplexing circuit 102 includes M ⁇ L switch groups. Each switch group includes N switch tubes (for example, T 1 ,..., T N ) and is coupled between a data line and a corresponding data output terminal. Each switch is coupled to one of the L ⁇ N strobe control terminals of the control circuit 103. The switch can output the data signal from the corresponding data output terminal to the corresponding data line according to the control signal from the coupled gating control terminal. Each gating control terminal is coupled to M switching tubes spaced apart (L ⁇ N-1) switching tubes from each other, and provides control signals to corresponding switching tubes.
  • M is an integer
  • L and N are integers of 2 or more.
  • FIG. 1 only shows a case where two data output terminals DATA (2k + 1) and DATA (2k + 2) are connected to the multiplexing circuit 102.
  • the data output terminals DATA (2k + 1) pass through the switch groups S (2k + 1,1) , ..., S (2k + 1, L) to the L data lines DL i + 1 , ..., DL i + L outputs a data signal
  • the data output terminal DATA (2k + 2) passes through the switch groups S (2k + 2,1) , ..., S (2k + 2, L) to the L data lines DL i + L + 1 , ..., DL i + 2L output data signal.
  • the first poles of the N switching transistors T 1 to T N in the corresponding switch group S (2k + 1,1) are coupled in parallel to the data output terminal DATA (2k +1)
  • the second pole is coupled in parallel to the data line DL i + 1
  • the control poles are respectively coupled to the gate control terminals SW 1 , SW L + 1 , SW 2L + 1 , ..., SW ( N-1) ⁇ L + 1 .
  • the switch group S (2k + 1,1) can be provided according to the gate control terminals SW 1 , SW L + 1 , SW 2L + 1 , ..., SW (N-1) ⁇ L + 1 provided at intervals of L from each other.
  • the gate control signal controls the corresponding N switches T 1 to T N to be turned on or off, so that the data signal at the data output terminal DATA (2k + 1) is output to the data line DL i + 1 .
  • the connection relationship and function of the switch tubes in the switch group coupled to other data output terminals are similar.
  • switch group S (2k + 1,1) of the switch T and the switch control electrode group S (2k + 2,1) 1 in T 1 as the control switch The poles are coupled in parallel to the gate control terminal SW 1 .
  • the control poles of the M corresponding switch transistors T 1 are coupled to the gate control terminal SW 1 in parallel.
  • a gate control terminal SW to switch the M T provides a gate control signal which controls to turn on or off.
  • the data output terminals DATA (2k + 1 ) are respectively connected to adjacent L data lines via the switch groups S (2k + 1 , 1) , ..., S (2k + 1, L) .
  • DL i + 1 ,..., DL i + L output data signals
  • the data output terminal DATA (2k + 2) passes through the switch group S (2k + 2,1) , ..., S (2k + 2, L) to adjacent
  • the output data signals of the L data lines DL i + L + 1 ,... DL i + 2L are merely examples.
  • the data output terminal DATA (2k + 1) of the odd-numbered bits can also be connected to the adjacent data output terminal DATA (2k + 2) of the next even-numbered bits through the multiplexing circuit 102
  • the 2L data lines are alternately coupled.
  • the switching transistor may be an oxide thin film transistor.
  • the control electrode of the oxide thin film transistor is coupled to the corresponding gate control terminal, the first electrode is coupled to the corresponding data output terminal, and the second electrode is coupled to the corresponding data line.
  • the switching transistor T 1 in S (2k + 1,1) is taken as an example.
  • T 1 may be an oxide thin film transistor.
  • the control electrode of T 1 and the corresponding gate control terminal SW 1 is coupled, the first pole is coupled to the corresponding data output terminal DATA (2k + 1) , and the second pole is coupled to the corresponding data line DL i + 1 .
  • FIG. 2 is a timing chart of signals used in the data driving circuit shown in FIG. 1.
  • FIG. 2 The working process of the data driving circuit of the embodiment shown in FIG. 1 will be described in detail below with reference to the timing diagram shown in FIG. 2.
  • the gate control terminals SW 1 ,..., SW L provide the L switch tubes T 1 in the switch group S (2k + 1 , 1) , ..., S (2k + 1, L) in turn.
  • the gating control signal causes the L switching transistors T 1 to be sequentially turned on, thereby sequentially outputting the data signals from the data output terminal DATA (2k + 1) to the data lines DL i + 1 ,..., DL i + L. This process is repeated until the time period t 1 ends.
  • the gate control terminals SW L + 1 , ..., SW 2L are sequentially turned to the L switch tubes T in the switch group S (2k + 1 , 1) , ..., S (2k + 1, L) . 2 provides the selected communication control number, and the rest of the process is similar to the process of t 1 time period.
  • each gating control terminal provides a gating control signal only in one time period, and each switch tube only Work within the time period, and output the data signal to the coupled data line.
  • the time periods t 1 ,..., T N may be 2 to 3 seconds.
  • the data driving circuit includes a DATA 1, 2 two data output terminal DATA, DATA 1 data output terminal 3 via the switch groups S 11, S 12 and S 13 corresponding to the three adjacent R, G And B sub-pixel columns output data signals.
  • Each switch group includes two switch tubes T 1 and T 2. The first poles of the switch tubes T 1 and T 2 in each switch group S 11 , S 12 and S 13 are coupled to the data output terminal DATA 1 in parallel.
  • the second poles are respectively coupled in parallel to three adjacent R, G, and B sub-pixel columns.
  • the control poles of the switching tubes T 1 and T 2 in S 11 , S 12 and S 13 in the switching group are sequentially coupled to the gate control terminals SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , and SW 6 . Relationship between the data output terminal connected to the data output terminal DATA 1 DATA 2 is similar.
  • FIG. 4 illustrates a schematic diagram of a data driving circuit according to another embodiment of the present disclosure.
  • the data output terminal of the odd-numbered bits and the data output terminal of the next even-numbered bits are alternately coupled to the adjacent 2L data lines through the multiplexing circuit 102.
  • the data output terminals DATA (2k + 1) respectively output data signals to the odd-numbered L data lines through the switch groups of the odd-numbered bits.
  • the data output terminal DATA (2k + 2) respectively outputs data signals to the even-numbered L data lines through the even-numbered switch groups.
  • the other connection relationships and the roles played by the components in the embodiment shown in FIG. 4 are similar to the embodiment shown in FIG. 1.
  • FIG. 5 is a circuit diagram of another example of a data driving circuit according to an embodiment of the present disclosure, in which M is equal to 2, N is equal to 2, L is equal to 3, a data output line and sub-pixel columns arranged in the order of R, G, and B Coupling.
  • the data output terminal DATA 1 is in the first, third, and third positions via the switch groups S 11 , S 13, and S 22 in the first, third, and fifth positions, respectively.
  • the fifth, R, B, and G sub-pixel columns output data signals.
  • the data output terminal DATA 2 passes through the switch groups S 12 , S 21, and S 23 in the second, fourth, and sixth positions to the G, R, and B sub-positions in the second, fourth, and sixth positions, respectively.
  • the pixel column outputs a data signal.
  • the other connection relationships and the functions played by the components in the embodiment shown in FIG. 5 are similar to those in the embodiment shown in FIG. 3, and are not repeated here.
  • FIG. 6 is a schematic diagram of a method for driving a data driving circuit according to an embodiment of the present disclosure.
  • control signals are sequentially provided through L gating control terminals, so that one switch tube in each switch group works.
  • the data signal from the corresponding data output terminal is output to the corresponding data line through the turned-on switch tube.
  • FIG. 7 is a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a scan driving circuit 701, a data driving circuit 100 as shown in FIG. 1, and a pixel circuit 702.
  • the scan driving circuit 701 provides a scan signal to the pixel circuit 702 through a scan line Scan.
  • the data driving circuit 100 supplies a data signal to the pixel circuit 702 through the data line DL.
  • FIG. 8 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes an array substrate 700 as shown in FIG. 7.
  • the display panel 800 provided by the embodiment of the present disclosure can be used for any product or component having a display function.
  • Products or components with display functions include, but are not limited to: display panels, wearable devices, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, etc.

Abstract

一种数据驱动电路（100）及其驱动方法、阵列基板（700）和显示面板（800）。数据驱动电路（100）包括数据驱动器（101）、多路复用电路（102）和控制电路（103）。数据驱动器（101）包括M个数据输出端，每个数据输出端经由多路复用电路（102）向对应的L条数据线输出数据信号。多路复用电路（102）包括M×L个开关组，每个开关组包括N个开关管（T 1、T 2、…、T N）并被耦接在一条数据线与对应的数据输出端之间。每个开关管（T 1，T 2，…，T N）与控制电路（103）的L×N个选通控制端（SW 1、SW 2、…、SW L、SW L+1、SW L+2、…、SW 2L、…、SW (N-1) ×L+1、SW (N-1) ×L+2，…、SW N ×L）中的一个耦接。每个选通控制端（SW 1，SW 2，…，SW L，SW L+1，SW L+2，…，SW 2L，…，SW (N-1) ×L+1，SW (N-1) ×L+2，…，SW N ×L）与彼此间隔(L×N-1)个开关管的M个开关管耦接。其中，M是整数，L和N是大于等于2的整数。

Description

数据驱动电路及其驱动方法、阵列基板和显示面板
相关申请的交叉引用
本申请要求于2018年7月2日递交的中国专利申请第201810706862.4号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及用于显示面板的数据驱动电路及其驱动方法、阵列基板和显示面板。
背景技术
当前，显示面板的窄边框化已成为趋势。在显示面板中，可通过复用电路来对数据输出线路进行复用，从而减少数据输出端的数量，以实现显示面板的窄边框。通常，复用电路可使用氧化物薄膜晶体管(TFT)实现。
发明内容
本公开的实施例提供了一种数据驱动电路、阵列基板、显示面板和用于驱动数据驱动电路的方法。
根据本公开的第一方面，提供了一种数据驱动电路。该数据驱动电路包括数据驱动器、多路复用电路和控制电路。该数据驱动器包括M个数据输出端，每个数据输出端经由多路复用电路向对应的L条数据线输出数据信号。该多路复用电路包括M×L个开关组，每个开关组包括N个开关管并被耦接在一条数据线与对应的数据输出端之间。每个开关管与控制电路的L×N个选通控制端中的一个耦接，并被配置为根据来自所耦接的选通控制端的控制信号，将来自所对应的数据输出端的数据信号输出到所对应的数据线。每个所述选通控制端与彼此间隔(L×N-1)个所述开关管的M个开关管耦接，并被配置为向所对应的开关管提供控制信号。其中，M是整 数，L和N是大于等于2的整数。
在本公开的实施例中，开关管是氧化物薄膜晶体管。氧化物薄膜晶体管的控制极与所对应的选通控制端耦接，第一极与所对应的数据输出端耦接，第二极与所对应的数据线耦接。
在本公开的实施例中，奇数位的数据输出端与相邻的下一个偶数位的数据输出端通过多路复用电路与相邻的2L条数据线交替耦接。
在本公开的实施例中，M个所述数据输出端各自通过多路复用电路与相邻的L条数据线耦接。
在本公开的实施例中，N是2、3或4。
在本公开的实施例中，L是2或3。
根据本公开的第二方面，提供了一种阵列基板。该阵列基板包括扫描驱动电路、根据本公开的第一方面所述的数据驱动电路、以及像素电路。其中，扫描驱动电路被配置为通过扫描线向像素电路提供扫描信号。数据驱动电路被配置为通过数据线向像素电路提供数据信号。
根据本公开的第三方面，提供了一种显示面板。该显示面板包括根据本公开的第二方面所述的阵列基板。
根据本公开的第四方面，提供了一种用于驱动根据本公开的第一方面所述的数据驱动电路的驱动方法。在该驱动方法中，在N个时间段中的每个时间段，通过L个选通控制端依次提供控制信号，以使得每个开关组中的一个开关管工作，以将来自对应的数据输出端的数据信号输出到对应的数据线。在不同的时间段，L个选通控制端是不同的，并且每个开关组中工作的开关管是不同的。
在本公开的实施例中，每个时间段中包括一个或多个扫描周期。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中，贯穿这些附图的各个视图，相应的参考 编号指示相应的部件或特征：
图1是根据本公开的一个实施例的数据驱动电路的示意性电路图；
图2是用于如图1所示的数据驱动电路的各信号的时序图；
图3是根据本公开的实施例的数据驱动电路的一个示例的电路图；
图4是根据本公开的另一个实施例的数据驱动电路的示意性电路图；
图5是根据本公开的实施例的数据驱动电路的另一个示例的电路图；
图6是根据本公开的实施例的用于驱动数据驱动电路的方法的示意性流程图；
图7是根据本公开的实施例的阵列基板的示意性框图；
图8是根据本公开的实施例的显示面板的示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开保护的范围。
当介绍本公开的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电 极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
由氧化物薄膜晶体管实现的复用电路应用在显示技术领域时，氧化物晶体管长时间处于高频充放电状态。由于氧化物薄膜晶体管的可信赖性低，造成氧化物薄膜晶体管的阈值电压产生正向漂移，从而导致与复用电路的输出线耦接的装置充电不足。例如导致像素驱动电路充电不完全，显示面板不能正常工作。另外，长时间处于高频充放电状态会降低晶体管的寿命，从而影响复用电路以及显示装置的寿命。
本公开的实施例提供了一种数据驱动电路，该数据驱动电路能够减少高频充放电持续时间，从而提高其中的复用电路的信赖性。图1是根据本公开的一个实施例的数据驱动电路100的示意性电路图。如图1所示，数据驱动电路100可包括数据驱动器101、多路复用电路102和控制电路103。
在本公开的实施例中，数据驱动器101包括M个数据输出端。每个数据输出端经由多路复用电路102向对应的L条数据线输出数据信号。多路复用电路102包括M×L个开关组。每个开关组包括N个开关管(例如，T 1、…、T N)并被耦接在一条数据线与对应的数据输出端之间。每个开关管与控制电路103的L×N个选通控制端中的一个耦接。开关管可根据来自所耦接的选通控制端的控制信号，将来自所对应的数据输出端的数据信号输出到所对应的数据线。每个选通控制端与彼此间隔(L×N-1)个开关管的M个开关管耦接，并向所对应的开关管提供控制信号。在本公开的实施例中，M是整数，L和N是大于等于2的整数。
为便于说明，图1仅示出了两个数据输出端DATA (2k+1)和DATA (2k+2)与多路复用电路102连接的情形。如图1所示，数据输出端DATA (2k+1)经由开关组S (2k+1,1)、…、S (2k+1,L)分别向L条数据线DL i+1、…、DL i+L输出数 据信号，数据输出端DATA (2k+2)经由开关组S (2k+2,1)、…、S (2k+2,L)分别向L条数据线DL i+L+1、…、DL i+2L输出数据信号。例如，对于数据输出端DATA (2k+1)，对应的开关组S (2k+1,1)中的N个开关管T 1到T N的第一极并联耦接到数据输出端DATA (2k+1)，第二极并联耦接在数据线DL i+1，控制极分别耦接到彼此间隔为L的选通控制端SW 1、SW L+1、SW 2L+1、…、SW (N-1)×L+1。这样，开关组S (2k+1,1)可根据彼此间隔为L的选通控制端SW 1、SW L+1、SW 2L+1、…、SW (N-1)×L+1提供的选通控制信号，控制对应的N个开关管T 1到T N的导通或关断，从而将数据输出端DATA (2k+1)的数据信号输出到数据线DL i+1中。与其他数据输出端耦接的开关组中的开关管的连接关系和作用与此类似。
此外，例如，对于选通控制端SW 1，开关组S (2k+1,1)中的开关管T 1的控制极与开关组S (2k+2,1)中的开关管T 1的控制极并联耦接到选通控制端SW 1。开关组S (2k+1,1)中的开关管T 1与开关组S (2k+2,1)中的开关管T 1间隔(L×N-1)个开关管。在数据驱动器101有M个数据输出端的情况下，存在M个对应的开关管T 1的控制极并联耦接到选通控制端SW 1。该M个开关管T 1中的相邻两个开关管T 1之间均间隔(L×N-1)个开关管。选通控制端SW 1向该M个开关管T 1提供选通控制信号，控制其导通或关断。
在图1所示的实施例中，数据输出端DATA (2k+1)经由开关组S (2k+1,1)、…、S (2k+1,L)分别向相邻的L条数据线DL i+1、…、DL i+L输出数据信号，数据输出端DATA (2k+2)经由开关组S (2k+2,1)、…、S (2k+2,L)分别向相邻的L条数据线DL i+L+1、…、DL i+2L输出数据信号仅作为示例。在本公开的实施例中，奇数位的数据输出端DATA (2k+1)也可以与相邻的下一个偶数位的数据输出端DATA (2k+2)通过多路复用电路102与相邻的2L条数据线交替耦接。这种耦接方式将在下面参照图4和图5进行详细描述。在本公开的实施例中，开关管可以是氧化物薄膜晶体管。氧化物薄膜晶体管的控制极与所对应的选通控制端耦接，第一极与对应的数据输出端耦接，第二极与对应的数据线耦接。在图1所示的实施例中，以S (2k+1,1)中的开关管T 1为例，T 1可以是氧化物薄膜晶体管，T 1的控制极与所对应的选通控制端SW 1耦接，第一极与 对应的数据输出端DATA (2k+1)耦接，第二极与对应的数据线DL i+1耦接。
应当理解，除了氧化物薄膜晶体管之外，开关管也可以是其它类型的晶体管，例如多晶硅晶体管、单晶硅晶体管等。图2是用于如图1所示的数据驱动电路的各信号的时序图。下面结合图2所示的时序图，对图1所示的实施例的数据驱动电路的工作过程进行详细描述。以数据输出端DATA (2k+1)为例。在t 1时间段内，选通控制端SW 1、…、SW L依次向开关组S (2k+1,1)、…、S (2k+1,L)中的L个开关管T 1提供选通控制信号，使得L个开关管T 1依次导通，从而将来自数据输出端DATA (2k+1)的数据信号依次向数据线DL i+1、…、DL i+L输出。重复此过程，直至t 1时间段结束。在t 2时间段内，选通控制端SW L+1、…、SW 2L依次向开关组S (2k+1,1)、…、S (2k+1,L)中的L个开关管T 2提供选通信控制号，其余过程与t 1时间段的过程类似。与t 1和t 2时间段类似，执行t 3至t N时间段内的过程。如上所述，t 1时间段内的L个导通控制端SW 1、…、SW L与t 2时间段内的L个导通控制端SW L+1、…、SW 2L不同。应当理解，在图2所示的N个不同的时间段t 1、…、t N内，每个选通控制端仅在一个时间段内提供选通控制信号，而每个开关管仅在一个时间段内工作，将数据信号输出到所耦接的数据线。
在本公开的实施例中，时间段t 1、…、t N可以是2～3秒。
图3是根据本公开的实施例的数据驱动电路的一个示例的电路图，其中，M等于2，N等于2，L等于3，数据输出线与以R、G、B顺序布置的子像素列耦接。如图3所示，数据驱动电路包括DATA 1、DATA 2两个数据输出端，数据输出端DATA 1经由3个开关组S 11、S 12和S 13向对应的3个相邻的R、G、B子像素列输出数据信号。每个开关组包括2个开关管T 1和T 2，每个开关组S 11、S 12和S 13中的开关管T 1和T 2的第一极并联耦接到数据输出端DATA 1，第二极分别并联耦接到3个相邻的R、G、B子像素列。开关组中S 11、S 12和S 13中的开关管T 1和T 2的控制极顺序耦接到选通控制端SW 1、SW 2、SW 3、SW 4、SW 5、SW 6。数据输出端DATA 2的连接关系与数据输出端DATA 1类似。
图4示出了根据本公开的另一实施例的数据驱动电路的示意图。在所 示的数据驱动电路中，奇数位的数据输出端与相邻的下一个偶数位的数据输出端通过多路复用电路102与相邻的2L条数据线交替耦接。如图4所示，数据输出端DATA (2k+1)经由奇数位的开关组分别向奇数位的L条数据线输出数据信号。数据输出端DATA (2k+2)经由偶数位的开关组分别向偶数位的L条数据线输出数据信号。图4所示的实施例的其他连接关系和各部件所起的作用与图1所示的实施例类似。
图5是根据本公开的实施例的数据驱动电路的另一个示例的电路图，其中，M等于2，N等于2，L等于3，数据输出线与以R、G、B顺序布置的子像素列耦接。在图5所示的数据驱动电路中，数据输出端DATA 1经由处于第一位、第三位、第五位的开关组S 11、S 13和S 22分别向处于第一位、第三位、第五位的R、B、G子像素列输出数据信号。数据输出端DATA 2经由处于第二位、第四位、第六位的开关组S 12、S 21和S 23分别向处于第二位、第四位、第六位的G、R、B子像素列输出数据信号。图5所示的实施例的其他连接关系和各部件所起的作用与图3所示的实施例类似，在此不再赘述。
图6是根据本公开的实施例的用于驱动数据驱动电路的方法的示意图。如图6所示，在步骤601，在N个时间段中的每个时间段内，通过L个选通控制端依次提供控制信号，以使得每个开关组中的一个开关管工作。然后，在步骤602，通过导通的开关管，来自对应的数据输出端的数据信号被输出到对应的数据线。
上述过程与参照图2所描述的类似，在此不再赘述。
图7是根据本公开的实施例的阵列基板的示意性框图。如图7所示，阵列基板包括扫描驱动电路701、如图1所示的数据驱动电路100、以及像素电路702。在本公开的实施例中，扫描驱动电路701通过扫描线Scan向像素电路702提供扫描信号。数据驱动电路100通过数据线DL向像素电路702提供数据信号。
图8是根据本公开的实施例的显示面板的示意图。如图8所示，显示面板包括如图7所示的阵列基板700。本公开的实施例提供的显示面板800 可以用于任何具有显示功能的产品或部件。具有显示功能的产品或部件包括但不限制于：显示面板、可穿戴设备、移动电话、平板电脑、电视机、笔记本电脑、数码相框、导航仪等。
此处已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开范围和精神内的此类形式或者修改。

Claims (10)

  1. 一种数据驱动电路，包括：数据驱动器、多路复用电路和控制电路；
    其中，所述数据驱动器包括M个数据输出端，每个所述数据输出端经由所述多路复用电路向对应的L条数据线输出数据信号；
    所述多路复用电路包括M×L个开关组，每个所述开关组包括N个开关管并被耦接在一条数据线与对应的数据输出端之间；
    每个所述开关管与所述控制电路的L×N个选通控制端中的一个耦接，并被配置为根据来自所耦接的选通控制端的控制信号，将来自所对应的数据输出端的数据信号输出到所对应的数据线；
    每个所述选通控制端与彼此间隔(L×N-1)个所述开关管的M个开关管耦接，并被配置为向所对应的开关管提供控制信号；
    其中，M是整数，L和N是大于等于2的整数。
  2. 根据权利要求1所述的数据驱动电路，其中，所述开关管是氧化物薄膜晶体管，所述氧化物薄膜晶体管的控制极与所对应的选通控制端耦接，第一极与所对应的数据输出端耦接，第二极与所对应的数据线耦接。
  3. 根据权利要求1所述的数据驱动电路，其中，奇数位的所述数据输出端与相邻的下一个偶数位的所述数据输出端通过所述多路复用电路与相邻的2L条所述数据线交替耦接。
  4. 根据权利要求1所述的数据驱动电路，其中，所述M个所述数据输出端各自通过所述多路复用电路与相邻的L条所述数据线耦接。
  5. 根据权利要求1所述的数据驱动电路，其中，N是2、3或4。
  6. 根据权利要求1所述的数据驱动电路，其中，L是2或3。
  7. 一种阵列基板，包括：扫描驱动电路、根据权利要求1至6中任一项所述的数据驱动电路、以及像素电路；
    其中，所述扫描驱动电路被配置为通过扫描线向所述像素电路提供扫描信号；
    所述数据驱动电路被配置为通过数据线向所述像素电路提供数据信号。
  8. 一种显示面板，包括根据权利要求7所述的阵列基板。
  9. 一种用于驱动根据权利要求1至6任一项所述的数据驱动电路的驱动方法，包括：
    在N个时间段中的每个所述时间段，通过L个选通控制端依次提供控制信号，以使得每个开关组中的一个开关管工作，以将来自对应的数据输出端的数据信号输出到对应的数据线；
    其中，在不同的所述时间段，所述L个选通控制端是不同的，并且每个所述开关组中工作的所述开关管是不同的。
  10. 根据权利要求9所述的驱动方法，其中，所述N个时间段中的一个或多个构成一个扫描周期。
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