WO2017092089A1 - 栅极驱动电路和使用栅极驱动电路的显示器 - Google Patents

栅极驱动电路和使用栅极驱动电路的显示器 Download PDF

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Publication number
WO2017092089A1
WO2017092089A1 PCT/CN2015/098300 CN2015098300W WO2017092089A1 WO 2017092089 A1 WO2017092089 A1 WO 2017092089A1 CN 2015098300 W CN2015098300 W CN 2015098300W WO 2017092089 A1 WO2017092089 A1 WO 2017092089A1
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Prior art keywords
electrically connected
gate
signal
transistor
source
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PCT/CN2015/098300
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English (en)
French (fr)
Inventor
李亚锋
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武汉华星光电技术有限公司
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Priority to US14/906,702 priority Critical patent/US9779684B2/en
Publication of WO2017092089A1 publication Critical patent/WO2017092089A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to a display, in particular to a gate driver (Gate driver on Array, GOA) display of the circuit.
  • GOA Gate driver on Array
  • the GOA circuit uses a thin film transistor liquid crystal display Array process to fabricate a gate driver with a thin film transistor (Thin film).
  • a transistor, TFT thin film transistor array of glass substrates to achieve a progressive scan driving method.
  • the touch device is made up of a display panel and a touch screen (Touch)
  • the Panel is used in combination, so the GOA circuit for the display panel needs to periodically pause the output of the scan signal to the TFT array substrate in accordance with the scan period of the touch screen, so that the display panel assumes a black screen mode.
  • the display panel Before the GOA circuit resumes outputting the scan signal, the display panel needs to be woken up from the black screen mode.
  • the GOA circuit needs to set all the scan lines to be turned on for a period of time, and all the data lines output a specific low voltage to clear the residual charge in the pixel capacitors to avoid picture sticking. This period of time is called the scan line fully open (All Gate On) stage.
  • the GOA circuit includes a plurality of GOA circuit units, each of which is composed of a plurality of transistors. Since the GOA circuit directly forms the side of the glass substrate, the smaller the number of transistors per GOA circuit unit, the less the glass substrate area occupied by the GOA circuit. As such, a GOA circuit unit using fewer transistors would facilitate a narrower edge display panel.
  • the technical solution of the present invention provides a gate driving circuit including a plurality of GOA circuit units. a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is configured to use a scan signal output by the GOA circuit unit of the previous stage, a scan signal output by the GOA circuit unit of the subsequent stage, a first clock signal, The second clock signal, the third clock signal, the fourth clock signal, the first gate turn-on signal, and the second gate turn-on signal output a scan signal at the output end.
  • Each level of the GOA circuit unit includes an input control module, an output control module, a pull-down module, and a pull-up maintenance module.
  • the input control module is configured to output a control signal at the control node according to the first clock signal, the third clock signal, and the first gate turn-on signal.
  • the input control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • the gate of the first transistor is electrically connected to the first clock signal, and the drain thereof is electrically connected to the scan signal output by the previous stage GOA circuit unit.
  • the gate of the second transistor is electrically connected to the first gate turn-on signal, the drain thereof is electrically connected to the source of the first transistor, and the source thereof is electrically connected to the control node.
  • the gate of the third transistor is electrically connected to the first gate turn-on signal, and the drain thereof is electrically connected to the source of the second transistor.
  • the gate of the fourth transistor is electrically connected to the third clock signal, the drain thereof is electrically connected to the source of the third transistor, and the source thereof is electrically connected to the scan of the output of the subsequent stage GOA circuit unit signal.
  • the output control module is electrically connected to the control node, and is configured to output the scan signal at the output end according to the control signal and the second clock signal.
  • the pull-down module is electrically connected to the output control module for pulling the scan signal to a low level.
  • the pull-up maintaining module is electrically connected to the output end and the second gate turn-on signal, and is configured to keep the scan signal outputted at the output end high when receiving the second gate turn-on signal Level.
  • the output control module includes a fifth transistor, a sixth transistor, and a capacitor.
  • the gate of the fifth transistor is electrically connected to the first fixed voltage, and the drain thereof is electrically connected to the control node.
  • the gate of the sixth transistor is electrically connected to the source of the fifth transistor, the drain thereof is electrically connected to the second clock signal, and the source thereof is electrically connected to the output end. Both ends of the capacitor are respectively connected to a source and a gate of the sixth transistor.
  • the pull-down module comprises a seventh transistor and an eighth transistor.
  • the gate of the seventh transistor is electrically connected to the first gate turn-on signal, and the drain thereof is electrically connected to the output terminal and the source of the sixth transistor.
  • the gate of the eighth transistor is electrically connected to the fourth clock signal, the drain thereof is electrically connected to the source of the seventh transistor, and the source thereof is electrically connected to the second fixed voltage.
  • the pull-up sustaining module comprises a ninth transistor and a tenth transistor.
  • the gate of the ninth transistor is electrically connected to the second gate-on signal, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the second fixed voltage.
  • the gate of the tenth transistor is electrically connected to the second gate turn-on signal, the drain thereof is electrically connected to the first fixed voltage, and the source thereof is electrically connected to the output end.
  • the pull-up sustaining module comprises a ninth transistor and a tenth transistor.
  • the gate of the ninth transistor is electrically connected to the second gate-on signal, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the second fixed voltage.
  • the gate and the drain of the tenth transistor are electrically connected to the second gate turn-on signal, and the source thereof is electrically connected to the output end.
  • the pulses of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially output in turn, and do not overlap each other.
  • the first fixed voltage is a high level and the second fixed voltage is a low level.
  • the first gate turn-on signal and the second gate turn-on signal are mutually inverted.
  • the technical solution of the present invention further provides a display including a source driver and a gate driving circuit as described above, wherein the gate driving circuit outputs a scan signal such that a plurality of the transistors are turned on, and the source driver outputs corresponding data.
  • the signal is applied to a plurality of said pixel units to display gray scales.
  • each stage of the GOA circuit unit of the gate driving circuit of the present invention is composed of ten transistors, and the number of transistors used is small, which has the beneficial effect of facilitating the design of the narrow bezel display.
  • the input control module of the GOA circuit unit includes a second transistor and a third transistor that are controlled by a first gate open signal. Since the first transistor and the second transistor are connected in series, the third transistor and the fourth transistor are connected in series, so that leakage current can be reduced, and there is an advantageous effect of improving the stability of each stage of the GOA circuit unit.
  • Figure 1 is a functional block diagram of a liquid crystal display of the present invention.
  • FIG. 2 is a circuit diagram of a GOA circuit unit of a gate driving circuit of a first embodiment of the present invention.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in a forward scan.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in reverse scan.
  • Fig. 5 is a circuit diagram of a GOA circuit unit of a gate driving circuit of a second embodiment of the present invention.
  • FIG. 1 is a functional block diagram of a display 10 of the present invention.
  • Display 10 can be a liquid crystal display or an organic light emitting diode display.
  • the display 10 includes a glass substrate 14 and a source driver (source) Driver)16.
  • a plurality of pixels arranged in a matrix and a gate driving (GOA) circuit 12 are disposed on the glass substrate 14, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • RGB red, green and blue
  • the GOA circuit 12 outputs a scan signal such that the transistors 22 of each row are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different gray scales. .
  • the GOA circuit 12 turns off the scan signal of the row, and then the GOA circuit 12 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 charges the pixel unit 20 of the next row. Discharge. This is continued until all the pixel units 20 are fully charged, and charging starts from the first line.
  • the source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n) according to the first embodiment of the present invention.
  • the GOA circuit 12 includes a plurality of cascade-connected GOA circuit units SR(n). Each stage of the GOA circuit unit SR(n) is used to output the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1) and the subsequent stage GOA circuit unit SR(n+1).
  • the scan signal G(n+1), the first clock signal CKV1, the second clock signal CKV2, the third clock signal CKV3, the fourth clock signal CKV4, the first gate-on signal Gas1, and the second gate-on signal Gas2 are The output terminal OUT outputs a scan signal G(n).
  • Each stage of the GOA circuit unit SR(n) includes an input control module 100, an output control module 200, a pull-down module 300, and a pull-up maintenance module 400.
  • the input control module 100 is configured to output a control signal Q(n) at the control node Q according to the first clock signal CKV1, the third clock signal CKV3, and the first gate-on signal Gas1.
  • the input control module 100 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the gate of the first transistor T1 is electrically connected to the first clock signal CKV1, and the drain thereof is electrically connected to the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1).
  • the gate of the second transistor T2 is electrically connected to the first gate-on signal Gas1, the drain thereof is electrically connected to the source of the first transistor T1, and the source thereof is electrically connected to the control node Q.
  • the gate of the third transistor T3 is electrically connected to the first gate-on signal Gas1, and the drain thereof is electrically connected to the source of the second transistor T2.
  • the gate of the fourth transistor T4 is electrically connected to the third clock signal CKV3, the drain thereof is electrically connected to the source of the third transistor T3, and the source thereof is electrically connected to the output of the first stage GOA circuit unit SR(n+1). Scan signal G(n+1).
  • the output control module 200 is electrically connected to the control node Q for outputting the scan signal G(n) at the output terminal OUT according to the control signal Q(n) and the second clock signal CKV2.
  • the pull-down module 300 is electrically connected to the output control module 200 for pulling the scan signal G(n) to a low level.
  • the pull-up maintaining module 400 is electrically connected to the output terminal OUT and the second gate-on signal Gas2 for maintaining the high level of the scan signal G(n) outputted at the output terminal OUT when receiving the second gate-on signal Gas2.
  • the output control module 200 includes a fifth transistor T5, a sixth transistor T6, and a capacitor C1.
  • the gate of the fifth transistor T5 is electrically connected to the first fixed voltage VGH, and the drain thereof is electrically connected to the control node Q(n).
  • the gate of the sixth transistor T6 is electrically connected to the source of the fifth transistor T5, the drain thereof is electrically connected to the second clock signal CKV2, and the source thereof is electrically connected to the output terminal OUT. Both ends of the capacitor C1 are respectively connected to the source and the gate of the sixth transistor T6.
  • the pull-down module 300 includes a seventh transistor T7 and an eighth transistor T8.
  • the gate of the seventh transistor T7 is electrically connected to the first gate-on signal Gas1, and the drain thereof is electrically connected to the source of the output terminal OUT and the sixth transistor T6.
  • the gate of the eighth transistor T8 is electrically connected to the fourth clock signal CKV4, the drain thereof is electrically connected to the source of the seventh transistor T7, and the source thereof is electrically connected to the second fixed voltage VGL.
  • the pull-up sustaining module 400 includes a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is electrically connected to the second gate-on signal Gas2, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the second fixed voltage VGL.
  • the gate of the tenth transistor T10 is electrically connected to the second gate-on signal Gas2, the drain thereof is electrically connected to the first fixed voltage VGH, and the source thereof is electrically connected to the output terminal OUT.
  • each transistor is an N-type metal oxide.
  • the semiconductor, NMOS transistor has a first fixed voltage VGH at a high level and a second fixed voltage VGL at a low level.
  • the first gate-on signal Gas1 and the second gate-on signal Gas2 are mutually inverted.
  • the pulses of the first clock signal CKV1, the second clock signal CKV2, the third clock signal CKV3, and the fourth clock signal CKV4 are sequentially output in turn, and do not overlap each other.
  • FIG. 3 is a timing diagram of various input signals, output signals and node voltages shown in FIG. 2 during forward scanning.
  • the second gate-on signal Gas2 will be at a low level, and all the GOA circuit units SR(n) will The scan signal G(n-1) output from the previous stage GOA circuit unit SR(n-1) and the scan signal G(n+1) outputted by the subsequent stage GOA circuit unit SR(n+1) are at the output terminal OUT
  • the scan signal G(n) is output. Specifically, during the period t1 shown in FIG.
  • the first gate-on signal Gas1, the first clock signal CKV1, and the scan signal G(n-1) are both at a high level, and at this time, the transistors T1 and T2 are both turned on. So that the high level scan signal G(n-1) is transmitted to the control node Q via the transistors T1, T2, at which time the control signal Q(n) is also at a high level. Since the first fixed voltage VGH is always at a high level, the transistor T5 is kept open at all times, at which time the transistor T5 conducts a high level control signal Q(n) to charge the capacitor C1.
  • the transistor T6 turns on to turn on the high level second clock signal CKV2 to the output terminal OUT, so that the scan signal G(n) becomes a high level.
  • the first gate-on signal Gas1, the third clock signal CKV3, and the scan signal G(n+1) are all at a high level, and at this time, the transistors T3 and T4 are all turned on, so that the high-level scan signal G (n+1) is transmitted to the control node Q via the transistors T3, T4.
  • the transistor T6 turns on the low-level second clock signal CKV2 to the output terminal OUT, so that the scan signal G(n) becomes a low level.
  • the first gate-on signal Gas1 and the fourth clock signal CKV4 are both at a high level.
  • the transistors T7 and T8 are all turned on, so that the second fixed voltage VGL of the low level is transmitted through the transistors T7 and T8.
  • the scanning signal G(n) becomes a low level.
  • the first gate-on signal Gas1 and the first clock signal CKV1 are both at a high level, and at this time, the transistors T1 and T2 are all turned on, so that the low-level scan signal G(n-1) passes through the transistor T1.
  • T2 is transmitted to the control node Q, and the control signal Q(n) is also at a low level.
  • the first gate-on signal Gas1 is at a low level, so the transistors T2, T3, and T7 are all off.
  • the second gate-on signal Gas2 is at a high level, so the transistors T9 and T10 are all turned on.
  • the transistor T9 turns on the second fixed voltage VGL of the low level to the control node Q
  • the transistor T10 turns on the first fixed voltage VGH of the high level to the output terminal OUT, so that the control signal Q(n) is low.
  • the scan signal G(n) is at a high level.
  • all of the GOA circuit units SR(n) continue to output the high level scan signal Q(n) for a period of time, at which time the source driver 16 (shown in Figure 1) outputs a particular gray level (eg, black gray scale).
  • the data signal is supplied to all of the pixel units 20 to remove the charge remaining in the pixel capacitors to avoid picture sticking.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in reverse scan.
  • the difference between FIG. 4 and FIG. 3 is that the timings of the forward scan and the reverse scan are slightly different, but those skilled in the art can understand the timing difference between the two according to the architecture of the GOA circuit unit SR(n) disclosed in FIG. 2, This will not be repeated.
  • Each of the transistors in this embodiment is exemplified by an NMOS transistor.
  • those skilled in the art can obtain a GOA circuit unit implemented by a PMOS transistor according to the circuit of the present invention, which will not be described below.
  • the GOA circuit unit of this embodiment is composed of ten transistors, and the number of transistors used is small, which has the beneficial effect of facilitating the design of the narrow bezel display.
  • the input control module 100 of the GOA circuit unit SR(n) includes the second transistor T2 and the third transistor T3 controlled by the first gate-on signal Gas1. Since the first transistor T1 and the second transistor are connected in series T2, the third transistor T3 and the fourth transistor T4 are connected in series, so that leakage current can be reduced, and there is an advantageous effect of improving the stability of each stage of the GOA circuit unit SR(n).
  • FIG. 5 is a circuit diagram of a GOA circuit unit SR(n) according to a second embodiment of the present invention.
  • the pull-up maintaining module 500 of FIG. 5 includes a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is electrically connected to the second gate-on signal Gas2, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the second fixed voltage VGL.
  • the gate and the drain of the tenth transistor T10 are electrically connected to the second gate-on signal Gas2, and the source thereof is electrically connected to the output terminal OUT.
  • the tenth transistor T10 transmits the second gate-on signal Gas2 of the high level to the output terminal OUT as the scan signal G(n).
  • the connection and operation modes of the remaining components in this embodiment are the same as those in FIG. 2 to FIG. 4, and are not described herein.
  • the GOA circuit unit of the present embodiment is composed of ten transistors, and the number of transistors used is small, which has the beneficial effect of facilitating the design of the narrow bezel display.
  • the input control module 100 of the GOA circuit unit SR(n) includes the second transistor T2 and the third transistor T3 controlled by the first gate-on signal Gas1. Since the first transistor T1 and the second transistor are connected in series T2, the third transistor T3 and the fourth transistor T4 are connected in series, so that leakage current can be reduced, and there is an advantageous effect of improving the stability of each stage of the GOA circuit unit SR(n).

Abstract

一种栅极驱动电路，其包含数个GOA电路单元（12）。每一级GOA电路单元（12）包含输入控制模块（100）、输出控制模块（200）、下拉模块（300）和上拉维持模块（400）。输入控制模块（100）包括第一晶体管（T1）、第二晶体管（T2）、第三晶体管（T3）和第四晶体管（T4）。每一级GOA电路单元（12）由十个晶体管构成，使用的晶体管数量较少，具有便于窄边框显示器设计的有益效果。另外，GOA电路单元的输入控制模块（100）包含由第一栅极开启信号（Gas1）控制的第二晶体管（T2）和第三晶体管（T3）。由于第一晶体管（T1）和第二晶体管（T2）串联，第三晶体管（T3）和第四晶体管（T4）串联，因此可以减少漏电流，具有提高每一级GOA电路单元稳定性的有益效果。

Description

栅极驱动电路和使用栅极驱动电路的显示器 技术领域
本发明是有关于一种显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的显示器。
 背景技术
GOA电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的玻璃基板上，以实现逐行扫描的驱动方式。
由于触控装置是由显示面板和触摸屏(Touch Panel)搭配使用，因此用于显示面板的GOA电路需要配合触摸屏的扫描周期而定时地暂停输出扫描信号予TFT阵列基板，使得显示面板呈现黑屏模式。在GOA电路恢复输出扫描信号前，需将显示面板从黑屏模式唤醒。此时GOA电路需要在一段时间内将所有的扫描线均设置为导通状态，让所有数据线输出特定低电压以清空像素电容中残留的电荷，以避免画面残留的现象。此段时间称为扫描线全开(All Gate On)阶段。
GOA电路包含数个GOA电路单元，每一GOA电路单元由数个晶体管构成。由于GOA电路直接形成玻璃基板的侧边上，因此每一GOA电路单元的晶体管数量越少，GOA电路占用的玻璃基板面积就越少。如此一来，使用较少晶体管的GOA电路单元将有利于窄边化的显示面板。
因此如何制造一种使用较少晶体管的GOA电路单元的栅极驱动电路是业界努力的目标。
 技术问题
本发明的目的是提供一种栅极驱动电路和使用栅极驱动电路的显示面板，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元。数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一栅极开启信号以及第二栅极开启信号，在输出端输出扫描信号。每一级GOA电路单元包含输入控制模块、输出控制模块、下拉模块和上拉维持模块。所述输入控制模块用来依据所述第一时钟信号、所述第三时钟信号和所述第一栅极开启信号，在控制节点输出控制信号。所述输入控制模块包括第一晶体管、第二晶体管、第三晶体管和第四晶体管。所述第一晶体管的栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号。所述第二晶体管的栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第一晶体管的源极，其源极电性连接所述控制节点。所述第三晶体管的栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第二晶体管的源极。所述第四晶体管的栅极电性连接所述第三时钟信号，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述后一级GOA电路单元输出的扫描信号。所述输出控制模块电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号。所述下拉模块电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。所述上拉维持模块电性连接所述输出端和所述第二栅极开启信号，用来当接收所述第二栅极开启信号时，在所述输出端输出的所述扫描信号保持高电平。
依据本发明的实施例，所述输出控制模块包含第五晶体管、第六晶体管和电容。所述第五晶体管的栅极电性连接第一固定电压，其漏极电性连接所述控制节点。所述第六晶体管的栅极电性连接所述第五晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端。所述电容的两端分别连接所述第六晶体管的源极和栅极。
依据本发明的实施例，所述下拉模块包含第七晶体管和第八晶体管。所述第七晶体管的栅极电性连接所述第一栅极开启信号，其漏极电性连接所述输出端及所述第六晶体管的源极。所述第八晶体管的栅极电性连接所述第四时钟信号，其漏极电性连接所述第七晶体管的源极，其源极电性连接第二固定电压。
依据本发明的实施例，所述上拉维持模块包含第九晶体管和第十晶体管。所述第九晶体管的栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压。所述第十晶体管的栅极电性连接所述第二栅极开启信号，其漏极电性连接所述第一固定电压，其源极电性连接所述输出端。
依据本发明的实施例，所述上拉维持模块包含第九晶体管和第十晶体管。所述第九晶体管的栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压。所述第十晶体管的栅极和漏极皆电性连接所述第二栅极开启信号，其源极电性连接所述输出端。
依据本发明的实施例，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
依据本发明的实施例，所述第一固定电压为高电平，所述第二固定电压为低电平。
依据本发明的实施例，所述第一栅极开启信号和所述第二栅极开启信号互为反相。
本发明的技术方案又提供一种显示器包含源极驱动器以及如上述的栅极驱动电路，所述栅极驱动电路输出扫描信号使得数个所述晶体管开启，同时所述源极驱动器输出对应的数据信号至数个所述像素单元使其显示灰阶。
 有益效果
相较于现有技术，本发明的栅极驱动电路的每一级GOA电路单元是由十个晶体管构成，使用的晶体管数量较少，具有便于窄边框显示器设计的有益效果。另外，GOA电路单元的输入控制模块包含由第一栅极开启信号控制的第二晶体管和第三晶体管。由于第一晶体管和第二晶体管串联，第三晶体管和第四晶体管串联，因此可以减少漏电流，具有提高每一级GOA电路单元稳定性的有益效果。
 附图说明
图1是本发明的液晶显示器的功能方块图。
图2是本发明第一实施例的栅极驱动电路的GOA电路单元的电路图。
图3是图2所示各种输入信号、输出信号和节点电压在正向扫描时的时序图。
图4是图2所示各种输入信号、输出信号和节点电压在反向扫描时的时序图。
图5是本发明第二实施例的栅极驱动电路的GOA电路单元的电路图。
 本发明的最佳实施方式
请参阅图1，图1是本发明的显示器10的功能方块图。显示器10可以是液晶显示器或是有机发光二极管显示器。显示器10包含玻璃基板14以及源极驱动器(source driver)16。玻璃基板14上设置数个呈矩阵排列的像素(pixel)和栅极驱动(GOA)电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。以一个1024 × 768分辨率的液晶显示器10来说，共需要1024 × 768 × 3个像素单元20组合而成。GOA电路12输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。
在目前的液晶显示面板设计中，GOA电路12即每隔一固定间隔输出扫描信号。以一个1024 × 768分辨率的液晶显示器10以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉冲为16.67ms/768=21.7μs。而源极驱动器16则在这21.7μs的时间内，将像素单元20充放电到所需的电压，以显示出相对应的灰阶。
请参阅图2，图2是本发明第一实施例的GOA电路单元SR(n)的电路图。GOA电路12包含数个串接(cascade-connected)的GOA电路单元SR(n)。每一级GOA电路单元SR(n)用来依据前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)、后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)、第一时钟信号CKV1、第二时钟信号CKV2、第三时钟信号CKV3、第四时钟信号CKV4、第一栅极开启信号Gas1以及第二栅极开启信号Gas2，在输出端OUT输出扫描信号G(n)。每一级GOA电路单元SR(n)包含输入控制模块100、输出控制模块200、下拉模块300和上拉维持模块400。输入控制模块100用来依据第一时钟信号CKV1、第三时钟信号CKV3和第一栅极开启信号Gas1，在控制节点Q输出控制信号Q(n)。输入控制模块100包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1的栅极电性连接第一时钟信号CKV1，其漏极电性连接前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)。第二晶体管T2的栅极电性连接第一栅极开启信号Gas1，其漏极电性连接第一晶体管T1的源极，其源极电性连接控制节点Q。第三晶体管T3的栅极电性连接第一栅极开启信号Gas1，其漏极电性连接第二晶体管T2的源极。第四晶体管T4的栅极电性连接第三时钟信号CKV3，其漏极电性连接第三晶体管T3的源极，其源极电性连接后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)。输出控制模块200电性连接于控制节点Q，用来依据控制信号Q(n)和第二时钟信号CKV2，在输出端OUT输出扫描信号G(n)。下拉模块300电性连接输出控制模块200，用来将扫描信号G(n)下拉至低电平。上拉维持模块400电性连接输出端OUT和第二栅极开启信号Gas2，用来当接收第二栅极开启信号Gas2时，在输出端OUT输出的扫描信号G(n)保持高电平。
输出控制模块200包含第五晶体管T5、第六晶体管T6和电容C1。第五晶体管T5的栅极电性连接第一固定电压VGH，其漏极电性连接控制节点Q(n)。第六晶体管T6的栅极电性连接第五晶体管T5的源极，其漏极电性连接第二时钟信号CKV2，其源极电性连接输出端OUT。电容C1的两端分别连接第六晶体管T6的源极和栅极。
下拉模块300包含第七晶体管T7和第八晶体管T8。第七晶体管T7的栅极电性连接第一栅极开启信号Gas1，其漏极电性连接输出端OUT及第六晶体管T6的源极。第八晶体管T8的栅极电性连接第四时钟信号CKV4，其漏极电性连接第七晶体管T7的源极，其源极电性连接第二固定电压VGL。
上拉维持模块400包含第九晶体管T9和第十晶体管T10。第九晶体管T9的栅极电性连接第二栅极开启信号Gas2，其漏极电性连接控制节点Q，其源极电性连接第二固定电压VGL。第十晶体管T10的栅极电性连接第二栅极开启信号Gas2，其漏极电性连接第一固定电压VGH，其源极电性连接输出端OUT。
依据图2所示的实施例，每一晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管，第一固定电压VGH为高电平，第二固定电压VGL为低电平。第一栅极开启信号Gas1和第二栅极开启信号Gas2互为反相。第一时钟信号CKV1、第二时钟信号CKV2、第三时钟信号CKV3和第四时钟信号CKV4的脉冲是依序轮流输出，且互不重叠。
请一并参阅图2和图3，图3是图2所示各种输入信号、输出信号和节点电压在正向扫描时的时序图。当每一级GOA电路单元SR(n)收到高电平的第一栅极开启信号Gas1时，第二栅极开启信号Gas2会处于低电平，此时所有GOA电路单元SR(n)会依据前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)以及后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)在输出端OUT输出扫描信号G(n)。具体来说，在图3所示的t1期间，第一栅极开启信号Gas1、第一时钟信号CKV1和扫描信号G(n-1)皆为高电平，此时晶体管T1、T2皆为开启，使得高电平的扫描信号G(n-1)会经由晶体管T1、T2传送至控制节点Q，此时控制信号Q(n)也是处于高电平。因为第一固定电压VGH一直处于高电平，所以晶体管T5会一直保持开启，此时晶体管T5导通高电平的控制信号Q(n)以对电容C1充电。在t2期间，因为电容C1保持电荷的因素，因此晶体管T6会开启以导通高电平的第二时钟信号CKV2至输出端OUT，使得扫描信号G(n)变为高电平。在t3期间，第一栅极开启信号Gas1、第三时钟信号CKV3和扫描信号G(n+1)皆为高电平，此时晶体管T3、T4皆为开启，使得高电平的扫描信号G(n+1)会经由晶体管T3、T4传送至控制节点Q。此时晶体管T6会导通低电平的第二时钟信号CKV2至输出端OUT，使得扫描信号G(n)变为低电平。在t4期间，第一栅极开启信号Gas1和第四时钟信号CKV4皆为高电平，此时晶体管T7、T8皆为开启，使得低电平的第二固定电压VGL会经由晶体管T7、T8传送至输出端OUT。此时扫描信号G(n)变为低电平。在t5期间，第一栅极开启信号Gas1和第一时钟信号CKV1皆为高电平，此时晶体管T1、T2皆为开启，使得低电平的扫描信号G(n-1)会经由晶体管T1、T2传送至控制节点Q，此时控制信号Q(n)也是处于低电平。
在t6期间，第一栅极开启信号Gas1处于低电平，所以晶体管T2、T3、T7皆为断开。第二栅极开启信号Gas2处于高电平，所以晶体管T9、T10皆为开启。此时，晶体管T9导通低电平的第二固定电压VGL至控制节点Q，晶体管T10导通高电平的第一固定电压VGH至输出端OUT，使得控制信号Q(n)为低电平，扫描信号G(n)为高电平。在t6期间，亦即扫描线全开(All Gate On)阶段，所有的GOA电路单元SR(n)都会持续输出高电平扫描信号Q(n)一段时间，此时源极驱动器16(图1所示)会输出特定灰阶(例如黑色灰阶)的数据信号给所有的像素单元20，以清除残留于像素电容中的电荷，以避免画面残留的现象。
图4是图2所示各种输入信号、输出信号和节点电压在反向扫描时的时序图。图4与图3的差异在于正向扫描和反向扫描的时序稍有不同，但是本领域技术人员可依据图2所揭示的GOA电路单元SR(n)的架构了解两者的时序差异，在此不另赘述。
本实施例的每一晶体管是以NMOS晶体管为例做说明，但是本领域技术人员可以根据本发明的电路得到以PMOS晶体管实现的GOA电路单元，以下不再赘述。
本实施例的GOA电路单元是由十个晶体管构成，使用的晶体管数量较少，具有便于窄边框显示器设计的有益效果。另外，GOA电路单元SR(n)的输入控制模块100包含由第一栅极开启信号Gas1控制的第二晶体管T2和第三晶体管T3。由于第一晶体管T1和第二晶体管串联T2，第三晶体管T3和第四晶体管T4串联，因此可以减少漏电流，具有提高每一级GOA电路单元SR(n)稳定性的有益效果。
请参阅图5，图5是本发明第二实施例的GOA电路单元SR(n)的电路图。不同于图2的上拉维持模块400，图5的上拉维持模块500包含第九晶体管T9和第十晶体管T10。第九晶体管T9的栅极电性连接第二栅极开启信号Gas2，其漏极电性连接控制节点Q，其源极电性连接第二固定电压VGL。第十晶体管T10的栅极和漏极皆电性连接第二栅极开启信号Gas2，其源极电性连接输出端OUT。也就是说，当第二栅极开启信号Gas2为高电平时，第十晶体管T10是将高电平的第二栅极开启信号Gas2传送至输出端OUT以做为扫描信号G(n)。本实施例其余组件的连接与运作模式皆与图2-图4相同，在此不另赘述。
相较于现有技术，本实施例的GOA电路单元是由十个晶体管构成，使用的晶体管数量较少，具有便于窄边框显示器设计的有益效果。另外，GOA电路单元SR(n)的输入控制模块100包含由第一栅极开启信号Gas1控制的第二晶体管T2和第三晶体管T3。由于第一晶体管T1和第二晶体管串联T2，第三晶体管T3和第四晶体管T4串联，因此可以减少漏电流，具有提高每一级GOA电路单元SR(n)稳定性的有益效果。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一栅极开启信号以及第二栅极开启信号，在输出端输出扫描信号，每一级GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号、所述第三时钟信号和所述第一栅极开启信号，在控制节点输出控制信号，其包括：
    第一晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号；
    第二晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第一晶体管的源极，其源极电性连接所述控制节点；
    第三晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第二晶体管的源极；
    第四晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述后一级GOA电路单元输出的扫描信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平；以及
    上拉维持模块，电性连接所述输出端和所述第二栅极开启信号，用来当接收所述第二栅极开启信号时，在所述输出端输出的所述扫描信号保持高电平。
  2. 如权利要求1所述的栅极驱动电路，其中所述输出控制模块包含：
    第五晶体管，其栅极电性连接第一固定电压，其漏极电性连接所述控制节点；
    第六晶体管，其栅极电性连接所述第五晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第六晶体管的源极和栅极。
  3. 如权利要求2所述的栅极驱动电路，其中所述下拉模块包含：
    第七晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述输出端及所述第六晶体管的源极；
    第八晶体管，其栅极电性连接所述第四时钟信号，其漏极电性连接所述第七晶体管的源极，其源极电性连接第二固定电压。
  4. 如权利要求3所述的栅极驱动电路，其中所述上拉维持模块包含：
    第九晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述第一固定电压，其源极电性连接所述输出端。
  5. 如权利要求3所述的栅极驱动电路，其中所述上拉维持模块包含：
    第九晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极和漏极皆电性连接所述第二栅极开启信号，其源极电性连接所述输出端。
  6. 如权利要求1所述的栅极驱动电路，其中所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
  7. 如权利要求1所述的栅极驱动电路，其中所述第一固定电压为高电平，所述第二固定电压为低电平。
  8. 如权利要求1所述的栅极驱动电路，其中所述第一栅极开启信号和所述第二栅极开启信号互为反相。
  9. 一种显示器，其包含：
    源极驱动器，输出对应的数据信号至数个像素单元使其显示灰阶；以及
    栅极驱动电路，用來输出扫描信号使得数个晶体管开启，所述栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一栅极开启信号以及第二栅极开启信号，在输出端输出扫描信号，每一级GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号、所述第三时钟信号和所述第一栅极开启信号，在控制节点输出控制信号，其包括：
    第一晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号；
    第二晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第一晶体管的源极，其源极电性连接所述控制节点；
    第三晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述第二晶体管的源极；
    第四晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述后一级GOA电路单元输出的扫描信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平；以及
    上拉维持模块，电性连接所述输出端和所述第二栅极开启信号，用来当接收所述第二栅极开启信号时，在所述输出端输出的所述扫描信号保持高电平。
  10. 如权利要求9所述的显示器，其中所述输出控制模块包含：
    第五晶体管，其栅极电性连接第一固定电压，其漏极电性连接所述控制节点；
    第六晶体管，其栅极电性连接所述第五晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第六晶体管的源极和栅极。
  11. 如权利要求10所述的显示器，其中所述下拉模块包含：
    第七晶体管，其栅极电性连接所述第一栅极开启信号，其漏极电性连接所述输出端及所述第六晶体管的源极；
    第八晶体管，其栅极电性连接所述第四时钟信号，其漏极电性连接所述第七晶体管的源极，其源极电性连接第二固定电压。
  12. 如权利要求11所述的显示器，其中所述上拉维持模块包含：
    第九晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述第一固定电压，其源极电性连接所述输出端。
  13. 如权利要求11所述的显示器，其中所述上拉维持模块包含：
    第九晶体管，其栅极电性连接所述第二栅极开启信号，其漏极电性连接所述控制节点，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极和漏极皆电性连接所述第二栅极开启信号，其源极电性连接所述输出端。
  14. 如权利要求9所述的显示器，其中所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
  15. 如权利要求9所述的显示器，其中所述第一固定电压为高电平，所述第二固定电压为低电平。
  16. 如权利要求9所述的显示器，其中所述第一栅极开启信号和所述第二栅极开启信号互为反相。
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