WO2017197992A1 - 像素内存储单元、像素内数据存储方法以及像素阵列 - Google Patents

像素内存储单元、像素内数据存储方法以及像素阵列 Download PDF

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Publication number
WO2017197992A1
WO2017197992A1 PCT/CN2017/079288 CN2017079288W WO2017197992A1 WO 2017197992 A1 WO2017197992 A1 WO 2017197992A1 CN 2017079288 W CN2017079288 W CN 2017079288W WO 2017197992 A1 WO2017197992 A1 WO 2017197992A1
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terminal
node
transistor
data
level
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PCT/CN2017/079288
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English (en)
French (fr)
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谭文
陈佳
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/561,886 priority Critical patent/US10147367B2/en
Publication of WO2017197992A1 publication Critical patent/WO2017197992A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present invention relates to the storage of data voltages within pixels, and more particularly to an in-pixel memory cell, an in-pixel data storage method, and a pixel array.
  • the current MIP display technology is basically a CMOS LTPS process, and the in-pixel memory cells in the MIP display technology are all composed of CMOS circuits. This process is complicated and the yield is low, which greatly increases the cost of the MIP display technology product, and limits the cost. MIP display technology process compatibility and application range.
  • an in-pixel memory unit comprising: a data input circuit connected to a data line (DATA), a first control signal terminal (S1), a first data latch terminal (IN1), and a second a data latch terminal (IN2), and configured to read a data voltage (Vdata) on the data line to the first data latch terminal when a first control signal of the first control signal terminal is at its active level (IN1) and the second data latch terminal (IN2); a first data latch circuit connected to the first data latch terminal (IN1) and configured to hold the first data latch a level of the terminal (IN1); a second data latch circuit connected to the second data latch terminal (IN2) and configured to maintain a level of the second data latch terminal (IN2); a control circuit connected to the first data latch terminal (IN1) and the driver node (M), and configured to level the drive node (M) with the first data latch terminal (IN1) The level is reversed; and the driving circuit is connected to the driving node (M), the second data latch terminal (Vdata) on the data line to the first data
  • the first data latch circuit is further connected to the drive node (M) and the second control signal terminal (S2), and is configured to be at the second control signal terminal (S2)
  • the active level thereof causes the level of the first data latch terminal (IN1) to be opposite to the level of the driving node (M);
  • the second data latch circuit is further connected to the output terminal (OUT) And the second control signal terminal (S2), and is further configured to cause a level of the second data latch terminal (IN2) when the second control signal terminal (S2) is at its active level
  • the output (OUT) has the opposite level.
  • the first data latch circuit includes: a first holding transistor (T10) having a gate connected to the second control signal terminal (S2), and a first pole connecting the first data latch The terminal (IN1) and the second pole are connected to the first node (N); the first control transistor (T8) of the first node has a gate and a first pole connected to the first power voltage terminal, and a second pole connected to the first a node (N); and a second control transistor (T9) of the first node, whose gate is connected to the driving node (M), the first pole is connected to the first node (N), and the second pole is connected to the second Power supply voltage terminal.
  • T10 holding transistor having a gate connected to the second control signal terminal (S2), and a first pole connecting the first data latch
  • the terminal (IN1) and the second pole are connected to the first node (N)
  • the first control transistor (T8) of the first node has a gate and a first pole connected to the first power voltage terminal, and a second pole connected to the first a no
  • the second data latch circuit comprises: a second holding transistor (T5) having a gate connected to the second control signal terminal (S2) and a first pole connected to the second data latch The terminal (IN2) and the second pole are connected to the second node (Q); the first control transistor (T3) of the second node has a gate and a first pole connected to the third power voltage terminal, and a second pole connected to the a second node (Q); and a second control transistor (T4) of the second node, the gate of which is connected to the output terminal (OUT), the first pole is connected to the second node (Q), and the second pole is connected to the fourth Power supply voltage terminal.
  • T5 second holding transistor having a gate connected to the second control signal terminal (S2) and a first pole connected to the second data latch
  • the terminal (IN2) and the second pole are connected to the second node (Q)
  • the first control transistor (T3) of the second node has a gate and a first pole connected to the third power voltage terminal, and a second pole connected to the a second
  • the second data latch circuit is further connected to the first node (N), and the second data latch circuit comprises: a second holding transistor (T5) whose gate is connected a second control signal terminal (S2), a first pole connected to the second data latch terminal (IN2), and a second pole connected to the second node (Q); a first control transistor (T3) of the second node, a gate connected to the first node (N), a first pole connected to the third power voltage terminal, a second pole connected to the second node (Q), and a second control transistor (T4) of the second node A gate is connected to the output terminal (OUT), a first pole is connected to the second node (Q), and a second pole is connected to the fourth power voltage terminal.
  • the data input circuit comprises: a first input transistor (T11) having a gate connected to the first control signal terminal (S1), a first pole connecting the data line (DATA), And a second pole connected to the first data latch terminal (IN1); and a second input transistor (T12) having a gate connected to the first control signal terminal (S1) and a first pole connected to the data line ( DATA), and the second pole is connected to the second data latch terminal (IN2).
  • the driving control circuit includes: a first driving control transistor (T6) having a gate and a first pole connected to the first power voltage terminal, and a second pole connected to the driving node (M);
  • the second driving control transistor (T7) has a gate connected to the first data latch terminal (IN1), a first pole connected to the driving node (M), and a second pole connected to the second power voltage terminal.
  • the driving circuit comprises: a first driving transistor (T1) having a gate connected to the driving node (M), a first pole connected to the third power voltage terminal, and a second pole connecting the output And a second driving transistor (T2) having a gate connected to the second data latch terminal (IN2), a first pole connected to the output terminal (OUT), and a second pole connected to the fourth power source Voltage terminal.
  • each transistor is an NMOS transistor, an active level of the driving node (M) is a high level, and the first power supply voltage end is a first high power supply voltage terminal (VDD),
  • the second power voltage terminal is a first low power voltage terminal (VSS),
  • the third power voltage terminal is a second high power voltage terminal (VDH), and
  • the fourth power voltage terminal is a second low power voltage terminal (VDL) ).
  • each transistor is a PMOS transistor, an active level of the driving node (M) is a low level, and the first power supply voltage end is a first low power supply voltage terminal (VSS),
  • the second power voltage terminal is a first high power voltage terminal (VDD), the third power voltage terminal is a second low power voltage terminal (VDL), and the fourth power voltage terminal is a second high power voltage terminal (VDH) ).
  • an in-pixel data storage method comprising: in a first time period, a first control signal of the first control signal terminal (S1) is at an active level thereof, and the second control The second control signal of the signal terminal (S2) is at its inactive level, and the data input circuit reads the data voltage (Vdata) on the data line (DATA) to the first data latch terminal (IN1) And the second data latch terminal (IN2), the level of the driving node (M) is opposite to the level of the first data latch terminal (IN1), and the output terminal of the driving circuit ( The level of OUT) is opposite to the level of the data voltage; in the second period, the second control signal of the second control signal terminal (S2) is at its active level, and the first control signal terminal (S1) The first control signal is at its inactive level, and the data input circuit isolates the data line (DATA) from the first data latch (IN1) and the second data latch (IN2) The first data latch circuit remains a level of the first data latch terminal (IN1),
  • the data voltage is a high level
  • the first control signal is an active level
  • the second control signal is an inactive level
  • the first data lock The storage terminal (IN1) and the second data latch terminal (IN2) are at a high level
  • the drive node (M) is at a low level
  • the output terminal (OUT) of the drive circuit is at a low level
  • the first control signal is an inactive level
  • the second control signal is an active level
  • the first data latch circuit keeps the first data latch terminal (IN1) high Level
  • the second data latch circuit keeps the second data latch terminal (IN2) at a high level
  • the output terminal (OUT) of the driver circuit remains at a low level.
  • the data voltage is a low level
  • the first control signal is an active level
  • the second control signal is an inactive level
  • the first data lock The storage terminal (IN1) and the second data latch terminal (IN2) are at a low level
  • the drive node (M) is at a high level
  • an output terminal (OUT) of the drive circuit is at a high level
  • the first control signal is an inactive level
  • the second control signal is an active level
  • the first data latch circuit keeps the first data latch terminal (IN1) low Level
  • the second data latch circuit keeps the second data latch terminal (IN2) low
  • the output terminal (OUT) of the driver circuit remains at a high level.
  • the first control signal in the first period, is an active level, the second control signal is an inactive level, the data voltage is a high level, the first input transistor (T11) and the second input transistor (T12) are turned on such that the first data latch terminal (IN1) and the second data latch terminal (IN2) are at a high level, the first driving control The transistor (T6) and the second drive control transistor (T7) are turned on such that the drive node (M) is at a low level, the first drive transistor (T1) is turned off, and the second drive transistor (T2) Turning on, the output terminal (OUT) of the driving circuit is at a low level, the first holding transistor (T10) and the second holding transistor (T5) are turned off; in the second period, the first control signal The second control signal is an active level, the first input transistor (T11) and the second input transistor (T12) are turned off, and the first control transistor (T8) of the first node is an inactive level.
  • the first holding transistor (T10) is turned on to maintain the level of the first data latch terminal (IN1) at a high level
  • the first control transistor (T3) of the second node is turned on
  • the first The second control transistor (T4) of the two nodes is turned off such that the second node (Q) is at a high level
  • the second holding transistor (T5) is turned on such that the second data latch terminal (IN2) is powered
  • the level remains high, the first drive transistor (T1) remains off and the second drive transistor (T2) remains conductive such that the output (OUT) of the drive circuit remains low.
  • the first control signal in the first period, is an active level, the second control signal is an inactive level, the data voltage is a low level, the first input transistor (T11) and the second input transistor (T12) are turned on such that the first data latch terminal (IN1) and the second data latch terminal (IN2) are at a low level, the first driving control The transistor (T6) is turned on and the second driving control transistor (T7) is turned off such that the driving node (M) is at a high level, the first driving transistor (T1) is turned on and the second driving transistor ( T2) cutoff causes the output terminal (OUT) of the driving circuit to be at a high level, the first holding transistor (T10) and the second holding transistor (T5) are turned off; in the second period, the first control The signal is an inactive level, the second control signal is an active level, the first input transistor (T11) and the second input transistor (T12) are turned off, and the first control transistor of the first node (T8) And the second control transistor (T9) of the first
  • the first control signal in the first period, is an active level, the second control signal is an inactive level, the data voltage is a high level, the first input transistor (T11) and the second input transistor (T12) are turned on such that the first data latch terminal (IN1) and the second data latch terminal (IN2) are at a high level, the first driving control The transistor (T6) is turned on and the second driving control transistor (T7) is turned off such that the driving node (M) is at a low level, the first driving transistor (T1) is turned on, and the second driving transistor ( T2) cutoff causes the output terminal (OUT) of the driving circuit to be low level, the first holding transistor (T10) and The second holding transistor (T5) is turned off; in the second period, the first control signal is an inactive level, the second control signal is an active level, the first input transistor (T11) and the The second input transistor (T12) is turned off, the first control transistor (T8) of the first node is turned on, and the second control transistor (T9) of the
  • the first control signal in the first period, is an active level, the second control signal is an inactive level, the data voltage is a low level, the first input transistor (T11) and the second input transistor (T12) are turned on such that the first data latch terminal (IN1) and the second data latch terminal (IN2) are at a low level, the first driving control The transistor (T6) and the second driving control transistor (T7) are turned on such that the driving node (M) is at a high level, the first driving transistor (T1) is turned off, and the second driving transistor (T2) Turning on, the output terminal (OUT) of the driving circuit is at a high level, the first holding transistor (T10) and the second holding transistor (T5) are turned off; in the second period, the first control signal The second control signal is an active level, the first input transistor (T11) and the second input transistor (T12) are turned off, and the first control transistor (T8) of the first node is an inactive level.
  • the first holding transistor (T10) is turned on such that the level of the first data latch terminal (IN1) is kept low
  • the first control transistor (T3) of the second node is turned on and the second
  • the second control transistor (T4) of the node is turned off such that the second node (Q) is at a low level
  • the second holding transistor (T5) is turned on such that a level of the second data latch terminal (IN2) Keeping low, the first drive transistor (T1) remains off and the second drive transistor (T2) remains conductive such that the output (OUT) of the drive circuit remains high.
  • a pixel array each of which includes an in-pixel memory cell and a liquid crystal display unit according to an embodiment of the present invention.
  • 1 is a schematic diagram of a MIP pixel circuit
  • FIG. 2 is a circuit schematic diagram of an in-pixel memory cell MIP composed of a CMOS circuit
  • FIG. 3A is a schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the present invention.
  • FIG. 3B is another schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the present invention.
  • FIG. 3C is still another schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pixel array in accordance with an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a method for storing data in an pixel according to an embodiment of the present invention
  • FIG. 6A is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3B according to the first embodiment of the present invention
  • 6B is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3C according to the first embodiment of the present invention
  • FIG. 7 is a signal timing diagram of an in-pixel memory cell MIP according to an embodiment of the present invention.
  • FIG. 8A and 8B are the in-pixel memory cells shown in FIG. 6B according to the first embodiment of the present invention. Schematic diagram of the circuit operation of the MIP in the case of storing black state data;
  • FIG. 9A and FIG. 9B are schematic diagrams showing the circuit operation of the in-pixel memory cell MIP shown in FIG. 6B in the case of storing white state data according to the first embodiment of the present invention
  • FIG. 10A is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3B according to a second embodiment of the present invention.
  • FIG. 10B is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3C according to a second embodiment of the present invention.
  • FIG. 11A and FIG. 11B are circuit operation diagrams of the in-pixel memory cell MIP shown in FIG. 10B in the case of storing black state data according to a second embodiment of the present invention
  • 12A and 12B are diagrams showing the circuit operation of the in-pixel memory cell MIP shown in FIG. 10B in the case of storing white state data according to the second embodiment of the present invention.
  • FIG. 1 shows a schematic diagram of a conventional MIP pixel circuit.
  • the MIP pixel circuit includes a memory cell, a switching transistor T, and a liquid crystal display cell LC, and the memory cell is constituted by a latch.
  • the switching transistor T When the switching transistor T is turned on, the data voltage Vdata is input to the memory cell, and when the switching transistor T is turned off, the data voltage Vdata is held by the memory cell, specifically, the one end (ie, P point) applied to the liquid crystal display unit LC is maintained. The voltage does not change.
  • FIG. 2 shows a circuit schematic of an in-pixel memory cell MIP composed of a CMOS circuit.
  • the MIP circuit includes a CMOS transmission gate M1, a CMOS transmission gate M2, a CMOS transmission gate M3, a CMOS transmission gate M4, an inverter INV1, and an inverter INV2.
  • the MIP circuit is a 1-bit memory cell capable of storing black and white voltages, whereby the MIP pixels can be displayed in black and white.
  • the control signal S1 is at a low level and the control signal /S1
  • the CMOS transmission gate M1 is turned on and the CMOS transmission gate M2 is turned off.
  • the A point level is also high level and the B point level is low level, so that the CMOS transmission gate M3 is turned on and the CMOS transmission is performed.
  • the gate M4 is turned off so that the power supply voltage VDH is output to the output terminal C.
  • the CMOS transmission gate M1 is turned off and the CMOS transmission gate M2 is turned on, and the gate M2 is transmitted by the inverter INV1, the inverter INV2, and the CMOS.
  • the hold circuit is constructed, the level A is maintained at a high level, and the supply voltage VDH is kept output to the output terminal C.
  • the CMOS transmission gate M1 is turned on and the CMOS transmission gate M2 is turned off.
  • the level is also low and the level B is at a high level, so that the CMOS transmission gate M3 is turned off and the CMOS transmission gate M4 is turned on, so that the power supply voltage VDL is output to the output terminal C.
  • the CMOS transmission gate M1 is turned off and the CMOS transmission gate M2 is turned on, and the gate M2 is transmitted by the inverter INV1, the inverter INV2, and the CMOS.
  • the hold circuit is constructed, the level of point A is kept low, and the supply voltage VDL is kept output to the output terminal C.
  • the MIP pixel displays a black state
  • the MIP pixel displays a white state
  • the in-pixel memory cell MIP shown in FIG. 2 is composed of a CMOS circuit, which is based on a CMOS LTPS process, and has a complicated process and a low yield.
  • FIG. 3A is a schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the present invention.
  • the in-pixel memory unit includes a data input circuit 310, a first data latch circuit 320, a second data latch circuit 330, a drive control circuit 340, and a drive circuit 350.
  • the data input circuit 310 is connected to the data line DATA, the first control signal terminal S1, the first data latch terminal IN1, and the second data latch terminal IN2, and is configured as a first control at the first control signal terminal S1.
  • the data voltage Vdata on the data line DATA is read onto the first data latch terminal IN1 and the second data latch terminal IN2 when the signal is at its active level.
  • the first data latch circuit 320 is coupled to the first data latch terminal IN1 and is configured to maintain a level of the first data latch terminal IN1.
  • the second data latch circuit 330 is coupled to the second data latch terminal IN2 and is configured to maintain the level of the second data latch terminal IN2.
  • the drive control circuit 340 is connected to the first data latch terminal IN1 and the drive node M, and is configured to make the level of the drive node M opposite to the level of the first data latch terminal IN1.
  • the driving circuit 350 is connected to the driving node M, the second data latch terminal IN2, and the output terminal OUT, and is configured to set a third power voltage of the third power voltage terminal when the driving node M is at its active level. Output to the output terminal OUT and output a fourth power supply voltage of the fourth power supply voltage terminal to the output terminal OUT when the second data latch terminal IN2 is at its active level.
  • FIG. 3B is another schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the present invention.
  • the first data latch circuit 320 is further connected to the drive node M and the second control signal terminal S2, and is configured to be in the second control.
  • the signal terminal S2 is at its active level
  • the level of the first data latch terminal IN1 is opposite to the level of the drive node M.
  • the second data latch circuit 330 is further connected to the output terminal OUT and the second control signal terminal S2, and is further configured to cause the second control signal terminal S2 to be at its active level.
  • the level of the second data latch terminal IN2 is opposite to the level of the output terminal OUT.
  • FIG. 3C is still another schematic block diagram of an in-pixel memory unit MIP according to an embodiment of the invention.
  • the first data latch circuit 320 is further connected to the first node N, and is configured to make the level of the first node N and the driving node The level of M is reversed.
  • the second data latch circuit 330 is further connected to the first node N, and is further configured to be under the control of the first node N when the second control signal terminal S2 is at its active level The level of the second data latch terminal IN2 is made opposite to the level of the output terminal OUT.
  • FIG. 4 is a schematic diagram of a pixel array, each of which includes an in-pixel memory cell MIP and a liquid crystal display unit LC, in accordance with an embodiment of the present invention, in accordance with an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a method for storing data in an pixel according to an embodiment of the present invention.
  • the first control signal of the first control signal terminal S1 is at its active level
  • the second control signal of the second control signal terminal S2 is at its inactive level
  • the data input circuit 310 Reading the data voltage Vdata on the data line DATA to the first data latch terminal IN1 and the second data latch terminal IN2
  • the drive control circuit 340 causing the level of the drive node M Contrary to the level of the first data latch terminal IN1
  • the drive circuit 350 The level of the output terminal OUT is opposite to the level of the data voltage Vdata.
  • the second control signal of the second control signal terminal S2 is at its active level
  • the first control signal of the first control signal terminal S1 is at its inactive level
  • the data input circuit 310 The data line DATA is isolated from the first data latch terminal IN1 and the second data latch terminal IN2, and the first data latch circuit 310 maintains the level of the first data latch terminal IN1.
  • the second data latch circuit 320 maintains the level of the second data latch terminal IN2 such that the level of the output terminal OUT of the driver circuit 350 remains unchanged.
  • input data can be divided into black state data and white state data, for example, black state data is a high level, and white state data is a low level.
  • the data voltage Vdata is at a high level
  • the first control signal is an active level
  • the second control signal is an inactive level
  • the first data latch terminal IN1 and The second data latch terminal IN2 is at a high level
  • the driving node M is at a low level
  • the output terminal OUT of the driving circuit is at a low level
  • the first control signal Is an inactive level
  • the second control signal is an active level
  • the first data latch circuit keeps the first data latch terminal IN1 at a high level
  • the second data latch circuit maintains the The second data latch terminal IN2 is at a high level
  • the output terminal OUT of the drive circuit is maintained at a low level.
  • the data voltage Vdata is at a low level
  • the first control signal is an active level
  • the second control signal is an inactive level
  • the first data latch terminal IN1 and The second data latch terminal IN2 is at a low level
  • the drive node M is at a high level
  • the output terminal OUT of the drive circuit is at a high level
  • the first control signal is in a white state data hold period. Is an inactive level
  • the second control signal is an active level
  • the first data latch circuit keeps the first data latch terminal IN1 at a low level
  • the second data latch circuit maintains the The second data latch terminal IN2 is at a low level
  • the output terminal OUT of the drive circuit is maintained at a high level.
  • the in-pixel memory cell MIP is composed of a single type of MOS transistor, for example, only composed of an NMOS transistor, or only a PMOS transistor.
  • the in-pixel memory cell MIP is constituted by an NMOS transistor, and according to the second embodiment of the present invention, the in-pixel memory cell MIP is constituted by a PMOS transistor.
  • FIG. 6A is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3B according to the first embodiment of the present invention.
  • the active levels of the first control signal and the second control signal are at a high level, and the active level of the drive node M is also at a high level.
  • the data input circuit includes a first input transistor T11 and a second input transistor T12.
  • the gate of the first input transistor T11 is connected to the first control signal terminal S1, the first pole is connected to the data line DATA, and the second pole is connected to the first data latch terminal IN1.
  • the gate of the second input transistor T12 is connected to the first control signal terminal S1, the first electrode is connected to the data line DATA, and the second electrode is connected to the second data latch terminal IN2.
  • the first data latch circuit 220 includes a first holding transistor T10, a first control transistor T8 of the first node N, and a second control transistor T9 of the first node.
  • the gate of the first holding transistor T10 is connected to the second control signal terminal S2, the first pole is connected to the first data latch terminal IN1, and the second pole is connected to the first node N.
  • the gate of the first control transistor T8 of the first node N and the first pole are connected to the first power voltage terminal, and the second pole is connected to the first node N.
  • the gate of the second control transistor T9 of the first node N is connected to the driving node M, the first pole is connected to the first node N, and the second pole is connected to the second power voltage terminal.
  • the second data latch circuit 330 includes a second holding transistor T5, a first control transistor T3 of the second node Q, and a second control transistor T4 of the second node Q.
  • the gate of the second holding transistor T5 is connected to the second control signal terminal S2, the first pole is connected to the second data latch terminal IN2, and the second pole is connected to the second node Q.
  • the gate of the first control transistor T3 of the second node Q and the first pole are connected to the third power voltage terminal, and the second pole is connected to the second node Q.
  • the gate of the second control transistor T4 of the second node Q is connected to the output terminal OUT, the first pole is connected to the second node Q, and the second pole is connected to the fourth power voltage terminal.
  • the drive control circuit 340 includes a first drive control transistor T6 and a second drive control transistor T7.
  • the gate of the first driving control transistor T6 and the first pole are connected to the first power voltage terminal, and the second pole is connected to the driving node M.
  • the gate of the second driving control transistor T7 is connected to the first data latch terminal IN1, the first pole is connected to the driving node M, and the second pole is connected to the second power voltage terminal.
  • the driving circuit 350 includes a first driving transistor T1 and a second driving transistor T2.
  • the gate of the first driving transistor T1 is connected to the driving node M, the first pole is connected to the third power voltage terminal, and the second pole is connected to the output terminal OUT.
  • the gate of the second driving transistor T2 is connected to the second data latch terminal IN2, the first pole is connected to the output terminal OUT, and the second pole is connected to the fourth power voltage terminal.
  • each transistor is an NMOS transistor, an active level of the driving node M is a high level, and the first power supply voltage terminal is a first high power supply voltage terminal VDD, the second The power supply voltage terminal is a first low power supply voltage terminal VSS, the third power supply voltage terminal is a second high power supply voltage terminal VDH, and the fourth power supply voltage terminal is a second low power supply voltage terminal VDL.
  • the first power supply voltage provided by the first high power supply voltage terminal VDD and the third power supply voltage provided by the second high power supply voltage terminal VDH may be the same or different, and the second power supply provided by the first low power supply voltage terminal VSS
  • the voltage and the fourth supply voltage provided by the second low supply voltage terminal VDL may be the same or different.
  • FIG. 6B is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3C according to the first embodiment of the present invention.
  • the circuit schematic shown in FIG. 6B differs from the circuit schematic shown in FIG. 6A only in the manner in which the first control transistor T3 of the second node Q in the second data latch circuit 330 is connected. Description of the same circuit portion in FIG. 6B as that in FIG. 6A is omitted here.
  • the second data latch circuit is also connected to the first node (N). Specifically, the gate of the first control transistor T3 of the second node Q is connected to the first node N, the first pole is connected to the third power voltage terminal, and the second pole is connected to the second node Q.
  • FIG. 7 is a signal timing diagram of an in-pixel memory cell MIP according to an embodiment of the present invention
  • FIGS. 8A and 8B are diagrams showing the in-pixel memory cell MIP shown in FIG. 6B in the case of storing black state data according to the first embodiment of the present invention
  • FIG. 9A and FIG. 9B are circuit operation schematic diagrams of the in-pixel memory cell MIP shown in FIG. 6B in the case of storing white state data according to the first embodiment of the present invention.
  • the first control signal S1 is an active level (high level)
  • the second control signal S2 is an inactive level (low level).
  • the data voltage Vdata is at a high level, and the first input transistor T11 and the second input transistor T12 are turned on.
  • the first data latch terminal IN1 and the second data latch terminal IN2 are at a high level, and the first driving control transistor T6 and the second driving control transistor T7 are turned on such that the driving node M Low level, the first driving transistor T1 is turned off and the second driving transistor T2 is turned on such that the output terminal OUT of the driving circuit is at a low level, the first holding transistor T10 and the second holding transistor T5
  • the second control transistor T9 of the first node N is turned off, and the second control transistor T4 of the second node Q is turned off.
  • the first control signal is an inactive level (low level), and the second control signal is an active level (high level)
  • the first The input transistor T11 and the second input transistor T12 are turned off, the first control transistor T8 of the first node N is turned on, and the second control transistor T9 of the first node N is turned off such that the first node N is high Level
  • the first holding transistor T10 is turned on to maintain the level of the first data latch terminal IN1 at a high level
  • the first control transistor T3 of the second node Q is turned on and the second The second control transistor T4 of the node Q is turned off such that the second node Q is at a high level
  • the second holding transistor T5 is turned on to maintain a level of the second data latch terminal IN2 at a high level.
  • the first driving transistor T1 is kept off and the second driving transistor T2 is kept turned on so that the output terminal OUT of the driving circuit is kept at a low level.
  • the first driving control transistor T6 and the second driving control transistor T7 by appropriately setting the channel width and length of the first driving control transistor T6 and the second driving control transistor T7, the first driving control transistor T6 and the When the second driving control transistor T7 is turned on, the on-state impedance of the first driving control transistor T6 is much larger than the on-state impedance of the second driving control transistor T7, so that the level of the driving node M is the same as The level of the second power supply voltage terminal VSS is the same.
  • the first control signal is an active level (high level)
  • the second control signal is an inactive level (low level)
  • the data The voltage Vdata is at a low level
  • the first input transistor T11 and the second input transistor T12 are turned on such that the first data latch terminal IN1 and the second data latch terminal IN2 are at a low level.
  • the first driving control transistor T6 is turned on and the second driving control transistor T7 is turned off such that the driving node M is at a high level, the first driving transistor T1 is turned on, and the second driving transistor T2 is turned off so that The output terminal OUT of the driving circuit is at a high level, the first holding transistor T10 and the second holding transistor T5 are turned off, the second control transistor T9 of the first node N is turned on, and the second node Q is The second control transistor T4 is turned on.
  • the first control signal is an inactive level (low level)
  • the second control signal is an active level (high level)
  • the first The input transistor T11 and the second input transistor T12 are turned off, and the first control transistor T8 of the first node N and the second control transistor T9 of the first node N are turned on to make the first node N low.
  • the first holding transistor T10 is turned on such that the level of the first data latch terminal IN1 is kept low
  • the first control transistor T3 of the second node Q is turned off
  • the second node Q The second control transistor T4 is turned on such that the second node Q is at a low level
  • the second holding transistor T5 is turned on to maintain a level of the second data latch terminal IN1 at a low level.
  • the first driving transistor T1 is kept turned on and the second driving transistor T2 is kept off so that the output terminal OUT of the driving circuit is maintained at a high level.
  • the first embodiment of the present invention by appropriately setting the channel width and length of the first control transistor T8 of the first node N and the second control transistor T9 of the first node N, When the first control transistor T8 of a node N and the second control transistor T9 of the first node N are both turned on, the on-state impedance of the first control transistor T8 of the first node N is much larger than the first node N.
  • the second control transistor T9 has an on-state impedance such that the level of the first node N is the same as the level of the second power supply voltage terminal VSS.
  • the first control transistor T3 of the second node Q and the second control transistor of the second node Q in the white state data writing and holding period T4 is all turned on.
  • the first control transistor at the second node Q can be made by appropriately setting the channel width and length of the first control transistor T3 of the second node Q and the second control transistor T4 of the second node Q
  • the on-state impedance of the first control transistor T3 of the second node Q is much larger than the pass of the second control transistor T4 of the second node Q.
  • the state impedance is such that the level of the second node Q is the same as the level of the fourth power supply voltage terminal VDL.
  • the black state data writing period and the black state data holding period are two consecutive periods (ie, the first period and the second period), and constitute a complete a black state data write and hold operation;
  • the white state data write period and the white state data hold period are two consecutive periods (ie, a first period and a second period), and constitute a complete white state Data write and hold operations.
  • the white state data writing and holding period is shown in FIG. 7 after the black state data writing and holding period, it should be understood that the present invention is not limited thereto, and several black states may exist continuously. During the data write and hold period, there may be several white state data write and hold periods continuously, and the white state data write and hold period may also occur before the black state data write and hold period.
  • the data voltage of the black state data is Vdd
  • the data voltage of the white state data is Vss
  • the first power voltage of the first power voltage terminal VDD is Vdd
  • the second power source of the second power voltage terminal VSS The voltage is Vss.
  • the actual operating high voltage and the operating low voltage of the driving node M are not equal to Vdd and Vss and are equal to VMcc and VMee, respectively.
  • VMcc Vdd-Vth6
  • VMee (R7/(R6+R7)) ⁇ (Vdd ⁇ Vss)+Vss
  • R7 represents the on-resistance of the transistor T7
  • R6 represents the on-resistance of the transistor T6
  • Vth6 represents the transistor T6. Threshold voltage.
  • VNcc Vdd-Vth8
  • VMee (R9(R8+R9)) ⁇ (Vdd ⁇ Vss)+Vss
  • R9 represents the on-resistance of the transistor T9
  • R8 represents the on-resistance of the transistor T8
  • Vth8 represents the transistor T8. Threshold voltage.
  • the third power supply voltage of the third power supply voltage terminal VDH is Vdh
  • the fourth power supply voltage of the fourth power supply voltage terminal VDL is Vdl.
  • VMcc and VNcc are collectively referred to as Vcc
  • VMee and VNee are collectively referred to as Vee.
  • Vcc of the driving node M and the third power supply voltage Vdh satisfy the following relationship, that is, when Vcc-Vdh>Vth1, the transistor T1 is in a saturated conduction state, and Vth1 is The threshold voltage of transistor T1.
  • Vth3 is the threshold voltage of the transistor T3. That is, it is necessary to satisfy (R7/(R6+R7))*(Vdd-Vss)+Vss-Vdl ⁇ Vth3.
  • FIG. 10A is a circuit schematic diagram of the in-pixel memory cell MIP shown in FIG. 3B according to a second embodiment of the present invention.
  • the active levels of the first control signal and the second control signal are low level, and the active level of the drive node M is also low.
  • the data input circuit 310 includes a first input transistor T11 and a second input transistor T12.
  • the gate of the first input transistor T11 is connected to the first control signal terminal S1, the first pole is connected to the data line DATA, and the second pole is connected to the first data latch terminal IN1.
  • the gate of the second input transistor T12 is connected to the first control signal terminal S1, the first electrode is connected to the data line DATA, and the second electrode is connected to the second data latch terminal IN2.
  • the first data latch circuit 320 includes a first holding transistor T10, a first control transistor T8 of the first node N, and a second control transistor T9 of the first node N.
  • the gate of the first holding transistor T10 is connected to the second control signal terminal S2, the first pole is connected to the first data latch terminal IN1, and the second pole is connected to the first node N.
  • the gate of the first control transistor T8 of the first node N and the first pole are connected to the first power voltage terminal, and the second pole is connected to the first node N.
  • the gate of the second control transistor T9 of the first node N is connected to the driving node M, the first pole is connected to the first node N, and the second pole is connected to the second power voltage terminal.
  • the second data latch circuit 330 includes a second holding transistor T5, a first control transistor T3 of the second node Q, and a second control transistor T4 of the second node Q.
  • the gate of the second holding transistor T5 is connected to the second control signal terminal S2, the first pole is connected to the second data latch terminal IN2, and the second pole is connected to the second node Q.
  • the gate of the first control transistor T3 of the second node Q and the first pole are connected to the third power voltage terminal, and the second pole is connected to the second node Q.
  • the gate of the second control transistor T4 of the second node Q is connected to the output terminal OUT, one pole is connected to the second node Q, and the second pole is connected to the fourth power voltage terminal.
  • the drive control circuit 340 includes a first drive control transistor T6 and a second drive control transistor T7.
  • the gate of the first driving control transistor T6 and the first pole are connected to the first power voltage terminal, and the second pole is connected to the driving node M.
  • the gate of the second driving control transistor T7 is connected to the first data latch terminal IN1, the first pole is connected to the driving node M, and the second pole is connected to the second power voltage terminal.
  • the driving circuit includes a first driving transistor T1 and a second driving transistor T2.
  • the gate of the first driving transistor T1 is connected to the driving node M, the first pole is connected to the third power voltage terminal, and the second pole is connected to the output terminal OUT.
  • the gate of the second driving transistor T2 is connected to the second data latch terminal IN2, the first pole is connected to the output terminal OUT, and the second pole is connected to the fourth power voltage terminal.
  • each transistor is a PMOS transistor, an active level of the driving node M is a low level, and the first power supply voltage terminal is a first low power supply voltage terminal VSS, the second The power supply voltage terminal is a first high power supply voltage terminal VDD, the third power supply voltage terminal is a second low power supply voltage terminal VDL, and the fourth power supply voltage terminal is a second high power supply voltage terminal VDH.
  • the first power supply voltage provided by the first low power supply voltage terminal VSS and the third power supply voltage provided by the second low power supply voltage terminal VDL may be the same or different, and the second power supply provided by the first high power supply voltage terminal VDD The voltage and the fourth supply voltage provided by the second high supply voltage terminal VDH may be the same or different.
  • Figure 10B is a circuit schematic diagram of the in-pixel memory cell MIP shown in Figure 3C in accordance with a second embodiment of the present invention.
  • the circuit schematic shown in FIG. 10B differs from the circuit schematic shown in FIG. 10A only in the manner in which the first control transistor T3 of the second node Q in the second data latch circuit 330 is connected. Description of the same circuit portion in FIG. 10B as that in FIG. 10A is omitted here.
  • the second data latch circuit is further connected to the first node N.
  • the gate of the first control transistor T3 of the second node Q is connected to the first node N
  • the first pole is connected to the third power voltage terminal
  • the second pole is connected to the second node Q.
  • FIGS. 10B, 11A-11B, and 12A-12B Next, a data storage operation of an in-pixel memory cell in accordance with a second embodiment of the present invention will be described with reference to FIGS. 10B, 11A-11B, and 12A-12B.
  • the first control signal is an active level (low level)
  • the second control signal is an inactive level (high level)
  • the first input transistor T11 and the second input transistor T12 are turned on such that the first data latch terminal IN1 and the second data latch terminal IN2 are at a high level
  • the first Drive control transistor T6 is turned on and the second driving control transistor T7 is turned off such that the driving node M is at a low level
  • the first control transistor T8 and the second control transistor T9 of the first node N cause the first node N to be high Level
  • the first driving transistor T1 is turned on and the second driving transistor T2 is turned off such that the output terminal OUT of the driving circuit is at a low level
  • the first holding transistor T10 and the second holding transistor T5 are turned off.
  • the first control signal is an inactive level (high level)
  • the second control signal is an active level (low level)
  • the first input The transistor T11 and the second input transistor T12 are turned off, the first control transistor T8 of the first node N is turned on, and the second control transistor T9 of the first node N is turned on to make the first node N high.
  • the first holding transistor T10 is turned on to maintain the level of the first data latch terminal IN1 at a high level
  • the first control transistor T3 of the second node Q is turned off
  • the second control transistor T4 of Q is turned on such that the second node Q is at a high level
  • the second holding transistor T5 is turned on to maintain a level of the second data latch terminal IN2 at a high level.
  • the first driving transistor T1 is kept turned on and the second driving transistor T2 is kept off so that the output terminal OUT of the driving circuit is kept at a low level.
  • the second embodiment of the present invention by appropriately setting the channel width and length of the first control transistor T8 of the first node N and the second control transistor T9 of the first node N, When the first control transistor T8 of a node N and the second control transistor T9 of the first node N are turned on, the on-state impedance of the first control transistor T8 of the first node N is much larger than that of the first node N.
  • the second control transistor T9 has an on-state impedance such that the level of the drive node M is the same as the level of the second supply voltage terminal VDD.
  • the first control signal is an active level (low level), and the second control signal is an inactive level (high level), the data voltage Is low level, the first input transistor T11 and the second input transistor T12 are turned on such that the first data latch terminal IN1 and the second data latch terminal IN2 are at a low level, the first A driving control transistor T6 and the second driving control transistor T7 are turned on such that the driving node M is at a high level, the second control transistor T9 of the first node N is turned off, the first driving transistor T1 is turned off and The second driving transistor T2 is turned on such that the output terminal OUT of the driving circuit is at a high level, the second control transistor T4 of the second node Q is turned off, and the first holding transistor T10 and the second holding transistor T5 are turned off. cutoff.
  • the first control signal is an inactive level (high level), and the second control signal is an active level (low level)
  • the first input The transistor T11 and the second input transistor T12 are turned off, the first control transistor T8 of the first node is turned on, and the second control transistor T9 of the first node is turned off such that the first node N is at a low level
  • the first holding transistor T10 is turned on to keep the level of the first data latch terminal IN1 low
  • the first control transistor T3 of the second node is turned on
  • the second node is second
  • the control transistor T4 is turned off such that the second node Q is at a low level
  • the second holding transistor T5 is turned on such that a level of the second data latch terminal IN2 is maintained at a low level
  • the first driving transistor T1 remains off and the second drive transistor T2 remains conductive such that the output terminal OUT of the drive circuit remains at a high level.
  • the second embodiment of the present invention by appropriately setting the channel width and length of the first driving control transistor T6 and the second driving control transistor T7, the first driving control transistor T6 and the When the second driving control transistor T7 is turned on, the on-state impedance of the first driving control transistor T6 is much larger than the on-state impedance of the second driving control transistor T7, so that the level of the driving node M is the same as The level of the second power supply voltage terminal VDD is the same.
  • the first control transistor T3 of the second node Q and the second control transistor of the second node Q in the black state data writing and holding period T4 is all turned on.
  • the first control transistor at the second node Q can be made by appropriately setting the channel width and length of the first control transistor T3 of the second node Q and the second control transistor T4 of the second node Q
  • the on-state impedance of the first control transistor T3 of the second node Q is much larger than the pass of the second control transistor T4 of the second node Q.
  • the state impedance is such that the level of the second node Q is the same as the level of the fourth power supply voltage terminal VDH.
  • the data voltage of the black state data is Vdd
  • the data voltage of the white state data is Vss
  • the second power voltage of the second power supply voltage terminal VDD is Vdd
  • the first power supply of the first power supply voltage terminal VSS The voltage is Vss.
  • the actual operating high voltage and the operating low voltage of the driving node M are not equal to Vdd and Vss and are equal to VMcc and VMee, respectively.
  • VMcc (R6/(R6+R7)) ⁇ (Vdd ⁇ Vss)+Vss
  • VMee Vss+Vth6
  • R7 represents the on-resistance of the transistor T7
  • R6 represents the on-resistance of the transistor T6
  • Vth6 represents the transistor T6. Threshold voltage, Vth6>0.
  • VNcc (R8/(R8+R9)) ⁇ (Vdd ⁇ Vss)+Vss
  • VMee Vss+Vth8
  • R9 represents the on-resistance of the transistor T9
  • R8 represents the on-resistance of the transistor T8
  • Vth8 represents the transistor T8. Threshold voltage, Vth8>0.
  • the third power supply voltage of the third power supply voltage terminal VDL is Vd1
  • the fourth power supply voltage of the fourth power supply voltage terminal VDH is Vdh.
  • VMcc and VNcc are collectively referred to as Vcc
  • VMee and VNee are collectively referred to as Vee.
  • Vth1 Is the threshold voltage of transistor T1.
  • the threshold voltage of the transistor T1 is the same as the threshold voltage of the transistor T6, by making Vdl>Vss+2Vth1, it can be ensured that the transistor T1 according to the second embodiment of the present invention is in a saturated conduction state in the black state data writing and display phase, thereby The output terminal OUT is caused to output a third power supply voltage Vdl.
  • Vth3 is the threshold voltage of transistor T3. That is, it is necessary to satisfy (R8/(R8+R9))*(Vdd-Vss)+Vss-Vdh>-Vth3.
  • a pixel array each of which includes an in-pixel memory unit and a liquid crystal display unit according to the first embodiment of the present invention.
  • a pixel array each of which includes an in-pixel memory unit and a liquid crystal display unit according to a second embodiment of the present invention.
  • the MOS LTPS process can be used to produce an in-pixel memory cell, which is relatively simple and has a high yield, thereby effectively reducing the production cost of the MIP pixel.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素内存储单元及数据存储方法、以及像素阵列。所述像素内存储单元包括：数据输入电路，其被配置为在第一控制信号端的第一控制信号处于其有效电平时将数据线（DATA）上的数据电压（Vdata）读取到第一数据锁存端（IN1）和第二数据锁存端（IN2）上；第一数据锁存电路（320），其被配置为保持所述第一数据锁存端（IN1）的电平；第二数据锁存电路（330），其被配置为保持所述第二数据锁存端（IN2）的电平；驱动控制电路（340），其被配置为使驱动节点（M）的电平与所述第一数据锁存端（IN1）的电平相反；以及驱动电路（350），其被配置为在所述驱动节点（M）处于其有效电平时将第三电源电压端的第三电源电压输出至输出端（OUT）并且在所述第二数据锁存端（IN2）处于其有效电平时将第四电源电压端的第四电源电压输出至所述输出端（OUT）。

Description

像素内存储单元、像素内数据存储方法以及像素阵列 技术领域
本发明涉及像素内数据电压的存储，并且更具体地涉及一种像素内存储单元、像素内数据存储方法以及像素阵列。
背景技术
目前，随着智能穿戴、移动应用等技术的发展，对超低功耗液晶LCD显示技术的发展提出了更高要求。像素内存储单元(Memory in Pixel，MIP)显示技术作为一种新型低功耗LCD显示技术，由于具有无需改变LCD工艺、无需新型材料开发、结构简单、成本低等特点，具有广阔的发展前景。
然而，目前的MIP显示技术基本为CMOS LTPS工艺，MIP显示技术中的像素内存储单元均由CMOS电路构成，这种工艺复杂且良率较低，大大增加了MIP显示技术产品成本，并且限制了MIP显示技术的工艺兼容和应用范围。
因此，需要一种基于简单工艺的像素内存储单元及数据存储方法。
发明内容
根据本发明一方面，提供了一种像素内存储单元，包括：数据输入电路，连接到数据线(DATA)、第一控制信号端(S1)、第一数据锁存端(IN1)以及第二数据锁存端(IN2)，并且被配置为在第一控制信号端的第一控制信号处于其有效电平时将所述数据线上的数据电压(Vdata)读取到所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)上；第一数据锁存电路，连接到所述第一数据锁存端(IN1)，并且被配置为保持所述第一数据锁存端(IN1)的电平；第二数据锁存电路，连接到所述第二数据锁存端(IN2)，并且被配置为保持所述第二数据锁存端(IN2)的电平；驱动控制电路，连接到所述第一数据锁存端(IN1)以及驱动节点(M)，并且被配置为使所述驱动节点(M)的电平与所述第一数据锁存端(IN1)的电平相反；以及驱动电路，连接到驱动节点(M)、所述第二数据锁存端(IN2)以及输出端(OUT)，并且被配置为在所述驱动节点(M)处于其有效电平时将第三电源电压端的第三电源电 压输出至所述输出端(OUT)并且在所述第二数据锁存端(IN2)处于其有效电平时将第四电源电压端的第四电源电压输出至所述输出端(OUT)。
根据本发明实施例，所述第一数据锁存电路还连接到所述驱动节点(M)和第二控制信号端(S2)，并且被配置为在所述第二控制信号端(S2)处于其有效电平时使所述第一数据锁存端(IN1)的电平与所述驱动节点(M)的电平相反；以及所述第二数据锁存电路还连接到所述输出端(OUT)以及所述第二控制信号端(S2)，并且还被配置为在所述第二控制信号端(S2)处于其有效电平时使所述第二数据锁存端(IN2)的电平与所述输出端(OUT)的电平相反。
根据本发明实施例，所述第一数据锁存电路包括：第一保持晶体管(T10)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第一数据锁存端(IN1)、以及第二极连接第一节点(N)；第一节点的第一控制晶体管(T8)，其栅极和第一极连接第一电源电压端，第二极连接所述第一节点(N)；以及第一节点的第二控制晶体管(T9)，其栅极连接所述驱动节点(M)、第一极连接所述第一节点(N)以及第二极连接第二电源电压端。
根据本发明实施例，所述第二数据锁存电路包括：第二保持晶体管(T5)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第二数据锁存端(IN2)、以及第二极连接第二节点(Q)；第二节点的第一控制晶体管(T3)，其栅极和第一极连接第三电源电压端，第二极连接所述第二节点(Q)；以及第二节点的第二控制晶体管(T4)，其栅极连接所述输出端(OUT)、第一极连接所述第二节点(Q)以及第二极连接第四电源电压端。
根据本发明实施例，所述第二数据锁存电路还连接到所述第一节点(N)，并且所述第二数据锁存电路包括：第二保持晶体管(T5)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第二数据锁存端(IN2)、以及第二极连接第二节点(Q)；第二节点的第一控制晶体管(T3)，其栅极连接所述第一节点(N)、第一极连接第三电源电压端，第二极连接所述第二节点(Q)；以及第二节点的第二控制晶体管(T4)，其栅极连接所述输出端(OUT)、第一极连接所述第二节点(Q)以及第二极连接第四电源电压端。
根据本发明实施例，所述数据输入电路包括：第一输入晶体管(T11)，其栅极连接所述第一控制信号端(S1)、第一极连接所述数据线(DATA)、以 及第二极连接所述第一数据锁存端(IN1)；以及第二输入晶体管(T12)，其栅极连接所述第一控制信号端(S1)、第一极连接所述数据线(DATA)、以及第二极连接所述第二数据锁存端(IN2)。
根据本发明实施例，所述驱动控制电路包括：第一驱动控制晶体管(T6)，其栅极和第一极连接第一电源电压端、以及第二极连接所述驱动节点(M)；以及第二驱动控制晶体管(T7)，其栅极连接所述第一数据锁存端(IN1)、第一极连接所述驱动节点(M)、以及第二极连接第二电源电压端。
根据本发明实施例，所述驱动电路包括：第一驱动晶体管(T1)，其栅极连接所述驱动节点(M)、第一极连接第三电源电压端、以及第二极连接所述输出端(OUT)；以及第二驱动晶体管(T2)，其栅极连接所述第二数据锁存端(IN2)、第一极连接所述输出端(OUT)、以及第二极连接第四电源电压端。
根据本发明实施例，每个晶体管均为NMOS晶体管，所述驱动节点(M)的有效电平为高电平，所述第一电源电压端为第一高电源电压端(VDD)，所述第二电源电压端为第一低电源电压端(VSS)，所述第三电源电压端为第二高电源电压端(VDH)，所述第四电源电压端为第二低电源电压端(VDL)。
根据本发明实施例，每个晶体管均为PMOS晶体管，所述驱动节点(M)的有效电平为低电平，所述第一电源电压端为第一低电源电压端(VSS)，所述第二电源电压端为第一高电源电压端(VDD)，所述第三电源电压端为第二低电源电压端(VDL)，所述第四电源电压端为第二高电源电压端(VDH)。
根据本发明另一方面，提供了一种像素内数据存储方法，包括：在第一时段，所述第一控制信号端(S1)的第一控制信号处于其有效电平，所述第二控制信号端(S2)的第二控制信号处于其无效电平，所述数据输入电路将所述数据线(DATA)上的数据电压(Vdata)读取到所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)上，所述驱动节点(M)的电平与所述第一数据锁存端(IN1)的电平相反，并且所述驱动电路的输出端(OUT)的电平与所述数据电压的电平相反；在第二时段，所述第二控制信号端(S2)的第二控制信号处于其有效电平，所述第一控制信号端(S1)的第一控制信号处于其无效电平，所述数据输入电路将所述数据线(DATA)与所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)隔离，所述第一数据锁存电路保持 所述第一数据锁存端(IN1)的电平，并且所述第二数据锁存电路保持所述第二数据锁存端(IN2)的电平，从而使得所述驱动电路的输出端(OUT)的电平保持不变。
根据本发明实施例，在所述第一时段，所述数据电压为高电平，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为高电平，所述驱动节点(M)为低电平，所述驱动电路的输出端(OUT)为低电平；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一数据锁存电路保持所述第一数据锁存端(IN1)为高电平，所述第二数据锁存电路保持所述第二数据锁存端(IN2)为高电平，所述驱动电路的输出端(OUT)保持为低电平。
根据本发明实施例，在所述第一时段，所述数据电压为低电平，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为低电平，所述驱动节点(M)为高电平，所述驱动电路的输出端(OUT)为高电平；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一数据锁存电路保持所述第一数据锁存端(IN1)为低电平，所述第二数据锁存电路保持所述第二数据锁存端(IN2)为低电平，所述驱动电路的输出端(OUT)保持为高电平。
根据本发明实施例，在所述第一时段，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述数据电压为高电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)导通使得所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为高电平，所述第一驱动控制晶体管(T6)和所述第二驱动控制晶体管(T7)导通使得所述驱动节点(M)为低电平，所述第一驱动晶体管(T1)截止并且所述第二驱动晶体管(T2)导通使得所述驱动电路的输出端(OUT)为低电平，所述第一保持晶体管(T10)和第二保持晶体管(T5)截止；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)截止，所述第一节点的第一控制晶体管(T8)导通并且所述第一节点的第二控制晶体管(T9)截止使得所述第一节点(N)为高电平，所 述第一保持晶体管(T10)导通使得所述第一数据锁存端(IN1)的电平保持为高电平，所述第二节点的第一控制晶体管(T3)导通并且所述第二节点的第二控制晶体管(T4)截止使得所述第二节点(Q)为高电平，所述第二保持晶体管(T5)导通使得所述第二数据锁存端(IN2)的电平保持为高电平，所述第一驱动晶体管(T1)保持截止并且所述第二驱动晶体管(T2)保持导通使得所述驱动电路的输出端(OUT)保持为低电平。
根据本发明实施例，在所述第一时段，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述数据电压为低电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)导通使得所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为低电平，所述第一驱动控制晶体管(T6)导通并且所述第二驱动控制晶体管(T7)截止使得所述驱动节点(M)为高电平，所述第一驱动晶体管(T1)导通并且所述第二驱动晶体管(T2)截止使得所述驱动电路的输出端(OUT)为高电平，所述第一保持晶体管(T10)和第二保持晶体管(T5)截止；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)截止，所述第一节点的第一控制晶体管(T8)和所述第一节点的第二控制晶体管(T9)导通使得所述第一节点(N)为低电平，所述第一保持晶体管(T10)导通使得所述第一数据锁存端(IN1)的电平保持为低电平，所述第二节点的第一控制晶体管(T3)截止并且所述第二节点的第二控制晶体管(T4)导通使得所述第二节点(Q)为低电平，所述第二保持晶体管(T5)导通使得所述第二数据锁存端(IN1)的电平保持为低电平，所述第一驱动晶体管(T1)保持导通并且所述第二驱动晶体管(T2)保持截止使得所述驱动电路的输出端(OUT)保持为高电平。
根据本发明实施例，在所述第一时段，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述数据电压为高电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)导通使得所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为高电平，所述第一驱动控制晶体管(T6)导通以及所述第二驱动控制晶体管(T7)截止使得所述驱动节点(M)为低电平，所述第一驱动晶体管(T1)导通并且所述第二驱动晶体管(T2)截止使得所述驱动电路的输出端(OUT)为低电平，所述第一保持晶体管(T10)和 第二保持晶体管(T5)截止；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)截止，所述第一节点的第一控制晶体管(T8)导通并且所述第一节点的第二控制晶体管(T9)导通使得所述第一节点(N)为高电平，所述第一保持晶体管(T10)导通使得所述第一数据锁存端(IN1)的电平保持为高电平，所述第二节点的第一控制晶体管(T3)截止并且所述第二节点的第二控制晶体管(T4)导通使得所述第二节点(Q)为高电平，所述第二保持晶体管(T5)导通使得所述第二数据锁存端(IN1)的电平保持为高电平，所述第一驱动晶体管(T1)保持导通并且所述第二驱动晶体管(T2)保持截止使得所述驱动电路的输出端(OUT)保持为低电平。
根据本发明实施例，在所述第一时段，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述数据电压为低电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)导通使得所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)为低电平，所述第一驱动控制晶体管(T6)和所述第二驱动控制晶体管(T7)导通使得所述驱动节点(M)为高电平，所述第一驱动晶体管(T1)截止并且所述第二驱动晶体管(T2)导通使得所述驱动电路的输出端(OUT)为高电平，所述第一保持晶体管(T10)和第二保持晶体管(T5)截止；在所述第二时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一输入晶体管(T11)和所述第二输入晶体管(T12)截止，所述第一节点的第一控制晶体管(T8)导通并且所述第一节点的第二控制晶体管(T9)截止使得所述第一节点(N)为低电平，所述第一保持晶体管(T10)导通使得所述第一数据锁存端(IN1)的电平保持为低电平，所述第二节点的第一控制晶体管(T3)导通并且所述第二节点的第二控制晶体管(T4)截止使得所述第二节点(Q)为低电平，所述第二保持晶体管(T5)导通使得所述第二数据锁存端(IN2)的电平保持为低电平，所述第一驱动晶体管(T1)保持截止并且所述第二驱动晶体管(T2)保持导通使得所述驱动电路的输出端(OUT)保持为高电平。
根据本发明另一方面，提供了一种像素阵列，每个像素包括根据本发明实施例的像素内存储单元和液晶显示单元。
根据本发明实施例的像素内存储单元及数据存储方法，通过利用第一数 据锁存电路保持第一数据锁存端的电平并且利用第二数据锁存电路保持第二数据锁存端的电平，根据第一数据锁存端的电平控制驱动节点的电平，驱动节点的电平和第二数据锁存端的电平相反，然后根据驱动节点的电平和第二数据锁存端的电平在输出端输出高电源电压或低电源电压，由此可以实现黑白电压的存储，并由此实现MIP LCD的黑白显示。此外，通过采用单一类型的MOS晶体管MIP电路，可以应用单一MOS LTPS工艺还制造MIP像素，从而提高了产品良率并降低了生产成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
通过结合附图对本发明实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1为MIP像素电路的示意图；
图2为由CMOS电路构成的像素内存储单元MIP的电路原理图；
图3A为根据本发明实施例的像素内存储单元MIP的一种示意性框图；
图3B为根据本发明实施例的像素内存储单元MIP的另一示意性框图；
图3C为根据本发明实施例的像素内存储单元MIP的又一示意性框图；
图4为根据本发明实施例的像素阵列的示意图；
图5为根据本发明实施例的像素内数据存储方法的示意性流程图；
图6A为根据本发明第一实施例的图3B所示的像素内存储单元MIP的电路原理图；
图6B为根据本发明第一实施例的图3C所示的像素内存储单元MIP的电路原理图；
图7为根据本发明实施例的像素内存储单元MIP的信号时序图；
图8A和图8B为根据本发明第一实施例的图6B所示的像素内存储单元 MIP在存储黑态数据情况下的电路操作原理图；
图9A和图9B为根据本发明第一实施例的图6B所示的像素内存储单元MIP在存储白态数据情况下的电路操作原理图；
图10A为根据本发明第二实施例的图3B所示的像素内存储单元MIP的电路原理图；
图10B为根据本发明第二实施例的图3C所示的像素内存储单元MIP的电路原理图；
图11A和图11B为根据本发明第二实施例的图10B所示的像素内存储单元MIP在存储黑态数据情况下的电路操作原理图；以及
图12A和图12B为根据本发明第二实施例的图10B所示的像素内存储单元MIP在存储白态数据情况下的电路操作原理图。
具体实施方式
为了使得本发明实施例的目的、技术方案和优点更为明显，下面将参照附图详细描述本发明的示例实施例。显然，所描述的示例实施例仅仅是本发明的一部分实施例，而不是本发明的全部实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本发明的保护范围之内。
这里，需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
图1示出了传统的MIP像素电路的示意图。如图1所示，MIP像素电路包括存储单元、开关晶体管T、以及液晶显示单元LC，所述存储单元由锁存器构成。在开关晶体管T导通时，将数据电压Vdata输入到存储单元中，在开关晶体管T截止时，由存储单元保持数据电压Vdata，具体地保持施加到液晶显示单元LC的一端(即P点)的电压不变。
图2示出了由CMOS电路构成的像素内存储单元MIP的电路原理图。
如图2所示，MIP电路包括CMOS传输门M1、CMOS传输门M2、CMOS传输门M3、CMOS传输门M4、反相器INV1和反相器INV2。该MIP电路为1比特的存储单元，能够存储黑白电压，由此MIP像素可以实现黑白显示。
在输入电压Vdata为高电平时，在控制信号S1为低电平且控制信号/S1 为高电平时，CMOS传输门M1导通且CMOS传输门M2截止，此时，A点电平也为高电平并且B点电平为低电平，使得CMOS传输门M3导通且CMOS传输门M4截止，使得将电源电压VDH输出到输出端C点。然后，在控制信号S1变为高电平且控制信号/S1变为低电平时，CMOS传输门M1截止且CMOS传输门M2导通，由反相器INV1、反相器INV2和CMOS传输门M2构成保持电路，A点电平保持为高电平，并且保持将电源电压VDH输出到输出端C点。
另一方面，在输入电压Vdata为低电平时，在控制信号S1为低电平且控制信号/S1为高电平时，CMOS传输门M1导通且CMOS传输门M2截止，此时，A点电平也为低电平并且B点电平为高电平，使得CMOS传输门M3截止且CMOS传输门M4导通，使得将电源电压VDL输出到输出端C点。然后，在控制信号S1变为高电平且控制信号/S1变为低电平时，CMOS传输门M1截止且CMOS传输门M2导通，由反相器INV1、反相器INV2和CMOS传输门M2构成保持电路，A点电平保持为低电平，并且保持将电源电压VDL输出到输出端C点。
对于常白模式的液晶显示器而言，在输入电压Vdata为高电平时，MIP像素显示黑态，而在输入电压Vdata为低电平时，MIP像素显示白态。
图2所示的像素内存储单元MIP由CMOS电路构成，其基于CMOS LTPS工艺，工艺较复杂，良率较低。
图3A为根据本发明实施例的像素内存储单元MIP的一种示意性框图。如图3A所示，所述像素内存储单元包括：数据输入电路310、第一数据锁存电路320、第二数据锁存电路330、驱动控制电路340以及驱动电路350。
所述数据输入电路310连接到数据线DATA、第一控制信号端S1、第一数据锁存端IN1以及第二数据锁存端IN2，并且被配置为在第一控制信号端S1的第一控制信号处于其有效电平时将所述数据线DATA上的数据电压Vdata读取到所述第一数据锁存端IN1和所述第二数据锁存端IN2上。
所述第一数据锁存电路320连接到所述第一数据锁存端IN1，并且被配置为保持所述第一数据锁存端IN1的电平。
所述第二数据锁存电路330连接到所述第二数据锁存端IN2，并且被配置为保持所述第二数据锁存端IN2的电平。
所述驱动控制电路340连接到所述第一数据锁存端IN1以及驱动节点M，并且被配置为使所述驱动节点M的电平与所述第一数据锁存端IN1的电平相反。
所述驱动电路350连接到驱动节点M、所述第二数据锁存端IN2以及输出端OUT，并且被配置为在所述驱动节点M处于其有效电平时将第三电源电压端的第三电源电压输出至所述输出端OUT并且在所述第二数据锁存端IN2处于其有效电平时将第四电源电压端的第四电源电压输出至所述输出端OUT。
图3B为根据本发明实施例的像素内存储单元MIP的另一种示意性框图。在图3A所示的像素内存储单元MIP的基础上，所述第一数据锁存电路320还连接到所述驱动节点M和第二控制信号端S2，并且被配置为在所述第二控制信号端S2处于其有效电平时使所述第一数据锁存端IN1的电平与所述驱动节点M的电平相反。此外，所述第二数据锁存电路330还连接到所述输出端OUT以及所述第二控制信号端S2，并且还被配置为在所述第二控制信号端S2处于其有效电平时使所述第二数据锁存端IN2的电平与所述输出端OUT的电平相反。
图3C为根据本发明实施例的像素内存储单元MIP的又一示意性框图。在图3B所示的像素内存储单元的基础上，所述第一数据锁存电路320还连接到第一节点N，并且被配置为使所述第一节点N的电平与所述驱动节点M的电平相反。此外，所述第二数据锁存电路330还连接到所述第一节点N，并且还被配置为在所述第二控制信号端S2处于其有效电平时在所述第一节点N的控制下使所述第二数据锁存端IN2的电平与所述输出端OUT的电平相反。
图4为根据本发明实施例的像素阵列的示意图，每个像素包括根据本发明实施例的像素内存储单元MIP和液晶显示单元LC。
图5为根据本发明实施例的像素内数据存储方法的示意性流程图。
在数据写入时段，所述第一控制信号端S1的第一控制信号处于其有效电平，所述第二控制信号端S2的第二控制信号处于其无效电平，所述数据输入电路310将所述数据线DATA上的数据电压Vdata读取到所述第一数据锁存端IN1和所述第二数据锁存端IN2上，所述驱动控制电路340使所述驱动节点M的电平与所述第一数据锁存端IN1的电平相反，并且所述驱动电路350 的输出端OUT的电平与所述数据电压Vdata的电平相反。
在数据保持时段，所述第二控制信号端S2的第二控制信号处于其有效电平，所述第一控制信号端S1的第一控制信号处于其无效电平，所述数据输入电路310将所述数据线DATA与所述第一数据锁存端IN1和所述第二数据锁存端IN2隔离，所述第一数据锁存电路310保持所述第一数据锁存端IN1的电平，并且所述第二数据锁存电路320保持所述第二数据锁存端IN2的电平，从而使得所述驱动电路350的输出端OUT的电平保持不变。
根据本发明实施例，对于常白模式的液晶显示器，输入数据可以分为黑态数据和白态数据，例如，黑态数据为高电平，白态数据为低电平。
在黑态数据写入时段，所述数据电压Vdata为高电平，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述第一数据锁存端IN1和所述第二数据锁存端IN2为高电平，所述驱动节点M为低电平，所述驱动电路的输出端OUT为低电平；在黑态数据保持时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一数据锁存电路保持所述第一数据锁存端IN1为高电平，所述第二数据锁存电路保持所述第二数据锁存端IN2为高电平，所述驱动电路的输出端OUT保持为低电平。
在白态数据写入时段，所述数据电压Vdata为低电平，所述第一控制信号为有效电平，所述第二控制信号为无效电平，所述第一数据锁存端IN1和所述第二数据锁存端IN2为低电平，所述驱动节点M为高电平，所述驱动电路的输出端OUT为高电平；在白态数据保持时段，所述第一控制信号为无效电平，所述第二控制信号为有效电平，所述第一数据锁存电路保持所述第一数据锁存端IN1为低电平，所述第二数据锁存电路保持所述第二数据锁存端IN2为低电平，所述驱动电路的输出端OUT保持为高电平。
根据本发明实施例的像素内存储单元MIP由单一类型的MOS晶体管构成，例如仅由NMOS晶体管构成、或者仅由PMOS晶体管构成。
根据本发明第一实施例，像素内存储单元MIP由NMOS晶体管构成，根据本发明第二实施例，像素内存储单元MIP由PMOS晶体管构成。
图6A为根据本发明第一实施例的图3B所示的像素内存储单元MIP的电路原理图。在本发明第一实施例中，第一控制信号和第二控制信号的有效电平为高电平，并且驱动节点M的有效电平也为高电平。
如图6A所示，所述数据输入电路包括第一输入晶体管T11和第二输入晶体管T12。
所述第一输入晶体管T11的栅极连接所述第一控制信号端S1，第一极连接所述数据线DATA，第二极连接所述第一数据锁存端IN1。第二输入晶体管T12的栅极连接所述第一控制信号端S1，第一极连接所述数据线DATA，第二极连接所述第二数据锁存端IN2。
如图6A所示，所述第一数据锁存电路220包括第一保持晶体管T10、第一节点N的第一控制晶体管T8、以及第一节点的第二控制晶体管T9。
所述第一保持晶体管T10的栅极连接所述第二控制信号端S2，第一极连接所述第一数据锁存端IN1，以及第二极连接所述第一节点N。
所述第一节点N的第一控制晶体管T8的栅极和第一极连接第一电源电压端，第二极连接所述第一节点N。所述第一节点N的第二控制晶体管T9的栅极连接所述驱动节点M，第一极连接所述第一节点N，以及第二极连接第二电源电压端。
如图6A所示，所述第二数据锁存电路330包括第二保持晶体管T5、第二节点Q的第一控制晶体管T3、以及第二节点Q的第二控制晶体管T4。
所述第二保持晶体管T5的栅极连接所述第二控制信号端S2，第一极连接所述第二数据锁存端IN2，以及第二极连接所述第二节点Q。
所述第二节点Q的第一控制晶体管T3的栅极和第一极连接第三电源电压端，第二极连接所述第二节点Q。
所述第二节点Q的第二控制晶体管T4的栅极连接所述输出端OUT，第一极连接所述第二节点Q，以及第二极连接第四电源电压端。
如图6A所示，所述驱动控制电路340包括第一驱动控制晶体管T6和第二驱动控制晶体管T7。
所述第一驱动控制晶体管T6的栅极和第一极连接第一电源电压端，以及第二极连接所述驱动节点M。
所述第二驱动控制晶体管T7的栅极连接所述第一数据锁存端IN1，第一极连接所述驱动节点M，以及第二极连接第二电源电压端。
如图6A所示，所述驱动电路350包括第一驱动晶体管T1和第二驱动晶体管T2。
所述第一驱动晶体管T1的栅极连接所述驱动节点M，第一极连接第三电源电压端，以及第二极连接所述输出端OUT。
所述第二驱动晶体管T2的栅极连接所述第二数据锁存端IN2，第一极连接所述输出端OUT，以及第二极连接第四电源电压端。
根据本发明第一实施例，每个晶体管均为NMOS晶体管，所述驱动节点M的有效电平为高电平，所述第一电源电压端为第一高电源电压端VDD，所述第二电源电压端为第一低电源电压端VSS，所述第三电源电压端为第二高电源电压端VDH，所述第四电源电压端为第二低电源电压端VDL。所述第一高电源电压端VDD提供的第一电源电压与所述第二高电源电压端VDH提供的第三电源电压可以相同或不同，所述第一低电源电压端VSS提供的第二电源电压和所述第二低电源电压端VDL提供的第四电源电压可以相同或不同。
图6B为根据本发明第一实施例的图3C所示的像素内存储单元MIP的电路原理图。
图6B所示的电路原理图与图6A所示的电路原理图的区别仅在于：所述第二数据锁存电路330中所述第二节点Q的第一控制晶体管T3的连接方式。在此省略图6B中与图6A中相同电路部分的描述。
如图6B所示，所述第二数据锁存电路还连接到所述第一节点(N)。具体地，所述第二节点Q的第一控制晶体管T3的栅极连接所述第一节点N，第一极连接第三电源电压端，第二极连接所述第二节点Q。
图7为根据本发明实施例的像素内存储单元MIP的信号时序图，图8A和图8B为根据本发明第一实施例的图6B所示的像素内存储单元MIP在存储黑态数据情况下的电路操作原理图，图9A和图9B为根据本发明第一实施例的图6B所示的像素内存储单元MIP在存储白态数据情况下的电路操作原理图。
将结合图6B、图7、图8A－图8B以及图9A－图9B来具体地描述结合图5所示的像素内数据存储方法。
如图8A所示，在黑态数据写入时段TT1，所述第一控制信号S1为有效电平(高电平)，所述第二控制信号S2为无效电平(低电平)，所述数据电压Vdata为高电平，所述第一输入晶体管T11和所述第二输入晶体管T12导通 使得所述第一数据锁存端IN1和所述第二数据锁存端IN2为高电平，所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7导通使得所述驱动节点M为低电平，所述第一驱动晶体管T1截止并且所述第二驱动晶体管T2导通使得所述驱动电路的输出端OUT为低电平，所述第一保持晶体管T10和第二保持晶体管T5截止，所述第一节点N的第二控制晶体管T9截止，所述第二节点Q的第二控制晶体管T4截止。
如图8B所示，在黑态数据保持时段TT2，所述第一控制信号为无效电平(低电平)，所述第二控制信号为有效电平(高电平)，所述第一输入晶体管T11和所述第二输入晶体管T12截止，所述第一节点N的第一控制晶体管T8导通并且所述第一节点N的第二控制晶体管T9截止使得所述第一节点N为高电平，所述第一保持晶体管T10导通使得所述第一数据锁存端IN1的电平保持为高电平，所述第二节点Q的第一控制晶体管T3导通并且所述第二节点Q的第二控制晶体管T4截止使得所述第二节点Q为高电平，所述第二保持晶体管T5导通使得所述第二数据锁存端IN2的电平保持为高电平，所述第一驱动晶体管T1保持截止并且所述第二驱动晶体管T2保持导通使得所述驱动电路的输出端OUT保持为低电平。
根据本发明第一实施例，通过适当地设置所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7的沟道宽度和长度，可以使得在所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7均导通时所述第一驱动控制晶体管T6的通态阻抗远大于所述第二驱动控制晶体管T7的通态阻抗，从而使得所述驱动节点M的电平与所述第二电源电压端VSS的电平相同。
如图9A所示，在白态数据写入时段TT3，所述第一控制信号为有效电平(高电平)，所述第二控制信号为无效电平(低电平)，所述数据电压Vdata为低电平，所述第一输入晶体管T11和所述第二输入晶体管T12导通使得所述第一数据锁存端IN1和所述第二数据锁存端IN2为低电平，所述第一驱动控制晶体管T6导通并且所述第二驱动控制晶体管T7截止使得所述驱动节点M为高电平，所述第一驱动晶体管T1导通并且所述第二驱动晶体管T2截止使得所述驱动电路的输出端OUT为高电平，所述第一保持晶体管T10和第二保持晶体管T5截止，所述第一节点N的第二控制晶体管T9导通，所述第二节点Q的第二控制晶体管T4导通。
如图9B所示，在白态数据保持时段TT4，所述第一控制信号为无效电平(低电平)，所述第二控制信号为有效电平(高电平)，所述第一输入晶体管T11和所述第二输入晶体管T12截止，所述第一节点N的第一控制晶体管T8和所述第一节点N的第二控制晶体管T9导通使得所述第一节点N为低电平，所述第一保持晶体管T10导通使得所述第一数据锁存端IN1的电平保持为低电平，所述第二节点Q的第一控制晶体管T3截止并且所述第二节点Q的第二控制晶体管T4导通使得所述第二节点Q为低电平，所述第二保持晶体管T5导通使得所述第二数据锁存端IN1的电平保持为低电平，所述第一驱动晶体管T1保持导通并且所述第二驱动晶体管T2保持截止使得所述驱动电路的输出端OUT保持为高电平。
根据本发明第一实施例，通过适当地设置所述第一节点N的第一控制晶体管T8和所述第一节点N的第二控制晶体管T9的沟道宽度和长度，可以使得在所述第一节点N的第一控制晶体管T8和所述第一节点N的第二控制晶体管T9均导通时所述第一节点N的第一控制晶体管T8的通态阻抗远大于所述第一节点N的第二控制晶体管T9的通态阻抗，从而使得所述第一节点N的电平与所述第二电源电压端VSS的电平相同。
根据本发明第一实施例，关于图6A所示的电路，在白态数据写入和保持时段，所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4均导通。通过适当地设置所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4的沟道宽度和长度，可以使得在所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4均导通时所述第二节点Q的第一控制晶体管T3的通态阻抗远大于所述第二节点Q的第二控制晶体管T4的通态阻抗，从而使得所述第二节点Q的电平与所述第四电源电压端VDL的电平相同。
根据本发明第一实施例，应了解，所述黑态数据写入时段和所述黑态数据保持时段是连续的两个时段(即：第一时段和第二时段)，并且构成了完整的黑态数据写入和保持操作；所述白态数据写入时段和所述白态数据保持时段是连续的两个时段(即：第一时段和第二时段)，并且构成了完整的白态数据写入和保持操作。尽管图7中将白态数据写入和保持时段示出在黑态数据写入和保持时段之后，应了解本发明不限于此，可以连续地存在若干个黑态 数据写入和保持时段，可以连续地存在若干个白态数据写入和保持时段，并且白态数据写入和保持时段也可以出现在黑态数据写入和保持时段之前。
根据本发明第一实施例，黑态数据的数据电压为Vdd，白态数据的数据电压为Vss，第一电源电压端VDD的第一电源电压为Vdd，第二电源电压端VSS的第二电源电压为Vss。
由于晶体管阈值电压和沟道电阻分压等影响，驱动节点M的实际工作高电压和工作低电压不等于Vdd和Vss而分别等于VMcc和VMee。这里，VMcc＝Vdd－Vth6，VMee＝(R7/(R6+R7))×(Vdd－Vss)+Vss，R7表示晶体管T7的导通电阻，R6表示晶体管T6的导通电阻，Vth6为晶体管T6的阈值电压。
类似地，第一节点N的实际工作高电压和工作低电压不等于Vdd和Vss而分别等于VNcc和VNee。这里，VNcc＝Vdd－Vth8，VMee＝(R9(R8+R9))×(Vdd－Vss)+Vss，R9表示晶体管T9的导通电阻，R8表示晶体管T8的导通电阻，Vth8为晶体管T8的阈值电压。
另一方面，第三电源电压端VDH的第三电源电压为Vdh，第四电源电压端VDL的第四电源电压为Vdl。
为简化描述，可以假设根据本发明第一实施例的像素内存储单元MIP中的晶体管T8和晶体管T6的尺寸完全相同，晶体管T9和晶体管T7的尺寸完全相同，因此，R9＝R7，R8＝R6，Vth6＝Vth8，在此情况下，将VMcc和VNcc统称为Vcc，将VMee和VNee通称为Vee。
对于白态数据写入和显示阶段，在驱动节点M的实际工作高电压Vcc与第三电源电压Vdh满足以下关系时，即在Vcc－Vdh>Vth1时，晶体管T1处于饱和导通状态，Vth1为晶体管T1的阈值电压。通过使得Vdh<Vdd－2Vth1，可以保证根据本发明第一实施例的晶体管T1在白态数据写入和显示阶段处于饱和导通状态，从而使得输出端OUT输出第三电源电压Vdh。
对于白态数据写入和显示阶段，在第一节点N的实际工作低电压Vee与与第二节点Q处的低电压Vdl满足以下关系时，即在Vee－Vdl<Vth3时，晶体管T3才处于截止状态，Vth3为晶体管T3的阈值电压。也就是说，需要满足(R7/(R6+R7))×(Vdd－Vss)+Vss－Vdl<Vth3。通过使Vdl>(R7×Vdd+R6×Vss)/(R6+R7)-Vth3，可以保证根据本发明第一实施例的晶体管T3在白态数据写入和显示阶段处于截止状态，从而使得第二节点Q输出第四电源电压 Vdl，进而使得第二数据锁存电路能够锁存第二数据锁存端IN2的电压。
图10A为根据本发明第二实施例的图3B所示的像素内存储单元MIP的电路原理图。在本发明第二实施例中，第一控制信号和第二控制信号的有效电平为低电平，并且驱动节点M的有效电平也为低电平。
如图10A所示，所述数据输入电路310包括第一输入晶体管T11和第二输入晶体管T12。
所述第一输入晶体管T11的栅极连接所述第一控制信号端S1，第一极连接所述数据线DATA，第二极连接所述第一数据锁存端IN1。第二输入晶体管T12的栅极连接所述第一控制信号端S1，第一极连接所述数据线DATA，第二极连接所述第二数据锁存端IN2。
如图10A所示，所述第一数据锁存电路320包括第一保持晶体管T10、第一节点N的第一控制晶体管T8、以及第一节点N的第二控制晶体管T9。
所述第一保持晶体管T10的栅极连接所述第二控制信号端S2，第一极连接所述第一数据锁存端IN1，以及第二极连接所述第一节点N。
所述第一节点N的第一控制晶体管T8的栅极和第一极连接第一电源电压端，第二极连接所述第一节点N。所述第一节点N的第二控制晶体管T9的栅极连接所述驱动节点M，第一极连接所述第一节点N，以及第二极连接第二电源电压端。
如图10A所示，所述第二数据锁存电路330包括第二保持晶体管T5、第二节点Q的第一控制晶体管T3、以及第二节点Q的第二控制晶体管T4。
所述第二保持晶体管T5的栅极连接所述第二控制信号端S2，第一极连接所述第二数据锁存端IN2，以及第二极连接所述第二节点Q。
所述第二节点Q的第一控制晶体管T3的栅极和第一极连接第三电源电压端，第二极连接所述第二节点Q。
所述第二节点Q的第二控制晶体管T4的栅极连接所述输出端OUT，一极连接所述第二节点Q，以及第二极连接第四电源电压端。
如图10A所示，所述驱动控制电路340包括第一驱动控制晶体管T6和第二驱动控制晶体管T7。
所述第一驱动控制晶体管T6的栅极和第一极连接第一电源电压端，以及第二极连接所述驱动节点M。
所述第二驱动控制晶体管T7的栅极连接所述第一数据锁存端IN1，第一极连接所述驱动节点M，以及第二极连接第二电源电压端。
如图10A所示，所述驱动电路包括第一驱动晶体管T1和第二驱动晶体管T2。
所述第一驱动晶体管T1的栅极连接所述驱动节点M，第一极连接第三电源电压端，以及第二极连接所述输出端OUT。
所述第二驱动晶体管T2的栅极连接所述第二数据锁存端IN2，第一极连接所述输出端OUT，以及第二极连接第四电源电压端。
根据本发明第二实施例，每个晶体管均为PMOS晶体管，所述驱动节点M的有效电平为低电平，所述第一电源电压端为第一低电源电压端VSS，所述第二电源电压端为第一高电源电压端VDD，所述第三电源电压端为第二低电源电压端VDL，所述第四电源电压端为第二高电源电压端VDH。所述第一低电源电压端VSS提供的第一电源电压与所述第二低电源电压端VDL提供的第三电源电压可以相同或不同，所述第一高电源电压端VDD提供的第二电源电压和所述第二高电源电压端VDH提供的第四电源电压可以相同或不同。
图10B为根据本发明第二实施例的图3C所示的像素内存储单元MIP的电路原理图。
图10B所示的电路原理图与图10A所示的电路原理图的区别仅在于：所述第二数据锁存电路330中所述第二节点Q的第一控制晶体管T3的连接方式。在此省略图10B中与图10A中相同电路部分的描述。
如图10B所示，所述第二数据锁存电路还连接到所述第一节点N。具体地，所述第二节点Q的第一控制晶体管T3的栅极连接所述第一节点N，第一极连接第三电源电压端，第二极连接所述第二节点Q。
下面，参考图10B、图11A－图11B以及图12A－图12B来描述根据本发明第二实施例的像素内存储单元的数据存储操作。
如图11A所示，在黑态数据写入时段，所述第一控制信号为有效电平(低电平)，所述第二控制信号为无效电平(高电平)，所述数据电压为高电平，所述第一输入晶体管T11和所述第二输入晶体管T12导通使得所述第一数据锁存端IN1和所述第二数据锁存端IN2为高电平，所述第一驱动控制晶体管 T6导通以及所述第二驱动控制晶体管T7截止使得所述驱动节点M为低电平，所述第一节点N的第一控制晶体管T8和第二控制晶体管T9导致使得第一节点N为高电平，所述第一驱动晶体管T1导通并且所述第二驱动晶体管T2截止使得所述驱动电路的输出端OUT为低电平，所述第一保持晶体管T10和第二保持晶体管T5截止。
如图11B所示，在黑态数据保持时段，所述第一控制信号为无效电平(高电平)，所述第二控制信号为有效电平(低电平)，所述第一输入晶体管T11和所述第二输入晶体管T12截止，所述第一节点N的第一控制晶体管T8导通并且所述第一节点N的第二控制晶体管T9导通使得所述第一节点N为高电平，所述第一保持晶体管T10导通使得所述第一数据锁存端IN1的电平保持为高电平，所述第二节点Q的第一控制晶体管T3截止并且所述第二节点Q的第二控制晶体管T4导通使得所述第二节点Q为高电平，所述第二保持晶体管T5导通使得所述第二数据锁存端IN2的电平保持为高电平，所述第一驱动晶体管T1保持导通并且所述第二驱动晶体管T2保持截止使得所述驱动电路的输出端OUT保持为低电平。
根据本发明第二实施例，通过适当地设置所述第一节点N的第一控制晶体管T8和所述第一节点N的第二控制晶体管T9的沟道宽度和长度，可以使得在所述第一节点N的第一控制晶体管T8和所述第一节点N的第二控制晶体管T9导通时所述第一节点N的第一控制晶体管T8的通态阻抗远大于所述第一节点N的第二控制晶体管T9的通态阻抗，从而使得所述驱动节点M的电平与所述第二电源电压端VDD的电平相同。
如图12A所示，在白态数据写入时段，所述第一控制信号为有效电平(低电平)，所述第二控制信号为无效电平(高电平)，所述数据电压为低电平，所述第一输入晶体管T11和所述第二输入晶体管T12导通使得所述第一数据锁存端IN1和所述第二数据锁存端IN2为低电平，所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7导通使得所述驱动节点M为高电平，所述第一节点N的第二控制晶体管T9截止，所述第一驱动晶体管T1截止并且所述第二驱动晶体管T2导通使得所述驱动电路的输出端OUT为高电平，所述第二节点Q的第二控制晶体管T4截止，所述第一保持晶体管T10和第二保持晶体管T5截止。
如图12B所示，在白态数据保持时段，所述第一控制信号为无效电平(高电平)，所述第二控制信号为有效电平(低电平)，所述第一输入晶体管T11和所述第二输入晶体管T12截止，所述第一节点的第一控制晶体管T8导通并且所述第一节点的第二控制晶体管T9截止使得所述第一节点N为低电平，所述第一保持晶体管T10导通使得所述第一数据锁存端IN1的电平保持为低电平，所述第二节点的第一控制晶体管T3导通并且所述第二节点的第二控制晶体管T4截止使得所述第二节点Q为低电平，所述第二保持晶体管T5导通使得所述第二数据锁存端IN2的电平保持为低电平，所述第一驱动晶体管T1保持截止并且所述第二驱动晶体管T2保持导通使得所述驱动电路的输出端OUT保持为高电平。
根据本发明第二实施例，通过适当地设置所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7的沟道宽度和长度，可以使得在所述第一驱动控制晶体管T6和所述第二驱动控制晶体管T7均导通时所述第一驱动控制晶体管T6的通态阻抗远大于所述第二驱动控制晶体管T7的通态阻抗，从而使得所述驱动节点M的电平与所述第二电源电压端VDD的电平相同。
根据本发明第二实施例，关于图10A所示的电路，在黑态数据写入和保持时段，所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4均导通。通过适当地设置所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4的沟道宽度和长度，可以使得在所述第二节点Q的第一控制晶体管T3和所述第二节点Q的第二控制晶体管T4均导通时所述第二节点Q的第一控制晶体管T3的通态阻抗远大于所述第二节点Q的第二控制晶体管T4的通态阻抗，从而使得所述第二节点Q的电平与所述第四电源电压端VDH的电平相同。
根据本发明第二实施例，黑态数据的数据电压为Vdd，白态数据的数据电压为Vss，第二电源电压端VDD的第二电源电压为Vdd，第一电源电压端VSS的第一电源电压为Vss。
由于晶体管阈值电压和沟道电阻分压等影响，驱动节点M的实际工作高电压和工作低电压不等于Vdd和Vss而分别等于VMcc和VMee。这里，VMcc＝(R6/(R6+R7))×(Vdd－Vss)+Vss，VMee＝Vss+Vth6，R7表示晶体管T7的导通电阻，R6表示晶体管T6的导通电阻，Vth6为晶体管T6的阈值电压， Vth6>0。
类似地，第一节点N的实际工作高电压和工作低电压不等于Vdd和Vss而分别等于VNcc和VNee。这里，VNcc＝(R8/(R8+R9))×(Vdd－Vss)+Vss，VMee＝Vss+Vth8，R9表示晶体管T9的导通电阻，R8表示晶体管T8的导通电阻，Vth8为晶体管T8的阈值电压，Vth8>0。
另一方面，第三电源电压端VDL的第三电源电压为Vdl，第四电源电压端VDH的第四电源电压为Vdh。
为简化描述，可以假设根据本发明第二实施例的像素内存储单元MIP中的晶体管T8和晶体管T6的尺寸完全相同，晶体管T9和晶体管T7的尺寸完全相同，因此，R9＝R7，R8＝R6，Vth6＝Vth8，在此情况下，将VMcc和VNcc统称为Vcc，将VMee和VNee通称为Vee。
对于黑态数据写入和显示阶段，在驱动节点M的实际工作低电压Vee与第三电源电压Vdl满足以下关系时，即在Vee－Vdl<－Vth1时，晶体管T1处于饱和导通状态，Vth1为晶体管T1的阈值电压。假设晶体管T1的阈值电压与晶体管T6的阈值电压相同，通过使得Vdl>Vss+2Vth1，可以保证根据本发明第二实施例的晶体管T1在黑态数据写入和显示阶段处于饱和导通状态，从而使得输出端OUT输出第三电源电压Vdl。
对于黑态数据写入和显示阶段，在第一节点N的实际工作高电压Vcc与与第二节点Q处的高电压Vdh满足以下关系时，即在Vcc－Vdh>－Vth3时，晶体管T3才处于截止状态，Vth3为晶体管T3的阈值电压。也就是说，需要满足(R8/(R8+R9))×(Vdd－Vss)+Vss－Vdh>－Vth3。通过使Vdh<(R8×Vdd+R9×Vss)/(R8+R9)+Vth3，可以保证根据本发明第二实施例的晶体管T3在黑态数据写入和显示阶段处于截止状态，从而使得第二节点Q输出第四电源电压Vdh，进而使得第二数据锁存电路能够锁存第二数据锁存端IN2的电压。
此外，根据本发明实施例，还提供了一种像素阵列，每个像素包括根据本发明第一实施例的像素内存储单元和液晶显示单元。
此外，根据本发明实施例，还提供了一种像素阵列，每个像素包括根据本发明第二实施例的像素内存储单元和液晶显示单元。
根据本发明实施例的像素内存储单元及数据存储方法、以及像素阵列， 通过采用单一类型的MOS晶体管构成像素内存储单元，可以利用MOS LTPS工艺来生产像素内存储单元，该工艺相对简单，产品良率也高，由此有效地降低了MIP像素的生产成本。
在上面详细描述了本发明的各个实施例。然而，本领域技术人员应该理解，在不脱离本发明的原理和精神的情况下，可对这些实施例进行各种修改，组合或子组合，并且这样的修改应落入本发明的范围内。
本申请要求2016年5月18日提交的申请号为201610330824.4且发明名称为“像素内存储单元、像素内数据存储方法以及像素阵列”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (12)

  1. 一种像素内存储单元，包括：
    数据输入电路，连接到数据线(DATA)、第一控制信号端(S1)、第一数据锁存端(IN1)以及第二数据锁存端(IN2)，并且被配置为在第一控制信号端的第一控制信号处于其有效电平时将所述数据线上的数据电压(Vdata)读取到所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)上；
    第一数据锁存电路，连接到所述第一数据锁存端(IN1)，并且被配置为保持所述第一数据锁存端(IN1)的电平；
    第二数据锁存电路，连接到所述第二数据锁存端(IN2)，并且被配置为保持所述第二数据锁存端(IN2)的电平；
    驱动控制电路，连接到所述第一数据锁存端(IN1)以及驱动节点(M)，并且被配置为使所述驱动节点(M)的电平与所述第一数据锁存端(IN1)的电平相反；以及
    驱动电路，连接到驱动节点(M)、所述第二数据锁存端(IN2)以及输出端(OUT)，并且被配置为在所述驱动节点(M)处于其有效电平时将第三电源电压端的第三电源电压输出至所述输出端(OUT)并且在所述第二数据锁存端(IN2)处于其有效电平时将第四电源电压端的第四电源电压输出至所述输出端(OUT)。
  2. 如权利要求1所述的像素内存储单元，其中，
    所述第一数据锁存电路还连接到所述驱动节点(M)和第二控制信号端(S2)，并且被配置为在所述第二控制信号端(S2)处于其有效电平时使所述第一数据锁存端(IN1)的电平与所述驱动节点(M)的电平相反；以及
    所述第二数据锁存电路还连接到所述输出端(OUT)以及所述第二控制信号端(S2)，并且还被配置为在所述第二控制信号端(S2)处于其有效电平时使所述第二数据锁存端(IN2)的电平与所述输出端(OUT)的电平相反。
  3. 如权利要求2所述的像素内存储单元，其中，所述第一数据锁存电路包括：
    第一保持晶体管(T10)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第一数据锁存端(IN1)、以及第二极连接第一节点(N)；
    第一节点的第一控制晶体管(T8)，其栅极和第一极连接第一电源电压端，第二极连接所述第一节点(N)；以及
    第一节点的第二控制晶体管(T9)，其栅极连接所述驱动节点(M)、第一极连接所述第一节点(N)以及第二极连接第二电源电压端。
  4. 如权利要求3所述的像素内存储单元，其中，所述第二数据锁存电路包括：
    第二保持晶体管(T5)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第二数据锁存端(IN2)、以及第二极连接第二节点(Q)；
    第二节点的第一控制晶体管(T3)，其栅极和第一极连接第三电源电压端，第二极连接所述第二节点(Q)；
    第二节点的第二控制晶体管(T4)，其栅极连接所述输出端(OUT)、第一极连接所述第二节点(Q)以及第二极连接第四电源电压端。
  5. 如权利要求3所述的像素内存储单元，其中，所述第二数据锁存电路还连接到所述第一节点(N)，并且所述第二数据锁存电路包括：
    第二保持晶体管(T5)，其栅极连接所述第二控制信号端(S2)、第一极连接所述第二数据锁存端(IN2)、以及第二极连接第二节点(Q)；
    第二节点的第一控制晶体管(T3)，其栅极连接所述第一节点(N)、第一极连接第三电源电压端，第二极连接所述第二节点(Q)；
    第二节点的第二控制晶体管(T4)，其栅极连接所述输出端(OUT)、第一极连接所述第二节点(Q)以及第二极连接第四电源电压端。
  6. 如权利要求4或5所述的像素内存储单元，其中，所述数据输入电路包括：
    第一输入晶体管(T11)，其栅极连接所述第一控制信号端(S1)、第一极连接所述数据线(DATA)、以及第二极连接所述第一数据锁存端(IN1)；以及
    第二输入晶体管(T12)，其栅极连接所述第一控制信号端(S1)、第一极连接所述数据线(DATA)、以及第二极连接所述第二数据锁存端(IN2)。
  7. 如权利要求6所述的像素内存储单元，其中，所述驱动控制电路包括：
    第一驱动控制晶体管(T6)，其栅极和第一极连接第一电源电压端、以及第二极连接所述驱动节点(M)；以及
    第二驱动控制晶体管(T7)，其栅极连接所述第一数据锁存端(IN1)、第一极连接所述驱动节点(M)、以及第二极连接第二电源电压端。
  8. 如权利要求7所述的像素内存储单元，其中，所述驱动电路包括：
    第一驱动晶体管(T1)，其栅极连接所述驱动节点(M)、第一极连接第三电源电压端、以及第二极连接所述输出端(OUT)；以及
    第二驱动晶体管(T2)，其栅极连接所述第二数据锁存端(IN2)、第一极连接所述输出端(OUT)、以及第二极连接第四电源电压端。
  9. 如权利要求8所述的像素内存储单元，其中，每个晶体管均为NMOS晶体管，所述驱动节点(M)的有效电平为高电平，所述第一电源电压端为第一高电源电压端(VDD)，所述第二电源电压端为第一低电源电压端(VSS)，所述第三电源电压端为第二高电源电压端(VDH)，所述第四电源电压端为第二低电源电压端(VDL)。
  10. 如权利要求8所述的像素内存储单元，其中，每个晶体管均为PMOS晶体管，所述驱动节点(M)的有效电平为低电平，所述第一电源电压端为第一低电源电压端(VSS)，所述第二电源电压端为第一高电源电压端(VDD)，所述第三电源电压端为第二低电源电压端(VDL)，所述第四电源电压端为第二高电源电压端(VDH)。
  11. 一种像素内数据存储方法，所述像素包括如权利要求1－10任一项所述的像素内存储单元和液晶显示单元，所述数据存储方法包括：
    在第一时段，所述第一控制信号端(S1)的第一控制信号处于其有效电平，所述第二控制信号端(S2)的第二控制信号处于其无效电平，所述数据输入电路将所述数据线(DATA)上的数据电压(Vdata)读取到所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)上，所述驱动节点(M)的电平与所述第一数据锁存端(IN1)的电平相反，并且所述驱动电路的输出端(OUT)的电平与所述数据电压的电平相反；
    在第二时段，所述第二控制信号端(S2)的第二控制信号处于其有效电平，所述第一控制信号端(S1)的第一控制信号处于其无效电平，所述数据输入电路将所述数据线(DATA)与所述第一数据锁存端(IN1)和所述第二数据锁存端(IN2)隔离，所述第一数据锁存电路保持所述第一数据锁存端(IN1)的电平，并且所述第二数据锁存电路保持所述第二数据锁存端(IN2) 的电平，从而使得所述驱动电路的输出端(OUT)的电平保持不变。
  12. 一种像素阵列，每个像素包括如权利要求1－10任一项所述的像素内存储单元和液晶显示单元。
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