WO2017179250A1 - 半導体パッケージの製造方法及びCu合金の切断方法 - Google Patents

半導体パッケージの製造方法及びCu合金の切断方法 Download PDF

Info

Publication number
WO2017179250A1
WO2017179250A1 PCT/JP2017/000475 JP2017000475W WO2017179250A1 WO 2017179250 A1 WO2017179250 A1 WO 2017179250A1 JP 2017000475 W JP2017000475 W JP 2017000475W WO 2017179250 A1 WO2017179250 A1 WO 2017179250A1
Authority
WO
WIPO (PCT)
Prior art keywords
alloy
cut
intermetallic compound
semiconductor package
lead frame
Prior art date
Application number
PCT/JP2017/000475
Other languages
English (en)
French (fr)
Inventor
清多郎 鷲塚
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2018511883A priority Critical patent/JP6579264B2/ja
Publication of WO2017179250A1 publication Critical patent/WO2017179250A1/ja
Priority to US16/157,295 priority patent/US20190043735A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • B23K1/0008Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016Brazing of electronic components
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29CSHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C70/00Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts
    • B29C70/68Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • C22C9/01Alloys based on copper with aluminium as the next major constituent
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • C22C9/05Alloys based on copper with manganese as the next major constituent
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • C22C9/06Alloys based on copper with nickel or cobalt as the next major constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00Articles made by soldering, welding or cutting
    • B23K2101/36Electric or electronic devices
    • B23K2101/40Semiconductor devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29KINDEXING SCHEME ASSOCIATED WITH SUBCLASSES B29B, B29C OR B29D, RELATING TO MOULDING MATERIALS OR TO MATERIALS FOR MOULDS, REINFORCEMENTS, FILLERS OR PREFORMED PARTS, e.g. INSERTS
    • B29K2705/00Use of metals, their alloys or their compounds, for preformed parts, e.g. for inserts
    • B29K2705/08Transition metals
    • B29K2705/10Copper
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29LINDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
    • B29L2031/00Other particular articles
    • B29L2031/34Electrical apparatus, e.g. sparking plugs or parts thereof
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C12/00Alloys based on antimony or bismuth
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29311Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325Material
    • H01L2224/32501Material at the bonding interface
    • H01L2224/32503Material at the bonding interface comprising an intermetallic compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/83095Temperature settings
    • H01L2224/83096Transient conditions
    • H01L2224/83097Heating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/8381Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01025Manganese [Mn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01026Iron [Fe]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01038Strontium [Sr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01052Tellurium [Te]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01083Bismuth [Bi]

Definitions

  • the present invention relates to a semiconductor package manufacturing method and a Cu alloy cutting method.
  • an electronic component such as a semiconductor chip is mounted on a thin metal plate and then separated into individual pieces.
  • a method for facilitating singulation for example, as described in Patent Document 1, a method of previously performing V-groove processing using a dicer or the like at a location where a lead frame is cut is known. It was. Further, as a method of cutting the lead frame, punching by press working is known. For example, after placing a resin-sealed semiconductor package on a lower mold of a press mold, the upper mold of the mold is lowered. . Thus, punching is performed by the upper die and the lower die, and the lead frame is cut.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to manufacture a semiconductor package by preventing burrs and sagging from occurring on a cut surface when a lead frame is cut.
  • a semiconductor package manufacturing method of the present invention includes a step of preparing a lead frame having a cut portion made of a Cu alloy, and a bonding material containing Sn or Sn alloy is applied to the cut portion. Heating the part to be cut and reacting Sn or Sn alloy contained in the bonding material with the Cu alloy constituting the part to be cut to form an intermetallic compound having voids; It has the process of cut
  • the cut portion of the lead frame is made of a Cu alloy, and heating is performed in a state where a bonding material containing Sn or an Sn alloy is applied to the cut portion.
  • the Sn or Sn alloy reacts with the Cu alloy by heating to form an intermetallic compound (for example, (Cu, Ni) 6 Sn 5 ), and the intermetallic compound and the part to be cut are firmly joined.
  • an intermetallic compound for example, (Cu, Ni) 6 Sn 5
  • the intermetallic compound and the part to be cut are firmly joined.
  • an intermetallic compound for example, (Cu, Ni) 6 Sn 5
  • the intermetallic compound and the part to be cut are firmly joined.
  • the intermetallic compound When the intermetallic compound is formed, voids are generated. Further, the formed intermetallic compound becomes a brittle member whose ductility is lost.
  • a force for cutting is applied to the intermetallic compound that is firmly bonded to the part to be cut, cracks develop without deformation
  • the Cu alloy bonded to the intermetallic compound is originally a material having ductility, but cannot be extended because it is firmly bonded to the intermetallic compound, resulting in fracture. As a result, burrs and sagging are prevented from occurring on the cut surface of the Cu alloy constituting the part to be cut, and a clean cut surface can be obtained. Moreover, since it is not necessary to provide a V-groove in the part to be cut with this method, cutting can be performed satisfactorily even when the lead frame is thin. In addition, there is no problem due to shavings generated during V-groove processing.
  • the lead frame is provided with a mounting portion made of a Cu alloy, and a bonding material containing Sn or Sn alloy is applied to the mounting portion to mount an electronic component.
  • the electronic component and the mounting part can be joined with an intermetallic compound. Since the intermetallic compound formed of the Cu alloy and Sn or Sn alloy has a high melting point, the electronic component and the mounting part can be bonded by bonding having excellent heat resistance. Further, when the mounting portion is heated while pressurizing the electronic component, voids generated along with the formation of the intermetallic compound are pushed out by pressurization to become a dense intermetallic compound. Therefore, it becomes strong joining.
  • the method for manufacturing a semiconductor package of the present invention it is preferable to simultaneously perform the heating of the part to be cut and the heating while pressing the mounting part.
  • the reaction for forming the intermetallic compound in the mounting part and the part to be cut can be performed in the same process.
  • a dense intermetallic compound having a strong bonding force can be formed in a mounting portion that is heated while being pressurized, and a brittle intermetallic compound having a void can be formed in a portion to be cut that is heated without being pressurized. .
  • the electronic component is preferably a semiconductor chip.
  • the Cu alloy is preferably a Cu—Ni alloy or a Cu—Mn alloy. Further, a Cu—Ni alloy having a Ni content of 3 wt% or more and 15 wt% or less is more preferable. Cu—Ni alloys or Cu—Mn alloys can react rapidly with Sn or Sn alloys to form intermetallic compounds. An intermetallic compound is more reliably formed when the Ni content is a Cu—Ni alloy having a proportion of 3 wt% or more and 15 wt% or less.
  • the Cu alloy cutting method includes a step of applying a bonding material containing Sn or a Sn alloy to a cut portion made of a Cu alloy, and heating the cut portion to add Sn or Sn contained in the bonding material. It has the process of forming the intermetallic compound which has a space
  • the cut surface of the Cu alloy constituting the cut portion is formed by reacting the cut portion made of Cu alloy with Sn or the Sn alloy to form an intermetallic compound having voids and cutting the cut portion together with the intermetallic compound. As a result, it is possible to prevent burrs and sagging from occurring and to obtain a clean cut surface.
  • This cutting method can be preferably used as a cutting method for a material made of a Cu alloy regardless of its shape.
  • the present invention it is possible to manufacture a semiconductor package by preventing burrs and sagging from occurring on the cut surface when the lead frame is cut. Moreover, the cutting method of Cu alloy which can cut
  • FIG. 1 is a top view showing an example of a lead frame.
  • 2A to 2D are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor package of the present invention.
  • 3A to 3D are cross-sectional views schematically showing another example of the semiconductor package manufacturing method of the present invention.
  • 4A is a cross-sectional observation photograph of the mounting portion with a metal microscope
  • FIG. 4B is a cross-section observation photograph with the metal microscope before cutting the cut portion.
  • FIG. 5 is a cross-sectional observation photograph taken with a metallographic microscope after the cut portion of Example 1 was cut.
  • FIG. 6 is a cross-sectional observation photograph taken with a metallographic microscope after the cut portion of Comparative Example 1 is cut.
  • the present invention is not limited to the following configurations, and can be applied with appropriate modifications without departing from the scope of the present invention. Note that the present invention also includes a combination of two or more desirable configurations of the present invention described below.
  • FIG. 1 is a top view showing an example of a lead frame.
  • a lead frame having a cut portion made of a Cu alloy is prepared.
  • the lead frame 100 is provided with a mounting part 120 that is a part for mounting an electronic component, and a to-be-cut part 110 that is a part to be cut when singulated is provided at the end of each lead 130. ing.
  • the material of the part to be cut 110 is a Cu alloy.
  • the Cu alloy examples include a Cu—Ni alloy, a Cu—Mn alloy, a Cu—Al alloy, and a Cu—Cr alloy. Among these, a Cu—Ni alloy or a Cu—Mn alloy is preferable.
  • the Cu—Ni alloy is preferably a Cu—Ni alloy having a Ni ratio of 3 wt% or more and 30 wt% or less. For example, Cu-3Ni, Cu-5Ni, Cu-10Ni, Cu-15Ni, Cu-20Ni, Cu -25Ni or Cu-30Ni. Further, a Cu—Ni alloy having a Ni ratio of 3 wt% or more and 15 wt% or less is more preferable.
  • the Cu—Ni alloy includes alloys containing a third component such as a Cu—Ni—Co alloy, a Cu—Ni—Fe alloy, a Cu—Ni—Si alloy, a Cu—Ni—P alloy, and the like.
  • the Cu—Mn alloy is preferably a Cu—Mn alloy having a Mn ratio of 5 wt% or more and 30 wt% or less, such as Cu-5Mn, Cu-10Mn, Cu-15Mn, Cu-20Mn, Cu-25Mn, or Cu-30Mn.
  • the Cu—Al alloy is preferably a Cu—Al alloy having an Al ratio of 5% by weight or more and 10% by weight or less, and examples thereof include Cu-5Al and Cu-10Al.
  • the Cu—Cr alloy is preferably a Cu—Cr alloy having a Cr ratio of 5 wt% or more and 10 wt% or less, and examples thereof include Cu-5Cr and Cu-10Cr.
  • the Cu alloy may contain Mn and Ni simultaneously, such as Cu—Mn—Ni, and may contain a third component such as P.
  • Cu-3Ni indicates an alloy containing 3% by weight of Ni and the balance being Cu. The same applies to Mn.
  • the material constituting the lead frame may be a Cu alloy as a whole, or the part to be cut may be a Cu alloy and the other part may be another material. As will be described later, when the intermetallic compound is also formed in the mounting portion, the mounting portion is also preferably made of a Cu alloy.
  • the position of the cut portion provided in the lead frame which is a portion to be cut in the present invention, is not limited to the end of each lead, but is cut when a semiconductor package is manufactured using the lead frame. Any site may be used. For example, it may be the end of a suspension lead (a lead that supports a die pad) or a dam bar (a connecting portion that connects each lead).
  • 2A to 2D are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor package of the present invention.
  • 2A to 2D are cross-sectional views schematically showing only the periphery of the part to be cut 110 of the lead frame 100.
  • FIG. 1
  • a bonding material 30 containing Sn or an Sn alloy is applied to the part to be cut 110.
  • the Sn or Sn alloy include Sn alone, Cu, Ni, Ag, Au, Sb, Zn, Bi, In, Ge, Al, Co, Mn, Fe, Cr, Mg, Mn, Pd, Si, An alloy containing Sn and at least one selected from the group consisting of Sr, Te and P can be given.
  • Sn, Sn-3Ag-0.5Cu, Sn-3.5Ag, Sn-0.75Cu, Sn-58Bi, Sn-0.7Cu-0.05Ni, Sn-5Sb, Sn-2Ag-0.5Cu- 2Bi, Sn-57Bi-1Ag, Sn-3.5Ag-0.5Bi-8In, Sn-9Zn, or Sn-8Zn-3Bi is preferable.
  • Sn-3Ag-0.5Cu indicates an alloy containing 3% by weight of Ag, 0.5% by weight of Cu, and the balance being Sn.
  • the bonding material containing Sn or Sn alloy is preferably a paste containing Sn or Sn alloy, and a commercially available solder paste containing Sn or Sn alloy and a flux can be used as the paste.
  • the metal component contained in the paste does not need to be Sn or Sn alloy alone, but includes metal components such as Cu, Cu alloy, Ni, Ni alloy, Ag, Ag alloy, etc. with Sn or Sn alloy as a main component. You can leave. Examples of the method for applying the bonding material to the cut portion include screen printing and application using a dispenser.
  • the part to be cut is heated.
  • the temperature reaches the melting point of Sn or Sn alloy contained in the bonding material by heating, the Sn or Sn alloy is melted.
  • Sn or the Sn alloy and the Cu alloy (for example, Cu—Ni alloy) constituting the cut portion 110 react to generate an intermetallic compound 10 (for example, (Cu, Ni) 6 Sn 5 ).
  • This heating is preferably performed in a state in which the cut portion and the bonding material are not pressurized, and voids 11 are formed in the intermetallic compound 10 in accordance with the reaction in which the intermetallic compound 10 is generated.
  • the intermetallic compound 10 having the voids 11 therein becomes a brittle member whose ductility is lost. And the intermetallic compound 10 and the to-be-cut
  • the temperature rising rate is preferably 5 ° C./second or more, and more preferably 8 ° C./second or more.
  • intermetallic compound can be easily confirmed by observing the cross section including the part to be cut using a metal microscope.
  • an intermetallic compound such as (Cu, Ni) 6 Sn 5 is generated by performing composition analysis by energy dispersive X-ray analysis (EDX) or the like and crystal structure analysis by microscopic X-ray diffraction or the like. You can confirm that.
  • EDX energy dispersive X-ray analysis
  • the punch 40 is disposed on the intermetallic compound 10, the die 41 is disposed below the to-be-cut portion 110, and the to-be-cut portion 110 is cut together with the intermetallic compound 10 by punching. .
  • a crack develops without deformation.
  • disconnected part 110 joined with the intermetallic compound 10 is a material which has ductility originally, since it is joined firmly with the intermetallic compound 10, it cannot extend. Lead to breakage.
  • FIG. 2D shows a cut surface of the semiconductor package 1 obtained after cutting the part to be cut. There are no burrs or sagging on the cut surface, and the intermetallic compound 10 remains at each end of the cut portion.
  • the cutting method is not limited to punching, and examples include dicing and cutting with an ultrasonic cutter.
  • 3A to 3D are cross-sectional views schematically showing another example of the semiconductor package manufacturing method of the present invention.
  • 3A to 3D are cross-sectional views schematically showing only the periphery of the mounting portion 120 and the periphery of the cut portion 110 of the lead frame 100.
  • FIG. In the lead frame used in this embodiment, both the mounting portion and the cut portion are formed of a Cu alloy.
  • the entire lead frame may be a Cu alloy, and other parts may be other materials as long as the mounting portion and the cut portion are Cu alloys.
  • the Cu alloy constituting the mounting part and the Cu alloy constituting the part to be cut may have different compositions, but the entire lead frame is preferably a Cu alloy having the same composition. Since the preferable example of Cu alloy which comprises a mounting part is the same as what was mentioned as an example of Cu alloy which comprises a to-be-cut part, the detailed description is abbreviate
  • a bonding material 30 containing Sn or Sn alloy is applied to the mounting portion 120 and the cut portion 110.
  • the same bonding material may be applied to the mounting portion 120 and the cut portion 110, or different bonding materials may be applied.
  • Examples of the method of applying the bonding material to the mounting portion and the cut portion include screen printing, application using a dispenser, and the like. It is preferable to apply the bonding material to the mounting portion and the cut portion at the same time.
  • the electronic component 50 is mounted on the bonding material 30 on the mounting unit 120.
  • Examples of electronic components include semiconductor chips (IGBT (Insulated Gate Bipolar Transistor), MOSFETs (Metal Oxide Semiconductor Field Effect Transistor), Schottky barrier diodes, LEDs, etc.), capacitors, inductors, thermistors, resistors, varistors, resistors, and the like.
  • a semiconductor chip is preferable.
  • the present invention is particularly suitable for application to a semiconductor package in which a semiconductor chip is die-bonded.
  • a plating layer made of Au, Ag, Ni, Pd, Cu, or an alloy containing these metals may be formed on the surface of the electrode that contacts the bonding material in the electronic component.
  • a plating layer composed of a plurality of layers such as a layer may be formed.
  • the electrode in which the part which a joining material contacts in a mounting part was formed in the mounting part may be sufficient.
  • a plating layer made of Au, Ag, Ni, Pd, Cu or an alloy containing these metals may be formed on the surface of the electrode.
  • a plating layer composed of a plurality of layers such as a Ni / Au plating layer and a Ni / Pd / Au plating layer may be formed.
  • the plating layer which consists of Sn or Sn alloy may be formed. 3A to 3D, the electrode of the electronic component and the electrode of the mounting part are omitted.
  • the mounting part 120 is heated while the electronic component 50 is pressurized.
  • the temperature reaches the melting point of Sn or Sn alloy contained in the bonding material by heating, the Sn or Sn alloy is melted.
  • the Sn or Sn alloy and the Cu alloy (for example, Cu—Ni alloy) constituting the mounting portion 120 react to generate an intermetallic compound 20 (for example, (Cu, Ni) 6 Sn 5 ).
  • the voids are pushed out of the intermetallic compound, so that a dense intermetallic compound is generated.
  • the mounting part 120 and the electronic component 50 are firmly joined by the dense intermetallic compound 20. Since the intermetallic compound has a melting point higher than that of Sn or an Sn alloy, it is possible to achieve bonding with high heat resistance.
  • the intermetallic compound 10 having the voids 11 is formed by heating the part to be cut 110 without pressing the part to be cut 110 and the bonding material 30. As described above, the intermetallic compound having voids becomes a brittle member whose ductility is lost.
  • the process for facilitating the cutting is an efficient process as compared with the method of performing V-groove processing on the part to be cut.
  • 3C and 3D show a step of cutting the cut portion 110 together with the intermetallic compound 10 in the same manner as the steps shown in FIGS. 2C and 2D.
  • the cut portion is preferably cut after the electronic component 50 is molded with the resin 60.
  • the cut portion 110 is located outside the resin 60.
  • the electronic component 50 may be connected to the electrode of the lead frame by wire bonding or the like.
  • a Cu alloy constituting a part to be cut is reacted with Sn or a Sn alloy to form an intermetallic compound having voids, and the part to be cut is cut together with the intermetallic compound.
  • This is a method of cutting an alloy. If the material to cut
  • disconnect is Cu alloy, it can apply not only to the to-be-cut part of a lead frame, but the shape is not limited.
  • the materials described in the semiconductor package manufacturing method of the present invention can be preferably used.
  • Examples of the form of the Cu alloy include a round wire, a flat wire, a knitted wire, a bar material, a plate material, a foil, a circular tube, and a square tube.
  • the cutting method may be determined according to the shape or the like of the Cu alloy to be cut, and punching, shearing, dicing or the like can be suitably used.
  • the cutting method of Cu alloy of this invention includes the drilling to a member other than the cutting
  • Example 1 Printing solder paste A commercially available solder paste (SAC305: Sn-3Ag-0.5Cu) was applied by screen printing onto a lead frame made of Cu-10Ni and having a thickness of 200 ⁇ m. 5 mm square was printed on the mounting part for mounting the Si chip, and 5 mm ⁇ 1 mm was printed on the part to be cut at once. The thickness of the screen printing metal plate was 50 ⁇ m.
  • the Si chip having a thickness of 300 ⁇ m and 5 mm square was mounted on the solder paste applied to the mounting part of the Si chip.
  • the mounting surface of the Si chip was subjected to Au plating.
  • the lead frame mounted with the heated Si chip was heated at 260 ° C./30 seconds in a nitrogen atmosphere and heated at 260 ° C. for 5 minutes.
  • the mounting part was heated while applying a pressure of 10 MPa. It was 20 micrometers when the thickness of the intermetallic compound formed on the to-be-cut part after a heating was measured using the metal microscope.
  • Example 2 Each step was performed in the same manner as in Example 1 except that the thickness of the screen printing metal plate was changed to change the coating thickness of the solder paste.
  • Table 1 shows the thickness of the intermetallic compound formed on the part to be cut after heating.
  • Example 5 Each step was performed in the same manner as in Example 4 except that the material of the lead frame was changed as shown in Table 1.
  • Comparative Example 2 The material of the lead frame was Cu, and each process was performed in the same manner as in Example 1 without applying the solder paste to the part to be cut.
  • FIG. 4A is a cross-sectional observation photograph of the mounting portion with a metal microscope
  • FIG. 4B is a cross-section observation photograph with the metal microscope before cutting the cut portion.
  • Si means Si chip
  • Cu—Ni means lead frame
  • IMC means intermetallic compound.
  • FIG. 5 is a cross-sectional observation photograph with a metal microscope after cutting the cut portion of Example 1
  • FIG. 6 is a cross-section observation photograph with a metal microscope after cutting the cut portion of Comparative Example 1. It can be seen that the cut portion of Example 1 has a clean cut surface free from burrs and sagging, whereas the cut portion of Comparative Example 1 has burrs and sagging.
  • Table 1 summarizes the observation results of the lead frame material used in each of the examples and comparative examples, the solder paste, the thickness of the intermetallic compound formed on the cut portion after heating, and the cut surface.
  • the observation results of the cut surface were as follows. ⁇ : A beautiful cut surface free of burrs and sagging was obtained. X: Sag or burr

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

本発明の半導体パッケージの製造方法は、Cu合金からなる被切断部を有するリードフレームを準備する工程と、上記被切断部にSn又はSn合金を含む接合材料を塗布する工程と、上記被切断部を加熱することにより、上記接合材料に含まれるSn又はSn合金と上記被切断部を構成するCu合金とを反応させて空隙を有する金属間化合物を形成させる工程と、上記被切断部を上記金属間化合物と共に切断する工程を有することを特徴とする。

Description

半導体パッケージの製造方法及びCu合金の切断方法
本発明は、半導体パッケージの製造方法及びCu合金の切断方法に関する。
リードフレームを用いた半導体パッケージの製造工程においては、薄肉の金属板に半導体チップ等の電子部品を実装した後、個片化が行われる。
これまで、個片化を容易にするための方法として、例えば特許文献1に記載されるようにリードフレームを切断する箇所に予めダイサー等を用いてV溝加工を行っておく方法が知られていた。また、リードフレームを切断する方法としてはプレス加工による打ち抜きが知られており、例えば、樹脂封止された半導体パッケージをプレス金型の下型に載置した後、金型の上型を下降させる。これにより、上型のパンチと下型のダイによって打ち抜き加工を行い、リードフレームの切断を行う。
特開2007-189150号公報
特許文献1に記載の方法ではV溝加工を行う手間がかかる。また、V溝加工時に発生する削りかすが電子部品を実装する部分に付着してしまうと接合不良やショート不良という問題を引き起こす可能性がある。
さらに、V溝が形成されたリードフレームを用いて電子部品実装の工程を行うとリードフレームがV溝を起点として意図せずに変形してしまうことがある。また、リードフレームの厚さが薄い場合にはV溝の形成自体が難しくなり意図した位置での切断ができないことがある。一方、V溝を設けずにリードフレームを切断した場合には切断面にバリやダレが生じることがある。
なお、本明細書において、バリとは切断面の下面側に生じる突起を意味し、ダレとは切断面の上面側が切断刃の圧力により丸くなった部分を意味する。
本発明は上記の問題を解決するためになされたものであり、リードフレームの切断の際に切断面にバリやダレが生じることを防止して半導体パッケージを製造することを目的とする。
上記目的を達成するため、本発明の半導体パッケージの製造方法は、Cu合金からなる被切断部を有するリードフレームを準備する工程と、上記被切断部にSn又はSn合金を含む接合材料を塗布する工程と、上記被切断部を加熱することにより、上記接合材料に含まれるSn又はSn合金と上記被切断部を構成するCu合金とを反応させて空隙を有する金属間化合物を形成させる工程と、上記被切断部を上記金属間化合物と共に切断する工程を有することを特徴とする。
本発明の半導体パッケージの製造方法では、リードフレームの被切断部がCu合金からなり、上記被切断部にSn又はSn合金を含む接合材料を塗布した状態で加熱を行う。
加熱によりSn又はSn合金とCu合金が反応して金属間化合物(例えば(Cu,Ni)Sn)が形成され、金属間化合物と被切断部が強固に接合された状態となるが、金属間化合物が形成される際に空隙(ボイド)が生じる。また、形成された金属間化合物は延性が失われた脆い部材となる。
被切断部と強固に接合された上記金属間化合物に対して切断するための力を加えると、金属間化合物には変形を伴わずにクラックが進展する。金属間化合物と接合されているCu合金は本来は延性を有する材料であるが、金属間化合物と強固に接合されているために延びることができずに破断に至る。その結果、被切断部を構成するCu合金の切断面にバリやダレが生じることが防止されて、綺麗な切断面を得ることができる。
また、この方法であると被切断部にV溝を設ける必要がないので、リードフレームの厚さが薄い場合であっても切断を良好に行うことができる。また、V溝加工の際に発生する削りかすに起因する問題も起こらない。
本発明の半導体パッケージの製造方法では、上記リードフレームにはCu合金からなる実装部が設けられており、上記実装部にSn又はSn合金を含む接合材料を塗布して電子部品を搭載し、上記電子部品を加圧しながら上記実装部を加熱して、上記接合材料に含まれるSn又はSn合金と上記実装部を構成するCu合金とを反応させて緻密な金属間化合物を形成させる工程とをさらに有することが好ましい。
上記方法であると、電子部品と実装部の接合を金属間化合物によって行うことができる。Cu合金とSn又はSn合金により形成される金属間化合物は融点が高いため、電子部品と実装部の間を耐熱性に優れた接合により接合させることができる。また、電子部品を加圧しながら実装部を加熱すると、金属間化合物の形成に伴い発生する空隙が加圧により外に押し出されて緻密な金属間化合物となる。そのため、強固な接合となる。
本発明の半導体パッケージの製造方法では、上記被切断部の加熱と、上記実装部の加圧しながらの加熱を同時に行うことが好ましい。
被切断部の加熱と実装部の加熱を同時に行うことにより、実装部と被切断部で金属間化合物を形成させる反応を同じプロセスで行うことができる。
加圧しながら加熱する実装部では強固な接合力を有する緻密な金属間化合物を形成させることができ、加圧せずに加熱する被切断部では空隙を有する脆い金属間化合物を形成させることができる。
本発明の半導体パッケージの製造方法では、上記電子部品は、半導体チップであることが好ましい。
本発明の半導体パッケージの製造方法では、上記Cu合金は、Cu-Ni合金又はCu-Mn合金であることが好ましい。また、Niの割合が3重量%以上15重量%以下のCu-Ni合金であることがより好ましい。
Cu-Ni合金又はCu-Mn合金はSn又はSn合金と速やかに反応して金属間化合物を形成することができる。Niの割合が3重量%以上15重量%以下のCu-Ni合金であると金属間化合物がより確実に形成される。
本発明のCu合金の切断方法は、Cu合金からなる被切断部にSn又はSn合金を含む接合材料を塗布する工程と、上記被切断部を加熱することにより、上記接合材料に含まれるSn又はSn合金と上記被切断部を構成するCu合金とを反応させて空隙を有する金属間化合物を形成させる工程と、上記被切断部を上記金属間化合物と共に切断する工程を有することを特徴とする。
Cu合金からなる被切断部をSn又はSn合金と反応させて空隙を有する金属間化合物を形成させ、被切断部を金属間化合物と共に切断することにより、被切断部を構成するCu合金の切断面にバリやダレが生じることが防止されて、綺麗な切断面を得ることができる。
この切断方法は、Cu合金からなる材料の切断方法として、その形状を問わず好適に使用することができる。
本発明によれば、リードフレームの切断の際に切断面にバリやダレが生じることを防止して半導体パッケージを製造することができる。また、Cu合金からなる材料を切断面にバリやダレが生じることを防止して切断することが可能なCu合金の切断方法を提供することができる。
図1は、リードフレームの一例を示す上面図である。 図2A~図2Dは、本発明の半導体パッケージの製造方法の一例を模式的に示す断面図である。 図3A~図3Dは、本発明の半導体パッケージの製造方法の別の一例を模式的に示す断面図である。 図4(a)は実装部の金属顕微鏡による断面観察写真であり、図4(b)は、被切断部の切断前の金属顕微鏡による断面観察写真である。 図5は実施例1の被切断部の切断後の金属顕微鏡による断面観察写真である。 図6は比較例1の被切断部の切断後の金属顕微鏡による断面観察写真である。
以下、本発明の半導体パッケージの製造方法及びCu合金の切断方法について説明する。
しかしながら、本発明は、以下の構成に限定されるものではなく、本発明の要旨を変更しない範囲において適宜変更して適用することができる。
なお、以下において記載する本発明の個々の望ましい構成を2つ以上組み合わせたものもまた本発明である。
図1は、リードフレームの一例を示す上面図である。
本発明の半導体パッケージの製造方法では、Cu合金からなる被切断部を有するリードフレームを準備する。
リードフレーム100には、電子部品を実装するための部位である実装部120が設けられており、各リード130の末端に、個片化の際に切断する部位である被切断部110が設けられている。被切断部110の材質はCu合金となっている。
Cu合金としては、例えば、Cu-Ni合金、Cu-Mn合金、Cu-Al合金又はCu-Cr合金が挙げられる。これらの中では、Cu-Ni合金又はCu-Mn合金が好ましい。
Cu-Ni合金は、Niの割合が3重量%以上30重量%以下であるCu-Ni合金が好ましく、例えば、Cu-3Ni、Cu-5Ni、Cu-10Ni、Cu-15Ni、Cu-20Ni、Cu-25Ni、又は、Cu-30Niが挙げられる。また、Niの割合が3重量%以上15重量%以下であるCu-Ni合金がより好ましい。Cu-Ni合金には、Cu-Ni-Co合金、Cu-Ni-Fe合金、Cu-Ni-Si合金、Cu-Ni-P合金等のように第3成分を含む合金も含まれる。
Cu-Mn合金は、Mnの割合が5重量%以上30重量%以下であるCu-Mn合金が好ましく、例えば、Cu-5Mn、Cu-10Mn、Cu-15Mn、Cu-20Mn、Cu-25Mn、又は、Cu-30Mnが挙げられる。
Cu-Al合金は、Alの割合が5重量%以上10重量%以下であるCu-Al合金が好ましく、例えば、Cu-5Al、又は、Cu-10Alが挙げられる。
Cu-Cr合金は、Crの割合が5重量%以上10重量%以下であるCu-Cr合金が好ましく、例えば、Cu-5Cr、又は、Cu-10Crが挙げられる。
なお、Cu合金は、Cu-Mn-Ni等のようにMn及びNiを同時に含んでいてもよく、また、P等の第3成分を含んでいてもよい。
上記表記において、例えば、「Cu-3Ni」は、Niを3重量%含有し、残部をCuとする合金であることを示している。Mnについても同様である。
リードフレームを構成する材料は、全体がCu合金であってもよいし、被切断部がCu合金であって他の部分は他の材料であってもよい。後述するように実装部にも金属間化合物を形成させる場合には、実装部もCu合金からなることが好ましい。
また、本発明において切断する部位となる、リードフレームに設けられる被切断部の位置は、各リードの末端に限定されるものではなく、リードフレームを用いて半導体パッケージを製造する際に切断される部位であればよい。例えば、吊りリード(ダイパッドを支持するリード)の末端や、ダムバー(各リード間を接続する連結部)であってもよい。
図2A~図2Dは、本発明の半導体パッケージの製造方法の一例を模式的に示す断面図である。図2A~図2Dは、リードフレーム100の被切断部110の周囲のみを模式的に示す断面図である。
まず、図2Aに示すように、被切断部110にSn又はSn合金を含む接合材料30を塗布する。
Sn又はSn合金としては、例えば、Sn単体、又は、Cu、Ni、Ag、Au、Sb、Zn、Bi、In、Ge、Al、Co、Mn、Fe、Cr、Mg、Mn、Pd、Si、Sr、Te及びPからなる群より選ばれる少なくとも1種とSnとを含む合金が挙げられる。中でも、Sn、Sn-3Ag-0.5Cu、Sn-3.5Ag、Sn-0.75Cu、Sn-58Bi、Sn-0.7Cu-0.05Ni、Sn-5Sb、Sn-2Ag-0.5Cu-2Bi、Sn-57Bi-1Ag、Sn-3.5Ag-0.5Bi-8In、Sn-9Zn、又は、Sn-8Zn-3Biが好ましい。
上記表記において、例えば、「Sn-3Ag-0.5Cu」は、Agを3重量%、Cuを0.5重量%含有し、残部をSnとする合金であることを示している。
Sn又はSn合金を含む接合材料は、Sn又はSn合金を含むペーストであることが好ましく、上記ペーストとしては、Sn又はSn合金とフラックスとを含む、市販のソルダペーストを用いることができる。また、ペーストに含まれる金属成分は、Sn又はSn合金のみである必要はなく、Sn又はSn合金を主成分として、Cu、Cu合金、Ni、Ni合金、Ag、Ag合金などの金属成分を含んでいても良い。
被切断部に接合材料を塗布する方法としては、例えば、スクリーン印刷、ディスペンサーによる塗布等の方法が挙げられる。
次に、図2Bに示すように、被切断部を加熱する。加熱により温度が接合材料に含まれるSn又はSn合金の融点以上に達すると、Sn又はSn合金が溶融する。さらに加熱が続くと、Sn又はSn合金と被切断部110を構成するCu合金(例えばCu-Ni合金)とが反応して金属間化合物10(例えば(Cu,Ni)Sn)が生成する。
この加熱は被切断部及び接合材料を加圧しない状態で行われることが好ましく、金属間化合物10が生成する反応に伴い、金属間化合物10の中には空隙11が形成される。内部に空隙11を有する金属間化合物10は延性が失われた脆い部材となる。
そして、金属間化合物10と被切断部110が強固に接合された状態となる。
加熱時の昇温速度を速くすると、空隙を有する金属間化合物が形成されやすいため好ましい。昇温速度は5℃/秒以上であることが好ましく、8℃/秒以上であることがより好ましい。
金属間化合物が生成していることは、被切断部を含む断面を金属顕微鏡を用いて観察することによって簡易的に確認することができる。詳細には、エネルギー分散型X線分析(EDX)等による組成分析と、微小部X線回折等による結晶構造解析とを行うことによって、(Cu,Ni)Sn等の金属間化合物が生成したことを確認することができる。
次に、図2Cに示すように、金属間化合物10の上にパンチ40を配置し、被切断部110の下にダイ41を配置してパンチングにより被切断部110を金属間化合物10と共に切断する。
切断するための力がパンチ40により加えられた金属間化合物10には変形を伴わずにクラックが進展する。そして、金属間化合物10と接合されている被切断部110を構成するCu合金は本来は延性を有する材料であるが、金属間化合物10と強固に接合されているために延びることができずに破断に至る。その結果、被切断部110を構成するCu合金の切断面にバリやダレが生じることが防止されて、綺麗な切断面を得ることができる。
図2Dには、被切断部の切断後に得られる半導体パッケージ1の切断面を示している。切断面にはバリやダレが生じておらず、また、切断された部分のそれぞれの端部には金属間化合物10が残っている。
なお、切断の方法はパンチングに限定されるものではなく、ダイシングや超音波カッターでの切断等が挙げられる。
次に、本発明の別の形態として、実装部に電子部品を搭載する工程を含む形態について説明する。
図3A~図3Dは、本発明の半導体パッケージの製造方法の別の一例を模式的に示す断面図である。図3A~図3Dは、リードフレーム100の実装部120の周囲及び被切断部110の周囲のみを模式的に示す断面図である。
本実施形態で使用するリードフレームは、実装部と被切断部が共にCu合金で形成されている。リードフレーム全体がCu合金であってもよく、実装部と被切断部がCu合金であれば他の部分は他の材料であってもよい。実装部を構成するCu合金と被切断部を構成するCu合金は異なる組成であってもよいが、リードフレーム全体が同じ組成のCu合金であることが好ましい。
実装部を構成するCu合金の好ましい例は、被切断部を構成するCu合金の例として挙げたものと同じであるためその詳細な説明は省略する。
まず、図3Aに示すように、実装部120及び被切断部110にSn又はSn合金を含む接合材料30を塗布する。実装部120と被切断部110に同じ接合材料を塗布してもよいし、異なる接合材料を塗布してもよい。
実装部及び被切断部に接合材料を塗布する方法としては、例えば、スクリーン印刷、ディスペンサーによる塗布等の方法が挙げられる。実装部及び被切断部に対する接合材料の塗布は同時に行うことが好ましい。
実装部120の上の接合材料30に電子部品50を搭載する。
電子部品としては、例えば、半導体チップ(IGBT(Insulated Gate Bipolar Transistor)、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)、ショットキーバリアダイオード、LED等)、コンデンサ、インダクタ、サーミスタ、抵抗器、バリスタ、その他チップ状の積層フィルタ等が挙げられ、これらの中では半導体チップが好ましい。
本発明は、半導体チップをダイボンドするタイプの半導体パッケージに適用することに特に適している。
電子部品において接合材料が接触する電極の表面には、Au、Ag、Ni、Pd、Cu又はこれらの金属を含む合金からなるめっき層が形成されていてもよい。電極側から1層目がNi、2層目がAuであるNi/Auめっき層、電極側から1層目がNi、2層目がPd、3層目がAuであるNi/Pd/Auめっき層等の複数層からなるめっき層が形成されていてもよい。
また、実装部において接合材料が接触する部分が実装部に形成された電極であってもよい。この電極の表面にもAu、Ag、Ni、Pd、Cu又はこれらの金属を含む合金からなるめっき層が形成されていてもよい。Ni/Auめっき層、Ni/Pd/Auめっき層等の複数層からなるめっき層が形成されていてもよい。また、Sn又はSn合金からなるめっき層が形成されていてもよい。
なお、図3A~図3Dでは、電子部品の電極及び実装部の電極は省略している。
次に、図3Bに示すように、電子部品50を加圧しながら実装部120を加熱する。
加熱により温度が接合材料に含まれるSn又はSn合金の融点以上に達すると、Sn又はSn合金が溶融する。さらに加熱が続くと、Sn又はSn合金と実装部120を構成するCu合金(例えばCu-Ni合金)とが反応して金属間化合物20(例えば(Cu,Ni)Sn)が生成する。
電子部品を加圧しながら実装部を加熱することにより空隙が金属間化合物の外部に押し出されるため、緻密な金属間化合物が生成する。緻密な金属間化合物20により実装部120と電子部品50が強固に接合される。金属間化合物はSn又はSn合金よりも融点が高いため、耐熱性の高い接合とすることができる。
電子部品50を加圧しながら実装部120を加熱すると同時に、被切断部110も加熱することが好ましい。被切断部110の加熱を被切断部110及び接合材料30を加圧しない状態で行うことにより、空隙11を有する金属間化合物10が形成される。上述したように空隙を有する金属間化合物は延性が失われた脆い部材となる。
実装部と被切断部を同時に加熱することにより、リードフレームへの電子部品の実装と被切断部の切断を容易にするための脆い金属間化合物の形成を同時に行うことができるので、被切断部の切断を容易にするための工程が被切断部にV溝加工を行う方法等に比べて効率のよい工程となる。
図3C及び図3Dには、図2C及び図2Dに示す工程と同様に、被切断部110を金属間化合物10と共に切断する工程を示している。
被切断部の切断は、電子部品50を樹脂60でモールドした後に行うことが好ましい。被切断部110は、樹脂60の外側に位置することとなる。
なお、図面には示していないが、電子部品50は、ワイヤボンディング等によってリードフレームの電極と接続されていてもよい。
上記方法により、実装部に電子部品を金属間化合物により強固に接合すると共に、被切断部を切断面にバリやダレが生じることなく切断して、半導体パッケージ1を製造することができる。
次に、本発明のCu合金の切断方法について説明する。
本発明のCu合金の切断方法は、被切断部を構成するCu合金をSn又はSn合金と反応させて空隙を有する金属間化合物を形成させ、被切断部を金属間化合物と共に切断することによりCu合金を切断する方法である。切断する材料がCu合金であれば、リードフレームの被切断部に限らずに適用することができ、その形状は限定されない。
Cu合金及びSn又はSn合金としては、上記本発明の半導体パッケージの製造方法で説明した材料を好適に使用することができる。
Cu合金の形態としては、丸線、平角線、編線、棒材、板材、箔、円管、角管等を挙げることができる。
切断の方法は切断するCu合金の形状等によって決定すればよく、パンチング、シャーリング、ダイシング等を好適に用いることができる。
また、本発明のCu合金の切断方法には、部材を2つ以上に切り離す切断の他に、部材に対する穴あけも含まれる。穴あけ用パンチを接触させる部位に金属間化合物を形成させ、穴あけ部を金属間化合物と共に打ち抜いて穴あけすることにより、穴壁にバリやダレのない穴を形成することができる。
以下、本発明の半導体パッケージの製造方法をより具体的に開示した実施例を示す。なお、本発明は、これらの実施例のみに限定されるものではない。
(実施例1)
(1)ソルダペーストの印刷
Cu-10Niからなる厚さ200μmのリードフレーム上に、市販のソルダペースト(SAC305:Sn-3Ag-0.5Cu)をスクリーン印刷により塗布した。
Siチップを実装する実装部には5mm角、被切断部には5mm×1mmとして一度に印刷した。スクリーン印刷のメタル版の厚みは50μmとした。
(2)Siチップの実装
実装部に塗布したソルダペーストの上に、厚み300μm、5mm角のSiチップを実装した。なお、Siチップの実装面にはAuめっき処理を施した。
(3)加熱
Siチップを実装したリードフレームを窒素雰囲気にて260℃/30秒で昇温し、260℃で5分間加熱した。実装部には10MPaでの加圧を加えながら加熱した。
加熱後に被切断部の上に形成された金属間化合物の厚さを金属顕微鏡を用いて測定したところ20μmであった。
(4)切断
被切断部にパンチとダイをセットし、パンチングにより被切断部を切断した。
(実施例2~4)
スクリーン印刷のメタル版の厚さを変更してソルダペーストの塗布厚みを変更した他は実施例1と同様にして各工程を行った。加熱後に被切断部の上に形成された金属間化合物の厚さを表1に示した。
(実施例5~7)
リードフレームの材質を表1に示すように変更した他は実施例4と同様にして各工程を行った。
(比較例1)
被切断部にソルダペーストを塗布せずに実施例1と同様にして各工程を行った。
(比較例2)
リードフレームの材質をCuとし、被切断部にソルダペーストを塗布せずに実施例1と同様にして各工程を行った。
(比較例3)
リードフレームの材質をCuとした他は実施例4と同様にして各工程を行った。
(断面観察)
図4(a)は実装部の金属顕微鏡による断面観察写真であり、図4(b)は、被切断部の切断前の金属顕微鏡による断面観察写真である。SiはSiチップ、Cu-Niはリードフレーム、IMCは金属間化合物を意味する。これらはいずれも実施例4の写真である。
図4(a)に示すように実装部ではSiチップとリードフレームの間に緻密な金属間化合物(IMC)が形成されており、被切断部ではリードフレームの上に空隙を有する金属間化合物(IMC)が形成されているのが分かる。
図5は実施例1の被切断部の切断後の金属顕微鏡による断面観察写真であり、図6は比較例1の被切断部の切断後の金属顕微鏡による断面観察写真である。
実施例1の被切断部はバリやダレのない綺麗な切断面となっているのに対し、比較例1の被切断部にはバリやダレが発生していることが分かる。
表1に、各実施例及び比較例で使用したリードフレームの材質、ソルダペースト、加熱後に被切断部の上に形成された金属間化合物の厚さ及び切断面の観察結果をまとめて示す。
切断面の観察結果は、以下の通りとした。
○:バリやダレのない綺麗な切断面が得られた。
×:切断面にダレ若しくはバリが発生した、又は、被切断部を切断できない箇所があった。
Figure JPOXMLDOC01-appb-T000001
表1より、実施例1~実施例7ではバリやダレのない綺麗な切断面が得られることが確認された。
比較例1及び2では被切断部にソルダペーストを塗布していないため、Cu-10Ni合金又はCuをそのまま切断している。Cu-10Ni合金及びCuは延性のある材料であるため切断によりバリやダレが発生した。
比較例3ではリードフレームの材質がCuであるためソルダペーストを塗布して加熱しても金属間化合物が生成せず、リードフレームの上にはSnを含む金属成分が残っている。この金属成分は切断性の向上には寄与しないので切断によりバリやダレが発生した。
1 半導体パッケージ
10 金属間化合物(空隙を有する金属間化合物)
11 空隙
20 金属間化合物(緻密な金属間化合物)
30 接合材料
40 パンチ
41 ダイ
50 電子部品
60 樹脂
100 リードフレーム
110 被切断部
120 実装部
130 リード

Claims (7)

  1. Cu合金からなる被切断部を有するリードフレームを準備する工程と、
    前記被切断部にSn又はSn合金を含む接合材料を塗布する工程と、
    前記被切断部を加熱することにより、前記接合材料に含まれるSn又はSn合金と前記被切断部を構成するCu合金とを反応させて空隙を有する金属間化合物を形成させる工程と、
    前記被切断部を前記金属間化合物と共に切断する工程を有することを特徴とする半導体パッケージの製造方法。
  2. 前記リードフレームにはCu合金からなる実装部が設けられており、
    前記実装部にSn又はSn合金を含む接合材料を塗布して電子部品を搭載し、
    前記電子部品を加圧しながら前記実装部を加熱して、前記接合材料に含まれるSn又はSn合金と前記実装部を構成するCu合金とを反応させて緻密な金属間化合物を形成させる工程とをさらに有する請求項1に記載の半導体パッケージの製造方法。
  3. 前記被切断部の加熱と、前記実装部の加圧しながらの加熱を同時に行う請求項2に記載の半導体パッケージの製造方法。
  4. 前記電子部品は、半導体チップである請求項2又は3に記載の半導体パッケージの製造方法。
  5. 前記Cu合金は、Cu-Ni合金又はCu-Mn合金である請求項1~4のいずれかに記載の半導体パッケージの製造方法。
  6. 前記Cu合金は、Niの割合が3重量%以上15重量%以下のCu-Ni合金である請求項5に記載の半導体パッケージの製造方法。
  7. Cu合金からなる被切断部にSn又はSn合金を含む接合材料を塗布する工程と、
    前記被切断部を加熱することにより、前記接合材料に含まれるSn又はSn合金と前記被切断部を構成するCu合金とを反応させて空隙を有する金属間化合物を形成させる工程と、
    前記被切断部を前記金属間化合物と共に切断する工程を有することを特徴とするCu合金の切断方法。
PCT/JP2017/000475 2016-04-15 2017-01-10 半導体パッケージの製造方法及びCu合金の切断方法 WO2017179250A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018511883A JP6579264B2 (ja) 2016-04-15 2017-01-10 半導体パッケージの製造方法及びCu合金の切断方法
US16/157,295 US20190043735A1 (en) 2016-04-15 2018-10-11 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND METHOD FOR CUTTING Cu ALLOY

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016082240 2016-04-15
JP2016-082240 2016-04-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/157,295 Continuation US20190043735A1 (en) 2016-04-15 2018-10-11 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND METHOD FOR CUTTING Cu ALLOY

Publications (1)

Publication Number Publication Date
WO2017179250A1 true WO2017179250A1 (ja) 2017-10-19

Family

ID=60041609

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/000475 WO2017179250A1 (ja) 2016-04-15 2017-01-10 半導体パッケージの製造方法及びCu合金の切断方法

Country Status (3)

Country Link
US (1) US20190043735A1 (ja)
JP (1) JP6579264B2 (ja)
WO (1) WO2017179250A1 (ja)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6430994A (en) * 1988-04-19 1989-02-01 Smc Corp Connection type pipe joint
JPH05145004A (ja) * 1991-11-21 1993-06-11 Sony Corp 半導体装置の製造方法
JPH10150136A (ja) * 1996-11-15 1998-06-02 Hitachi Cable Ltd 半導体リードフレーム打抜き用条材及びその製造方法
JP2002171055A (ja) * 2000-12-01 2002-06-14 Hitachi Ltd 電子回路基板と電子部品及び電子回路装置並びにこれらの製造方法
JP2005228835A (ja) * 2004-02-12 2005-08-25 Hitachi Cable Ltd 半導体装置の製造方法
JP2005288458A (ja) * 2004-03-31 2005-10-20 Toshiba Corp 接合体、半導体装置、接合方法、及び半導体装置の製造方法
JP2012122095A (ja) * 2010-12-08 2012-06-28 Hitachi Cable Ltd 電気・電子部品用銅合金材

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01309947A (ja) * 1988-06-06 1989-12-14 Kobe Steel Ltd 半田の耐脆化性に優れる電気・電子部品用銅合金およびその製造方法
US20070045833A1 (en) * 2005-08-25 2007-03-01 Ting Zhong Copper bump barrier cap to reduce electrical resistance
WO2008041350A1 (en) * 2006-09-29 2008-04-10 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same joint
JP4917668B1 (ja) * 2010-12-29 2012-04-18 パナソニック株式会社 多層配線基板、多層配線基板の製造方法
KR102029802B1 (ko) * 2013-01-14 2019-10-08 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 장치
JP6352009B2 (ja) * 2013-04-16 2018-07-04 ローム株式会社 半導体装置
JP6173943B2 (ja) * 2014-02-20 2017-08-02 株式会社神戸製鋼所 耐熱性に優れる表面被覆層付き銅合金板条
JP6659950B2 (ja) * 2016-01-15 2020-03-04 富士通株式会社 電子装置及び電子機器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6430994A (en) * 1988-04-19 1989-02-01 Smc Corp Connection type pipe joint
JPH05145004A (ja) * 1991-11-21 1993-06-11 Sony Corp 半導体装置の製造方法
JPH10150136A (ja) * 1996-11-15 1998-06-02 Hitachi Cable Ltd 半導体リードフレーム打抜き用条材及びその製造方法
JP2002171055A (ja) * 2000-12-01 2002-06-14 Hitachi Ltd 電子回路基板と電子部品及び電子回路装置並びにこれらの製造方法
JP2005228835A (ja) * 2004-02-12 2005-08-25 Hitachi Cable Ltd 半導体装置の製造方法
JP2005288458A (ja) * 2004-03-31 2005-10-20 Toshiba Corp 接合体、半導体装置、接合方法、及び半導体装置の製造方法
JP2012122095A (ja) * 2010-12-08 2012-06-28 Hitachi Cable Ltd 電気・電子部品用銅合金材

Also Published As

Publication number Publication date
JPWO2017179250A1 (ja) 2018-12-20
US20190043735A1 (en) 2019-02-07
JP6579264B2 (ja) 2019-09-25

Similar Documents

Publication Publication Date Title
KR101528515B1 (ko) 접합 방법, 접합 구조, 전자 장치, 전자 장치의 제조 방법 및 전자 부품
JP5943066B2 (ja) 接合方法および接合構造体の製造方法
KR101285958B1 (ko) 땜납 합금 및 반도체 장치
TWI480382B (zh) A conductive material, a connecting method using the same, and a connecting structure
US20080122050A1 (en) Semiconductor Device And Production Method For Semiconductor Device
JP2014223678A5 (ja)
JP5943065B2 (ja) 接合方法、電子装置の製造方法、および電子部品
EP3192610B1 (en) Lead-free eutectic solder alloy comprising zinc as the main component and aluminum as an alloying metal
KR20140110926A (ko) 접합 방법, 접합 구조체 및 그 제조 방법
JP5231727B2 (ja) 接合方法
CN107848075B (zh) 接合用构件、接合用构件的制造方法和接合方法
JP6579264B2 (ja) 半導体パッケージの製造方法及びCu合金の切断方法
JP7386826B2 (ja) 成形はんだ及び成形はんだの製造方法
JP6887183B1 (ja) はんだ合金および成形はんだ
JP6724979B2 (ja) 接合体
WO2015190501A1 (ja) パッケージ封止方法及び封止用ペースト
JP5633815B2 (ja) Au−Sn合金はんだ
JP4677849B2 (ja) はんだ接合方法
US11618108B2 (en) Molded solder and molded solder production method
JP5744080B2 (ja) 接合体および半導体装置
JP2007090404A (ja) 接合体、半導体装置及び接合体の製造方法
JP2019135734A (ja) 接合用シート、その製造方法、半導体モジュール及びその製造方法
JP2017124426A (ja) Cu系基材とZn−Al系合金はんだとのクラッド材によって接合された接合体
JP2016097406A (ja) Au−Ag−Sn系はんだ合金
JP2017127897A (ja) Au−Ge系はんだ合金

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2018511883

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17782069

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17782069

Country of ref document: EP

Kind code of ref document: A1