WO2017177519A1 - 一种抑制有源沟道区光致漏电流产生的mos管及应用 - Google Patents

一种抑制有源沟道区光致漏电流产生的mos管及应用 Download PDF

Info

Publication number
WO2017177519A1
WO2017177519A1 PCT/CN2016/084131 CN2016084131W WO2017177519A1 WO 2017177519 A1 WO2017177519 A1 WO 2017177519A1 CN 2016084131 W CN2016084131 W CN 2016084131W WO 2017177519 A1 WO2017177519 A1 WO 2017177519A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
drain
metal
substrate
channel region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/084131
Other languages
English (en)
French (fr)
Inventor
刘召军
张珂
彭灯
王河深
莫炜静
刘熹
黄茂森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Yat Sen University
SYSU CMU Shunde International Joint Research Institute
Original Assignee
Sun Yat Sen University
SYSU CMU Shunde International Joint Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Yat Sen University, SYSU CMU Shunde International Joint Research Institute filed Critical Sun Yat Sen University
Priority to US16/092,763 priority Critical patent/US20190148231A1/en
Publication of WO2017177519A1 publication Critical patent/WO2017177519A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of optoelectronic devices, and more particularly to a MOS transistor and application for suppressing generation of photoinduced leakage current in an active channel region.
  • Addressable driver circuits are currently used in many ways.
  • the addressing mechanism there are generally two types, namely an active matrix and a passive matrix.
  • active matrices Compared to passive matrices, active matrices have better controllability, reduce crosstalk, and enable large-scale and high-resolution displays. And there is also the advantage of high energy utilization, which can achieve more grayscale for high quality display.
  • Active matrix displays have been in development for decades and have been used in applications such as active matrix liquid crystal displays, active matrix organic light emitting diode displays, and recently developed active matrix light emitting diode displays.
  • the commonly used 2T1C driving circuit is as shown in FIG. 1, and includes an addressing transistor T1, a driving transistor T2 and a storage capacitor.
  • the Vselect signal is used to control the gate T1 transistor.
  • the Vdata signal is transmitted to the gate of the T2 transistor to control the gate T2 transistor.
  • the LED anode is connected to VDD, so that it can work normally, that is, emit light.
  • the selection signal passes, the T1 transistor is turned off, but the LED is still required to continue to emit light.
  • the storage capacitor is used to maintain the potential of point A to ensure that sufficient current flows through the LED during an entire frame period.
  • the invention overcomes the phenomenon that the photocurrent excited by the illumination described above causes the reverse leakage current when the MOS transistor is in an off state, and firstly provides a MOS transistor for suppressing the generation of the photoinduced leakage current in the active channel region. Preparation.
  • the present invention also proposes a MOS transistor that suppresses generation of photoinduced leakage current in an active channel region.
  • the present invention also proposes an active addressing circuit using the MOS transistor that suppresses photo-induced leakage current generation in the active channel region.
  • a method for preparing a MOS transistor for suppressing generation of photoinduced leakage current in an active channel region wherein the preparation process is: forming a source and a drain at both ends of the substrate by ion implantation, and preparing a gate oxide in a middle portion of the upper surface of the substrate a layer, a polysilicon or a metal is deposited on the gate oxide layer to form a gate, the preparation process further includes: depositing an isolation layer over the gate, the source and the drain, and etching a contact hole over the source and the drain to Leading the source and the drain, depositing metal in the contact hole above the source and the drain, etching the metal in the contact hole on the drain to isolate the open source and the drain, and directly extending the metal in the contact on the source Covers the active channel region to block light.
  • the substrate is a silicon substrate.
  • the isolation layer is a SiO 2 isolation layer.
  • a MOS transistor for suppressing generation of photo-leakage current in an active channel region comprising a substrate, a gate insulating layer is deposited on a middle portion of the upper surface of the substrate, and a gate electrode is formed on the gate insulating layer by polysilicon or metal, and ion implantation is performed
  • a source and a drain are formed at both ends of the substrate, and an isolation layer is deposited on the gate, the source and the drain, and an isolation layer above the source and the drain is etched with a contact hole for extracting the source and the drain.
  • Metal is deposited in the contact holes on the source and the drain, and the metal in the contact hole on the drain is etched with isolation notches for isolating the source and the drain, and the metal on the source directly extends over the active channel region. .
  • the substrate is a silicon substrate.
  • the two isolation layers are SiO 2 isolation layers.
  • An active addressing circuit for applying the MOS transistor for suppressing photo-leakage current generation in an active channel region, wherein a MOS transistor in the active address circuit suppresses light leakage current in an active channel region MOS tube.
  • the technical solution of the present invention has the beneficial effects that the MOS tube proposed by the invention effectively blocks the light, suppresses the generation of the photocurrent, improves the off-state characteristic of the transistor, and improves the active seek. Address drive circuit performance.
  • Figure 1 is a schematic diagram of a 2T1C active drive circuit.
  • Figure 2 is a comparison of the transfer characteristics of the transistor under different conditions.
  • FIG 3 is a schematic cross-sectional view of a conventional MOS tube.
  • FIG. 4 is a three-dimensional structural view of the MOS transistor of the present invention.
  • FIG. 5 is a schematic view showing the planar structure of the MOS transistor according to the present invention.
  • Fig. 6 is a schematic diagram showing the setting of simulation basic parameters for simulating the MOS tube of the present invention.
  • Figure 7 is a graph showing the transfer characteristics of PMOS tubes of different X lengths based on the present invention.
  • Figure 8 is a PCB layout of an active addressing circuit that automatically eliminates photoinduced leakage current.
  • FIG. 9 is a comparison diagram of charge and discharge of a storage capacitor in an active drive circuit of an embodiment.
  • Figure 10 is a PCB layout of four sets of MOS tubes of different X lengths and comb gates.
  • Figure 11 is a comparative schematic diagram of the transfer characteristic curve based on Figure 10.
  • the present invention proposes to extend a certain length of metal from the source of the MOS transistor to cover the active channel of the MOS transistor. Above the area, thus playing the role of avoiding direct light from the channel.
  • This design effectively blocks the light and suppresses the generation of photocurrent, which not only improves the off-state characteristics of the transistor, but also improves the performance of the active address drive circuit.
  • Illumination excites additional electron-hole pairs in the active channel region of the MOS transistor, resulting in a large reverse leakage current when the transistor is turned off.
  • the illumination power is 1w
  • V ds is set to -1V
  • the gate voltage is gradually increased from -5V to 5V
  • the threshold voltage is -0.5V, that is, when it is greater than -0.5V, it is off state.
  • Figure 2 is a comparison of the transfer characteristics of the transistor under different conditions, from which the performance difference of the MOS tube under illumination conditions can be seen. It can be clearly seen from the figure that the leakage current in the off state is several orders of magnitude larger than that in the absence of light conditions, and the effect of visible light on the performance of the MOS tube is still very large. This proves our idea that the lighting conditions do have a huge impact on the leakage current when the MOS transistor is off. ring.
  • the present invention devises a novel MOS tube structure capable of blocking illumination and suppressing the generation of photoinduced leakage current in the active channel region.
  • MOS transistors use a doping process to generate source and drain electrodes across the silicon substrate, and the two electrodes are taken out by deposition of metal and appropriate etching. Thereafter, a gate oxide layer is deposited over the active channel region, and polysilicon is deposited thereon to form a gate.
  • Figure 3 The cross-sectional view is shown in Figure 3.
  • the metal portion of the source is extended to a certain length and covers the active channel region, thereby avoiding the active channel region directly exposed to the light to generate excess.
  • Photocurrent The specific practices are as follows:
  • a method for preparing a MOS transistor for suppressing generation of photo-induced leakage current in an active channel region wherein a preparation process is: forming a source and a drain at both ends of the substrate by ion implantation, and preparing a gate oxide layer in a middle portion of the upper surface of the substrate Depositing polysilicon or metal on the gate oxide layer to form a gate, depositing an isolation layer over the gate, the source and the drain, and etching a contact hole over the source and the drain to extract the source and the drain, Metal is deposited on the contact holes above the source and drain, the metal on the drain is etched to isolate the open source and drain, and the metal on the source extends directly over the active channel region to block light.
  • a preparation process is: forming a source and a drain at both ends of the substrate by ion implantation, and preparing a gate oxide layer in a middle portion of the upper surface of the substrate Depositing polysilicon or metal on the gate oxide layer to form a gate, depositing an isolation layer over the
  • a MOS transistor prepared by the above preparation method for suppressing photo-leakage current generation in an active channel region comprising a substrate, a gate insulating layer deposited on a middle portion of the upper surface of the substrate, and polysilicon or metal formed on the gate insulating layer a gate, a source and a drain formed at both ends of the substrate by ion implantation, an isolation layer deposited over the gate, the source and the drain, and an isolation layer above the source and the drain etched for extracting the source And a contact hole of the drain, metal is deposited in the contact hole on the source and the drain, and the metal in the contact hole on the drain is etched with an isolation gap for isolating the source and the drain, and the metal on the source directly extends Over the active channel region.
  • the present embodiment is simulated by software, and the basic parameters of the simulation are shown in FIG. 6.
  • the transistor is a silicon substrate, a phosphorus-doped PMOS, and a SiO2 layer and a metal portion are deposited thereon by a semiconductor process.
  • V GS is gradually increased from -5V to 5V
  • V DS is set to -1V
  • the PMOS transistor is illuminated with 1w power and 625nm wavelength illumination.
  • the transfer characteristic curve of the PMOS tube is as shown in FIG.
  • MCF Metal Cover Factor
  • an active addressing circuit capable of automatically eliminating photo-leakage current is also designed.
  • T1 is an address transistor
  • T2 is a drive transistor
  • C is a storage capacitor
  • Vselect is a selection signal that controls the T1 transistor switch
  • Vdata is a data signal that carries a signal that controls the LED to turn off.
  • an active addressing circuit that automatically eliminates photo-leakage current is designed based on the proposed new MOS. Its layout is shown in Figure 8:
  • Figure 8 shows the 2T1C circuit layout in a simplified manner.
  • the elongated region at 1 is a comb-shaped grid, and the lower portion is a metal coating.
  • the structure of the T1 transistor can be understood.
  • the storage capacitor is composed of two parts. The first part is composed of a passivation layer of SiO2 interposed between the source metal and the polysilicon. The second part is composed of a gate insulator (usually SiO2 or a high-k material) sandwiched between polysilicon and an active single crystal silicon layer. The LED pixel can be connected to the output part.
  • the circuit structure can successfully eliminate the influence of photocurrent, and the structure is simple and easy to implement. Below we will demonstrate the enhancement of the capacitor's ability to maintain potential by calculation and comparison.
  • the write period represents the period in which the T1 transistor is gated and the data signal reaches the T2 gate through T1, which is the charging portion for the capacitor.
  • the hold period represents that the selection signal has passed, the T1 transistor is turned off but the LED is still required to be illuminated. At this time, the T2 transistor is driven mainly by the potential held by the capacitor. If there is leakage current, the capacitor will appear as a gradual discharge.
  • V D stand for Vdata.
  • R on and R off are the channel resistances of the T1 transistor in the open and closed states, respectively.
  • the normal operation of the circuit requires:
  • V signal is the voltage at point A.
  • T writing and T holding are the write period and the hold period, respectively. This means that the shorter the write period and the longer the hold period, the better the effect of the drive circuit.
  • the design of the metal cap layer has little effect on the charging time and may cause several us delays.
  • the addition of the metal cap layer obviously makes the potential of the storage capacitor last longer, that is, greater than 40 ms. If there is no metal cover, the potential can only be maintained for a few ms, far from meeting the requirements for maintaining the LED's normal operation throughout the cycle. This shows that the design can enhance the ability of the storage capacitor to maintain the potential in the circuit, thereby improving the quality of the circuit.
  • the present invention proposes a novel MOS tube structure and circuit structure capable of eliminating the influence of photocurrent.
  • this structure will affect the original layout, and will even directly affect the aspect ratio of the device and cause other performance degradation. Therefore, appropriate trade-offs should be made between the overlay and the channel width to length ratio to achieve an optimal design.
  • the distance from the source to the drain fracture is defined as the length of the overlay (section X), and the effects of different overlay lengths are verified by analytical simulation.
  • the invention achieves the optimization result by designing a plurality of sets of MOS tubes with different X lengths and comb gate numbers, and takes several sets of data as shown in FIG. 10 and Table 1 as an example, and finally determines the number of comb gates to be 9 When the metal cover length is 5um, the device performance is the best.
  • the number of comb-shaped grids is 9 and the length of the metal-clad layer is 5 um, and the structure has the best performance.
  • the transistor with the structure shown in this scheme can effectively prevent the active channel region from being directly exposed to light and eliminate unnecessary photocurrent.
  • the source addressing circuit structure based on this can also effectively eliminate the phenomenon of photo leakage current.
  • the MOS transistor will have better off-state characteristics, the effect of the storage capacitor holding potential in the drive circuit will be better, the circuit performance will be more stable, and the LED will also exhibit better work quality.

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种抑制有源沟道区光致漏电流产生的MOS管及应用，其制备过程为：通过离子注入在衬底两端形成源极和漏极。在衬底上表面的中部制备栅氧化层，在栅氧化层上沉积多晶硅或金属形成栅极，在栅极、源极与漏极上方沉积隔离层，并在源极和漏极上方刻蚀出接触孔，以引出源极和漏极，在源极和漏极上方的接触孔上沉积金属，刻蚀漏极上的金属用于隔离开源极和漏极，而源极上的金属直接延伸覆盖过有源沟道区，起到遮挡光线的作用。该MOS管有效的遮挡了其上方射入的光线，抑制了光致漏电流的产生，既改善了晶体管的关态特性，也提高了有源寻址驱动电路的工作性能。

Description

一种抑制有源沟道区光致漏电流产生的MOS管及应用 技术领域
本发明涉及光电子器件领域，更具体地，涉及一种抑制有源沟道区光致漏电流产生的MOS管及应用。
背景技术
可寻址驱动电路目前已应用于诸多方面。在寻址机制上，一般分为两种，即有源矩阵和无源矩阵。相比于无源矩阵，有源矩阵拥有更好的可控性，可减少串扰，能实现大规模及高分辨率的显示。并且还有能量利用率高，可为高质量显示实现更多的灰度的优点。有源矩阵显示目前已经发展了数十年，并且已有诸多应用，比如有源矩阵液晶显示，有源矩阵有机发光二极管显示，以及最近正在发展的有源矩阵发光二极管显示等。
有源驱动电路有许多种，其中常用的2T1C驱动电路如图1所示，包括寻址晶体管T1，驱动晶体管T2和一个存储电容。Vselect信号用来控制选通T1晶体管，当T1晶体管打开，Vdata信号被传输至T2晶体管的栅极，控制选通T2管。当T2管打开时，LED阳极即与VDD相连，从而能够正常工作，即发光。当选择信号经过后，T1晶体管关闭，但还需要LED继续发光，此时存储电容就用来保持A点的电位，以保证在一整个帧周期内，都能有足够的电流流经LED。但是当有环境光存在时，尤其当该电路被应用于本身就具有比较高的发光强度LED显示时，光线将在MOS管有源沟道区激发额外的电子空穴对，导致MOS管关闭时，依然存在一定量的反向漏电流。当该漏电流较大时，将严重影响存储电容保持电位的能力，从而减小了相应LED的发光时间及发光质量。同理，T2管的关态漏电流也将带来预期之外的不利效果。这些都将降低基于该种有源驱动的电路的LED，LCD及OLED显示，或光通信设备的应用质量和效果。
发明内容
本发明为克服上述现有技术所述的光照激发的光电流导致MOS管关态时的反向漏电流增加的现象，首先提供一种抑制有源沟道区光致漏电流产生的MOS管的制备方法。
本发明还提出一种抑制有源沟道区光致漏电流产生的MOS管。
本发明还提出一种应用该抑制有源沟道区光致漏电流产生的MOS管的有源寻址电路。
为解决上述技术问题，本发明的技术方案如下：
一种抑制有源沟道区光致漏电流产生的MOS管的制备方法，其制备过程为：通过离子注入在衬底两端形成源极和漏极，在衬底上表面的中部制备栅氧化层，在栅氧化层上沉积多晶硅或金属形成栅极，该制备过程还包括：在栅极、源极与漏极上方沉积隔离层，并在源极和漏极上方刻蚀出接触孔，以引出源极和漏极，在源极和漏极上方的接触孔中沉积金属，刻蚀漏极上接触孔中的金属用于隔离开源极和漏极，而源极上接触中的金属直接延伸覆盖过有源沟道区，起到遮挡光线的作用。
优选的，所述衬底为硅衬底。
优选的，所述隔离层为SiO2隔离层。
一种抑制有源沟道区光致漏电流产生的MOS管，包括衬底，衬底上表面的中部沉积有栅绝缘层，在栅绝缘层上有多晶硅或金属形成栅极，通过离子注入在衬底两端形成的源极和漏极，在栅极、源极与漏极上方沉积有隔离层，源极和漏极上方的隔离层刻蚀有用于引出源极和漏极的接触孔，在源极和漏极上的接触孔中沉积有金属，漏极上接触孔中金属刻蚀有用于隔离源极和漏极的隔离缺口，源极上的金属直接延伸覆盖过有源沟道区。
优选的，所述衬底为硅衬底。
优选的，所述二隔离层为SiO2隔离层。
一种应用所述抑制有源沟道区光致漏电流产生的MOS管的有源寻址电路，所述有源寻址电路中的MOS管为抑制有源沟道区光致漏电流产生的MOS管。
与现有技术相比，本发明技术方案的有益效果是：本发明提出的MOS管有效的遮挡了光线，抑制了光电流的产生，既改善了晶体管的关态特性，也提高了有源寻址驱动电路的工作性能。
附图说明
图1为2T1C有源驱动电路示意图。
图2为对晶体管不同条件下转移特性曲线的对比图。
图3为传统MOS管的截面示意图。
图4为本发明所述MOS管的三维结构图。
图5为本发明所述MOS管的平面结构示意图。
图6为对本发明MOS管进行仿真的仿真基本参数设置示意图。
图7为基于本发明的不同X长度的PMOS管的转移特性曲线图。
图8为自动消除光致漏电流的有源寻址电路的PCB版图。
图9为实施例有源驱动电路中存储电容充放电对比图。
图10为四组不同X长度和梳状栅个数的MOS管进行的PCB版图。
图11为基于图10的转移特性曲线的对比示意图。
具体实施方式
附图仅用于示例性说明，不能理解为对本专利的限制；为了更好说明本实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；
对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。下面结合附图和实施例对本发明的技术方案做进一步的说明。
针对现有技术中提到的光照激发的光电流导致MOS管关态时的反向漏电流增加的现象，本发明提出从MOS管源极引伸出一定长度金属，覆盖在MOS管有源沟道区上面，从而起到避免光线直射沟道的效果。
该种设计有效的遮挡了光线，抑制了光电流的产生，既改善了晶体管的关态特性，也提高了有源寻址驱动电路的工作性能。且金属覆盖层越长，抑制效果越好，但是却会降低器件的沟道宽长比，从而降低器件开态时的特性。所以应在覆盖层和沟道宽长比之间做出合适的取舍，从而达到最优化设计。
经过大量的实验及研究发现，光照会影响MOS晶体管性能：
光照会在MOS晶体管有源沟道区激发出额外的电子空穴对，从而使晶体管在关闭状态时，也存在着较大的反向漏电流。我们通过软件仿真验证了该想法。
我们分别测试了无光条件下，以及蓝光，红光，绿光照射时，沟道长度为2um的PMOS晶体管的Ids。光照功率为1w，并设置Vds为-1V，栅极电压由-5V逐渐增加到5V，阈值电压为-0.5V，即当其大于-0.5V时即为关闭状态。
图2则为对晶体管不同条件下转移特性曲线的对比，由此可看出MOS管在光照条件下性能的差别。从图中可清晰看出，有光条件下关态的漏电流要比无光条件时大几个数量级，可见光照对MOS管性能的影响还是非常大的。由此证明了我们的想法，光照条件确实会对MOS晶体管关闭状态时的漏电流有巨大影 响。
基于上述发现，本发明设计了一种能遮挡光照，抑制有源沟道区光致漏电流产生的新型MOS管结构。
传统MOS管是利用掺杂工艺在硅衬底两端生成源极与漏极，并通过沉积金属以及适当的刻蚀将这两极引出。之后，在有源沟道区之上沉积栅氧化层，再将多晶硅沉积其上形成栅极。截面图如图3所示。
而本发明所提出的新型结构与传统的主要区别是将源极的金属部分延伸一定长度，覆盖在有源沟道区上面，从而避免了有源沟道区直接暴露在光照下而产生多余的光电流。具体做法如下：
一种抑制有源沟道区光致漏电流产生的MOS管制备方法，其制备过程为：通过离子注入在衬底两端形成源极和漏极，在衬底上表面的中部制备栅氧化层，在栅氧化层上沉积多晶硅或金属形成栅极，在栅极、源极与漏极上方沉积隔离层，并在源极和漏极上方刻蚀出接触孔，以引出源极和漏极，在源极和漏极上方的接触孔上沉积金属，刻蚀漏极上的金属用于隔离开源极和漏极，而源极上的金属直接延伸覆盖过有源沟道区，起到遮挡光线的作用。
采用上述制备方法制备得到的一种抑制有源沟道区光致漏电流产生的MOS管，包括衬底，衬底上表面的中部沉积有栅绝缘层，在栅绝缘层上有多晶硅或金属形成栅极，通过离子注入在衬底两端形成的源极和漏极，在栅极、源极与漏极上方沉积有隔离层，源极和漏极上方的隔离层刻蚀有用于引出源极和漏极的接触孔，在源极和漏极上的接触孔中沉积有金属，漏极上接触孔中金属刻蚀有用于隔离源极和漏极的隔离缺口，源极上的金属直接延伸覆盖过有源沟道区。
这样的结构既不会加入其它多余材料而引起无法预期的其他性能改变，也能达到良好的遮光效果，且简便易行，便于实现。具体三维、平面结构图如图4、5所示，其中箭头表示光照方向，X表示金属覆盖层的长度。
为证明该该MOS管结构的有效性，本实施例用软件进行仿真，仿真的基本参数如图6所示。采用晶体管为硅衬底，磷掺杂的PMOS，并通过半导体工艺对其沉积SiO2层和金属部分。仿真时，VGS从-5V逐渐增加至5V，VDS设置为-1V，并使用1w功率，波长为625nm的光照对此PMOS晶体管进行光照。该PMOS管的转移特性曲线如图7所示。
其中，MCF(Metal Cover Factor)为金属覆盖层的长度与沟道长度的比值， 即：
Figure PCTCN2016084131-appb-000001
该参数作为一个更具有相对借鉴意义的参考指数，更形象的表示出覆盖层长度与有源沟道长度的关系。从图7中可以看出，无光条件下，漏电流大小为2.5×10-13A，有光照却无金属覆盖层时(MCF＝0％)，漏电流约为1×10-8A，增加了几个数量级。而当有一定长度的金属覆盖层后，光照下的激发的光电流有明显的减少，且MCF指数越高，光电流抑制效果越好。说明本发明确实能有有效的消除光电流的影响，提高晶体管性能。
本实施例中还设计了一种可以自动消除光致漏电流的有源寻址电路。
本实施例是基于背景部分已介绍了传统2T1C电路，在该电路中T1为寻址晶体管，T2为驱动晶体管，C为存储电容。Vselect为选择信号，控制T1晶体管开关，Vdata为数据信号，承载着控制LED亮灭的信号。在本实例中，基于所提出的新的MOS设计了一种可以自动消除光致漏电流的有源寻址电路。其版图如图8所示：
图8已简洁的显示了2T1C电路版图。对于晶体管T2，①处细长区域即为梳状栅，其下方的②处部分为金属覆盖层。同理可理解T1晶体管的结构。而在该种电路结构中，存储电容由两部分组成。第一部分为源极金属和多晶硅之间夹着SiO2钝化层构成。第二部分为多晶硅与有源单晶硅层之间夹着栅极绝缘物(通常为SiO2或者高k材料)构成。LED像素接与输出部分即可。
该种电路结构能成功的消除光电流影响，且结构简便易实现。下面我们将通过计算与对比，来展示该新型电路对电容保持电位能力的增强效果。
我们分别从两方面进行讨论。写入时期代表着T1晶体管被选通，数据信号通过T1到达T2栅极的时期，此时对于电容来说即为充电部分。保持时期代表着选择信号已经通过，T1晶体管关闭但仍需LED发光，此时主要靠电容保持的电位来驱动T2晶体管。若存在漏电流，则电容将表现为逐渐放电。
令VD代表Vdata。当像素被选中时，写入电压和保持电压满足：
Figure PCTCN2016084131-appb-000002
其中，τon＝RonCholding   τoff＝RoffCholding
Ron和Roff为T1晶体管分别在打开和关闭状态时的沟道电阻。而电路正常运行要求：
Figure PCTCN2016084131-appb-000003
Figure PCTCN2016084131-appb-000004
其中，Vsignal即为A点的电压。Twriting和Tholding分别是写入期时间和保持期时间。这意味着，写入期时间越短，保持期时间越长，该驱动电路的效果越好。
我们通过实验测得有金属覆盖层以及无金属覆盖层的晶体管开态电流Ids分别是：2.75×10-5A和3.11×10-5A,而关态电流Ids则是：3.43×10-13A和6.94×10-9A，实验所用的总电容为15.6pf。最终，应用该设计前后的存储电容充放电对比为图9所示。
由图9可以看出，金属覆盖层的设计对充电时间的影响并不大，可能会引起几个us的延迟。但是在MOS管关闭状态时，加入金属覆盖层后明显能使存储电容的电位保持时间更长，即大于40ms。若无金属覆盖层，该电位只能保持几个ms，远远不能达到维持LED在整个周期内正常工作的要求。由此说明，该设计确实能增强电路中存储电容保持电位的能力，从而提高电路的工作质量等。
本发明提出了能消除光电流影响的新型MOS管结构和电路结构。由于金属覆盖层越长，抑制效果越好，但是因此器件漏极与栅极之间的距离也越大。尤其当版图的面积有限，这种结构将会影响原有的布局，甚至将直接影响器件的宽长比而导致其他性能的下降。所以应在覆盖层和沟道宽长比之间做出合适的取舍，从而达到最优化设计。
定义源极至漏极断口的距离为覆盖层长度(X部分)，通过分析仿真来验证不同覆盖层长度的影响。
本发明通过设计多组不同X长度和梳状栅个数的MOS管进行对比，来达到最优化结果，以如图10，表1几组数据为例，最终测得梳状栅个数为9，金属覆盖层长度为5um时，器件性能最好。
表1
Figure PCTCN2016084131-appb-000005
其转移特性曲线的对比如图11所示。
由此看以看出梳状栅个数为9，金属覆盖层长度为5um时，该结构的工作性能最好。
采用本方案所示结构的晶体管，可以有效的避免有源沟道区直接暴露在光线下，消除不必要的光电流。而以此为基础的源寻址电路结构也可有效的消除光致漏电流现象。此时，MOS晶体管将有更好的关态特性，驱动电路中存储电容保持电位的效果也会更好，电路性能更加稳定，LED也将呈现出更好的工作质量。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (7)

  1. 一种抑制有源沟道区光致漏电流产生的MOS管的制备方法，其制备过程为：通过离子注入在衬底两端形成源极和漏极，在衬底上表面的中部制备栅氧化层，在栅氧化层上沉积多晶硅或金属形成栅极，其特征在于，该制备过程还包括：在栅极、源极与漏极上方沉积隔离层，并在源极和漏极上方刻蚀出接触孔，以引出源极和漏极，在源极和漏极上方的接触孔中沉积金属，刻蚀漏极上接触孔中的金属用于隔离开源极和漏极，而源极上接触中的金属直接延伸覆盖过有源沟道区，起到遮挡光线的作用。
  2. 根据权利要求1所述的抑制有源沟道区光致漏电流产生的MOS管制备方法，其特征在于，所述衬底为硅基材料衬底，玻璃石英衬底或氮化物衬底。
  3. 根据权利要求1所述的抑制有源沟道区光致漏电流产生的MOS管制备方法，其特征在于，所述栅氧化层为SiO2、HfO、Al2O3或ZrO氧化物，隔离层为SiO2或SiNx隔离层。
  4. 一种抑制有源沟道区光致漏电流产生的MOS管，包括衬底，衬底上表面的中部沉积有栅绝缘层，在栅绝缘层上有多晶硅或金属形成栅极，通过离子注入在衬底两端形成的源极和漏极，其特征在于，在栅极、源极与漏极上方沉积有隔离层，源极和漏极上方的隔离层刻蚀有用于引出源极和漏极的接触孔，在源极和漏极上的接触孔中沉积有金属，漏极上接触孔中金属刻蚀有用于隔离源极和漏极的隔离缺口，源极上的金属直接延伸覆盖过有源沟道区。
  5. 根据权利要求4所述的抑制有源沟道区光致漏电流产生的MOS管，其特征在于，所述衬底为硅基材料衬底，玻璃石英衬底或氮化物衬底。
  6. 根据权利要求4所述的抑制有源沟道区光致漏电流产生的MOS管，其特征在于，所述栅氧化层为SiO2、HfO、Al2O3或ZrO氧化物，隔离层为SiO2或SiNx隔离层。
  7. 一种应用权利要求4至6任一项所述抑制有源沟道区光致漏电流产生的MOS管的有源寻址电路，其特征在于，所述有源寻址电路中的MOS管为抑制有源沟道区光致漏电流产生的MOS管。
PCT/CN2016/084131 2016-04-12 2016-05-31 一种抑制有源沟道区光致漏电流产生的mos管及应用 Ceased WO2017177519A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/092,763 US20190148231A1 (en) 2016-04-12 2016-05-31 Mos transistor for suppressing generation of photo-induced leakage current in active channel region and application thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610227996.9 2016-04-12
CN201610227996.9A CN105742364A (zh) 2016-04-12 2016-04-12 一种抑制有源沟道区光致漏电流产生的mos管及应用

Publications (1)

Publication Number Publication Date
WO2017177519A1 true WO2017177519A1 (zh) 2017-10-19

Family

ID=56255326

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/084131 Ceased WO2017177519A1 (zh) 2016-04-12 2016-05-31 一种抑制有源沟道区光致漏电流产生的mos管及应用

Country Status (3)

Country Link
US (1) US20190148231A1 (zh)
CN (1) CN105742364A (zh)
WO (1) WO2017177519A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000914A (zh) * 2006-01-11 2007-07-18 爱普生映像元器件有限公司 显示装置
CN102184965A (zh) * 2010-01-15 2011-09-14 佳能株式会社 驱动晶体管的方法和包含由该方法驱动的晶体管的器件
CN102487041A (zh) * 2010-12-02 2012-06-06 京东方科技集团股份有限公司 阵列基板及其制造方法和电子纸显示器

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368581A (en) * 1976-12-01 1978-06-19 Hitachi Ltd Semiconductor device
US4523189A (en) * 1981-05-25 1985-06-11 Fujitsu Limited El display device
JPS58137256A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 絶縁ゲ−ト半導体装置
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
US5404326A (en) * 1992-06-30 1995-04-04 Sony Corporation Static random access memory cell structure having a thin film transistor load
US5838038A (en) * 1992-09-22 1998-11-17 Kabushiki Kaisha Toshiba Dynamic random access memory device with the combined open/folded bit-line pair arrangement
EP0606758B1 (en) * 1992-12-30 2000-09-06 Samsung Electronics Co., Ltd. Method of producing an SOI transistor DRAM
JPH07302912A (ja) * 1994-04-29 1995-11-14 Semiconductor Energy Lab Co Ltd 半導体装置
US5624863A (en) * 1995-07-17 1997-04-29 Micron Technology, Inc. Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
JPH09191088A (ja) * 1995-11-09 1997-07-22 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
JP3433101B2 (ja) * 1998-06-03 2003-08-04 三洋電機株式会社 表示装置
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
TW525216B (en) * 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
US7087975B2 (en) * 2000-12-28 2006-08-08 Infineon Technologies Ag Area efficient stacking of antifuses in semiconductor device
US6555883B1 (en) * 2001-10-29 2003-04-29 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
US6552597B1 (en) * 2001-11-02 2003-04-22 Power Integrations, Inc. Integrated circuit with closely coupled high voltage output and offline transistor pair
KR100858297B1 (ko) * 2001-11-02 2008-09-11 삼성전자주식회사 반사-투과형 액정표시장치 및 그 제조 방법
JP4088190B2 (ja) * 2002-05-21 2008-05-21 セイコーエプソン株式会社 電気光学装置及び電子機器
TWI338346B (en) * 2002-09-20 2011-03-01 Semiconductor Energy Lab Display device and manufacturing method thereof
JP2005250448A (ja) * 2004-02-05 2005-09-15 Sharp Corp 電子素子、表示素子及びその製造方法
JP2006066573A (ja) * 2004-08-26 2006-03-09 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP4844133B2 (ja) * 2006-01-25 2011-12-28 ソニー株式会社 半導体装置
US8921186B2 (en) * 2008-05-15 2014-12-30 Great Wall Semiconductor Corporation Semiconductor device and method of forming high voltage SOI lateral double diffused MOSFET with shallow trench insulator
US9041202B2 (en) * 2008-05-16 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
KR101463580B1 (ko) * 2008-06-03 2014-11-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US7851857B2 (en) * 2008-07-30 2010-12-14 Freescale Semiconductor, Inc. Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications
US20130020632A1 (en) * 2011-07-18 2013-01-24 Disney Donald R Lateral transistor with capacitively depleted drift region
JP5848680B2 (ja) * 2011-11-22 2016-01-27 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6048026B2 (ja) * 2012-09-20 2016-12-21 富士通株式会社 電源回路及び電源装置
CN103383946B (zh) * 2013-07-12 2016-05-25 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
US9306014B1 (en) * 2013-12-27 2016-04-05 Power Integrations, Inc. High-electron-mobility transistors
JP6310831B2 (ja) * 2014-09-26 2018-04-11 株式会社ジャパンディスプレイ センサ付き表示装置及び表示装置の制御方法
US9721634B2 (en) * 2015-04-27 2017-08-01 Qualcomm Incorporated Decoupling of source line layout from access transistor contact placement in a magnetic tunnel junction (MTJ) memory bit cell to facilitate reduced contact resistance
CN106558592B (zh) * 2015-09-18 2019-06-18 鸿富锦精密工业（深圳）有限公司 阵列基板、显示装置及阵列基板的制备方法
CN205810819U (zh) * 2016-04-12 2016-12-14 中山大学 抑制有源沟道区光致漏电流产生的mos管及有源寻址电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000914A (zh) * 2006-01-11 2007-07-18 爱普生映像元器件有限公司 显示装置
CN102184965A (zh) * 2010-01-15 2011-09-14 佳能株式会社 驱动晶体管的方法和包含由该方法驱动的晶体管的器件
CN102487041A (zh) * 2010-12-02 2012-06-06 京东方科技集团股份有限公司 阵列基板及其制造方法和电子纸显示器

Also Published As

Publication number Publication date
US20190148231A1 (en) 2019-05-16
CN105742364A (zh) 2016-07-06

Similar Documents

Publication Publication Date Title
CN103219391B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN107068770B (zh) 一种薄膜晶体管及其制备方法、阵列基板、显示面板
JP5600255B2 (ja) 表示装置、スイッチング回路および電界効果トランジスタ
CN103500754B (zh) Oled显示面板及其制作方法、显示装置
KR101850662B1 (ko) 고해상도 amoled 백플레인의 제조방법
CN105702623B (zh) Tft阵列基板的制作方法
CN104637950A (zh) 薄膜晶体管驱动背板及其制造方法
CN103633110A (zh) 有机发光显示器件及其制造方法
CN105336746B (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
US11114630B2 (en) Display panel, manufacturing method thereof, display device
KR101788488B1 (ko) 박막 트랜지스터 어레이 기판의 제조방법
CN106711087A (zh) 薄膜晶体管的制作方法
CN105324848A (zh) 作为显示装置的像素元件的氧化物半导体晶体管及其制造方法
CN103296058B (zh) 显示面板及其制作方法
US20210408063A1 (en) Array substrate and method of manufacturing same
CN109003943B (zh) 一种阵列基板及其制备方法
JP6901070B2 (ja) Ｔｆｔバックプレーンの製造方法及びｔｆｔバックプレーン
CN104157609A (zh) Tft基板的制作方法及其结构
CN107819012A (zh) N型薄膜晶体管及其制备方法、oled显示面板及其制备方法
CN205810819U (zh) 抑制有源沟道区光致漏电流产生的mos管及有源寻址电路
US10802363B2 (en) Array substrate and manufacturing method therefor, display device and driving method therefor
WO2017177519A1 (zh) 一种抑制有源沟道区光致漏电流产生的mos管及应用
CN104022129A (zh) 显示器件的阵列基板及其制备方法
CN104460165B (zh) 一种液晶显示器和液晶面板以及阵列基板
CN105405894B (zh) 薄膜晶体管及其制造方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16898334

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16898334

Country of ref document: EP

Kind code of ref document: A1