WO2017161678A1 - 一种移位寄存器及其驱动方法、相应的栅极驱动电路和显示装置 - Google Patents

一种移位寄存器及其驱动方法、相应的栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017161678A1
WO2017161678A1 PCT/CN2016/083888 CN2016083888W WO2017161678A1 WO 2017161678 A1 WO2017161678 A1 WO 2017161678A1 CN 2016083888 W CN2016083888 W CN 2016083888W WO 2017161678 A1 WO2017161678 A1 WO 2017161678A1
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Prior art keywords
thin film
film transistor
pull
shift register
gate
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Ceased
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PCT/CN2016/083888
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English (en)
French (fr)
Inventor
陈沫
赵剑
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/526,315 priority Critical patent/US10127995B2/en
Publication of WO2017161678A1 publication Critical patent/WO2017161678A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a corresponding gate driving circuit, and a display device.
  • the display panel of the conventional liquid crystal display device is composed of an array substrate and a counter substrate sandwiching a liquid crystal layer.
  • the array substrate is provided with a vertical and horizontal array pixel matrix, wherein the pixel structure of the array substrate comprises a thin film transistor (TFT) and
  • TFT thin film transistor
  • the pixel electrode, the pixel electrode and the common electrode form a capacitance; the TFT inputs different voltages to the pixel electrode under the control of the intersecting data lines and the scanning lines, thereby forming different electric fields on the liquid crystal capacitor, and the electric field controls the liquid crystal deflection to realize the display function of the panel.
  • the GOA technology is a technology that integrates a scanning circuit on an array substrate. Each GOA unit is scanned as a shift register. The signal is sequentially transmitted to the next GOA unit, and the TFT switch is turned on line by line to complete the data signal input of the pixel unit.
  • the gate driving circuit of the GOA technology includes a plurality of signal lines for supplying signals and a shift register for storing signal data. As shown in FIG. 1, for convenience of explanation, the signals transmitted by the signal lines mark the signal lines as follows:
  • the signal line includes: a trigger signal line for inputting an initial trigger signal STV to the shift register; and a low signal line for inputting a low level signal VSS to the shift register; the first clock signal line and the second clock signal line, It is used to provide a complementary clock pulse signal to the shift register, that is, the first clock signal CLK and the second clock signal CLKB.
  • the shift register includes: a pull-up driving unit, a pull-up unit, a pull-down driving unit, a pull-down unit, and a reset unit;
  • the pull-up driving unit is connected to the trigger signal line transmitting the trigger signal STV, the second clock signal line transmitting the second clock signal CLKB, and the connection pull-up node PU; and the pull-up unit is connected to the first clock signal line transmitting the first clock signal CLK , pull-up node PU, and output signal end; pull-down unit drive unit is connected to second clock signal line, pull-up node PU, lower Pulling node PD and low-level signal terminal VSS; pull-down unit is connected to second clock signal line, pull-up node PU, pull-down node PD, low-level signal terminal VSS, and output signal terminal; reset unit is connected to pull-up node PU, The pull-down node PD, the low-level signal terminal VSS, and the reset signal line that transmits the reset signal.
  • the gate driving circuit including the above shift register performs scanning, it is necessary to change the electric field direction (ie, polarity inversion) on the liquid crystal capacitor for each frame, and the leakage current and parasitic capacitance of the TFT during the polarity inversion process.
  • the crosstalk will cause the positive and negative charges on the two electrodes of the liquid crystal capacitor to not completely cancel, and the residual DC charge will be accumulated on the electrode, which will affect the liquid crystal deflection and form an afterimage.
  • the object of the present invention is to provide a shift register and a driving method, a gate driving circuit and a display device, to solve the problem that the shift register in the prior art is used for the gate driving circuit and the gate scanning is performed.
  • the positive and negative charges on the electrodes cannot be completely canceled, and the residual DC charge is accumulated on the electrodes, which affects the deflection of the liquid crystal to form a residual image.
  • An embodiment of the present invention provides a shift register, including a pull-up driving unit, a pull-up unit, a pull-down unit, a pull-down driving unit, and a reset unit, where the pull-up driving unit is connected to the pull-up unit through a pull-up node, where The reset unit is configured to pull down a potential of a gate line connected to a signal output end of the shift register after the normal output of the shift register is completed, the shift register further comprising a discharge auxiliary unit, a discharge driving unit, and a discharge Control signal terminal;
  • a discharge auxiliary unit configured to pull down a potential of the pull-up node according to a discharge control signal input by the discharge control signal end;
  • a discharge driving unit configured to raise a potential of a gate line connected to a signal output end of the shift register according to a discharge control signal input by the discharge control signal end;
  • the reset unit is further configured to: after the discharge driving unit pulls up the potential of the gate line connected to the signal output end of the shift register and output is completed, pull down the signal output end of the shift register again The potential of the connected gate line.
  • the shift register is provided with the discharge auxiliary unit and the discharge driving unit. After the scanning of the gate driving circuit is completed, the discharge driving unit can pull according to the control of the discharge control signal. High signal output of the shift register The potential of the gate line connected to the terminal is output and is pulled down again by the reset unit, so that the residual DC charge of all the liquid crystal capacitors is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage, thereby improving the display quality.
  • the pull-up driving unit includes a first thin film transistor and a second thin film transistor, and a gate of the first thin film transistor, a source, and a source of the second thin film transistor are electrically connected to the trigger signal end, a drain of the first thin film transistor and a drain of the second thin film transistor are electrically connected to the pull-up node, and a gate of the second thin film transistor is electrically connected to the second clock signal end;
  • the pull-up unit includes a third thin film transistor and a capacitor, a gate of the third thin film transistor and a first end of the capacitor are electrically connected to the pull-up node, and a source of the third thin film transistor is electrically connected a clock signal end, the drain of the third thin film transistor and the second end of the capacitor are electrically connected to the signal output end;
  • the pull-down unit includes a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor, and a gate of the fourth thin film transistor and a gate of the fifth thin film transistor are electrically connected to a pull-down node, and the fourth thin film transistor a source electrically connecting the pull-up node, a drain of the fourth thin film transistor, a drain of the fifth thin film transistor, and a drain of the sixth thin film transistor electrically connected to a low-level signal end, a source of the fifth thin film transistor and a source of the sixth thin film transistor are electrically connected to the signal output end, and a gate of the sixth thin film transistor is electrically connected to the second clock signal end;
  • the pull-down driving unit includes a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor, wherein a gate, a source, and a source of the eighth thin film transistor are electrically connected
  • the second clock signal end, the drain of the seventh thin film transistor, the gate of the eighth thin film transistor, and the source of the ninth thin film transistor are electrically connected, the drain of the eighth thin film transistor and the tenth a source of the thin film transistor is electrically connected to the pull-down node, a gate of the ninth thin film transistor and a gate of the tenth thin film transistor are electrically connected to the pull-up node, a drain of the ninth thin film transistor
  • the drain of the tenth thin film transistor is electrically connected to the low level signal terminal;
  • the reset unit includes an eleventh thin film transistor and a twelfth thin film transistor, and a gate of the eleventh thin film transistor and a gate of the twelfth thin film transistor are electrically connected to a reset signal end, the eleventh thin film a source of the transistor is electrically connected to the pull-up node, a drain of the eleventh thin film transistor and a drain of the twelfth thin film transistor are electrically connected to the low-level signal terminal, the twelfth thin film transistor The source is electrically connected to the signal output.
  • the discharge auxiliary unit includes a thirteenth thin film transistor, a gate of the thirteenth thin film transistor is connected to a discharge control signal end, and a source of the thirteenth thin film transistor is connected to the pull-up node, The drain of the thirteenth thin film transistor is electrically connected to the low level signal terminal.
  • the discharge driving unit includes a fourteenth thin film transistor, a gate of the fourteenth thin film transistor is electrically connected to the discharge control signal end, and a source of the fourteenth thin film transistor is electrically connected to the first At the clock signal end, a drain of the fourteenth thin film transistor is electrically connected to the signal output terminal.
  • all of the above thin film transistors are N-type thin film transistors.
  • the embodiment of the invention further provides a gate driving circuit comprising a plurality of cascaded shift registers, the shift register being a shift register as described in any of the above embodiments.
  • the gate driving circuit further includes a discharge control signal line for providing a discharge control signal to the discharge control signal end of the shift register to control the discharge auxiliary unit and the discharge drive unit;
  • the discharge control signal is maintained at a low level during scanning of the gate driving circuit, and provides a high level of one clock cycle after the scanning of the gate driving circuit ends, wherein the clock cycle is in the shift register The period of the clock signal.
  • the embodiment of the invention further provides a display device comprising the gate driving circuit provided by the above embodiment.
  • the gate driving circuit or the shift register included in the display device is provided with the discharge auxiliary unit and the discharge driving unit, so that after the scanning of the gate driving circuit is completed,
  • the discharge driving unit can raise the potential of the gate line connected to the signal output end of the shift register and output it according to the control of the discharge control signal, and pull it down again by the reset unit, so that all the liquid crystal capacitors are The residual DC charge is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage, which improves the display quality.
  • the embodiment of the present invention further provides a method for driving a shift register, which is used to drive the shift register according to any of the above embodiments, and includes:
  • the first clock signal and the second clock signal are complementary pulse signals;
  • the initial trigger signal has the same trigger and is triggered by two clock high pulses of the same interval of the second clock signal a high-level pulse;
  • the reset signal has two reset high-level pulses spaced apart, and the previous reset high-level pulse lags the previous one of the initial trigger signal by a high-level pulse for one clock cycle.
  • the latter reset high level pulse is synchronized with the latter trigger high level pulse;
  • the discharge control signal has a discharge high level pulse of a duration of one clock period, the discharge high level
  • the rising edge of the pulse is earlier than the rising edge of the triggering high-level pulse for a half of the clock cycle, and the falling edge of the discharging high-level pulse is synchronized with the falling edge of the subsequent triggering high-level pulse;
  • the clock period is a period of the first clock signal and the second clock signal.
  • the gate driving circuit or the shift register included in the display device is provided with the discharge auxiliary unit and the discharge driving unit, so that after the scanning of the gate driving circuit is completed
  • the discharge driving unit can pull up the potential of the gate line connected to the signal output end of the shift register according to the control of the discharge control signal, and output it, and pull it down again by the reset unit, thereby all the liquid crystal
  • the residual DC charge of the capacitor is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage, thereby improving the display quality.
  • 1 is a schematic structural diagram of a prior art shift register
  • FIG. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a specific shift register according to an embodiment of the present invention.
  • FIG. 4 is a timing diagram of a specific shift register according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • an embodiment of the present invention provides a shift register including a pull-up driving unit 11, a pull-up unit 12, a pull-down unit 13, a pull-down driving unit 14, and a reset unit 15.
  • the pull-up driving unit 11 passes through a pull-up node PU.
  • the reset unit 15 is configured to pull down the potential of the gate line connected to the signal output end of the shift register after the normal output of the shift register is completed, and the shift register further includes a discharge auxiliary unit 16 and a discharge driving unit. 17, and the discharge control signal terminal;
  • the discharge auxiliary unit 16 is configured to pull down the potential of the pull-up node PU according to the discharge control signal input by the discharge control signal end;
  • the discharge driving unit 17 is configured to increase the potential of the gate line connected to the signal output end of the shift register according to the discharge control signal input by the discharge control signal end;
  • the reset unit 15 is further configured to pull down the potential of the gate line connected to the signal output end of the shift register again after the discharge driving unit 17 pulls up the potential of the gate line connected to the signal output end of the shift register and outputs the completion. .
  • the shift register is provided with the discharge auxiliary unit 16 and the discharge driving unit 17, so that after the scanning of the gate driving circuit is completed, the discharge driving unit 17 can pull up the signal output of the shift register according to the control of the discharge control signal.
  • the potential of the gate line connected to the terminal is output and is pulled down again by the reset unit 15, so that the residual DC charge of all the liquid crystal capacitors is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage, thereby improving the display quality.
  • a specific shift register is provided in conjunction with FIG. 2, as shown in FIG.
  • the pull-up driving unit 11 includes a first thin film transistor M1 and a second thin film transistor M2.
  • the gate of the first thin film transistor M1, the source and the source of the second thin film transistor M2 are electrically connected to the trigger signal terminal STV, and the first thin film transistor M1
  • the drain and the drain of the second thin film transistor M2 are electrically connected to the pull-up node PU, and the gate of the second thin film transistor M2 is electrically connected to the second clock signal terminal CLKB.
  • the pull-up unit 12 includes a third thin film transistor M3 and a capacitor C1.
  • the gate of the third thin film transistor M3 and the first end of the capacitor C1 are electrically connected to the pull-up node PU, and the source of the third thin film transistor M3 is electrically connected to the first clock signal.
  • a terminal CLK, a drain of the third thin film transistor M3 and a second end of the capacitor C1 are electrically connected to the signal output end;
  • the pull-down unit 13 includes a fourth thin film transistor M4, a fifth thin film transistor M5, and a sixth thin film transistor M6.
  • the gate of the fourth thin film transistor M4 and the gate of the fifth thin film transistor M5 are electrically connected to the pull-down node PD, and the fourth thin film transistor M4 Source connection Point PU, the drain of the fourth thin film transistor M4, the drain of the fifth thin film transistor M5, and the drain of the sixth thin film transistor M6 are electrically connected to the low level signal terminal VSS, the source of the fifth thin film transistor M5, and the sixth thin film.
  • the source of the transistor M6 is electrically connected to the signal output terminal, and the gate of the sixth thin film transistor M6 is electrically connected to the second clock signal terminal CLKB.
  • the pull-down driving unit 14 includes a seventh thin film transistor M7, an eighth thin film transistor M8, a ninth thin film transistor M9, and a tenth thin film transistor M10, and the gate, the source, and the source of the eighth thin film transistor M8 are electrically Connecting the second clock signal terminal CLKB, the drain of the seventh thin film transistor M7, the gate of the eighth thin film transistor M8 and the source of the ninth thin film transistor M9 are electrically connected, the drain of the eighth thin film transistor M8 and the tenth thin film transistor
  • the source of M10 is electrically connected to the pull-down node PD, the gate of the ninth thin film transistor M9 and the gate of the tenth thin film transistor M10 are electrically connected to the pull-up node PU, the drain of the ninth thin film transistor M9 and the drain of the tenth thin film transistor M10.
  • the pole is electrically connected to the low level signal terminal VSS.
  • the reset unit 15 includes an eleventh thin film transistor M11 and a twelfth thin film transistor M12.
  • the gate of the eleventh thin film transistor M11 and the gate of the twelfth thin film transistor M12 are electrically connected to the reset signal end, and the eleventh thin film transistor M11
  • the source is electrically connected to the pull-up node PU
  • the drain of the eleventh thin film transistor M11 and the drain of the twelfth thin film transistor M12 are electrically connected to the low-level signal terminal VSS
  • the source of the twelfth thin film transistor M12 is electrically connected to the signal output. end.
  • the discharge auxiliary unit 16 includes a thirteenth thin film transistor M13, the gate of the thirteenth thin film transistor M13 is connected to the discharge control signal terminal, and the source of the thirteenth thin film transistor M13 is connected to the pull-up node PU, and the thirteenth thin film transistor The drain of M13 is electrically connected to the low level signal terminal VSS.
  • the discharge driving unit 17 includes a fourteenth thin film transistor M14.
  • the gate of the fourteenth thin film transistor M14 is electrically connected to the discharge control signal terminal, and the source of the fourteenth thin film transistor M14 is electrically connected to the first clock signal terminal CLK.
  • the drain of the fourteen thin film transistor M14 is electrically connected to the signal output terminal.
  • all of the above thin film transistors are N-type thin film transistors.
  • the first clock signal CLK and the second clock signal CLKB are complementary pulse signals;
  • the initial trigger signal STV has the same trigger high level pulse with the same interval as the two clock high level pulses of the same interval of the second clock signal CLKB
  • the reset signal has two reset high-level pulses spaced apart, the previous reset high-level pulse lags the initial trigger signal STV by the previous trigger high-level pulse for one clock cycle, and the latter resets the high-level pulse with the STV
  • the discharge control signal has a discharge high-level pulse whose duration is equal to the duration of the clock period t, and the rising edge of the discharge high-level pulse is earlier than the rising edge of the latter-trigger high-level pulse by half a clock The period t, the falling edge of the discharge high level pulse is synchronized with the falling edge of the latter trigger high level pulse; wherein the clock period t is the period of the first clock signal CLK and the second clock signal CLKB.
  • the shift register is provided with a discharge auxiliary unit and a discharge driving unit.
  • the discharge driving unit can raise the signal output end of the shift register according to the control of the discharge control signal.
  • the potential of the connected gate line is output and is pulled down again by the reset unit, so that the residual DC charge of all the liquid crystal capacitors is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage, thereby improving the display quality.
  • an embodiment of the present invention further provides a gate driving circuit including a plurality of cascaded shift registers 10, and the shift register 10 refers to the shift register shown in FIG. 2 and FIG. 3, and each shift register 10 The output is in order of 1, 2, ... (n-1) and (n).
  • the gate driving circuit further includes a discharge control signal line for providing a discharge control signal to the discharge control signal terminal of the shift register 10 to control the discharge auxiliary unit and the discharge driving unit;
  • the discharge control signal is held low during the scanning process of the gate driving circuit, and is supplied with a high level of a clock cycle after the scanning of the gate driving circuit ends, and the clock period is the period of the clock signal in the shift register 10.
  • the embodiment of the invention further provides a display device comprising the gate driving circuit provided in the above embodiment.
  • the shift register included in the gate driving circuit or the display device is provided with a discharge auxiliary unit and a discharge driving unit.
  • the discharge driving unit can be controlled according to the discharge control signal. Pull up the potential of the gate line connected to the signal output terminal of the shift register and output it, and pull it down again by the reset unit, so that the residual DC charge of all the liquid crystal capacitors is completely released, avoiding residual DC charge affecting the liquid crystal flip to generate afterimage, improving display quality.
  • the embodiment of the present invention further provides a driving method of a shift register for driving the shift register of the above embodiment, including:
  • the first clock signal and the second clock signal are complementary pulse signals;
  • the initial trigger signal has a trigger high level pulse that is spaced apart and is the same as the two clock high level pulses of the same interval of the second clock signal;
  • the reset signal has Two reset high-level pulses spaced apart, the previous reset high-level pulse lags the previous trigger high-level pulse of the initial trigger signal by one clock cycle, and the latter reset high-level pulse is synchronized with the latter-triggered high-level pulse.
  • the discharge control signal has a discharge high-level pulse of a duration of one clock cycle, and the rising edge of the discharge high-level pulse is earlier than the rising edge of the latter-trigger high-level pulse by half a clock cycle, and the discharge high-level pulse The falling edge is synchronized with the falling edge of the next triggered high level pulse; wherein the clock period is the period of the first clock signal and the second clock signal.
  • the shift register included in the gate driving circuit or the display device is provided with a discharge auxiliary unit and a discharge driving unit, so that after the scanning of the gate driving circuit is completed, the discharge driving unit can be based on the discharge control signal Controlling, pulling up the potential of the gate line connected to the signal output end of the shift register and outputting it, and pulling it down again by the reset unit, so that the residual DC charge of all the liquid crystal capacitors is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage.
  • the discharge driving unit can be based on the discharge control signal Controlling, pulling up the potential of the gate line connected to the signal output end of the shift register and outputting it, and pulling it down again by the reset unit, so that the residual DC charge of all the liquid crystal capacitors is completely released, and the residual DC charge is prevented from affecting the liquid crystal flip to generate an afterimage.

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  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

一种移位寄存器及驱动方法、栅极驱动电路和显示装置。移位寄存器包括上拉驱动单元11、上拉单元12、下拉单元13、下拉驱动单元14和复位单元15，上拉驱动单元11通过上拉节点PU与上拉单元12连接，还包括放电辅助单元16、放电驱动单元17和放电控制信号端；放电辅助单元16，用于根据放电控制信号，拉低上拉节点PU的电位；放电驱动单元17，用于根据放电控制信号，拉高移位寄存器的信号输出端所连接的栅线的电位；复位单元15，还用于在放电驱动单元17拉高移位寄存器的信号输出端所连接的栅线的电位并输出完成之后，再次拉低栅线的电位。

Description

一种移位寄存器及其驱动方法、相应的栅极驱动电路和显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、相应的栅极驱动电路和显示装置。
背景技术
在平面显示领域中，液晶显示装置以其具有的重量轻、体积小、厚度薄等特点，己广泛地应用在各种尺寸的终端显示设备中。传统液晶显示装置的显示面板由阵列基板和对向基板夹设液晶层构成，阵列基板上设置有垂直和水平阵列式像素矩阵，其中阵列基板的像素结构包括薄膜晶体管(Thin Film Transistor，TFT)和像素电极，像素电极与公共电极构成电容；TFT在交叉的数据线和扫描线控制下向像素电极输入不同的电压，从而在液晶电容上形成不同的电场，电场控制液晶偏转，实现面板的显示功能。
随着技术的发展，出现了阵列基板栅驱动技术(Gate Driver on Array，GOA)技术，GOA技术是一种将扫描电路集成于阵列基板上的技术，每个GOA单元作为一个移位寄存器将扫描信号依次传递给下一GOA单元，逐行开启TFT开关，完成像素单元的数据信号输入。GOA技术的栅极驱动电路包括用于提供信号的多条信号线和用于存储信号数据的移位寄存器，如图1，为了方便说明，以信号线所传输的信号标记信号线，如下：
信号线包括：触发信号线，用于给移位寄存器输入初始触发信号STV；拉低信号线，用于给移位寄存器输入低电平信号VSS；第一时钟信号线和第二时钟信号线，用于给移位寄存器提供互补时钟脉冲信号，即第一时钟信号CLK和第二时钟信号CLKB。
移位寄存器包括：上拉驱动单元、上拉单元、下拉驱动单元、下拉单元、和复位单元；
上拉驱动单元连接传输触发信号STV的触发信号线、传输第二时钟信号CLKB的第二时钟信号线、以及连接上拉节点PU；上拉单元连接传输第一时钟信号CLK的第一时钟信号线、上拉节点PU、以及输出信号端；下拉单元驱动单元连接第二时钟信号线、上拉节点PU、下 拉节点PD、以及低电平信号端VSS；下拉单元连接第二时钟信号线、上拉节点PU、下拉节点PD、低电平信号端VSS、以及输出信号端；复位单元连接上拉节点PU、下拉节点PD、低电平信号端VSS、以及传输复位信号的复位信号线。
但是，包括上述移位寄存器的栅极驱动电路进行扫描时，需要每一帧都要改变液晶电容上的电场方向(即极性翻转)，在极性翻转过程中，由于TFT的漏电和寄生电容的串扰，会导致液晶电容两个电极上的正负电荷不能完全抵消，在电极上集聚残留直流电荷，影响液晶偏转从而形成残像。
发明内容
本发明的目的是提供一种移位寄存器及驱动方法、栅极驱动电路和显示装置，以解决现有技术中的移位寄存器用于栅极驱动电路并进行栅极扫描时，液晶电容两个电极上的正负电荷不能完全抵消，在电极上集聚残留直流电荷，影响液晶偏转从而形成残像的问题。
本发明的目的是通过以下技术方案实现的：
本发明实施例提供一种移位寄存器，包括上拉驱动单元、上拉单元、下拉单元、下拉驱动单元和复位单元，所述上拉驱动单元通过上拉节点与所述上拉单元连接，所述复位单元用于在所述移位寄存器正常输出完成之后拉低所述移位寄存器的信号输出端所连接的栅线的电位，所述移位寄存器还包括放电辅助单元、放电驱动单元和放电控制信号端；
放电辅助单元，用于根据所述放电控制信号端输入的放电控制信号，拉低所述上拉节点的电位；
放电驱动单元，用于根据所述放电控制信号端输入的放电控制信号，拉高所述移位寄存器的信号输出端所连接的栅线的电位；
所述复位单元，还用于在所述放电驱动单元拉高所述移位寄存器的信号输出端所连接的栅线的电位并输出完成之后，再次拉低所述移位寄存器的信号输出端所连接的栅线的电位。
本发明实施例中，所述移位寄存器设置有所述放电辅助单元和所述放电驱动单元，使栅极驱动电路扫描完成之后，所述放电驱动单元能够根据所述放电控制信号的控制，拉高所述移位寄存器的信号输出 端所连接的栅线的电位并输出，并由所述复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
优选地，所述上拉驱动单元包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管的栅极、源极和所述第二薄膜晶体管的源极电连接触发信号端，所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极电连接所述上拉节点，所述第二薄膜晶体管的栅极电连接第二时钟信号端；
所述上拉单元包括第三薄膜晶体管和电容，所述第三薄膜晶体管的栅极和所述电容的第一端电连接所述上拉节点，所述第三薄膜晶体管的源极电连接第一时钟信号端，所述第三薄膜晶体管的漏极和所述电容的第二端电连接信号输出端；
所述下拉单元包括第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管，所述第四薄膜晶体管的栅极和所述第五薄膜晶体管的栅极电连接下拉节点，所述第四薄膜晶体管的源极电连接所述上拉节点，所述第四薄膜晶体管的漏极、所述第五薄膜晶体管的漏极和所述第六薄膜晶体管的漏极电连接低电平信号端，所述第五薄膜晶体管的源极和所述第六薄膜晶体管的源极电连接所述信号输出端，所述第六薄膜晶体管的栅极电连接第二时钟信号端；
所述下拉驱动单元包括第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和第十薄膜晶体管，所述第七薄膜晶体管的栅极、源极和所述第八薄膜晶体管的源极电连接所述第二时钟信号端，所述第七薄膜晶体管的漏极、第八薄膜晶体管的栅极和第九薄膜晶体管的源极电连接，所述第八薄膜晶体管的漏极和所述第十薄膜晶体管的源极电连接所述下拉节点，所述第九薄膜晶体管的栅极和所述第十薄膜晶体管的栅极电连接所述上拉节点，所述第九薄膜晶体管的漏极和所述第十薄膜晶体管的漏极电连接所述低电平信号端；
所述复位单元包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管的栅极和所述第十二薄膜晶体管的栅极电连接复位信号端，所述第十一薄膜晶体管的源极电连接所述上拉节点，所述第十一薄膜晶体管的漏极和所述第十二薄膜晶体管的漏极电连接所述低电平信号端，所述第十二薄膜晶体管的源极电连接所述信号输出端。
优选地，所述放电辅助单元包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极连接放电控制信号端，所述第十三薄膜晶体管的源极连接所述上拉节点，所述第十三薄膜晶体管的漏极电连接低电平信号端。
优选地，所述放电驱动单元包括第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电连接所述放电控制信号端，所述第十四薄膜晶体管的源极电连接所述第一时钟信号端，所述第十四薄膜晶体管的漏极电连接所述信号输出端。
优选地，上述全部薄膜晶体管均为N型薄膜晶体管。
本发明实施例还提供一种栅极驱动电路，包括多个级联的移位寄存器，所述移位寄存器是如上述任一实施例所述的移位寄存器。
优选地，栅极驱动电路还包括放电控制信号线，所述放电控制信号线用于为所述移位寄存器的放电控制信号端提供放电控制信号，以控制所述放电辅助单元和所述放电驱动单元；
所述放电控制信号在所述栅极驱动电路扫描过程中保持低电平，在所述栅极驱动电路扫描结束后提供一个时钟周期的高电平，所述时钟周期为所述移位寄存器中时钟信号的周期。
本发明实施例还提供一种显示装置，包括如上实施例提供的所述栅极驱动电路。
本发明实施例中，所述栅极驱动电路或所述显示装置所包括的所述移位寄存器，设置有所述放电辅助单元和所述放电驱动单元，使栅极驱动电路扫描完成之后，所述放电驱动单元能够根据所述放电控制信号的控制，拉高所述移位寄存器的信号输出端所连接的栅线的电位并输出，并由所述复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
本发明实施例还提供一种移位寄存器的驱动方法，用于驱动如上任一实施例所述的移位寄存器，包括：
由第一时钟信号端、第二时钟信号端、触发信号端、低电平信号端、复位信号端和放电控制信号端一一对应地提供第一时钟信号、第二时钟信号、初始触发信号、低电平信号、复位信号和放电控制信号；
所述第一时钟信号和所述第二时钟信号为互补的脉冲信号；所述初始触发信号具有相间隔、且与所述第二时钟信号的相同间隔的两个时钟高电平脉冲相同的触发高电平脉冲；所述复位信号具有相间隔的两个复位高电平脉冲，前一所述复位高电平脉冲落后所述初始触发信号的前一所述触发高电平脉冲一个时钟周期，后一所述复位高电平脉冲与后一所述触发高电平脉冲同步；所述放电控制信号具有一个时长为一个所述时钟周期的时长的放电高电平脉冲，所述放电高电平脉冲的上升沿早于后一所述触发高电平脉冲的上升沿半个所述时钟周期，所述放电高电平脉冲的下降沿与后一所述触发高电平脉冲的下降沿同步；其中，所述时钟周期为所述第一时钟信号和所述第二时钟信号的周期。
本发明实施例有益效果如下：所述栅极驱动电路或所述显示装置所包括的所述移位寄存器，设置有所述放电辅助单元和所述放电驱动单元，使栅极驱动电路扫描完成之后，所述放电驱动单元能够根据所述放电控制信号的控制，拉高所述移位寄存器的信号输出端所连接的栅线的电位并输出，并由所述复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
附图说明
图1为现有技术的移位寄存器的结构示意图；
图2为本发明实施例提供的移位寄存器的结构示意图；
图3为本发明实施例提供的具体的移位寄存器的结构示意图；
图4为本发明实施例提供的具体的移位寄存器的时序图；
图5为本发明实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合说明书附图对本发明实施例的实现过程进行详细说明。需要注意的是，自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
参见图2，本发明实施例提供一种移位寄存器，包括上拉驱动单元11、上拉单元12、下拉单元13、下拉驱动单元14和复位单元15，上拉驱动单元11通过上拉节点PU与上拉单元12连接，复位单元15用于在移位寄存器正常输出完成之后拉低移位寄存器的信号输出端所连接的栅线的电位，移位寄存器还包括放电辅助单元16、放电驱动单元17、和放电控制信号端；
放电辅助单元16，用于根据放电控制信号端输入的放电控制信号，拉低上拉节点PU的电位；
放电驱动单元17，用于根据放电控制信号端输入的放电控制信号，拉高移位寄存器的信号输出端所连接的栅线的电位；
复位单元15，还用于在放电驱动单元17拉高移位寄存器的信号输出端所连接的栅线的电位并输出完成之后，再次拉低移位寄存器的信号输出端所连接的栅线的电位。
本发明实施例中，移位寄存器设置有放电辅助单元16和放电驱动单元17，使栅极驱动电路扫描完成之后，放电驱动单元17能够根据放电控制信号的控制，拉高移位寄存器的信号输出端所连接的栅线的电位并输出，并由复位单元15再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
结合图2提供一种具体的移位寄存器，如图3所示：
上拉驱动单元11包括第一薄膜晶体管M1和第二薄膜晶体管M2，第一薄膜晶体管M1的栅极、源极和第二薄膜晶体管M2的源极电连接触发信号端STV，第一薄膜晶体管M1的漏极和第二薄膜晶体管M2的漏极电连接上拉节点PU，第二薄膜晶体管M2的栅极电连接第二时钟信号端CLKB。
上拉单元12包括第三薄膜晶体管M3和电容C1，第三薄膜晶体管M3的栅极和电容C1的第一端电连接上拉节点PU，第三薄膜晶体管M3的源极电连接第一时钟信号端CLK，第三薄膜晶体管M3的漏极和电容C1的第二端电连接信号输出端；
下拉单元13包括第四薄膜晶体管M4、第五薄膜晶体管M5和第六薄膜晶体管M6，第四薄膜晶体管M4的栅极和第五薄膜晶体管M5的栅极电连接下拉节点PD，第四薄膜晶体管M4的源极电连接上拉节 点PU，第四薄膜晶体管M4的漏极、第五薄膜晶体管M5的漏极和第六薄膜晶体管M6的漏极电连接低电平信号端VSS，第五薄膜晶体管M5的源极和第六薄膜晶体管M6的源极电连接信号输出端，第六薄膜晶体管M6的栅极电连接第二时钟信号端CLKB。
下拉驱动单元14包括第七薄膜晶体管M7、第八薄膜晶体管M8、第九薄膜晶体管M9和第十薄膜晶体管M10，第七薄膜晶体管M7的栅极、源极和第八薄膜晶体管M8的源极电连接第二时钟信号端CLKB，第七薄膜晶体管M7的漏极、第八薄膜晶体管M8的栅极和第九薄膜晶体管M9的源极电连接，第八薄膜晶体管M8的漏极和第十薄膜晶体管M10的源极电连接下拉节点PD，第九薄膜晶体管M9的栅极和第十薄膜晶体管M10的栅极电连接上拉节点PU，第九薄膜晶体管M9的漏极和第十薄膜晶体管M10的漏极电连接低电平信号端VSS。
复位单元15包括第十一薄膜晶体管M11和第十二薄膜晶体管M12，第十一薄膜晶体管M11的栅极和第十二薄膜晶体管M12的栅极电连接复位信号端，第十一薄膜晶体管M11的源极电连接上拉节点PU，第十一薄膜晶体管M11的漏极和第十二薄膜晶体管M12的漏极电连接低电平信号端VSS，第十二薄膜晶体管M12的源极电连接信号输出端。
优选地，放电辅助单元16包括第十三薄膜晶体管M13，第十三薄膜晶体管M13的栅极连接放电控制信号端，第十三薄膜晶体管M13的源极连接上拉节点PU，第十三薄膜晶体管M13的漏极电连接低电平信号端VSS。
优选地，放电驱动单元17包括第十四薄膜晶体管M14，第十四薄膜晶体管M14的栅极电连接放电控制信号端，第十四薄膜晶体管M14的源极电连接第一时钟信号端CLK，第十四薄膜晶体管M14的漏极电连接信号输出端。
优选地，上述全部薄膜晶体管(例如第一薄膜晶体管M1至第十四薄膜晶体管M14)均为N型薄膜晶体管。
需要说明的是，为了既能完成正常扫描和又能进行放电，需要对输入的各信号进行适应性的变化，对于图3所示的移位寄存器，可以提供如图4所示的时序，以信号端的标记命名传输的相对应的信号，如下：
第一时钟信号CLK和第二时钟信号CLKB为互补的脉冲信号；初始触发信号STV具有相间隔、且与第二时钟信号CLKB的相同间隔的两个时钟高电平脉冲相同的触发高电平脉冲；复位信号具有相间隔的两个复位高电平脉冲，前一复位高电平脉冲落后初始触发信号STV的前一触发高电平脉冲一个时钟周期，后一复位高电平脉冲与STV的后一触发高电平脉冲同步；放电控制信号具有一个时长等于时钟周期t的时长的放电高电平脉冲，放电高电平脉冲的上升沿早于后一触发高电平脉冲的上升沿半个时钟周期t，放电高电平脉冲的下降沿与后一触发高电平脉冲的下降沿同步；其中，时钟周期t为第一时钟信号CLK和第二时钟信号CLKB的周期。
本发明实施例中，移位寄存器，设置有放电辅助单元和放电驱动单元，使栅极驱动电路扫描完成之后，放电驱动单元能够根据放电控制信号的控制，拉高移位寄存器的信号输出端所连接的栅线的电位并输出，并由复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
参见图5，本发明实施例还提供一种栅极驱动电路，包括多个级联的移位寄存器10，移位寄存器10参考图2、图3所示的移位寄存器，各移位寄存器10的输出依次为1、2......(n-1)和(n)。
优选地，栅极驱动电路还包括放电控制信号线，放电控制信号线用于为移位寄存器10的放电控制信号端提供放电控制信号，以控制放电辅助单元和放电驱动单元；
放电控制信号在栅极驱动电路扫描过程中保持低电平，在栅极驱动电路扫描结束后提供一个时钟周期的高电平，时钟周期为移位寄存器10中时钟信号的周期。
需要说明的是，附图5中标记VSS、CLK、CLKB、STV、复位、放电控制的信号线均是以移位寄存器10的相应的信号端的命名进行标记的，在此不再赘述。
栅极驱动电路各移位寄存单元10使液晶电容放电的具体实现：放电控制信号端接收到高电平信号时，所有移位寄存单元10的第十三薄膜晶体管M13和第十四薄膜晶体管M14打开，M14使信号输出端在第一时钟信号端CLK接收到的第一时钟信号(一个时钟周期的电平脉冲)，即相邻移位寄存单元10在一个时钟周期内均有半个周期输出高 电平，从而实现所有像素的液晶电容全部放电的目的，第十三薄膜晶体管M13使上拉节点PU保持低电平，以免影响下一帧各个移位寄存单元10单元正常工作。
本发明实施例还提供一种显示装置，包括如上实施例提供的栅极驱动电路。
本发明实施例中，栅极驱动电路或显示装置所包括的移位寄存器，设置有放电辅助单元和放电驱动单元，使栅极驱动电路扫描完成之后，放电驱动单元能够根据放电控制信号的控制，拉高移位寄存器的信号输出端所连接的栅线的电位并输出，并由复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
本发明实施例还提供一种移位寄存器的驱动方法，用于驱动如上实施例的移位寄存器，包括：
由第一时钟信号端、第二时钟信号端、触发信号端、低电平信号端、复位信号端和放电控制信号端一一对应地提供第一时钟信号、第二时钟信号、初始触发信号、低电平信号、复位信号和放电控制信号；
第一时钟信号和第二时钟信号为互补的脉冲信号；初始触发信号具有相间隔、且与第二时钟信号的相同间隔的两个时钟高电平脉冲相同的触发高电平脉冲；复位信号具有相间隔的两个复位高电平脉冲，前一复位高电平脉冲落后初始触发信号的前一触发高电平脉冲一个时钟周期，后一复位高电平脉冲与后一触发高电平脉冲同步；放电控制信号具有一个时长为一个时钟周期的时长的放电高电平脉冲，放电高电平脉冲的上升沿早于后一触发高电平脉冲的上升沿半个时钟周期，放电高电平脉冲的下降沿与后一触发高电平脉冲的下降沿同步；其中，时钟周期为第一时钟信号和第二时钟信号的周期。
本发明实施例有益效果如下：栅极驱动电路或显示装置所包括的移位寄存器，设置有放电辅助单元和放电驱动单元，使栅极驱动电路扫描完成之后，放电驱动单元能够根据放电控制信号的控制，拉高移位寄存器的信号输出端所连接的栅线的电位并输出，并由复位单元再次拉低，从而全部液晶电容的残留直流电荷彻底释放，避免残留直流电荷影响液晶翻转产生残像，改善显示品质。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

  1. 一种移位寄存器，包括上拉驱动单元、上拉单元、下拉单元、下拉驱动单元和复位单元，所述上拉驱动单元通过上拉节点与所述上拉单元连接，所述复位单元用于在所述移位寄存器正常输出完成之后拉低所述移位寄存器的信号输出端所连接的栅线的电位，其特征在于，所述移位寄存器还包括放电辅助单元、放电驱动单元和放电控制信号端，其中：
    放电辅助单元，用于根据所述放电控制信号端输入的放电控制信号，拉低所述上拉节点的电位；
    放电驱动单元，用于根据所述放电控制信号端输入的放电控制信号，拉高所述移位寄存器的信号输出端所连接的栅线的电位；
    所述复位单元，还用于在所述放电驱动单元拉高所述移位寄存器的信号输出端所连接的栅线的电位并输出完成之后，再次拉低所述移位寄存器的信号输出端所连接的栅线的电位。
  2. 如权利要求1所述的移位寄存器，其特征在于，所述放电辅助单元包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极连接所述放电控制信号端，所述第十三薄膜晶体管的源极连接所述上拉节点，所述第十三薄膜晶体管的漏极电连接所述低电平信号端。
  3. 如权利要求1所述的移位寄存器，其特征在于，所述放电驱动单元包括第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电连接所述放电控制信号端，所述第十四薄膜晶体管的源极电连接所述第一时钟信号端，所述第十四薄膜晶体管的漏极电连接所述信号输出端。
  4. 如权利要求1所述的移位寄存器，其特征在于，
    所述上拉驱动单元包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管的栅极、源极和所述第二薄膜晶体管的源极电连接触发信号端，所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极电连接所述上拉节点，所述第二薄膜晶体管的栅极电连接第二时钟信号端；
    所述上拉单元包括第三薄膜晶体管和电容，所述第三薄膜晶体管的栅极和所述电容的第一端电连接所述上拉节点，所述第三薄膜晶体 管的源极电连接第一时钟信号端，所述第三薄膜晶体管的漏极和所述电容的第二端电连接信号输出端；
    所述下拉单元包括第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管，所述第四薄膜晶体管的栅极和所述第五薄膜晶体管的栅极电连接下拉节点，所述第四薄膜晶体管的源极电连接所述上拉节点，所述第四薄膜晶体管的漏极、所述第五薄膜晶体管的漏极和所述第六薄膜晶体管的漏极电连接低电平信号端，所述第五薄膜晶体管的源极和所述第六薄膜晶体管的源极电连接所述信号输出端，所述第六薄膜晶体管的栅极电连接第二时钟信号端；
    所述下拉驱动单元包括第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和第十薄膜晶体管，所述第七薄膜晶体管的栅极、源极和所述第八薄膜晶体管的源极电连接所述第二时钟信号端，所述第七薄膜晶体管的漏极、第八薄膜晶体管的栅极和第九薄膜晶体管的源极电连接，所述第八薄膜晶体管的漏极和所述第十薄膜晶体管的源极电连接所述下拉节点，所述第九薄膜晶体管的栅极和所述第十薄膜晶体管的栅极电连接所述上拉节点，所述第九薄膜晶体管的漏极和所述第十薄膜晶体管的漏极电连接所述低电平信号端；
    所述复位单元包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管的栅极和所述第十二薄膜晶体管的栅极电连接复位信号端，所述第十一薄膜晶体管的源极电连接所述上拉节点，所述第十一薄膜晶体管的漏极和所述第十二薄膜晶体管的漏极电连接所述低电平信号端，所述第十二薄膜晶体管的源极电连接所述信号输出端。
  5. 如权利要求4所述的移位寄存器，其特征在于，上述全部薄膜晶体管均为N型薄膜晶体管。
  6. 一种栅极驱动电路，包括多个级联的移位寄存器，其特征在于，所述移位寄存器是如权利要求1-5任一个所述的移位寄存器。
  7. 如权利要求6所述的栅极驱动电路，其特征在于，还包括放电控制信号线，所述放电控制信号线用于为所述移位寄存器的放电控制信号端提供放电控制信号，以控制所述放电辅助单元和所述放电驱动单元；
    所述放电控制信号在所述栅极驱动电路扫描过程中保持低电平，在所述栅极驱动电路扫描结束后提供一个时钟周期的高电平，所述时钟周期为所述移位寄存器中时钟信号的周期。
  8. 一种显示装置，其特征在于，包括如权利要求6或7所述的栅极驱动电路。
  9. 一种移位寄存器的驱动方法，用于驱动如权利要求1-5的任一个所述的移位寄存器，其特征在于，包括：
    由第一时钟信号端、第二时钟信号端、触发信号端、低电平信号端、复位信号端和放电控制信号端一一对应地提供第一时钟信号、第二时钟信号、初始触发信号、低电平信号、复位信号和放电控制信号；
    所述第一时钟信号和所述第二时钟信号为互补的脉冲信号；所述初始触发信号具有相间隔、且与所述第二时钟信号的相同间隔的两个时钟高电平脉冲相同的触发高电平脉冲；所述复位信号具有相间隔的两个复位高电平脉冲，前一所述复位高电平脉冲落后所述初始触发信号的前一所述触发高电平脉冲一个时钟周期，后一所述复位高电平脉冲与后一所述触发高电平脉冲同步；所述放电控制信号具有一个时长为一个所述时钟周期的时长的放电高电平脉冲，所述放电高电平脉冲的上升沿早于后一所述触发高电平脉冲的上升沿半个所述时钟周期，所述放电高电平脉冲的下降沿与后一所述触发高电平脉冲的下降沿同步；其中，所述时钟周期为所述第一时钟信号和所述第二时钟信号的周期。
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