WO2018201815A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018201815A1
WO2018201815A1 PCT/CN2018/079815 CN2018079815W WO2018201815A1 WO 2018201815 A1 WO2018201815 A1 WO 2018201815A1 CN 2018079815 W CN2018079815 W CN 2018079815W WO 2018201815 A1 WO2018201815 A1 WO 2018201815A1
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Prior art keywords
node
transistor
potential
terminal
signal
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PCT/CN2018/079815
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English (en)
French (fr)
Inventor
陈鹏
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/094,249 priority Critical patent/US11120729B1/en
Publication of WO2018201815A1 publication Critical patent/WO2018201815A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.
  • GOA Gate Driver on Array
  • a shift register including: an input terminal for receiving an input signal, a reset terminal for receiving a reset signal, a first clock terminal for receiving a first clock signal, and a second a clock end for receiving a second clock signal; a control end for receiving a control signal; an output end for outputting an output signal; and a node control circuit configured to be at the input signal, the reset signal, and the second node a potential at a first node is set under control of a potential, the node control circuit further configured to set the second node under control of the second clock signal and a potential at the first node a potential at the output, configured to output at the output under control of the first clock signal, a potential at the first node, a potential at the second node, and the reset signal
  • the output signal wherein the output circuit includes a denoising transistor including a gate connected to the second node, a drain connected to the output, and a source; and threshold voltage control a circuit configured to set a potential
  • the node control circuit includes: a first node control circuit configured to set a potential at the first node to be active in response to the input signal being valid, and responsive to Setting at least one of a reset signal or a potential at the second node to assert the potential at the first node to be inactive; and a second node control circuit configured to be responsive to the second clock signal The potential at the second node is asserted to be active, and the potential at the second node is set to be inactive in response to the potential at the first node being active.
  • the first node control circuit includes: a first transistor including a gate connected to the input, a first pole connected to the input, and a first node connected to the first node a second transistor comprising: a gate connected to the reset terminal, a first pole connected to the first node, and a second pole connected to a reference level terminal for supplying a reference voltage having an inactive level And a seventh transistor comprising a gate connected to the second node, a first pole connected to the first node, and a second pole connected to the reference level terminal.
  • the second node control circuit includes: a fifth transistor including a gate connected to the first node, a first pole connected to the second node, and connected to the a second pole of the reference level terminal; and a sixth transistor including a gate connected to the second clock terminal, a first pole connected to the second clock terminal, and a second pole connected to the second node.
  • the output circuit includes: a third transistor configured to transmit the first clock signal to the output terminal in response to a potential at the first node being active; a fourth transistor Configuring to transmit a source voltage of the denoising transistor to the output in response to the reset signal being active; an eighth transistor acting as the denoising transistor and configured to be responsive to the second node The potential at the location is effective to transfer the source voltage of the denoising transistor to the output; and a first capacitor is coupled between the first node and the output.
  • the third transistor includes a gate connected to the first node, a first pole connected to the first clock terminal, and a second pole connected to the output terminal
  • the fourth transistor includes a gate connected to the reset terminal, a first pole connected to the output terminal, and a second pole connected to a source of the denoising transistor.
  • the control terminal includes a first control terminal and a second control terminal
  • the threshold voltage control circuit includes: a ninth transistor configured to receive at the second control terminal The signal is inactive such that the gate of the denoising transistor is non-conducting with the source of the denoising transistor and is responsive to the signal received at the second control terminal being valid during the time interval a gate of the denoising transistor being electrically coupled to a source of the denoising transistor during the time interval; and a tenth transistor configured to be responsive to being valid at a signal received at the first control terminal a reference level terminal supplying a reference voltage having an inactive level is turned on with a source of the denoising transistor, and responsive to a signal received at the first control terminal being invalid during the time interval, The reference level terminal is non-conducting with the source of the denoising transistor.
  • the ninth transistor includes a gate connected to the second control terminal, a first pole connected to the second node, and a first source connected to the denoising transistor a diode
  • the tenth transistor includes a gate connected to the first control terminal, a first pole connected to the reference level terminal, and a second pole connected to a source of the noise canceling transistor.
  • the shift register further includes a second capacitor connected between a source of the denoising transistor and the reference level terminal.
  • a method of driving a shift register includes an input for receiving an input signal, a reset terminal for receiving a reset signal, a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, A control terminal for receiving a control signal, an output terminal for outputting an output signal, a node control circuit, an output circuit, and a threshold voltage control circuit.
  • the method includes: setting, by the node control circuit, a potential at a first node under control of the input signal, the reset signal, and a potential at a second node; at the second clock signal and Controlling, by the node control circuit, a potential at the second node under control of a potential at the first node; at the first clock signal, a potential at the first node, the second node
  • the output signal is output by the output circuit at the output terminal under control of the potential and the reset signal, wherein the output circuit includes a denoising transistor including a gate connected to the second node a drain connected to the output, and a source; and a source of the denoising transistor set by the threshold voltage control circuit under control of the control signal and a potential at the second node The potential at which to achieve a balance between the gate voltage and the source voltage of the denoising transistor over a time interval.
  • a gate driving circuit including N cascaded shift registers as described above, N being a positive integer greater than or equal to two.
  • the mth output of the shift register is coupled to the m+1th input of the shift register, m being an integer and 1 ⁇ m ⁇ N.
  • the nth output terminal of the shift register is connected to the n-1th reset terminal in the shift register, n is an integer and 1 ⁇ n ⁇ N.
  • a display device comprising the gate drive circuit as described above.
  • FIG. 1 is a block diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing an example circuit of a first node control circuit on the basis of FIG. 1;
  • FIG. 3 is a schematic diagram showing an example circuit of a second node control circuit on the basis of FIG. 1;
  • FIG. 4 is a schematic diagram showing an example circuit of an output circuit on the basis of FIG. 1;
  • FIG. 5 is a schematic diagram showing an example circuit of a threshold voltage control circuit on the basis of FIG. 1;
  • FIG. 6 is a schematic circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 7 is an example timing diagram of the shift register shown in FIG. 6;
  • FIG. 8 is a block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • FIG. 9 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • some of the transistors in the GOA structure need to be turned on for a long period of time to remove noise. These transistors may fail after long periods of operation, for example, become difficult to turn on. The Applicant has recognized that this may be due to the rise in the threshold voltage of these transistors due to the fact that the difference between their gate voltage and source voltage is at a high level for a long time. Based on the insights into this problem, a solution that is described in detail below in connection with the embodiments and the drawings is presented.
  • FIG. 1 is a block diagram of a shift register 10 in accordance with an embodiment of the present disclosure.
  • the shift register 10 includes an input terminal INPUT for receiving an input signal, a reset terminal RESET for receiving a reset signal, a first clock terminal CLK for receiving a first clock signal, and a second terminal for receiving The second clock terminal CLKB of the clock signal, the control terminal IN for receiving the control signal, and the output terminal OUTPUT for outputting the output signal.
  • the shift register 10 also includes a node control circuit, an output circuit 13, and a threshold voltage control circuit 14, shown as being embodied by both the first node control circuit 11 and the second node control circuit 12.
  • a node control circuit configured to set a potential at the first node PU under control of the input signal, the reset signal, and a potential at the second node PD, and at the second clock signal and the first The potential at the second node PD is set under the control of the potential at the node PU.
  • the first node control circuit 11 sets the potential of the first node PU to be active in response to the input signal being valid, and is responsive to at least the reset signal or the potential of the second node PD One is valid and the potential of the first node PU is set to be invalid.
  • the second node control circuit 12 sets the potential of the second node PD to be active in response to the second clock signal being active, and the second node in response to the potential at the first node PU being valid The potential of the PD is set to be invalid.
  • signal or potential active as used herein in connection with a component of a circuit or circuit means that the signal causes the components of the circuit or circuit to be enabled under the control of the signal or potential.
  • invalid signal or potential means that the signal or potential causes the components of the circuit or circuit to be disabled under the control of the signal or potential.
  • the active signal or potential has a high level and the inactive signal or potential has a low level.
  • the output circuit 13 is configured to output the output at the output terminal OUTPUT under the control of the first clock signal, the potential at the first node PU, the potential at the second node PD, and the reset signal Said output signal.
  • the output circuit 13 includes a denoising transistor including a gate connected to the second node PD, a drain connected to the output terminal OUTPUT, and a source.
  • the threshold voltage control circuit 14 is configured to set a potential at a source of the denoising transistor under control of the control signal and a potential at the second node PD to achieve the said time interval The balance between the gate voltage and the source voltage of the noise transistor.
  • the gate voltage and source voltage of the denoising transistor in shift register 10 are balanced (eg, equal or substantially equal) during the time interval, as will be described later describe). This is advantageous in avoiding the rise of its threshold voltage due to the transistor being turned on for a long time, thereby alleviating or even eliminating the failure of the transistor.
  • the first node control circuit 11 includes a first transistor M1, a second transistor M2, and a seventh transistor M7.
  • the first transistor M1 has a gate connected to the input terminal INPUT and a first pole and a second pole connected to the first node PU. When the input signal received at the input terminal INPUT is active, the first transistor M1 is turned on to set the potential of the first node PU to be active.
  • the second transistor M2 has a gate connected to the reset terminal RESET, a first pole connected to the first node PU, and a second pole connected to the reference level terminal VSS supplying the reference voltage having an inactive level.
  • the second transistor M2 is turned on to set the potential of the first node PU to be inactive.
  • the seventh transistor M7 has a gate connected to the second node PD, a first pole connected to the first node PU, and a second pole connected to the reference level terminal VSS. When the second node PD is at the active potential, the seventh transistor M7 is turned on to set the potential of the first node PU to be inactive.
  • the second node control circuit 12 includes a fifth transistor M5 and a sixth transistor M6.
  • the fifth transistor M5 has a gate connected to the first node PU, a first pole connected to the second node PD, and a second pole connected to the reference level terminal VSS. When the first node PU is at the active potential, the fifth transistor M5 is turned on to set the potential of the second node PD to be inactive.
  • the sixth transistor M6 has a gate and a second electrode connected to the second clock terminal CLKB and a first electrode connected to the second node PD. When the second clock signal received at the second clock terminal CLKB is active, the sixth transistor M6 is turned on to set the potential of the second node PD to be active.
  • the output circuit 13 includes a third transistor M3, a fourth transistor M4, an eighth transistor M8, and a first capacitor C1.
  • the eighth transistor M8 has a gate connected to the second node PD, a first pole connected to the output terminal OUTPUT, and a second pole connected to the threshold voltage control circuit 14.
  • the eighth transistor M8 acts as a denoising transistor. As will be described later, when the second node PD is at the active potential, the eighth transistor M8 is turned on to set the potential at the output terminal OUTPUT to be inactive. This can cause the output signal output at the output terminal OUTPUT to remain at an inactive potential, thereby eliminating noise.
  • the third transistor M3 has a gate connected to the first node PU, a first pole connected to the first clock terminal CLK, and a second pole connected to the output terminal OUTPUT.
  • the third transistor M3 is turned on to output the first clock signal received at the first clock terminal CLK as an output signal from the output terminal OUTPUT.
  • the fourth transistor M4 has a gate connected to the reset terminal RESET, a first pole connected to the output terminal OUTPUT, and a second pole connected to the threshold voltage control circuit 14. As will be described later, when the reset signal received at the reset terminal RESET is asserted, the fourth transistor M4 is turned on to set the potential at its output terminal OUTPUT to be inactive.
  • the first capacitor C1 is connected between the first node PU and the output terminal OUTPUT.
  • the first capacitor C1 may be charged such that the potential at the first node PU is set to be active.
  • FIG. 5 is a schematic diagram of an example circuit illustrating the threshold voltage control circuit 14 on the basis of FIG.
  • the threshold voltage control circuit 14 includes a ninth transistor M9 and a tenth transistor M10.
  • the control terminal IN shown in FIG. 1 is shown to include a first control terminal IN1 and a second control terminal IN2.
  • the ninth transistor M9 has a gate connected to the second control terminal IN2, a first pole connected to the second node PD, and a second pole connected to the output circuit 13.
  • the ninth transistor M9 is turned on to turn off the gate of the denoising transistor (for example, the eighth transistor M8 shown in FIG. 4).
  • the source of the noise transistor is turned on.
  • the gate voltage of the denoising transistor is equal to or substantially equal to the source voltage of the denoising transistor, thereby allowing a shortened period of time in which the gate-source voltage of the denoising transistor is at a high level. This is advantageous to alleviate or eliminate failure due to drift of the threshold voltage of the denoising transistor.
  • the phrase "A substantially equal to B" as used herein may mean that A is equal to B or the difference between A and B falls within a tolerance due to, for example, engineering errors.
  • the tenth transistor M10 has a gate connected to the first control terminal IN1, a first pole connected to the reference level terminal VSS, and a second pole connected to the second pole of the ninth transistor M9. As will be described later, the tenth transistor M10 is turned off when the signal received at the first control terminal IN1 is inactive to cause the source of the denoising transistor (for example, the eighth transistor M8 shown in FIG. 4) to be referenced.
  • the level terminal VSS is turned off, and is turned on when the signal received at the first control terminal IN1 is active to transfer the reference voltage having the inactive level from the reference level terminal VSS to the source of the noise removing transistor.
  • the threshold voltage control circuit 14 also optionally includes a second capacitor C2 coupled between the source of the denoising transistor (eg, the eighth transistor M8 shown in FIG. 4) and the reference level terminal VSS.
  • the second capacitor C2 is used to provide a buffering capability when the ninth transistor M9 is turned on to avoid potential damage caused by a sharp change in the gate-source voltage of the denoising transistor.
  • FIG. 6 is a schematic circuit diagram of a shift register 10 in accordance with an embodiment of the present disclosure.
  • the shift register 10 includes ten transistor circuits (M1 to M10), two capacitors (C1 and C2), and a plurality of input/output terminals (INPUT, RESET, CLK, CLKB, VSS, IN1, IN2). And OUTPUT).
  • each transistor is illustrated and described above as an N-type transistor, in other embodiments a P-type transistor is possible.
  • the active signal has a low level and the inactive signal has a high level.
  • Each transistor may take the form of, for example, a thin film transistor, although other embodiments are possible. Thin film transistors are typically fabricated such that their first and second electrodes are used interchangeably.
  • the source and drain of the transistor are defined in the application circuit.
  • the eighth transistor M8 functioning as a denoising transistor its first pole connected to the output terminal OUTPUT is defined as a drain, and its second pole connected to the second capacitor C2 is defined as a source.
  • FIG. 7 is an example timing diagram of the shift register 10 shown in FIG. 6. The operation of the shift register 10 will be described below with reference to Figs.
  • a first phase S1 the input signal received at the input INPUT is asserted such that the first transistor M1 is turned on to set the potential at the first node PU to be active. Due to the effective potential at the first node PU, the fifth transistor MS is turned on to set the potential at the second node PD to be invalid by transmitting the invalid reference voltage from the reference level terminal VSS to the second node PD. Due to the inactive potential at the second node PD, the seventh transistor M7 and the eighth transistor M8 are turned off. The effective potential at the first node PU also turns on the third transistor M3 to transfer the inactive first clock signal at the first clock terminal CLK to the output terminal OUTPUT. An output signal is output at the output terminal OUTPUT.
  • the input signal received at the input terminal INPUT is deactivated and the first transistor M1 is turned off. Due to the presence of the first capacitor C1, the first node PU remains at an active potential, and thus the second node PD remains at an inactive level.
  • the effective potential at the first node PU turns on the third transistor M3, and the active first clock signal at the first clock terminal CLK is transmitted to the output terminal OUTPUT through the third transistor M3. Due to the bootstrap effect of the first capacitor C1, the potential at the first node PU is changed to be further effective. A valid output signal is output at the output terminal OUTPUT.
  • the reset signal received at the reset terminal RESET is active, and the second clock signal received at the second clock terminal CLKB is active.
  • the second transistor M2 and the fourth transistor M4 are turned on due to the effective reset signal at the reset terminal RESET.
  • the fourth transistor M4 transfers the source voltage of the eighth transistor M8 to the output terminal OUTPUT. Since the signal received at the first control terminal IN1 is valid, the tenth transistor M10 is turned on and thus the source voltage of the eighth transistor M8 is equal to the invalid reference voltage of the reference level terminal VSS. Therefore, the potential at the output terminal OUTPUT is set to be inactive.
  • the second transistor M2 sets the potential of the first node PU to be inactive by transmitting the invalid reference voltage of the reference level terminal VSS to the first node PU, and the third transistor M3 and the fifth transistor M5 are turned off. Since the second clock signal at the second clock terminal CLKB is active, the sixth transistor M6 is turned on and the potential at the second node PD is set to be active, and the seventh transistor M7 and the eighth transistor M8 are turned on. As with the second transistor M2, the seventh transistor M7 also transmits the invalid reference voltage of the reference level terminal VSS to the first node PU such that the potential of the first node PU remains inactive.
  • the eighth transistor M8 also transmits the invalid reference voltage of the reference level terminal VSS to the output terminal OUTPUT, ensuring that the output signal at the output terminal OUTPUT is invalid, thereby reducing the noise at the output terminal OUTPUT. Therefore, the eighth transistor M8 is also referred to herein as a denoising transistor.
  • the first clock signal received at the first clock terminal CLK becomes active, and the second clock signal received at the second clock terminal CLKB becomes inactive. Since the third transistor M3 is in the off state at this time, the effective first clock signal cannot be transmitted to the output terminal OUTPUT, so that the output signal at the output terminal OUTPUT remains inactive.
  • the first node PU remains at an inactive potential and the second node PD remains at an active potential.
  • the denoising transistor M8 is turned on to continuously transmit the invalid reference voltage of the reference level terminal VSS to the output terminal OUTPUT, which ensures the stability of the output signal and eliminates noise.
  • the first clock signal received at the first clock terminal CLK becomes inactive, and the second clock signal received at the second clock terminal CLKB becomes active.
  • the active second clock signal at the second clock terminal CLKB turns on the sixth transistor M6, leaving the potential at the second node PD active. Therefore, the denoising transistor M8 is still in an on state to continue denoising.
  • the signal received at the first control terminal IN1 remains active, and the signal received at the second control terminal IN2 remains inactive.
  • the tenth transistor M10 is continuously turned on to continuously transfer the invalid reference voltage of the reference level terminal VSS to the source of the denoising transistor M8, and the ninth transistor M9 is continuously turned off to make the gate of the denoising transistor M8 and the denoising transistor
  • the source of M8 is not conductive.
  • the fourth stage S4 and the fifth stage S5 are shown as being performed only once in FIG. 7, in the application of the gate driving circuit, the fourth stage S4 and the fifth stage S5 may be repeated several times, so that denoising The transistor M8 is turned on for a long period of time.
  • the gate-source voltage of the denoising transistor M8 is at a high level for a long period of time, causing a drift of its threshold voltage. This can be mitigated or eliminated by subsequent stages of operation.
  • the first clock signal received at the first clock terminal CLK becomes active
  • the second clock signal received at the second clock terminal CLKB becomes inactive
  • the signal received at the first control terminal IN1 The signal becomes active from inactive
  • the signal received at the second control terminal IN2 is changed from invalid to valid.
  • the valid signal at the second control terminal IN2 turns on the ninth transistor M9 to turn on the gate of the denoising transistor M8 and the source of the denoising transistor M8, providing a gate voltage and a source voltage of the denoising transistor M8.
  • the balance, that is, the gate voltage of the denoising transistor M8 is equal to or substantially equal to the source voltage of the denoising transistor M8.
  • the effective potential at the second node PD also charges the second capacitor C2.
  • the invalid signal at the first control terminal IN1 turns off the tenth transistor M10 to disconnect the source of the denoising transistor M8 from the reference level terminal VSS and allows charging of the second capacitor C2.
  • the first node PU remains at an inactive potential and the second node PD remains at an active potential.
  • the first clock signal received at the first clock terminal CLK becomes inactive
  • the second clock signal received at the second clock terminal CLKB becomes active
  • the signal received at the second control terminal IN2 is still valid.
  • the active second clock signal at the second clock terminal CLKB turns on the sixth transistor M6, leaving the second node PD at an active potential.
  • the active signal at the second control terminal IN2 causes the ninth transistor M9 to remain on, thereby continuing to provide a balance between the gate voltage and the source voltage of the denoising transistor M8.
  • the signal received at the first control terminal IN1 is kept inactive during the time interval T
  • the signal received at the second control terminal IN2 is kept valid during the time interval T.
  • the balance between the gate voltage and the source voltage of the denoising transistor M8 is maintained for the time interval T. This can avoid the rise of the threshold voltage due to the de-noising transistor M8 being turned on for a long time, alleviating or eliminating the failure problem of the denoising transistor M8.
  • the first clock signal at the first clock terminal CLK and the second clock signal at the second clock terminal CLKB may be stopped from supplying until the input signal at the input terminal INPUT becomes active. Then, the first clock signal and the second clock signal are again supplied, and the operation of the shift register 10 is restarted from the first phase S1.
  • the period in which the first clock signal and the second clock signal are stopped is referred to as the blanking time Blanking Time.
  • the empty window time may roughly correspond to the vertical blanking interval of the display panel. If the threshold voltage control circuit 14 is not present, then the gate-source voltage of the denoising transistor M8 will continue to be at a high level during the window time, resulting in aggravation of the threshold voltage drift.
  • the gate-source voltage of the denoising transistor M8 is The empty window time is no longer at a high level, which is beneficial to alleviate the threshold voltage drift of the denoising transistor M8.
  • the first control terminal IN1 and the second control terminal IN2 may be respectively applied with an invalid signal and a valid signal at any time after the fifth phase S5, and the application is maintained for a time interval T up to any of the empty window times. time.
  • the first control terminal IN1 and the second control terminal IN2 are respectively applied with an invalid signal and a valid signal at the end of the fifth phase S5 and at the beginning of the sixth phase S6.
  • FIG. 8 is a block diagram of a gate drive circuit 80 in accordance with an embodiment of the present disclosure.
  • the gate driving circuit 80 includes N cascaded shift registers SR(1), SR(2), SR(3), ..., SR(N-1) and SR(N), which Each may take the form of a shift register 10 as described above with respect to Figures 1-7.
  • N may be an integer greater than or equal to two.
  • the first shift register SR(1) of each shift register receives the start signal STV as an input signal at its input terminal IN. Except for the last shift register SR(N), the output OUT of each of the shift registers is connected to the input IN of the next shift register, and the first shift register SR (1) In addition, the output terminal OUT of each of the shift registers is connected to the reset terminal RST of the adjacent previous shift register.
  • N shift registers SR(1), SR(2), SR(3), ..., SR(N-1) and SR(N) are also respectively connected to N gate lines G[1], G[ 2], G[3], ..., G[N-1] and G[N].
  • Each of the shift registers is further connected to a first clock line clk that transmits a clock signal, a second clock line clkb that transmits another clock signal that is inverted from the clock signal, and a first control line that transmits a control signal.
  • a second control line in2 that transmits another control signal inverted from the control signal
  • a reference voltage line vss that transmits a reference voltage having an inactive level.
  • the first clock terminal CLK of the 2k-1th shift register in each shift register is connected to the first clock line clk
  • the second clock terminal CLKB of the 2k-1th shift register is connected to the Two clock lines clkb.
  • the first clock terminal CLK of the 2kth shift register in each shift register is connected to the second clock line clkb, and the second clock terminal CLKB of the 2kth shift register is connected to the first clock line clk.
  • k is a positive integer and 2k ⁇ N.
  • FIG. 9 is a block diagram of a display device 90 in accordance with an embodiment of the present disclosure.
  • the display device 90 includes a display panel 91, a timing controller 92, a gate driver 93, and a data driver 94.
  • the gate driver 93 may take the form of the gate driving circuit 80 described above with respect to FIG. 8, and the first clock line clk, the second clock line clkb, the first control line in1, and the second control shown in FIG.
  • the line in2 and the reference voltage line vss are omitted in FIG. 9 for convenience of illustration.
  • the display panel 91 is connected to a plurality of gate lines GL extending in the first direction D1 and a plurality of data lines DL extending in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 91 includes a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL.
  • Display panel 91 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or any other suitable type of display panel.
  • the timing controller 92 controls the operations of the display panel 91, the gate driver 93, and the data driver 94.
  • the timing controller 92 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels.
  • Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 92 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • Implementations of timing controller 92 are known in the art.
  • the timing controller 92 can be implemented in a number of ways (e.g., using dedicated hardware) to perform the various functions discussed herein.
  • a "processor” is an example of a timing controller 92 that employs one or more microprocessors that can be programmed using software (e.g., microcode) to perform the various functions discussed herein.
  • the timing controller 92 can be implemented with or without a processor, and can also be implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions. Examples of timing controller 92 include, but are not limited to, conventional microprocessors, application specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).
  • the gate driver 93 receives the first control signal CONT1 from the timing controller 92.
  • the first control signal CONT1 may include two clock signals transmitted via the first and second clock lines clk and clkb shown in FIG. 8 and having opposite phases and via the first and second controls shown in FIG. Lines in1 and in2 transmit and have two control signals of opposite phases.
  • the gate driver 93 generates a plurality of gate driving signals for output to the gate line GL based on the first control signal CONT1.
  • the gate driver 93 may sequentially apply a plurality of gate driving signals to the gate lines GL.
  • the data driver 94 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 92.
  • the data driver 94 generates a plurality of data voltages based on the second control signal CONT2 and the output image data RGBD'.
  • the data driver 94 can apply the generated plurality of data voltages to the data line DL.
  • the gate driver 93 and/or the data driver 94 may be disposed on the display panel 91 or may be connected to the display panel 91 by, for example, a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the gate driver 93 can be integrated in the display panel 91 as a GOA circuit.
  • display device 90 can be any product or component having a display function, such as a cell phone, tablet, television, display, notebook, digital photo frame, navigator, and the like.

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Abstract

一种移位寄存器(10)，包括：节点控制电路(11,12)，被配置成在输入信号(INPUT)、复位信号(RESET)和第二节点(PD)处的电位的控制下设定第一节点(PU)处的电位，并且在第二时钟信号(CLKB)和第一节点(PU)处的电位的控制下设定第二节点(PD)处的电位；输出电路（13），被配置成在第一时钟信号(CLK)、第一节点(PU)处的电位、第二节点(PD)处的电位和复位信号(RESET)的控制下，在输出端(OUTPUT)输出输出信号，输出电路(13)包括去噪晶体管，其包括连接到第二节点(PD)的栅极、连接到输出端的漏极、以及源极；以及阈值电压控制电路(14)，被配置成在控制信号和第二节点(PD)处的电位的控制下，设定去噪晶体管的源极处的电位以实现在一时间间隔内去噪晶体管的栅极电压与源极电压之间的平衡。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请要求2017年5月4日提交的中国专利申请No.201710308386.6的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，具体涉及一种移位寄存器及其驱动方法和栅极驱动电路。
背景技术
随着被称为阵列基板栅极驱动(Gate Driver on Array，GOA)的技术的出现，具有窄边框的显示面板成为可能。GOA技术将包括级联的多个移位寄存器的栅极驱动电路直接集成在阵列基板上以代替外接驱动芯片，提供了高的集成度和小的占用面积等优点。
发明内容
根据本公开的一个方面，提供了一种移位寄存器，包括：输入端，用于接收输入信号；复位端，用于接收复位信号；第一时钟端，用于接收第一时钟信号；第二时钟端，用于接收第二时钟信号；控制端，用于接收控制信号；输出端，用于输出输出信号；节点控制电路，被配置成在所述输入信号、所述复位信号和第二节点处的电位的控制下设定第一节点处的电位，所述节点控制电路还被配置成在所述第二时钟信号和所述第一节点处的电位的控制下设定所述第二节点处的电位；输出电路，被配置成在所述第一时钟信号、所述第一节点处的电位、所述第二节点处的电位和所述复位信号的控制下，在所述输出端输出所述输出信号，其中所述输出电路包括去噪晶体管，其包括连接到所述第二节点的栅极、连接到所述输出端的漏极、以及源极；以及阈值电压控制电路，被配置成在所述控制信号和所述第二节点处的电位的控制下，设定所述去噪晶体管的源极处的电位以实现在一时间间隔内所述去噪晶体管的栅极电压与源极电压之间的平衡。
在一些示例性实施例中，所述节点控制电路包括：第一节点控制 电路，被配置成响应于所述输入信号有效而将所述第一节点处的电位设定为有效，并且响应于所述复位信号或所述第二节点处的电位中的至少一个有效而将所述第一节点处的电位设定为无效；以及第二节点控制电路，被配置成响应于所述第二时钟信号有效而将所述第二节点处的电位设定为有效，并且响应于所述第一节点处的电位有效而将所述第二节点处的电位设定为无效。
在一些示例性实施例中，所述第一节点控制电路包括：第一晶体管，包括连接到所述输入端的栅极、连接到所述输入端的第一极、以及连接到所述第一节点的第二极；第二晶体管，包括连接到所述复位端的栅极、连接到所述第一节点的第一极、连接到用于供应具有无效电平的参考电压的参考电平端的第二极；以及第七晶体管，包括连接到所述第二节点的栅极、连接到所述第一节点的第一极、以及连接到所述参考电平端的第二极。
在一些示例性实施例中，所述第二节点控制电路包括：第五晶体管，包括连接到所述第一节点的栅极、连接到所述第二节点的第一极、以及连接到所述参考电平端的第二极；以及第六晶体管，包括连接到所述第二时钟端的栅极、连接到所述第二时钟端的第一极、以及连接到所述第二节点的第二极。
在一些示例性实施例中，所述输出电路包括：第三晶体管，被配置成响应于所述第一节点处的电位有效而将所述第一时钟信号传送到所述输出端；第四晶体管，被配置成响应于所述复位信号有效而将所述去噪晶体管的源极电压传送到所述输出端；第八晶体管，充当所述去噪晶体管并且被配置成响应于所述第二节点处的电位有效而将所述去噪晶体管的源极电压传送到所述输出端；以及第一电容，连接在所述第一节点与所述输出端之间。
在一些示例性实施例中，所述第三晶体管包括连接到所述第一节点的栅极、连接到所述第一时钟端的第一极、以及连接到所述输出端的第二极，并且所述第四晶体管包括连接到所述复位端的栅极、连接到所述输出端的第一极、以及连接到所述去噪晶体管的源极的第二极。
在一些示例性实施例中，所述控制端包括第一控制端和第二控制端，并且所述阈值电压控制电路包括：第九晶体管，被配置成响应于 在所述第二控制端处接收的信号无效而使所述去噪晶体管的栅极与所述去噪晶体管的源极不导通，并且响应于在所述第二控制端处接收的信号在所述时间间隔内有效而使所述去噪晶体管的栅极在所述时间间隔内与所述去噪晶体管的源极导通；以及第十晶体管，被配置成响应于在所述第一控制端处接收的信号有效而使得用于供应具有无效电平的参考电压的参考电平端与所述去噪晶体管的源极导通，并且响应于在所述第一控制端处接收的信号在所述时间间隔内无效而使得所述参考电平端与所述去噪晶体管的源极不导通。
在一些示例性实施例中，所述第九晶体管包括连接到所述第二控制端的栅极、连接到所述第二节点的第一极、以及连接到所述去噪晶体管的源极的第二极，并且所述第十晶体管包括连接到所述第一控制端的栅极、连接到所述参考电平端的第一极、以及连接到所述去噪晶体管的源极的第二极。
在一些示例性实施例中，所述移位寄存器还包括第二电容，其连接在所述去噪晶体管的源极与所述参考电平端之间。
根据本公开的另一方面，提供了一种驱动移位寄存器的方法。所述移位寄存器包括用于接收输入信号的输入端、用于接收复位信号的复位端、用于接收第一时钟信号的第一时钟端、用于接收第二时钟信号的第二时钟端、用于接收控制信号的控制端、用于输出输出信号的输出端、节点控制电路、输出电路和阈值电压控制电路。所述方法包括：在所述输入信号、所述复位信号和第二节点处的电位的控制下，由所述节点控制电路设定第一节点处的电位；在所述第二时钟信号和所述第一节点处的电位的控制下，由所述节点控制电路设定所述第二节点处的电位；在所述第一时钟信号、所述第一节点处的电位、所述第二节点处的电位和所述复位信号的控制下，由所述输出电路在所述输出端输出所述输出信号，其中所述输出电路包括去噪晶体管，其包括连接到所述第二节点的栅极、连接到所述输出端的漏极、以及源极；以及在所述控制信号和所述第二节点处的电位的控制下，由所述阈值电压控制电路设定所述去噪晶体管的源极处的电位以实现在一时间间隔内所述去噪晶体管的栅极电压与源极电压之间的平衡。
根据本公开的又另一方面，提供了一种栅极驱动电路，包括N个级联的如上所述的移位寄存器，N为大于等于2的正整数。所述移位 寄存器中的第m个的输出端连接到所述移位寄存器中的第m+1个的输入端，m为整数且1≤m＜N。所述移位寄存器中的第n个的输出端连接到所述移位寄存器中的第n-1个的复位端，n为整数且1＜n≤N。
根据本公开的再另一方面，提供了一种显示装置，包括如上所述的栅极驱动电路。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1为根据本公开实施例的移位寄存器的框图；
图2为在图1的基础上图示出第一节点控制电路的示例电路的示意图；
图3为在图1的基础上图示出第二节点控制电路的示例电路的示意图；
图4为在图1的基础上图示出输出电路的示例电路的示意图；
图5为在图1的基础上图示出阈值电压控制电路的示例电路的示意图；
图6为根据本公开实施例的移位寄存器的示意电路图；
图7为图6所示的移位寄存器的示例时序图；
图8为根据本公开实施例的栅极驱动电路的框图；并且
图9为根据本公开实施例的显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图 也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
在一些情况下，GOA结构中的晶体管中的一些需要在长时间段内处于开启状态以去除噪音。这些晶体管在长期工作之后可能失效，例如变为不易开启。本申请人认识到，这可能是由于它们的栅极电压与源极电压之间差值在长时间内处于高水平的事实引起的这些晶体管的阈值电压的上升所致的。基于对此问题的洞见，提出了下面结合实施例和附图详细描述的解决方案。
图1为根据本公开实施例的移位寄存器10的框图。如图1所示，移位寄存器10包括用于接收输入信号的输入端INPUT、用于接收复位信号的复位端RESET、用于接收第一时钟信号的第一时钟端CLK、用于接收第二时钟信号的第二时钟端CLKB、用于接收控制信号的控制端IN和用于输出输出信号的输出端OUTPUT。移位寄存器10还包括被示出为由第一节点控制电路11和第二节点控制电路12两者体现的节点控制电路、输出电路13和阈值电压控制电路14。
节点控制电路被配置成在所述输入信号、所述复位信号和第二节点PD处的电位的控制下设定第一节点PU处的电位，并且在所述第二 时钟信号和所述第一节点PU处的电位的控制下设定第二节点PD处的电位。具体地，第一节点控制电路11响应于所述输入信号有效而将所述第一节点PU的电位设定为有效，并且响应于所述复位信号或所述第二节点PD的电位中的至少一个有效而将所述第一节点PU的电位设定为无效。第二节点控制电路12响应于所述第二时钟信号有效而将所述第二节点PD的电位设定为有效，并且响应于所述第一节点PU处的电位有效而将所述第二节点PD的电位设定为无效。
如本文中结合电路或电路的部件使用的短语“信号或电位有效”是指该信号使得该电路或电路的部件在该信号或电位的控制下被启用。相反，短语“信号或电位无效”是指该信号或电位使得该电路或电路的部件在该信号或电位的控制下被禁用。例如，对于N型晶体管，有效信号或电位具有高电平，并且无效信号或电位具有低电平。
输出电路13被配置成在所述第一时钟信号、所述第一节点PU处的电位、所述第二节点PD处的电位和所述复位信号的控制下，在所述输出端OUTPUT输出所述输出信号。如下面将描述的，所述输出电路13包括去噪晶体管，其包括连接到所述第二节点PD的栅极、连接到所述输出端OUTPUT的漏极、以及源极。
阈值电压控制电路14被配置成在所述控制信号和所述第二节点PD处的电位的控制下，设定所述去噪晶体管的源极处的电位以实现在一时间间隔内所述去噪晶体管的栅极电压与源极电压之间的平衡。通过在移位寄存器10中引入阈值电压控制电路，移位寄存器10中的去噪晶体管的栅极电压和源极电压在所述时间间隔内被平衡(例如，相等或基本上相等，如后面将描述的)。这有利于避免由于晶体管长时间处于开启状态而导致的其阈值电压的上升，从而缓解或者甚至消除晶体管的失效。
图2为在图1的基础上图示出第一节点控制电路11的示例电路的示意图。如图2所示，第一节点控制电路11包括第一晶体管M1、第二晶体管M2和第七晶体管M7。
第一晶体管M1具有与输入端INPUT连接的栅极和第一极以及与第一节点PU连接的第二极。当在输入端INPUT处接收的输入信号有效时，第一晶体管M1被开启以将第一节点PU的电位设定为有效。
第二晶体管M2具有与复位端RESET连接的栅极、与第一节点PU 连接的第一极、以及与供应具有无效电平的参考电压的参考电平端VSS连接的第二极。当在复位端RESET处接收的复位信号有效时，第二晶体管M2被开启以将第一节点PU的电位设定为无效。
第七晶体管M7具有与第二节点PD连接的栅极、与第一节点PU连接第一极、以及与参考电平端VSS连接的第二极。在第二节点PD处于有效电位时，第七晶体管M7被开启以将第一节点PU的电位设定为无效。
图3为在图1的基础上图示出第二节点控制电路12的示例电路的示意图。如图3所示，第二节点控制电路12包括第五晶体管M5和第六晶体管M6。
第五晶体管M5具有与第一节点PU连接的栅极、与第二节点PD连接的第一极、以及与参考电平端VSS连接的第二极。在第一节点PU处于有效电位时，第五晶体管M5被开启以将第二节点PD的电位设定为无效。
第六晶体管M6具有与第二时钟端CLKB连接的栅极和第二极以及与第二节点PD连接的第一极。当在第二时钟端CLKB处接收的第二时钟信号有效时，第六晶体管M6被开启以将第二节点PD的电位设定为有效。
图4为在图1的基础上图示出输出电路13的示例电路的示意图。如图4所示，输出电路13包括第三晶体管M3、第四晶体管M4、第八晶体管M8和第一电容C1。
第八晶体管M8具有与第二节点PD连接的栅极、与输出端OUTPUT连接的第一极、以及与阈值电压控制电路14连接的第二极。第八晶体管M8充当去噪晶体管。如后面将描述的，在第二节点PD处于有效电位时，第八晶体管M8被开启以将输出端OUTPUT处的电位设定为无效。这可以使得在输出端OUTPUT处输出的输出信号保持处于无效电位，从而消除噪声。
第三晶体管M3具有与第一节点PU连接的栅极、与第一时钟端CLK连接的第一极、以及与输出端OUTPUT连接的第二极。在第一节点PU处于有效电位时，第三晶体管M3被开启以将在第一时钟端CLK处接收的第一时钟信号作为输出信号从输出端OUTPUT处输出。
第四晶体管M4具有与复位端RESET连接的栅极、与输出端 OUTPUT连接的第一极、以及与阈值电压控制电路14连接的第二极。如后面将描述的，当在复位端RESET处接收的复位信号有效时，第四晶体管M4被开启以将其输出端OUTPUT处的电位设定为无效。
第一电容C1连接在第一节点PU与输出端OUTPUT之间。第一电容C1可以被充电以使得第一节点PU处的电位被设定为有效。
图5为在图1的基础上图示出阈值电压控制电路14的示例电路的示意图。如图5所示，阈值电压控制电路14包括第九晶体管M9和第十晶体管M10。在图5中，图1中所示的控制端IN被示出为包括第一控制端IN1和第二控制端IN2。
第九晶体管M9具有与第二控制端IN2连接的栅极、与第二节点PD连接的第一极、以及与输出电路13连接的第二极。如后面将描述的，当在第二控制端IN2处接收的信号有效时，第九晶体管M9被开启以使去噪晶体管(例如，图4中所示的第八晶体管M8)的栅极与去噪晶体管的源极导通。在这种情况下，去噪晶体管的栅极电压等于或基本上等于去噪晶体管的源极电压，从而允许其中去噪晶体管的栅-源电压处于高水平下的缩短的时间段。这有利于缓解或消除由于去噪晶体管的阈值电压的漂移所致的失效。如本文中使用的短语“A基本上等于B”可以是指A等于B或者A与B之间的差值落入由于例如工程误差而致的容差内。
第十晶体管M10具有与第一控制端IN1连接的栅极、与参考电平端VSS连接的第一极、以及与第九晶体管M9的第二极连接的第二极。如后面将描述的，第十晶体管M10当在第一控制端IN1处接收的信号无效时被关断以使去噪晶体管(例如，图4中所示的第八晶体管M8)的源极从参考电平端VSS断开，并且当在第一控制端IN1处接收的信号有效时被开启以将具有无效电平的参考电压从参考电平端VSS传送到去噪晶体管的源极。
阈值电压控制电路14还可选地包括连接在去噪晶体管(例如，图4中所示的第八晶体管M8)的源极与参考电平端VSS之间的第二电容C2。第二电容C2用于在第九晶体管M9被开启时提供缓冲能力以避免去噪晶体管的栅-源电压的急剧变化造成的潜在损坏。
图6为根据本公开实施例的移位寄存器10的示意电路图。如图6所示，移位寄存器10包括10个晶体管电路(M1～M10)、2个电容 (C1和C2)、以及若干输入/输出端子(INPUT、RESET、CLK、CLKB、VSS、IN1、IN2和OUTPUT)。
这样的移位寄存器10的配置已经在上面关于图2-5进行了详细描述，并且在此为了简洁起见不再重复。虽然各晶体管在上面被图示和描述为N型晶体管，但是在其他实施例中P型晶体管是可能的。在P型晶体管的情况下，有效信号具有低电平，并且无效信号具有高电平。各晶体管可以采取例如薄膜晶体管的形式，尽管其他实施例是可能的。薄膜晶体管典型地被制作使得它的第一电极和第二电极可互换地使用。在这种情况下，晶体管的源极和漏极是在应用电路中定义的。例如，对于充当去噪晶体管的第八晶体管M8，它的连接到输出端OUTPUT的第一极被定义为漏极，并且它的连接到第二电容C2的第二极被定义为源极。
图7为图6所示的移位寄存器10的示例时序图。下面结合图6和7描述移位寄存器10的操作。
在第一阶段S1，在输入端INPUT处接收的输入信号有效，使得第一晶体管M1开启以将第一节点PU处的电位设定为有效。由于第一节点PU处的有效电位，第五晶体管MS开启以通过将来自参考电平端VSS的无效参考电压传送到第二节点PD来将第二节点PD处的电位设定为无效。由于第二节点PD处的无效电位，第七晶体管M7和第八晶体管M8关断。第一节点PU处的有效电位还使第三晶体管M3开启以将第一时钟端CLK处的无效的第一时钟信号传送到输出端OUTPUT。输出端OUTPUT处输出无效的输出信号。
在第二阶段S2，在输入端INPUT处接收的输入信号无效，并且第一晶体管M1关断。由于第一电容C1的存在，第一节点PU保持处于有效电位，并且因此第二节点PD保持处于无效电平。第一节点PU处的有效电位使第三晶体管M3开启，并且第一时钟端CLK处的有效的第一时钟信号通过第三晶体管M3被传送到输出端OUTPUT。由于第一电容C1的自举效应，第一节点PU处的电位被改变为进一步有效。输出端OUTPUT处输出有效的输出信号。
在第三阶段S3，在复位端RESET处接收的复位信号有效，并且在第二时钟端CLKB处接收的第二时钟信号有效。由于复位端RESET处的有效的复位信号，第二晶体管M2和第四晶体管M4开启。第四晶 体管M4将第八晶体管M8的源极电压传送到输出端OUTPUT。由于在第一控制端IN1处接收的信号有效，所以第十晶体管M10被开启并且因此第八晶体管M8的源极电压等于参考电平端VSS的无效参考电压。因此，输出端OUTPUT处的电位被设定为无效。第二晶体管M2通过将参考电平端VSS的无效参考电压传送到第一节点PU而将第一节点PU的电位设定为无效，并且第三晶体管M3和第五晶体管M5关断。由于第二时钟端CLKB处的第二时钟信号有效，所以第六晶体管M6开启并将第二节点PD处的电位设定为有效，开启第七晶体管M7和第八晶体管M8。如同第二晶体管M2所做的，第七晶体管M7也将参考电平端VSS的无效参考电压传送至第一节点PU，使得第一节点PU的电位保持无效。如同第四晶体管M4所做的，第八晶体管M8也将参考电平端VSS的无效参考电压传送至输出端OUTPUT，确保输出端OUTPUT处的输出信号无效，从而降低输出端OUTPUT处的噪声。因此，第八晶体管M8在本文中也被称为去噪晶体管。
在第四阶段S4，在第一时钟端CLK处接收的第一时钟信号变为有效，并且在第二时钟端CLKB处接收的第二时钟信号变为无效。由于此时第三晶体管M3处于关断状态，因此有效的第一时钟信号无法传送到输出端OUTPUT，使得输出端OUTPUT处的输出信号保持无效。第一节点PU保持处于无效电位，并且第二节点PD保持处于有效电位。去噪晶体管M8处于开启状态以持续将参考电平端VSS的无效参考电压传送至输出端OUTPUT，保证了输出信号的稳定，消除了噪声。
在第五阶段S5，在第一时钟端CLK处接收的第一时钟信号变为无效，并且在第二时钟端CLKB处接收的第二时钟信号变为有效。第二时钟端CLKB处的有效的第二时钟信号使第六晶体管M6开启，使第二节点PD处的电位保持有效。因此，去噪晶体管M8仍然处于开启状态以持续进行去噪。从第一阶段S1至第五阶段S5，在第一控制端IN1处接收的信号保持有效，并且在第二控制端IN2处接收的信号保持无效。因此，第十晶体管M10持续开启以将参考电平端VSS的无效参考电压持续传送到去噪晶体管M8的源极，并且第九晶体管M9持续关断以使去噪晶体管M8的栅极与去噪晶体管M8的源极不导通。
虽然第四阶段S4和第五阶段S5在图7中被示出为仅执行一次， 但是在栅极驱动电路的应用中，第四阶段S4和第五阶段S5可以被重复若干次，使得去噪晶体管M8在长时间段内处于开启状态。在这种情况下，去噪晶体管M8的栅-源电压在长时间段内处于高水平，引起其阈值电压的漂移。这可以由后续阶段的操作来缓解或消除。
在第六阶段S6，在第一时钟端CLK处接收的第一时钟信号变为有效，在第二时钟端CLKB处接收的第二时钟信号变为无效，在第一控制端IN1处接收的信号由有效变为无效，并且在第二控制端IN2处接收的信号由无效变为有效。第二控制端IN2处的有效信号使第九晶体管M9开启以使去噪晶体管M8的栅极与去噪晶体管M8的源极导通，提供去噪晶体管M8的栅极电压与源极电压之间的平衡，即，去噪晶体管M8的栅极电压等于或基本上等于去噪晶体管M8的源极电压。第二节点PD处的有效电位还对第二电容C2充电。第一控制端IN1处的无效信号使第十晶体管M10关断以使去噪晶体管M8的源极从参考电平端VSS断开，并且允许对第二电容C2的充电。第一节点PU保持处于无效电位，并且第二节点PD保持处于有效电位。
在第七阶段S7，在第一时钟端CLK处接收的第一时钟信号变为无效，在第二时钟端CLKB处接收的第二时钟信号变为有效，在第一控制端IN1处接收的信号仍然无效，并且在第二控制端IN2处接收的信号仍然有效。第二时钟端CLKB处的有效的第二时钟信号使第六晶体管M6开启，使第二节点PD保持处于有效电位。第二控制端IN2处的有效信号使第九晶体管M9持续开启，从而继续提供去噪晶体管M8的栅极电压与源极电压之间的平衡。如图7所示，在第一控制端IN1处接收的信号在时间间隔T内被保持无效，并且在第二控制端IN2处接收的信号在该时间间隔T内被保持有效。作为结果，去噪晶体管M8的栅极电压与源极电压之间的平衡被保持该时间间隔T。这可以避免由于去噪晶体管M8长时间处于开启状态导致阈值电压的上升，缓解或消除去噪晶体管M8的失效问题。
在第七阶段S7之后，第一时钟端CLK处的第一时钟信号和第二时钟端CLKB处的第二时钟信号可以被停止供应，一直到输入端INPUT处的输入信号变为有效为止。然后，第一时钟信号和第二时钟信号再次被提供，并且移位寄存器10的操作再从第一阶段S1重新开始。其中第一时钟信号和第二时钟信号被停止供应的时间段被称之为 空窗时间Blanking Time。在栅极驱动电路的应用中，空窗时间可以粗略地对应于显示面板的垂直消隐间隔。如果阈值电压控制电路14不存在，那么在该空窗时间内去噪晶体管M8的栅-源电压将继续处于高水平，导致阈值电压漂移的加重。相比之下，通过在移位寄存器10中引入包括第九晶体管M9和第十晶体管M10(以及可选地第二电容C2)的阈值电压控制电路14，去噪晶体管M8的栅-源电压在空窗时间内不再处于高水平，有利于缓解去噪晶体管M8的阈值电压漂移。在实践中，第一控制端IN1和第二控制端IN2可以在第五阶段S5之后的任意时间处被分别施加无效信号和有效信号，并且该施加被维持时间间隔T直至空窗时间中的任意时刻。在图7所示的示例中，第一控制端IN1和第二控制端IN2在第五阶段S5的结束处和第六阶段S6的开始处被分别施加无效信号和有效信号。
图8为根据本公开实施例的栅极驱动电路80的框图。参考图8，栅极驱动电路80包括N个级联的移位寄存器SR(1)，SR(2)，SR(3)，...，SR(N-1)和SR(N)，其每一个可以采取如上面关于图1至7描述的移位寄存器10的形式。N可以是大于或等于2的整数。
在栅极驱动电路80中，各移位寄存器中的第一个移位寄存器SR(1)在其输入端IN处接收起始信号STV作为输入信号。除了最后一个移位寄存器SR(N)之外，各移位寄存器中的每一个的输出端OUT连接到相邻下一个移位寄存器的输入端IN，并且除了第一个移位寄存器SR(1)之外，各移位寄存器中的每一个的输出端OUT连接到相邻上一个移位寄存器的复位端RST。N个移位寄存器SR(1)，SR(2)，SR(3)，...，SR(N-1)和SR(N)还分别连接到N条栅线G[1]，G[2]，G[3]，...，G[N-1]和G[N]。各移位寄存器中的每一个还连接到传送一时钟信号的第一时钟线clk、传送与该时钟信号反相的另一时钟信号的第二时钟线clkb、传送一控制信号的第一控制线in1、传送与该控制信号反相的另一控制信号的第二控制线in2、以及传送具有无效电平的参考电压的参考电压线vss。特别地，各移位寄存器中的第2k-1个移位寄存器的第一时钟端CLK连接到第一时钟线clk，并且该第2k-1个移位寄存器的第二时钟端CLKB连接到第二时钟线clkb。各移位寄存器中的第2k个移位寄存器的第一时钟端CLK连接到第二时钟线clkb，并且该第2k个移位寄存器的第二时钟端CLKB连接到第一时钟线clk。k为正整数且2k≤N。
图9是根据本公开实施例的显示装置90的框图。参考图9，显示装置90包括显示面板91、时序控制器92、栅极驱动器93和数据驱动器94。栅极驱动器93可以采取上面关于图8所述的栅极驱动电路80的形式，并且在图8中示出的第一时钟线clk、第二时钟线clkb、第一控制线in1、第二控制线in2和参考电压线vss在图9中为了图示的方便被省略。
显示面板91连接至在第一方向D1上延伸的多个栅极线GL和在与第一方向D1交叉(例如，基本垂直)的第二方向D2上延伸的多个数据线DL。显示面板91包括以矩阵形式排列的多个像素(未示出)。所述像素中的每一个可电连接至栅极线GL中的对应一条栅极线和数据线DL中的对应一条数据线。显示面板91可以是液晶显示面板、有机发光二极管(OLED)显示面板或任何其他合适类型的显示面板。
时序控制器92控制显示面板91、栅极驱动器93和数据驱动器94的操作。时序控制器92从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器92基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。时序控制器92的实现方式是本领域已知的。时序控制器92可以以许多方式(例如诸如利用专用硬件)实现以便执行本文讨论的各种不同的功能。“处理器”是采用一个或多个微处理器的时序控制器92的一个示例，所述微处理器可以使用软件(例如微代码)进行编程以便执行本文讨论的各种不同的功能。时序控制器92可以在采用或者在不采用处理器的情况下实现，并且也可以实现为执行一些功能的专用硬件和执行其他功能的处理器的组合。时序控制器92的示例包括但不限于常规的微处理器、专用集成电路(ASIC)以及现场可编程门阵列(FPGA)。
栅极驱动器93从时序控制器92接收第一控制信号CONT1。第一控制信号CONT1可以包括经由在图8中示出的第一和第二时钟线clk和clkb传送且具有相反相位的两个时钟信号和经由在图8中示出的第 一和第二控制线in1和in2传送且具有相反相位的两个控制信号。栅极驱动器93基于第一控制信号CONT1生成用于输出到栅极线GL的多个栅极驱动信号。栅极驱动器93可顺序地将多个栅极驱动信号施加至栅极线GL。
数据驱动器94从时序控制器92接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动器94基于第二控制信号CONT2和输出图像数据RGBD’生成多个数据电压。数据驱动器94可将生成的多个数据电压施加至数据线DL。
在各实施例中，栅极驱动器93和/或数据驱动器94可被设置在显示面板91上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)而连接至显示面板91。例如，栅极驱动器93可被集成在显示面板91中作为GOA电路。作为示例而非限制，显示装置90可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
上述内容仅为便于理解本公开的目的而描述的特定实施方式，并非意图用以限定本公开。本领域普通技术人员可以对所描述的实施例做出各种修改与变化而不脱离本公开的范围。因此，本公开的范围以所附的权利要求书为准。

Claims (16)

  1. 一种移位寄存器，包括：
    输入端，用于接收输入信号；
    复位端，用于接收复位信号；
    第一时钟端，用于接收第一时钟信号；
    第二时钟端，用于接收第二时钟信号；
    控制端，用于接收控制信号；
    输出端，用于输出输出信号；
    节点控制电路，被配置成在所述输入信号、所述复位信号和第二节点处的电位的控制下设定第一节点处的电位，所述节点控制电路还被配置成在所述第二时钟信号和所述第一节点处的电位的控制下设定所述第二节点处的电位；
    输出电路，被配置成在所述第一时钟信号、所述第一节点处的电位、所述第二节点处的电位和所述复位信号的控制下，在所述输出端输出所述输出信号，其中所述输出电路包括去噪晶体管，其包括连接到所述第二节点的栅极、连接到所述输出端的漏极、以及源极；以及
    阈值电压控制电路，被配置成在所述控制信号和所述第二节点处的电位的控制下，设定所述去噪晶体管的源极处的电位以实现在一时间间隔内所述去噪晶体管的栅极电压与源极电压之间的平衡。
  2. 根据权利要求1所述的移位寄存器，其中所述节点控制电路包括：
    第一节点控制电路，被配置成响应于所述输入信号有效而将所述第一节点处的电位设定为有效，并且响应于所述复位信号或所述第二节点处的电位中的至少一个有效而将所述第一节点处的电位设定为无效；以及
    第二节点控制电路，被配置成响应于所述第二时钟信号有效而将所述第二节点处的电位设定为有效，并且响应于所述第一节点处的电位有效而将所述第二节点处的电位设定为无效。
  3. 根据权利要求2所述的移位寄存器，其中所述第一节点控制电路包括：
    第一晶体管，包括连接到所述输入端的栅极、连接到所述输入端 的第一极、以及连接到所述第一节点的第二极；
    第二晶体管，包括连接到所述复位端的栅极、连接到所述第一节点的第一极、连接到用于供应具有无效电平的参考电压的参考电平端的第二极；以及
    第七晶体管，包括连接到所述第二节点的栅极、连接到所述第一节点的第一极、以及连接到所述参考电平端的第二极。
  4. 根据权利要求3所述的移位寄存器，其中所述第二节点控制电路包括：
    第五晶体管，包括连接到所述第一节点的栅极、连接到所述第二节点的第一极、以及连接到所述参考电平端的第二极；以及
    第六晶体管，包括连接到所述第二时钟端的栅极、连接到所述第二时钟端的第一极、以及连接到所述第二节点的第二极。
  5. 根据权利要求1所述的移位寄存器，其中所述输出电路包括：
    第三晶体管，被配置成响应于所述第一节点处的电位有效而将所述第一时钟信号传送到所述输出端；
    第四晶体管，被配置成响应于所述复位信号有效而将所述去噪晶体管的源极电压传送到所述输出端；
    第八晶体管，充当所述去噪晶体管并且被配置成响应于所述第二节点处的电位有效而将所述去噪晶体管的源极电压传送到所述输出端；以及
    第一电容，连接在所述第一节点与所述输出端之间。
  6. 根据权利要求5所述的移位寄存器，其中所述第三晶体管包括连接到所述第一节点的栅极、连接到所述第一时钟端的第一极、以及连接到所述输出端的第二极，并且其中所述第四晶体管包括连接到所述复位端的栅极、连接到所述输出端的第一极、以及连接到所述去噪晶体管的源极的第二极。
  7. 根据权利要求1～6任一所述的移位寄存器，其中所述控制端包括第一控制端和第二控制端，并且其中所述阈值电压控制电路包括：
    第九晶体管，被配置成响应于在所述第二控制端处接收的信号无效而使所述去噪晶体管的栅极与所述去噪晶体管的源极不导通，并且响应于在所述第二控制端处接收的信号在所述时间间隔内有效而使所 述去噪晶体管的栅极在所述时间间隔内与所述去噪晶体管的源极导通；以及
    第十晶体管，被配置成响应于在所述第一控制端处接收的信号有效而使得用于供应具有无效电平的参考电压的参考电平端与所述去噪晶体管的源极导通，并且响应于在所述第一控制端处接收的信号在所述时间间隔内无效而使得所述参考电平端与所述去噪晶体管的源极不导通。
  8. 根据权利要求7所述的移位寄存器，其中所述第九晶体管包括连接到所述第二控制端的栅极、连接到所述第二节点的第一极、以及连接到所述去噪晶体管的源极的第二极，并且其中所述第十晶体管包括连接到所述第一控制端的栅极、连接到所述参考电平端的第一极、以及连接到所述去噪晶体管的源极的第二极。
  9. 根据权利要求7所述的移位寄存器，还包括第二电容，其连接在所述去噪晶体管的源极与所述参考电平端之间。
  10. 一种驱动移位寄存器的方法，所述移位寄存器包括用于接收输入信号的输入端、用于接收复位信号的复位端、用于接收第一时钟信号的第一时钟端、用于接收第二时钟信号的第二时钟端、用于接收控制信号的控制端、用于输出输出信号的输出端、节点控制电路、输出电路和阈值电压控制电路，所述方法包括：
    在所述输入信号、所述复位信号和第二节点处的电位的控制下，由所述节点控制电路设定第一节点处的电位；
    在所述第二时钟信号和所述第一节点处的电位的控制下，由所述节点控制电路设定所述第二节点处的电位；
    在所述第一时钟信号、所述第一节点处的电位、所述第二节点处的电位和所述复位信号的控制下，由所述输出电路在所述输出端输出所述输出信号，其中所述输出电路包括去噪晶体管，其包括连接到所述第二节点的栅极、连接到所述输出端的漏极、以及源极；以及
    在所述控制信号和所述第二节点处的电位的控制下，由所述阈值电压控制电路设定所述去噪晶体管的源极处的电位以实现在一时间间隔内所述去噪晶体管的栅极电压与源极电压之间的平衡。
  11. 根据权利要求10所述的方法，其中设定所述第一节点处的电位包括：
    响应于所述输入信号有效而将所述第一节点处的电位设定为有效；并且
    响应于所述复位信号或所述第二节点处的电位中的至少一个有效而将所述第一节点处的电位设定为无效。
  12. 根据权利要求10所述的方法，其中设定所述第二节点处的电位包括：
    响应于所述第二时钟信号有效而将所述第二节点处的电位设定为有效；并且
    响应于所述第一节点处的电位有效而将所述第二节点处的电位设定为无效。
  13. 根据权利要求10所述的方法，其中输出所述输出信号包括：
    响应于所述第一节点处的电位有效而将所述第一时钟信号传送到所述输出端；
    响应于所述复位信号有效而将所述去噪晶体管的源极电压传送到所述输出端；并且
    响应于所述第二节点处的电位有效而将所述去噪晶体管的源极电压传送到所述输出端。
  14. 根据权利要求10～13任一所述的方法，其中所述控制端包括第一控制端和第二控制端，并且其中设定所述去噪晶体管的源极处的电位包括：
    响应于在所述第二控制端处接收的信号无效而使所述去噪晶体管的栅极与所述去噪晶体管的源极不导通；
    响应于在所述第二控制端处接收的信号在所述时间间隔内有效而使所述去噪晶体管的栅极在所述时间间隔内与所述去噪晶体管的源极导通；
    响应于在所述第一控制端处接收的信号有效而使得用于供应具有无效电平的参考电压的参考电平端与所述去噪晶体管的源极导通；并且
    响应于在所述第一控制端处接收的信号在所述时间间隔内无效而使得所述参考电平端与所述去噪晶体管的源极不导通。
  15. 一种栅极驱动电路，包括N个级联的如权利要求1～9任一所述的移位寄存器，N为大于等于2的正整数，其中：
    所述移位寄存器中的第m个的输出端连接到所述移位寄存器中的第m+1个的输入端，m为整数且1≤m＜N；并且
    所述移位寄存器中的第n个的输出端连接到所述移位寄存器中的第n-1个的复位端，n为整数且1＜n≤N。
  16. 一种显示装置，包括如权利要求15所述的栅极驱动电路。
PCT/CN2018/079815 2017-05-04 2018-03-21 移位寄存器及其驱动方法、栅极驱动电路和显示装置 WO2018201815A1 (zh)

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KR102393141B1 (ko) * 2017-08-21 2022-05-02 엘지디스플레이 주식회사 게이트 구동회로 및 이를 이용한 표시장치와 그 구동 방법
CN107369428B (zh) * 2017-09-22 2019-12-03 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111179827B (zh) * 2020-01-15 2021-02-23 深圳市华星光电半导体显示技术有限公司 外部补偿goa电路及显示面板
CN115398519A (zh) 2021-03-05 2022-11-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208263A (zh) * 2013-03-14 2013-07-17 京东方科技集团股份有限公司 移位寄存器、显示装置、栅极驱动电路及驱动方法
CN103295511A (zh) * 2012-09-19 2013-09-11 上海中航光电子有限公司 一种移位寄存器及薄膜晶体管液晶显示器
CN104332126A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路和显示器
CN104332181A (zh) * 2014-11-03 2015-02-04 合肥鑫晟光电科技有限公司 一种移位寄存器及栅极驱动装置
CN105051826A (zh) * 2013-03-21 2015-11-11 夏普株式会社 移位寄存器
CN105528985A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN105528986A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 去噪方法、去噪装置、栅极驱动电路和显示装置
KR20160077315A (ko) * 2014-12-22 2016-07-04 엘지디스플레이 주식회사 스캔 구동부 및 이를 이용한 표시장치
CN106920526A (zh) * 2017-05-04 2017-07-04 合肥鑫晟光电科技有限公司 移位寄存器及其驱动方法和栅极驱动电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102654986A (zh) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 移位寄存器的级、栅极驱动器、阵列基板以及显示装置
CN102968950B (zh) * 2012-11-08 2015-06-24 京东方科技集团股份有限公司 一种移位寄存器单元及阵列基板栅极驱动装置
CN103761937B (zh) * 2014-01-27 2017-01-11 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
US11127336B2 (en) * 2015-09-23 2021-09-21 Boe Technology Group Co., Ltd. Gate on array (GOA) unit, gate driver circuit and display device
CN106057147B (zh) * 2016-06-28 2018-09-11 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106448539B (zh) * 2016-10-28 2023-09-19 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106356015B (zh) 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置
CN106531117B (zh) * 2017-01-05 2019-03-15 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
CN106951123B (zh) * 2017-03-21 2019-08-20 京东方科技集团股份有限公司 触控驱动单元及其驱动方法、触控驱动电路、显示装置
CN108257578A (zh) * 2018-04-16 2018-07-06 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动装置、显示装置
CN108877636B (zh) * 2018-08-29 2021-05-14 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295511A (zh) * 2012-09-19 2013-09-11 上海中航光电子有限公司 一种移位寄存器及薄膜晶体管液晶显示器
CN103208263A (zh) * 2013-03-14 2013-07-17 京东方科技集团股份有限公司 移位寄存器、显示装置、栅极驱动电路及驱动方法
CN105051826A (zh) * 2013-03-21 2015-11-11 夏普株式会社 移位寄存器
CN104332126A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路和显示器
CN104332181A (zh) * 2014-11-03 2015-02-04 合肥鑫晟光电科技有限公司 一种移位寄存器及栅极驱动装置
KR20160077315A (ko) * 2014-12-22 2016-07-04 엘지디스플레이 주식회사 스캔 구동부 및 이를 이용한 표시장치
CN105528985A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN105528986A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 去噪方法、去噪装置、栅极驱动电路和显示装置
CN106920526A (zh) * 2017-05-04 2017-07-04 合肥鑫晟光电科技有限公司 移位寄存器及其驱动方法和栅极驱动电路

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