WO2019223754A1 - 移位寄存器单元及其驱动方法、栅极驱动器、显示面板和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动器、显示面板和显示装置 Download PDF

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Publication number
WO2019223754A1
WO2019223754A1 PCT/CN2019/088091 CN2019088091W WO2019223754A1 WO 2019223754 A1 WO2019223754 A1 WO 2019223754A1 CN 2019088091 W CN2019088091 W CN 2019088091W WO 2019223754 A1 WO2019223754 A1 WO 2019223754A1
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Prior art keywords
terminal
voltage
shift register
node
electrode
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PCT/CN2019/088091
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English (en)
French (fr)
Inventor
李全虎
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京东方科技集团股份有限公司
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Priority to US16/649,720 priority Critical patent/US11120720B2/en
Publication of WO2019223754A1 publication Critical patent/WO2019223754A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the generation of a gate driving signal, and in particular, to a shift register unit and a driving method thereof, a gate driver including the shift register unit, a display panel, and a display device.
  • the existing gate driver often adopts a GOA (Gate Driver Array) design to integrate a switching circuit including a TFT (Thin Film Transistor, thin film transistor) in the peripheral area to form a gate driving circuit.
  • GOA Gate Driver Array
  • TFT Thin Film Transistor, thin film transistor
  • the structure of a PMOS shift register is relatively simple, and there is not much process margin reserved for PMOS process fluctuations and performance drift of PMOS devices. Its performance will be greatly affected when the threshold voltage Vth of the PMOS transistor changes greatly. The effect is that the PMOS device cannot work normally when the PMOS device has a large process fluctuation or a severe performance drift change in use of the PMOS device, which causes the display device to display abnormally.
  • a shift register unit including: an input terminal configured to receive an input pulse; a first voltage terminal configured to be applied with a first voltage; and a second voltage terminal configured to A second voltage is applied; a first clock signal terminal configured to receive a first clock signal; a second clock signal terminal configured to receive a second clock signal; a regulation terminal configured to receive a regulation signal; an output terminal, It is configured to output an output signal; a transmission terminal is configured to output a transmission signal; an input circuit is configured to: in response to the first clock signal received at the first clock signal terminal being valid, make the input terminal, The regulating terminal and the first node are turned on with each other, and in response to the first clock signal being invalid, the input terminal, the regulating terminal, and the first node are disconnected from each other; a first control circuit having a configuration As a result: in response to the potential of the second node being at an effective potential, the first voltage terminal and the third node are turned on, and in response to the first clock received
  • the input circuit includes a first transistor whose control electrode is connected to the first clock signal terminal, whose first electrode is connected to the first node, and whose second electrode is connected to the first node.
  • the first control circuit includes a third transistor whose control electrode is connected to the first clock signal terminal, whose first electrode is connected to the third node, and whose second electrode is connected to The second voltage terminal; and a fourth transistor whose control electrode is connected to the second node, whose first electrode is connected to the third node, and whose second electrode is connected to the first voltage terminal.
  • the output circuit includes a fifth transistor having a control electrode connected to the second node, a first electrode connected to the transfer terminal, and a second electrode connected to the second clock.
  • a signal terminal a sixth transistor whose control electrode is connected to the second node, a first electrode of which is connected to the output terminal, and a second electrode of which is connected to the second clock signal terminal;
  • a seventh transistor whose control electrode is Connected to the third node, its first electrode is connected to the first voltage terminal, its second electrode is connected to the output terminal;
  • an eighth transistor its control electrode is connected to the third node, its first An electrode is connected to the first voltage terminal, and a second electrode thereof is connected to the transfer terminal.
  • the output circuit further includes a first capacitor whose first electrode is connected to the control electrode of the sixth transistor, whose second electrode is connected to the output terminal, and a second capacitor, which is A first electrode is connected to the control electrode of the fifth transistor, and a second electrode thereof is connected to the transfer terminal.
  • the output circuit further includes: a third capacitor, a first electrode of which is connected to a control electrode of the eighth transistor, and a second electrode of which is connected to the first voltage terminal; and / or A four capacitor has a first electrode connected to the control electrode of the seventh transistor, and a second electrode connected to the first voltage terminal.
  • the shift register unit further includes a second control circuit configured to: when the potential of the first node is lower than the second voltage, make the The first node and the second node are disconnected.
  • the second control circuit includes an eleventh transistor, a control electrode of the eleventh transistor is connected to the second voltage terminal, a first electrode thereof is connected to the first node, and A second electrode is connected to the second node.
  • the shift register unit further includes a first feedback circuit configured to: in response to a transfer signal of the transfer terminal at an effective potential, make the output terminal and the adjustment The terminal is turned on.
  • the first feedback circuit includes a ninth transistor, a control electrode of the ninth transistor is connected to the transfer terminal, a first electrode thereof is connected to the regulation terminal, and a second electrode thereof is connected to The output.
  • the shift register unit further includes a first feedback circuit configured to: in response to an output signal of the output terminal at an effective potential, make the transfer terminal and the adjustment The terminal is turned on.
  • the first feedback circuit includes a ninth transistor, a control electrode of the ninth transistor is connected to the output terminal, a first electrode thereof is connected to the regulation terminal, and a second electrode thereof is connected to The delivery end.
  • the shift register unit further includes a second feedback circuit configured to: in response to a potential of the third node being at an effective potential, make the output terminal and the At least one of the transfer ends is in communication with the first node.
  • the first feedback circuit includes a tenth transistor, a control electrode of the tenth transistor is connected to the third node, and a first electrode thereof is connected to the output terminal and the transfer terminal. At least one of which a second electrode is connected to the first node.
  • a gate drive driver including N cascaded shift register units as described above, where N is an integer greater than or equal to 2, where the first of the N shift register units The transfer terminals of the m shift register units are connected to the input terminals of the m + 1th shift register unit of the N shift register units, where m is an integer and 1 ⁇ m ⁇ N.
  • a display panel including: a first voltage line configured to transmit a first voltage line voltage; a second voltage line configured to transmit a second voltage line voltage; a first clock Line, which is configured to transmit a first clock line clock signal; a second clock line, which is configured to transmit a second clock line clock signal; and the gate driver as described above, wherein: each of the N shift register units A first voltage terminal is connected to the first voltage line, each second voltage terminal of the N shift register units is connected to the second voltage line, and the 2k-1th of the N shift register units A first clock signal end of each shift register unit is connected to the first clock line, a second clock signal end thereof is connected to the second clock line, and the 2kth shift of the N shift register units A first clock signal terminal of the bit register unit is connected to the second clock line, and a second clock signal terminal thereof is connected to the first clock line, and k is a positive integer and 2k ⁇ N.
  • a display device including: the display panel as described above; and a timing controller configured to control an operation of the display panel, wherein the timing controller is configured to The first clock line and the second clock line are respectively supplied with the first clock line clock signal and the second clock line clock signal, wherein the first clock line clock signal and the first clock line clock signal are The clock signals of the two clock lines have the same period and duty cycle, and are different from each other in time by half a period; a voltage generator configured to supply at least the first voltage line and the second voltage line respectively The first voltage line voltage and the second voltage line voltage, wherein the first voltage line voltage is at an effective voltage level and the second voltage line voltage is at an invalid voltage level.
  • the first clock line clock signal and the second clock line clock signal each have a duty cycle of 50%.
  • a method for driving a shift register unit comprising: providing the first voltage to the first voltage terminal, and providing the second voltage terminal The second voltage, wherein the first voltage is at an effective voltage level, and the second voltage is at an invalid voltage level; providing the first clock signal to the first clock signal terminal, and providing the second clock A clock signal terminal providing the second clock signal, wherein the first clock signal and the second clock signal have the same period and duty cycle and are different from each other in time by half a period; and to the input The terminal provides the input pulse, and a pulse width of the input pulse is synchronized with a duration in which the first clock signal is invalid.
  • the first clock signal and the second clock signal each have a duty cycle of 50%.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an exemplary embodiment of the present disclosure
  • FIG. 2 shows an exemplary circuit diagram of the shift register unit shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a shift register unit according to another exemplary embodiment of the present disclosure.
  • FIG. 4 shows an exemplary circuit diagram of the shift register unit shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a shift register unit according to still another exemplary embodiment of the present disclosure.
  • FIG. 6 shows an exemplary circuit diagram of the shift register unit shown in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a shift register unit according to still another exemplary embodiment of the present disclosure.
  • FIG. 8 shows an exemplary circuit diagram of the shift register unit shown in FIG. 7;
  • FIGS. 9 is a timing diagram of the shift register unit shown in FIGS. 1 to 6;
  • FIGS. 7 to 8 are timing diagram of the shift register unit shown in FIGS. 7 to 8.
  • FIG. 11 is another timing diagram of the shift register unit shown in FIGS. 1 to 6, which shows a case where multiple output pulses are generated during one scan;
  • FIG. 12 is another timing diagram of the shift register unit shown in FIGS. 7 to 8, which shows a case where multiple output pulses are generated during one scan;
  • FIG. 13 shows a schematic structural diagram of a gate driver composed of the shift register units shown in FIGS. 1 to 8 and shows a connection condition of the gate driver in a display panel;
  • FIG. 14 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure.
  • FIG. 15 is a flowchart illustrating an exemplary method for driving a shift register unit according to an exemplary embodiment of the present disclosure.
  • the shift register unit 100 includes: an input terminal IN configured to receive an input pulse; a first voltage terminal VGH configured to be applied with a first voltage; a second voltage terminal VGL configured to be applied with a second voltage; and configured to receive a first The first clock signal terminal CLKA of the clock signal; the second clock signal terminal CLKB configured to receive the second clock signal; the adjustment terminal FIN configured to receive the adjustment signal; the output terminal OUT configured to output the output signal; Passing end CR.
  • the shift register unit 100 also includes an input circuit 10, an output circuit 20, and a control circuit 30, which are illustrated as blocks.
  • the input circuit 10 is configured to: in response to the first clock signal received at the first clock signal terminal CLKA being valid, enable the input terminal IN, the regulating terminal FIN and the first node N1 to be conductive with each other, and in response to the first clock signal CLKA being invalid, The input terminal IN, the adjustment terminal FIN, and the first node N1 are disconnected from each other.
  • the adjustment signal reduces the voltage difference between the adjustment terminal FIN and the first node N1, so that it can be prevented when the shift register unit 100 normally outputs The charge at the first node N1 leaks abnormally.
  • the first control circuit 30 is configured to make the first voltage terminal VGH and the third node N3 conductive in response to the potential of the second node N2 being at an effective potential, and be effective in response to the first clock signal received at the first clock signal terminal CLKA. To make the second voltage terminal VGL and the third node N3 conductive. It should be noted that, in the shift register unit 100, since the first node N1 and the second node N2 are turned on, the first node N1 and the second node N2 have the same potential in the shift register unit 100.
  • the output circuit 20 is configured to: in response to the potential of the second node N2 being at an effective potential, make the second clock signal terminal CLKB and the output terminal OUT and the transfer terminal CR conductive; A voltage terminal VGH is conductive with the output terminal OUT and the transfer terminal CR.
  • the term “effective potential” used herein refers to the potential required for the circuit element (eg, transistor) involved to be enabled, and the term “invalid potential” used herein refers to the circuit element involved being disabled The potential at which it is.
  • the effective potential is a high potential and the ineffective potential is a low potential.
  • the effective potential is a low potential and the ineffective potential is a high potential.
  • the effective or ineffective potential is not intended to refer to a specific potential, but may include a range of potentials.
  • the term “voltage level” may be used interchangeably with “potential”.
  • the source of the adjustment signal received by the adjustment terminal FIN does not need to be limited in the shift register unit 100, because in some exemplary embodiments of the present disclosure, the adjustment terminal FIN can receive external, An adjustment signal of an independent signal source, as long as the adjustment signal can reduce the voltage difference between the adjustment terminal FIN and the first node N1 when the input terminal IN, the adjustment terminal FIN, and the first node N1 are disconnected from each other.
  • the adjustment terminal FIN may also receive signals (including output signals and / or transfer signals) output from the shift register unit 100 as adjustment signals.
  • FIG. 2 an exemplary circuit diagram of the shift register unit 100 shown in FIG. 1 is shown.
  • An exemplary circuit configuration of the shift register unit 100 is described in detail below with reference to FIG. 2.
  • the transistors used in the exemplary embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • each transistor is typically made so that their source and drain can be used interchangeably, so there is no substantial difference in the description of the connection relationship between their source and drain.
  • one of the electrodes is referred to as a first electrode, the other is referred to as a second electrode, and a gate is referred to as a control electrode.
  • each transistor is illustrated and described as a P-type transistor, an N-type transistor is also possible.
  • N-type transistor the gate-on voltage has a high potential and the gate-off voltage has a low potential.
  • a P-type transistor is used as an example for description.
  • N-type transistors to replace one or more or all P-type transistors in the exemplary embodiments of the present disclosure under the teachings of the present disclosure, or may One or more components are added or removed from the exemplary embodiments without departing from the spirit and scope of the present disclosure.
  • other embodiments are also contemplated without conflict with the teachings of the present disclosure.
  • the input circuit 10 of the shift register unit 100 includes a first transistor M1 and a second transistor M2.
  • the control electrode of the first transistor M1 is connected to the first clock signal terminal CLKA, its first electrode is connected to the first node N1, and its second electrode is connected to the adjustment terminal FIN.
  • the control electrode of the second transistor M2 is connected to the first clock signal terminal CLKA, its first electrode is connected to the adjustment terminal FIN, and its second electrode is connected to the input terminal IN. Therefore, in response to the first clock signal received by the first clock signal terminal CLKA being valid, the input terminal IN, the adjustment terminal FIN, and the first node N1 are turned on to each other, and accordingly the input signal is applied to the first node N1.
  • the first control circuit 30 of the shift register unit 100 includes a third transistor M3 and a fourth transistor M4.
  • the control electrode of the third transistor M3 is connected to the first clock signal terminal CLKA, its first electrode is connected to the third node N3, and its second electrode is connected to the second voltage terminal VGL.
  • the control electrode of the fourth transistor M4 is connected to the second node N2, its first electrode is connected to the third node N3, and its second electrode is connected to the first voltage terminal VGH. Therefore, the first control circuit 30 is in response to the potential of the second node N2 being at an effective potential, and turns on the first voltage terminal VGH and the third node N3, and is effective in response to the first clock signal received at the first clock signal terminal CLKA. To make the second voltage terminal VGL and the third node N3 conductive.
  • the size of the third transistor M3 and the fourth transistor M4 is designed to have such an aspect ratio (which determines the equivalent on-resistance of the transistor), that is, the third node N3 When the four transistors M3 and M4 are both turned on, they are set to an inactive potential.
  • the output circuit 20 of the shift register unit 100 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first capacitor C1, a second capacitor C2, and a third capacitor C3.
  • the control electrode of the fifth transistor M5 is connected to the second node N2, its first electrode is connected to the transfer terminal CR, and its second electrode is connected to the second clock signal terminal CLKB.
  • the control electrode of the sixth transistor M6 is connected to the second node N2, its first electrode is connected to the output terminal OUT, and its second electrode is connected to the second clock signal terminal CLKB.
  • the control electrode of the seventh transistor M7 is connected to the third node N3, its first electrode is connected to the first voltage terminal VGH, and its second electrode is connected to the output terminal OUT.
  • the control electrode of the eighth transistor M8 is connected to the third node N3, its first electrode is connected to the first voltage terminal VGH, and its second electrode is connected to the transfer terminal CR.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor M6, and the second electrode thereof is connected to the output terminal OUT.
  • the first electrode of the second capacitor C2 is connected to the control electrode of the fifth transistor M5, and the second electrode thereof is connected to the transfer terminal CR.
  • the first electrode of the third capacitor C3 is connected to the control electrode of the eighth transistor M8, and the second electrode thereof is connected to the first voltage terminal VGH.
  • the output circuit 20 is in response to the potential of the first node N1 to be at an effective potential, and turns on the second clock signal terminal CLKB and both the output terminal OUT and the transfer terminal CR, and in response to the potential of the third node N3 to be at an effective potential,
  • the first voltage terminal VGH is turned on with both the output terminal OUT and the transfer terminal CR.
  • the existence of the first and second capacitors C1 and C2 is advantageous.
  • the output signal of the output terminal OUT and the transmission signal of the transmission terminal CR change from a high potential to a low potential
  • the potential at the second node N2 can be aided by the first
  • the second capacitors C1 and C2 are further lowered to further turn on the fifth transistor M5 and the sixth transistor M6, as will be described later.
  • the output circuit 20 may not include at least one of the first capacitor C1 and the second capacitor C2.
  • the presence of the third capacitor C3 may also be advantageous because it may make the potential at the third node N3 more stable.
  • the output circuit 20 may not include the third capacitor C3.
  • a capacitor may also be provided between the control electrode of the seventh transistor M7 and the first voltage terminal VGH, so that the potential at the third node N3 becomes more stable.
  • the transistor connected to the output terminal OUT (that is, The size of the transistors constituting the output circuit 20 and the first control circuit 30 described above can reduce the layout area of the shift register unit 100 and reduce its power consumption.
  • FIG. 3 illustrates a structure diagram of a shift register unit 110 according to another exemplary embodiment of the present disclosure.
  • the shift register unit 110 of FIG. 3 is different only in that it further includes a first feedback circuit 40. Therefore, for the sake of brevity, only the first feedback circuit 40 of the shift register unit 110 will be described below, and the same parts will not be described again.
  • the first feedback circuit 40 receives a signal from the output terminal OUT and / or the transfer terminal CR of the shift register unit 110 and sends the signal to the adjustment terminal FIN. Specifically, in some embodiments, the first feedback circuit 40 is configured to make the output terminal OUT and the adjustment terminal FIN conductive in response to the transmission signal of the transmission terminal CR being at an effective potential. In other embodiments, the first feedback circuit 40 is configured to make the transmitting terminal CR and the adjusting terminal FIN conductive in response to the output signal of the output terminal OUT being at an effective potential.
  • FIG. 4 shows an exemplary circuit diagram of the shift register unit 110 shown in FIG. 3.
  • the circuit diagram of the shift register unit 110 of FIG. 4 is different only in that it further includes a first feedback circuit 40. Therefore, only the first feedback circuit 40 of the shift register unit 110 will be described below, and the same parts will not be described again.
  • the first feedback circuit 40 includes a ninth transistor M9.
  • the control electrode of the ninth transistor M9 is connected to the transfer terminal CR, its first electrode is connected to the adjustment terminal FIN, and its second electrode is connected to the output terminal OUT. At this time, the output signal from the output terminal OUT is sent to the adjustment terminal FIN as an adjustment signal.
  • the control electrode of the ninth transistor M9 may be connected to the output terminal OUT, the first electrode thereof may be connected to the regulation terminal FIN, and the second electrode thereof may be connected to Passing CR. At this time, the transmission signal from the transmission terminal CR is sent to the adjustment terminal FIN as the adjustment signal.
  • the potential of the first node N1 can be maintained by the input circuit 10, so the following problems can be avoided:
  • the abnormal leakage of charge causes the potential of the second node N2 to be unstable, which in turn makes the output signal of the shift register unit 110 unstable, and may even cause the shift register unit 110 to fail.
  • FIG. 5 is a schematic structural diagram of a shift register unit 120 according to still another exemplary embodiment of the present disclosure. Compared with the shift register unit 110 shown in FIG. 3, the shift register unit 120 of FIG. 5 is different only in that it further includes a second feedback circuit 50. Therefore, for the sake of brevity, only the second feedback circuit 50 of the shift register unit 110 will be described below, and the same parts will not be described again.
  • the second feedback circuit 50 receives a signal from the output terminal OUT and / or the transfer terminal CR of the shift register unit 110, and in response to the potential of the third node N3 being at an effective potential, at least one of the output terminal OUT and the transfer terminal CR is connected to the first A node N1 is turned on.
  • the second feedback circuit 50 receives a signal from the output terminal OUT.
  • the second feedback circuit 50 may also receive signals from the transmitting terminal CR, or may receive signals from both the output terminal OUT and the transmitting terminal CR.
  • FIG. 6 shows an exemplary circuit diagram of the shift register unit 120 shown in FIG. 5.
  • the circuit diagram of the shift register unit 120 of FIG. 6 is different only in that it further includes a second feedback circuit 50. Therefore, only the second feedback circuit 50 of the shift register unit 120 will be described below, and the same parts will not be described again.
  • the second feedback circuit 50 includes a tenth transistor M10.
  • the control electrode of the tenth transistor M10 is connected to the third node N3, its first electrode is connected to the output terminal OUT, and its second electrode is connected to the first node N1. It is easy to understand that, in other embodiments not shown in the present disclosure, the first electrode of the tenth transistor M10 may also be connected to the transfer terminal CR, or may be connected to both the output terminal OUT and the transfer terminal CR.
  • FIG. 7 is a schematic structural diagram of a shift register unit 130 according to still another exemplary embodiment of the present disclosure. Compared with the shift register unit 120 shown in FIG. 5, the shift register unit 130 of FIG. 7 is different only in that it further includes a second control circuit 60. Therefore, for the sake of brevity, only the second control circuit 60 of the shift register unit 130 will be described below, and the same parts will not be described again.
  • the second control circuit 60 is disposed between the first node N1 and the second node N2, and is configured to: when the potential of the first node N1 is lower than the voltage of the second voltage terminal VGL, make the first node N1 and the second node N1 Node N2 is disconnected.
  • the role of the second control circuit 60 is that when the shift register unit 120 generates an output pulse, when the output signal of the output terminal OUT and the transmission signal of the transmission terminal CR change from a high potential to a low potential, the first node N1 and the second node
  • the potential at N2 can be further reduced by means of the first and second capacitors C1 and C2, so that the fifth transistor M5 and the sixth transistor M6 are further turned on.
  • the second control circuit 60 changes the first node N1 and the second node N1
  • the node N2 is turned off, so that the potential at the second node N2 is kept stable, so that the turning on of the fifth transistor M5 and the sixth transistor M6 is kept stable.
  • FIG. 8 shows an exemplary circuit diagram of the shift register unit 130 shown in FIG. 7.
  • the circuit diagram of the shift register unit 130 of FIG. 8 is different only in that it further includes a second control circuit 60. Therefore, only the second control circuit 60 of the shift register unit 130 will be described below, and the same parts will not be described again.
  • the second control circuit 60 includes an eleventh transistor M11.
  • the control electrode of the eleventh transistor M11 is connected to the second voltage terminal VGL, its first electrode is connected to the first node N1, and its second electrode is connected to the second node N2.
  • the potential at the second node N2 can be further reduced by means of the first and second capacitors C1 and C2.
  • the potential at a node N1 is also further reduced, and is lower than the second voltage at the second voltage terminal VGL, thereby causing the eleventh transistor M11 to be turned off, thereby disconnecting the first node N1 from the second node N2.
  • FIG. 9 there is shown an exemplary timing diagram of the shift register unit shown in FIGS. 2, 4, and 6.
  • the operations of the shift register units 100, 110, and 130 shown in FIGS. 2, 4, and 6 will be described in detail based on FIG. In the following, a high potential is represented by 1 and a low potential is represented by 0.
  • the size of the third transistor M3 and the fourth transistor M4 is designed such that the third node N3 is set to an inactive potential when both the third and fourth transistors M3 and M4 are turned on ( (Ie, high potential). Because the third node N3 is at a high potential, the seventh and eighth transistors M7 and M8 are turned off, and because the potential of the second node N2 is at a low potential, the fifth and sixth transistors M5 and M6 are turned on to enable the second
  • the adjustment signal received from the adjustment terminal FIN can also be at a low level, so as to reduce the voltage difference between the source and the drain of the first transistor M1, thereby reducing the first The possibility of leakage of a node N1 through the first transistor M1.
  • the shift register units 100, 110, 120 generate output pulses.
  • the ninth transistor M9 is turned off, thereby disconnecting the output terminal OUT from the adjustment terminal FIN.
  • the tenth transistor M10 is now turned on to transmit the output signal of the output terminal OUT to the first node N1 and to the first node N1 and the second node N2 is charged to keep the potentials of the first node N1 and the second node N2 stable.
  • the shift register units 100, 110, and 120 are reset. After that, the shift register units 100, 110, and 120 will keep the potentials of the output signals at the output terminal OUT and the transfer terminal CR unchanged until the next input pulse is received. When the next input pulse is received, the shift register units 100, 110, and 120 will repeat the operations in the first, second, and time periods P1, P2, and P3 described above.
  • FIG. 10 is an exemplary timing diagram of the shift register unit 130 shown in FIGS. 7 to 8.
  • the size of the third transistor M3 and the fourth transistor M4 is designed such that the third node N3 is set to an inactive potential when both the third and fourth transistors M3 and M4 are turned on ( (Ie, high potential). Because the third node N3 is at a high potential, the seventh and eighth transistors M7 and M8 are turned off, and because the potential of the second node N2 is at a low potential, the fifth and sixth transistors M5 and M6 are turned on to enable the second
  • the first node The potentials at N1 and the second node N2 become lower, that is, lower than the second voltage at the second voltage terminal VGL, thereby causing the eleventh transistor M1 to be turned off to disconnect the first node N1 and the second node N2 , Thereby preventing the potential change at the first node N1 due to the possible leakage of the charge from affecting the potential of the second node N2. Therefore, as clearly shown in FIG. 10, in the second time period P2, the potential at the second node N2 is lower than the potential at the first node N1.
  • the shift register unit 130 generates an output pulse.
  • the node N1 charges the first node N1 and the second node N2 to maintain the potentials of the first node N1 and the second node N2 to be stable.
  • the shift register unit 130 is reset. After that, the shift register unit 130 will keep the potentials of the output signals at the output terminal OUT and the transfer terminal CR unchanged until the next input pulse is received. When the next input pulse is received, the shift register unit 130 repeats the operations in the first, second, and third time periods P1, P2, and P3.
  • FIG. 11 shows another exemplary timing diagram of the shift register unit shown in FIGS. 1-6, which shows a case where multiple output pulses are generated during one scan; similarly, FIG. 12 shows FIG. 7 Another exemplary timing diagram of the shift register unit shown in ⁇ 8 also shows the case of multiple outputs during one scan.
  • the operation shown in FIG. 11 and FIG. 12 is when the shift register unit is in a cascaded state. Therefore, the scan signal STU is shown in FIG. 11 and FIG. 12, and the shift register unit receives the scan.
  • two output signal pulses are generated (correspondingly, two transfer signal pulses can also be included), followed by two output signal pulses or two
  • the transfer signal pulse can be sent to the next-stage shift register unit as an input pulse, and the two output signal pulses that are shifted continue to be generated accordingly.
  • the operation of the shift register unit is the same as that described above with respect to the first in FIG. 9 and FIG. 10.
  • the operations described in the second time period P1 and P2 are the same. Therefore, I will not repeat them here.
  • the shift register unit repeats the operations in the first and second time periods P2.1 and P2.2.
  • the operation of the shift register unit is the same as the operation described earlier with respect to the third time period P3 in FIGS. 9 and 10. Therefore, I will not repeat them here.
  • the shift register unit can generate two output signal pulses during one scan. It is easy to understand that the shift register unit according to the exemplary embodiment of the present disclosure can generate more output signal pulses in one scanning process as needed.
  • FIG. 13 shows a structure diagram of a gate driver 300 composed of the shift register units of FIGS. 1 to 8, and also shows an exemplary connection situation of the gate driver 300 in a schematic display panel.
  • the gate driver 300 includes 2N cascaded shift register units SR (1), SR (2), ..., SR (2N-1) and SR (2N), each of which can Takes the form of a shift register unit as described above with respect to FIGS. 1 to 5.
  • N may be an integer greater than or equal to 1.
  • an input terminal IN of each of the shift register units is connected to a transfer terminal CR of an adjacent previous shift register unit.
  • 2N shift register units SR (1), SR (2), ..., SR (2N-1) and SR (2N) in the gate driver 300 It can be connected to the 2N gate lines G [1], G [2], ..., G [2N-1] and G [2N] accordingly.
  • the first voltage terminal VH thereof is connected to the first
  • the voltage line vgh has a second voltage terminal connected to the second voltage line vgl, wherein the first voltage line vgh is configured to transmit a first voltage line voltage, and the second voltage line vgl is configured to transmit a second voltage line voltage.
  • the first clock signal terminal CLKA of the odd-numbered shift register unit in each shift register unit SR (1), SR (2), ..., SR (2N-1) and SR (2N) is connected to
  • the first clock line clk1 has a second clock signal terminal CLKB connected to the second clock line clk2; and the first clock signal terminal CLKA of the even-numbered shift register unit is connected to the second clock line clk2 and its second clock signal terminal CLKB is connected to the first clock line clk1.
  • FIG. 14 is a schematic structural diagram of a display device 500 according to an exemplary embodiment of the present disclosure.
  • the display device 500 includes a display panel 510, a timing controller 520, a gate driver 530, a data driver 540, and a voltage generator 550.
  • the gate driver 530 may take the form of the gate driver 300 shown above with respect to FIG. 13.
  • the first clock line clk1, the second clock line clk2, the first voltage line vgh, and the second voltage line vgl shown in FIG. 13 are omitted in FIG. 14 for convenience of illustration.
  • the display panel 510 is used to display the received image data.
  • the display panel 510 may have various types of structures, such as add-on, in-cell, on-cell, OGS, and the like.
  • the display panel 510 includes a plurality of gate lines GL extending in a first direction D1 and a plurality of data lines DL extending in a second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel of the display panel 510 includes a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL.
  • the display panel of the display panel 510 may be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or any other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 520 controls operations of the display panel 510, the gate driver 530, the data driver 540, and the voltage generator 550.
  • the timing controller 520 receives input image data RGBD and an input control signal CONT from an external device (for example, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each input pixel data may include red gray data R, green gray data G, and blue gray data B for a corresponding one of a plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.
  • the timing controller 520 generates output image data RGBD ', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • Implementations of the timing controller 520 are known in the art.
  • the timing controller 520 may be implemented in many ways, such as with dedicated hardware, for example, to perform the various functions discussed herein.
  • a "processor” is an example of a timing controller 520 employing one or more microprocessors that can be programmed using software (e.g., microcode) to perform the various functions discussed herein.
  • the timing controller 520 may be implemented with or without a processor, and may also be implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions. Examples of the timing controller 520 include, but are not limited to, a conventional microprocessor, an application specific integrated circuit (ASIC), and a field programmable gate array (FPGA).
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the gate driver 530 receives a first control signal CONT1 from the timing controller 520.
  • the first control signal CONT1 may include first and second clock line clock signals transmitted via the first and second clock lines clk1 and clk2 shown in FIG. 7.
  • the gate driver 530 generates a plurality of gate driving signals for output to the gate line GL based on the first control signal CONT1.
  • the gate driver 530 may sequentially apply a plurality of gate driving signals to the gate line GL.
  • the data driver 540 receives the second control signal CONT2 and the output image data RGBD 'from the timing controller 520.
  • the data driver 940 generates a plurality of data voltages based on the second control signal CONT2 and the output image data RGBD '.
  • the data driver 540 may apply a plurality of generated data voltages to the data line DL.
  • the voltage generator 550 supplies power to the display panel 510, the timing controller 520, the gate driver 530, the data driver 540, and potentially additional components. Specifically, the voltage generator 550 is configured to supply the first voltage line voltage and the second voltage transmitted via the first voltage line vgh and the second voltage line vgl shown in FIG. 7 under the control of the timing controller 520, respectively. Line voltage.
  • the configuration of the voltage generator 550 may be known in the art.
  • the voltage generator 550 may include a voltage converter such as a DC / DC converter and a crossbar switch. The voltage converter generates a plurality of output voltages having different voltage levels from an input voltage. Then, the crossbar switch can selectively couple these output voltages to the first voltage line vgh and the second voltage line vgl under the control of the timing controller 520, so as to supply the required first and second voltages.
  • the gate driver 530 and / or the data driver 540 may be disposed on the display panel 510, or may be connected to the touch display panel 510 by means of, for example, a tape carrier package (TCP).
  • TCP tape carrier package
  • the gate driver 530 may be integrated in the display panel 510 as a gate array driver (GOA) circuit.
  • GOA gate array driver
  • Examples of the display device 500 include, but are not limited to, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • an exemplary method 700 for driving a shift register unit according to an exemplary embodiment of the present disclosure is shown. It should be noted that the steps in the methods described below are exemplary, and they do not necessarily have to be performed in the order listed, but one or more of these steps may be in different orders or simultaneously according to the actual situation It is executed, and according to the actual situation, it can also include other additional steps.
  • the method 700 includes the following steps:
  • Step S701 providing a first voltage to the first voltage terminal VGH and a second voltage to the second voltage terminal VGL, wherein the first voltage is at an effective potential and the second voltage is at an invalid potential;
  • Step S702 providing a first clock signal to the first clock signal terminal CLKA and a second clock signal to the second clock signal terminal CLKB, wherein the first clock signal and the second clock signal have the same period and Duty cycles and differ from each other in time by half a cycle;
  • Step S703 An input pulse is provided to the input terminal IN, and a pulse width of the input pulse is synchronized with a duration when the first clock signal is invalid.
  • the first clock signal received from the first clock signal terminal CLKA and the second clock signal received from the second clock signal terminal CLKB each have a duty cycle of 50%.
  • the shift register unit can separate the output signal and the transfer signal by the output terminal OUT and the transfer terminal CR, the number of transistors connected to the output terminal OUT and the transfer terminal CR can be reduced.
  • the size can further save the layout area of the shift register unit and reduce its power consumption.
  • it can also avoid the potential instability of the second node N2 due to the abnormal leakage of the charge of the first node N11 during the normal output of the shift register unit, making the output signal of the shift register unit unstable and even causing the shift register unit to fail The problem. Therefore, when the transistors constituting the above-mentioned shift register unit are all P-type transistors, the stability of the shift register unit is high under conditions of large process fluctuations or severe drift changes in the performance of the PMOS device during use.

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Abstract

一种移位寄存器单元（100）及一种用于驱动所述移位寄存器单元（100）的方法、包括所述移位寄存器单元（100）的栅极驱动器、显示面板（510）以及显示装置（500），其中所述移位寄存器单元（100）包括：输入端（IN）、第一电压端（VGH）、第二电压端（VGL）、第一时钟信号端（CLKA）、第二时钟信号端（CLKB）、调节端（FIN）、输出端（OUT）、传递端（CR），以及还包括输入电路（10）、第一控制电路（30）和输出电路（20）。所述移位寄存器单元（100）通过提供调节信号来避免在正常输出时由于电荷异常泄漏而导致的输出信号不稳定，此外还通过输出端和传递端来分离输出信号和传递信号，从而降低与输出端和传递端连接的晶体管的尺寸，进而可以节省移位寄存器单元（100）的版图面积，同时可以降低其功耗。

Description

移位寄存器单元及其驱动方法、栅极驱动器、显示面板和显示装置
相关技术的交叉引用
本申请要求享有2018年5月24日提交的中国专利申请No.201810510507.X的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及栅极驱动信号的生成，尤其涉及一种移位寄存器单元及其驱动方法、包括该移位寄存器单元的栅极驱动器、显示面板和显示装置。
背景技术
现有的栅极驱动器常采用GOA(Gate Driver on Array，阵列基板行驱动)设计以将包括TFT(Thin Film Transistor，薄膜晶体管)的开关电路集成在上述周边区域构成栅极驱动电路。根据TFT的不同，GOA电路分为NMOS移位寄存器和PMOS移位寄存器。
一般而言，PMOS移位寄存器的结构较为简单，对于PMOS工艺波动和PMOS器件的性能漂移预留的工艺余量并不多，其性能在PMOS晶体管的阈值电压Vth变化较大时会受到较大影响，因此在PMOS器件具有较大工艺波动或者PMOS器件在使用中存在严重性能漂移变化的情况下无法实现PMOS器件正常工作的功能，导致显示器件显示异常。
发明内容
根据本公开的第一方面，提供了一种移位寄存器单元，包括：输入端，其配置成接收输入脉冲；第一电压端，其配置成被施加第一电压；第二电压端，其配置成被施加第二电压；第一时钟信号端，其配置成接收第一时钟信号；第二时钟信号端，其配置成接收第二时钟信号；调节端，其配置成接收调节信号；输出端，其配置成输出输出信号；传递端，其配置成输出传递信号；输入电路，其配置成：响应于在所述第一时钟信号端接收的所述第一时钟信号有效，使所述输入端、所述调节端和第一节点彼此导通，以及响应于所述第一时钟信号无效， 使所述输入端、所述调节端和所述第一节点彼此断开；第一控制电路，其配置成：响应于所述第二节点的电位处于有效电位，使所述第一电压端与第三节点导通，响应于在所述第一时钟信号端接收的所述第一时钟信号有效，使所述第二电压端与所述第三节点导通；输出电路，其配置成：响应于所述第二节点的电位处于有效电位，使所述第二时钟信号端与所述输出端和所述传递端导通，响应于所述第三节点的电位处于有效电位，使所述第一电压端与所述输出端和所述传递端导通；其中，所述第一节点与所述第二节点导通，其中，当所述输入端、所述调节端和所述第一节点彼此断开时，所述调节信号减小所述调节端与所述第一节点之间的电压差。
根据一些示例性实施例，所述输入电路包括：第一晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述第一节点，其第二电极连接到所述调节端；以及第二晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述调节端，其第二电极连接到所述输入端。
根据一些示例性实施例，所述第一控制电路包括：第三晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述第三节点，其第二电极连接到所述第二电压端；以及第四晶体管，其控制极连接到所述第二节点，其第一电极连接到所述第三节点，其第二电极连接到所述第一电压端。
根据一些示例性实施例，所述输出电路包括：第五晶体管，其控制极连接到所述第二节点，其第一电极连接到所述传递端，其第二电极连接到所述第二时钟信号端；第六晶体管，其控制极连接到所述第二节点，其第一电极连接到所述输出端，其第二电极连接到所述第二时钟信号端；第七晶体管，其控制极连接到所述第三节点，其第一电极连接到所述第一电压端，其第二电极连接到所述输出端；第八晶体管，其控制极连接到所述第三节点，其第一电极连接到所述第一电压端，其第二电极连接到所述传递端。
根据一些示例性实施例，所述输出电路还包括：第一电容器，其第一电极连接到所述第六晶体管的控制极，其第二电极连接到所述输出端；以及第二电容器，其第一电极连接到所述第五晶体管的控制极，其第二电极连接到所述传递端。
根据一些示例性实施例，所述输出电路还包括：第三电容器，其第一电极连接到所述第八晶体管的控制极，其第二电极连接到所述第一电压端；和/或第四电容器，其第一电极连接到所述第七晶体管的控制极，其第二电极连接到所述第一电压端。
根据一些示例性实施例，所述移位寄存器单元还包括第二控制电路，所述第二控制电路构造成：响应于所述第一节点的电位低于所述第二电压时，使所述第一节点和所述第二节点断开。
根据一些示例性实施例，所述第二控制电路包括第十一晶体管，所述第十一晶体管的控制极连接到所述第二电压端，其第一电极连接到所述第一节点，其第二电极连接到所述第二节点。
根据一些示例性实施例，所述移位寄存器单元还包括第一反馈电路，所述第一反馈电路构造成：响应于所述传递端的传递信号处于有效电位，使所述输出端与所述调节端导通。
根据一些示例性实施例，所述第一反馈电路包括第九晶体管，所述第九晶体管的控制极连接到所述传递端，其第一电极连接到所述调节端，其第二电极连接到所述输出端。
根据一些示例性实施例，所述移位寄存器单元还包括第一反馈电路，所述第一反馈电路构造成：响应于所述输出端的输出信号处于有效电位，使所述传递端与所述调节端导通。
根据一些示例性实施例，所述第一反馈电路包括第九晶体管，所述第九晶体管的控制极连接到所述输出端，其第一电极连接到所述调节端，其第二电极连接到所述传递端。
根据一些示例性实施例，所述移位寄存器单元还包括第二反馈电路，所述第二反馈电路构造成：响应于所述第三节点的电位处于有效电位，使所述输出端和所述传递端中的至少一个与所述第一节点导通。
根据一些示例性实施例，所述第一反馈电路包括第十晶体管，所述第十晶体管的控制极连接到所述第三节点，其第一电极连接到所述输出端和所述传递端中的至少一个，其第二电极连接到所述第一节点。
根据本公开的另一方面，提供了一种栅极驱动驱动器，包括N个级联的如上所述的移位寄存器单元，N为大于等于2的整数，其中N个移位寄存器单元中的第m个移位寄存器单元的传递端连接到N个移位寄存器单元中的第m+1个移位寄存器单元的输入端，m为整数且1 ≤m＜N。
根据本公开的另一方面，提供了一种显示面板，包括：第一电压线，其配置成传送第一电压线电压；第二电压线，其配置成传送第二电压线电压；第一时钟线，其配置成传送第一时钟线时钟信号；第二时钟线，其配置成传送第二时钟线时钟信号；以及如上所述的栅极驱动器，其中：所述N个移位寄存器单元的各第一电压端连接到所述第一电压线，所述N个移位寄存器单元的各第二电压端连接到所述第二电压线，所述N个移位寄存器单元中的第2k-1个移位寄存器单元的第一时钟信号端连接到所述第一时钟线，其第二时钟信号端连接到所述第二时钟线，并且所述N个移位寄存器单元中的第2k个移位寄存器单元的第一时钟信号端连接到所述第二时钟线，其第二时钟信号端连接到所述第一时钟线，并且其中，k为正整数且2k≤N。
根据本公开的另一方面，提供了一种显示装置，包括：如上所述的显示面板；时序控制器，其被配置成控制所述显示面板的操作，其中，所述时序控制器被配置成至少向所述第一时钟线和所述第二时钟线分别供应所述第一线时钟线时钟信号和所述第二时钟线时钟信号，其中，所述第一时钟线时钟信号与所述第二时钟线时钟信号具有相同的周期和占空比，并且在时序上彼此相差半个周期；电压生成器，其被配置成至少向所述第一电压线和所述第二电压线分别供应所述第一电压线电压和所述第二电压线电压，其中，所述第一电压线电压处于有效电压水平，所述第二电压线电压处于无效电压水平。
根据一些示例性实施例，所述第一时钟线时钟信号和所述第二时钟线时钟信号各自具有50％的占空比。
根据本公开的另一方面，提供了一种用于驱动如上所述的移位寄存器单元的方法，包括：向所述第一电压端提供所述第一电压，向所述第二电压端提供所述第二电压，其中，所述第一电压处于有效电压水平，所述第二电压处于无效电压水平；向所述第一时钟信号端提供所述第一时钟信号，以及向所述第二时钟信号端提供所述第二时钟信号，其中，所述第一时钟信号与所述第二时钟信号具有相同的周期和占空比，并且在时序上彼此相差半个周期；以及向所述输入端提供所述输入脉冲，所述输入脉冲的脉宽与所述第一时钟信号为无效的持续时间同步。
根据一些示例性实施例，，所述第一时钟信号和所述第二时钟信号各自具有50％的占空比。
附图说明
下面将结合附图对本公开的示例性具体实施方式进行详细的描述，以便能够对本公开要解决的问题、上述以及其他目的、特征和优点具有更加充分的认识和理解，附图中：
图1示出了根据本公开的一个示例性实施例的移位寄存器单元的结构示意图；
图2示出了图1所示的移位寄存器单元的示例性电路图；
图3示出了根据本公开的另一个示例性实施例的移位寄存器单元的结构示意图；
图4示出了图3所示的移位寄存器单元的示例性电路图；
图5示出了根据本公开的又一个示例性实施例的移位寄存器单元的结构示意图；
图6示出了图5所示的移位寄存器单元的示例性电路图；
图7示出了根据本公开的再一个示例性实施例的移位寄存器单元的结构示意图；
图8示出了图7所示的移位寄存器单元的示例性电路图；
图9是图1～6所示的移位寄存器单元的时序图；
图10是图7～8所示的移位寄存器单元的时序图；
图11是图1～6所示的移位寄存器单元的另一时序图，其显示了在一次扫描过程中生成多个输出脉冲的情况；
图12是图7～8所示的移位寄存器单元的另一时序图，其显示了在一次扫描过程中生成多个输出脉冲的情况；
图13显示了由图1～8所示的移位寄存器单元构成的栅极驱动器的结构示意图，并且显示了该栅极驱动器在显示面板中的连接情况；
图14是根据本公开的示例性实施例的显示装置的结构示意图；
图15是示出了用于驱动根据本公开的示例性实施例的移位寄存器单元的示例性方法的流程图。
贯穿全部附图，相同或者相似的部分、部件和/或元件由相同的附图标记指示。
具体实施方式
下面将结合附图，对本公开的示例性实施例中的技术方案进行清楚、完整地描述。将理解的是，尽管术语“第一”、“第二”、“第三”等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分也可以被称为第二或第三元件、部件或部分而不偏离本发明的教导。
本文中使用的术语仅用于描述特定实施例的目的，并且不意图限制本发明。如本文中使用的，单数形式“一个”、“一”和“该”旨在也包括复数形式，除非上下文清楚地另有指示。还要理解的是，术语“包括”和/或“包含”当在本说明书中使用时，是指所述及的特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或者添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。此外，本文中出现的术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被描述为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被描述为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本发明所属领域的普通技术人员所通常理解的相同含义。还要理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
需要说明的是，在本说明书的描述中，参考表述“一个实施例”、“一些实施例”、“示例性实施例”、“具体示例”、或“一些示例”等的描述，意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。因此，在本文中， 针对上述表述的示意性描述不必仅针对相同的实施例或示例。而是，所描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
为了清楚目的，本发明所属领域公知的某些技术、结构、材料未被详细描述，以避免使本申请变得冗长。
参见图1，其示出了根据本公开的一个示例性实施例的移位寄存器单元100的结构示意图。移位寄存器单元100包括：配置成接收输入脉冲的输入端IN；配置成被施加第一电压的第一电压端VGH；配置成被施加第二电压的第二电压端VGL；配置成接收第一时钟信号的第一时钟信号端CLKA；配置成接收第二时钟信号的第二时钟信号端CLKB；配置成接收调节信号的调节端FIN；配置成输出输出信号的输出端OUT；配置成输出传递信号的传递端CR。移位寄存器单元100还包括被图示为方块的输入电路10、输出电路20和控制电路30。
输入电路10配置成：响应于在第一时钟信号端CLKA接收的第一时钟信号有效，使输入端IN、调节端FIN和第一节点N1彼此导通，以及响应于第一时钟信号CLKA无效，使输入端IN、调节端FIN和第一节点N1彼此断开。当输入端IN、调节端FIN和第一节点N1彼此断开时，所述调节信号减小调节端FIN与第一节点N1之间的电压差，从而能够在移位寄存器单元100正常输出时防止第一节点N1处的电荷异常泄漏。
第一控制电路30配置成：响应于第二节点N2的电位处于有效电位，使第一电压端VGH与第三节点N3导通，响应于在第一时钟信号端CLKA接收的第一时钟信号有效，使第二电压端VGL与第三节点N3导通。需要指出的是，在移位寄存器单元100中，由于第一节点N1与第二节点N2导通，因此在移位寄存器单元100中第一节点N1和第二节点N2具有相同的电位。
输出电路20配置成：响应于第二节点N2的电位处于有效电位，使第二时钟信号端CLKB与输出端OUT和传递端CR导通，响应于第三节点N3的电位处于有效电位，使第一电压端VGH与输出端OUT和传递端CR导通。
需要说明的是，本文使用的术语“有效电位”是指所涉及的电路元件(例如，晶体管)被启用所需的电位，并且本文使用的术语“无效电位”是指所涉及的电路元件被禁用时所处的电位。对于N型晶体管而言，有效电位是高电位，并且无效电位是低电位。对于P型晶体管而言，有效电位是低电位，并且无效电位是高电位。而且将理解的是，有效电位或无效电位并不意图是指某一个具体的电位，而是可以包括一个电位的范围。另外，术语“电压水平”可以与“电位”互换地使用。
此外还需要说明的是，移位寄存器单元100中不必限定调节端FIN所接收的调节信号的来源，这是因为，在本公开的一些示例性实施例中，调节端FIN可以接收来自外部的、独立的信号源的调节信号，只要该调节信号能够在输入端IN、调节端FIN和第一节点N1彼此断开时减小调节端FIN与第一节点N1之间的电压差便可。当然，调节端FIN也可以接收从移位寄存器单元100输出的信号(包括输出信号和/或传递信号)来作为调节信号。
现在参见图2，其示出了图1所示的移位寄存器单元100的示例性电路图。下面参考图2来详细描述移位寄存器单元100的示例性电路构造。
需要指出的是，本公开的各示例性实施例中所采用的晶体管可以为薄膜晶体管或场效应管或具有相同特性的其他器件。在各示例性实施例中，各晶体管典型地被制作成使得它们的源极和漏极可互换地使用，因此其源极、漏极在连接关系的描述上并无实质性区别。在本公开的各示例性实施例中，为区分晶体管的源极和漏极，将其中一极称为第一电极，将另一极称为第二电极，并且将栅极称为控制极。在本公开的示例性实施例中，虽然各晶体管被图示和描述为P型晶体管，但是N型晶体管也是可能的。容易理解，在N型晶体管的情况下，栅极开启电压具有高电位，并且栅极关闭电压具有低电位。在本公开下面的示例性实施例中，作为示例，采用P型晶体管来进行描述。但容易理解的是，本领域的技术人员在本公开的教导下，可以采用N型晶体管来替换本公开各示例性实施例中的一个或多个或者全部P型晶体管，或者可以在本公开各示例性实施例中增加或去除一个或多个元器件，而不脱离本公开的精神和范围。此外，在不与本公开的教导相矛 盾的情况下，还可以设想其他实施例。
如图2所示，移位寄存器单元100的输入电路10包括第一晶体管M1和第二晶体管M2。第一晶体管M1的控制极连接到第一时钟信号端CLKA，其第一电极连接到第一节点N1，其第二电极连接到调节端FIN。第二晶体管M2的控制极连接到第一时钟信号端CLKA，其第一电极连接到调节端FIN，其第二电极连接到输入端IN。由此，响应于第一时钟信号端CLKA接收的第一时钟信号有效，使得输入端IN、调节端FIN和第一节点N1彼此导通，从而相应地将输入信号施加到第一节点N1。
移位寄存器单元100的第一控制电路30包括第三晶体管M3和第四晶体管M4。第三晶体管M3的控制极连接到第一时钟信号端CLKA，其第一电极连接到第三节点N3，其第二电极连接到第二电压端VGL。第四晶体管M4的控制极连接到第二节点N2，其第一电极连接到第三节点N3，其第二电极连接到第一电压端VGH。由此，第一控制电路30响应于第二节点N2的电位处于有效电位，使第一电压端VGH与第三节点N3导通，响应于在第一时钟信号端CLKA接收的第一时钟信号有效，使第二电压端VGL与第三节点N3导通。
需要指出的是，第三晶体管M3和第四晶体管M4的尺寸被设计成具有这样的宽长比(其决定了晶体管的等效导通电阻)，即：使得第三节点N3在第三、第四晶体管M3和M4两者都被开启的情况下被设定处于无效电位。
移位寄存器单元100的输出电路20包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第一电容器C1、第二电容器C2以及第三电容器C3。第五晶体管M5的控制极连接到第二节点N2，其第一电极连接到传递端CR，其第二电极连接到第二时钟信号端CLKB。第六晶体管M6的控制极连接到第二节点N2，其第一电极连接到输出端OUT，其第二电极连接到第二时钟信号端CLKB。第七晶体管M7的控制极连接到第三节点N3，其第一电极连接到第一电压端VGH，其第二电极连接到输出端OUT。第八晶体管M8的控制极连接到第三节点N3，其第一电极连接到第一电压端VGH，其第二电极连接到传递端CR。第一电容器C1的第一电极连接到第六晶体管M6的控制极，其第二电极连接到输出端OUT。第二电容器C2的第一电 极连接到第五晶体管M5的控制极，其第二电极连接到传递端CR。第三电容器C3的第一电极连接到第八晶体管M8的控制极，其第二电极连接到第一电压端VGH。由此，输出电路20响应于第一节点N1的电位处于有效电位，使第二时钟信号端CLKB与输出端OUT和传递端CR两者导通，响应于第三节点N3的电位处于有效电位，使第一电压端VGH与输出端OUT和传递端CR两者导通。
第一、第二电容器C1、C2的存在是有利的，当输出端OUT的输出信号和传递端CR的传递信号从高电位变成低电位时，第二节点N2处的电位可以借助于第一、第二电容器C1、C2而进一步降低，以使第五晶体管M5和第六晶体管M6进一步开启，如后面将描述的。可选地，输出电路20也可以不包括第一电容器C1和第二电容器C2中的至少一个。此外，第三电容器C3的存在也可以是有利的，因为其可以使第三节点N3处的电位变得更加稳定。可选地，输出电路20也可以不包括第三电容器C3。另外，在第七晶体管M7的控制极与第一电压端VGH之间也可以设置电容器，以使第三节点N3处的电位变得更加稳定。
在移位寄存器单元100以及下文中将要详细描述的移位寄存器单元中，通过令输出端OUT和传递端CR分离来分别生成输出信号和传递信号，可以降低与输出端OUT连接的晶体管(即，构成上述输出电路20和第一控制电路30的晶体管)的尺寸，从而可以节省移位寄存器单元100的版图面积，同时可以降低其功耗。
图3示出了根据本公开的另一个示例性实施例的移位寄存器单元110的结构示意图。与图1所示的移位寄存器单元100相比，图3的移位寄存器单元110的不同之处仅在于还包括第一反馈电路40。因此，为简洁起见，下文中仅就移位寄存器单元110的第一反馈电路40进行描述，相同的部分不再赘述。
第一反馈电路40从移位寄存器单元110的输出端OUT和/或传递端CR接收信号，并将所述信号输送到调节端FIN。具体而言，在一些实施例中，第一反馈电路40构造成：响应于传递端CR的传递信号处于有效电位，使输出端OUT与调节端FIN导通。而在另一些实施例中，第一反馈电路40构造成：响应于输出端OUT的输出信号处于有效电位，使传递端CR与调节端FIN导通。
图4示出了图3所示的移位寄存器单元110的示例性电路图。与 图2所示的移位寄存器单元110的电路图相比，图4的移位寄存器单元110的电路图的不同之处仅在于还包括第一反馈电路40。因此，下文中仅就移位寄存器单元110的第一反馈电路40进行描述，相同的部分不再赘述。
第一反馈电路40包括第九晶体管M9。第九晶体管M9的控制极连接到传递端CR，其第一电极连接到调节端FIN，其第二电极连接到输出端OUT。此时，输出端OUT的输出信号被输送到调节端FIN作为调节信号。容易理解的是，在本公开另外的未示出的实施例中，第九晶体管M9的控制极可以连接到输出端OUT，其第一电极可以连接到调节端FIN，其第二电极可以连接到传递端CR。此时，传递端CR的传递信号被输送到调节端FIN作为调节信号。通过引入反馈信号，移位寄存器单元110工作时，第一节点N1的电位可以通过输入电路10加以维持，因此可以避免了下述问题：在移位寄存器单元110正常输出时由于第一节点N1的电荷异常泄漏导致第二节点N2的电位不稳定，继而使得移位寄存器单元110的输出信号不稳定，甚至可能导致移位寄存器单元110失效。
图5示出了根据本公开的又一个示例性实施例的移位寄存器单元120的结构示意图。与图3所示的移位寄存器单元110相比，图5的移位寄存器单元120的不同之处仅在于还包括第二反馈电路50。因此，为简洁起见，下文中仅就移位寄存器单元110的第二反馈电路50进行描述，相同的部分不再赘述。
第二反馈电路50从移位寄存器单元110的输出端OUT和/或传递端CR接收信号，响应于第三节点N3的电位处于有效电位，使输出端OUT和传递端CR中的至少一个与第一节点N1导通。在图5所示的移位寄存器单元120中，第二反馈电路50从输出端OUT接收信号。但是容易理解的，在一些未示出的实施例中，第二反馈电路50也可以从传递端CR接收信号，或者可以从输出端OUT和传递端CR两者都接收信号。
图6示出了图5所示的移位寄存器单元120的示例性电路图。与图4所示的移位寄存器单元110的电路图相比，图6的移位寄存器单元120的电路图的不同之处仅在于还包括第二反馈电路50。因此，下文中仅就移位寄存器单元120的第二反馈电路50进行描述，相同的部 分不再赘述。
第二反馈电路50包括第十晶体管M10。第十晶体管M10的控制极连接到第三节点N3，其第一电极连接到输出端OUT，其第二电极连接到第一节点N1。容易理解的，在本公开的另一些未示出的实施例中，第十晶体管M10的第一电极也可以连接到传递端CR，或者可以连接到输出端OUT和传递端CR两者。
图7示出了根据本公开的再一个示例性实施例的移位寄存器单元130的结构示意图。与图5所示的移位寄存器单元120相比，图7的移位寄存器单元130的不同之处仅在于还包括第二控制电路60。因此，为简洁起见，下文中仅就移位寄存器单元130的第二控制电路60进行描述，相同的部分不再赘述。
第二控制电路60设置在第一节点N1和第二节点N2之间，并且构造成：响应于第一节点N1的电位低于第二电压端VGL的电压时，使第一节点N1与第二节点N2断开。第二控制电路60的作用是当移位寄存器单元120产生输出脉冲时，当输出端OUT的输出信号和传递端CR的传递信号从高电位变成低电位时，第一节点N1和第二节点N2处的电位可以借助于第一、第二电容器C1、C2而进一步降低，以使第五晶体管M5和第六晶体管M6进一步开启。此时，为了防止第一节点N1处的电荷泄漏而影响第二节点N2处的电位，从而影响第五晶体管M5和第六晶体管M6的开启，第二控制电路60将第一节点N1与第二节点N2断开，由此使第二节点N2处的电位保持稳定，从而使第五晶体管M5和第六晶体管M6的开启保持稳定。
图8示出了图7所示的移位寄存器单元130的示例性电路图。与图6所示的移位寄存器单元120的电路图相比，图8的移位寄存器单元130的电路图的不同之处仅在于还包括第二控制电路60。因此，下文中仅就移位寄存器单元130的第二控制电路60进行描述，相同的部分不再赘述。
第二控制电路60包括第十一晶体管M11。第十一晶体管M11的控制极连接到第二电压端VGL，其第一电极连接到第一节点N1，其第二电极连接到第二节点N2。当输出端OUT的输出信号和传递端CR的传递信号从高电位变成低电位时，第二节点N2处的电位可以借助于第一、第二电容器C1、C2而进一步降低，同时也使得第一节点N1处的 电位也进一步降低，并且低于第二电压端VGL处的第二电压，由此导致第十一晶体管M11截止，从而令第一节点N1与第二节点N2断开。
参见图9，其示出了图2、4、6所示的移位寄存器单元的示例性时序图。下面基于图9来具体描述图2、4、6所示的移位寄存器单元100、110、130的操作。在下文中，以1表示高电位，并且以0表示低电位。
在第一时间阶段P1，IN＝0，VGH＝1，VGL＝0，CLKA＝0，CLKB＝1。因为CLKA＝0，所以第一、第二晶体管M1、M2开启，使得此时第一节点N1和第二节点N2的电位处于低电位(即，有效电位)。第三晶体管M3也开启，以使第二电压端VGL与第三节点N3导通，同时第四晶体管M4开启，以使第一电压端VGH与第三节点N3导通。如前面已经描述的，第三晶体管M3和第四晶体管M4的尺寸被设计成使得第三节点N3在第三、第四晶体管M3和M4两者都被开启的情况下被设定处于无效电位(即，高电位)。因为第三节点N3处于高电位，所以第七、第八晶体管M7、M8关断，同时因为第二节点N2的电位处于低电位，所以第五、第六晶体管M5、M6开启，以使第二时钟信号端CLKB与输出端OUT和传递端CR都导通。此时，因为CLKB＝1，所以输出端OUT和传递端CR的输出也为1。
此外，对于移位寄存器单元110、120而言，在第一时间阶段P1，因为CR＝1，所以第九晶体管M9关断。而对于移位寄存器单元120而言，因为第三节点N3＝1，所以第十晶体管M10也关断。
在第二时间阶段P2，IN＝1，VGH＝1，VGL＝0，CLKA＝1，CLKB＝0。因为CLKA＝1，所以第一、第二晶体管M1、M2关断。在该时间阶段，第一节点N1和第二节点N2的电位继续保持处于低电位。因为N2＝0，所以第四晶体管M4保持开启，而因为CLKA＝1，所以第三晶体管M3关断，由此使得保持N3＝1。因为N3＝1，所以第七、第八晶体管M7、M8关断，同时因为N2＝0，所以第五、第六晶体管M5、M6开启，以使第二时钟信号端CLKB与输出端OUT和传递端CR都导通。此时，因为CLKB＝0，所以输出端OUT和传递端CR的输出也为0。
对于移位寄存器单元100，在第二时间阶段P2时，可以通过使从调节端FIN接收的调节信号也处于低电位，以便减小第一晶体管M1的源漏极间电压差，从而减小第一节点N1通过第一晶体管M1发生漏电的可能性。而对于移位寄存器单元110、120而言，在第二时间阶段 P2时，因为CR＝0，所以第九晶体管M9开启，以将输出端OUT的输出信号输送到调节端FIN作为调节信号，因为OUT＝0，并且第一节点N1和第二节点N2都处于低电位，因而可以减小第一晶体管M1的源漏极间电压差，从而减小了第一节点N1通过第一晶体管M1发生漏电的可能性。此外，对于移位寄存器单元120而言，在第二时间阶段P2时，因为第三节点N3＝1，所以第十晶体管M10继续保持关断。
因此，在第二时间阶段P2，移位寄存器单元100、110、120生成输出脉冲。
在第三时间阶段P3，IN＝1，VGH＝1，VGL＝0，CLKA＝0，CLKB＝1。因为CLKA＝0，所以第一、第二晶体管M1、M2开启，但因为IN＝1，所以第一节点N1和第二节点N2的电位现在处于高电位。第三晶体管M3开启，第四晶体管M4关断，所以现在第三节点N3＝0。因为N2＝1，所以第五、第六晶体管M5、M6关断，同时因为N3＝0，所以第七、第八晶体管M7、M8开启，以使第一电压端VGH与输出端OUT和传递端CR都导通。此时，因为VGH＝1，所以输出端OUT和传递端CR的输出也为1。
此外，对于移位寄存器单元110、120而言，在第三时间阶段P3，因为CR＝1，所以第九晶体管M9关断，从而将输出端OUT与调节端FIN断开。而对于移位寄存器单元120而言，因为第三节点N3＝0，所以第十晶体管M10现在开启，以将输出端OUT的输出信号输送到第一节点N1，给第一节点N1和第二节点N2充电，以维持第一节点N1和第二节点N2的电位稳定。
因此，在第三时间阶段P3，移位寄存器单元100、110、120实现复位。此后，移位寄存器单元100、110、120将保持输出端OUT和传递端CR的输出信号的电位不变，直到接收下一个输入脉冲时为止。当接收到下一个输入脉冲时，移位寄存器单元100、110、120将重复上述第一、第二、第时间阶段P1、P2、P3中的操作。
图10是图7～8所示的移位寄存器单元130的示例性时序图。
在第一时间阶段P1，IN＝0，VGH＝1，VGL＝0，CLKA＝0，CLKB＝1。因为CLKA＝0，所以第一、第二晶体管M1、M2开启，使得此时第一节点N1处于低电位，并且此时第十一晶体管M11开启，使得第一节点N1和第二节点N2导通，因此第二节点N2也处于低电位。第三晶 体管M3也开启，以使第二电压端VGL与第三节点N3导通，同时第四晶体管M4开启，以使第一电压端VGH与第三节点N3导通。如前面已经描述的，第三晶体管M3和第四晶体管M4的尺寸被设计成使得第三节点N3在第三、第四晶体管M3和M4两者都被开启的情况下被设定处于无效电位(即，高电位)。因为第三节点N3处于高电位，所以第七、第八晶体管M7、M8关断，同时因为第二节点N2的电位处于低电位，所以第五、第六晶体管M5、M6开启，以使第二时钟信号端CLKB与输出端OUT和传递端CR都导通。此时，因为CLKB＝1，所以输出端OUT和传递端CR的输出也为1。此外，因为CR＝1，所以第九晶体管M9关断，因为第三节点N3＝1，所以第十晶体管M10关断。
在第二时间阶段P2，IN＝1，VGH＝1，VGL＝0，CLKA＝1，CLKB＝0。因为CLKA＝1，所以第一、第二晶体管M1、M2关断。在该时间阶段，第一节点N1和第二节点N2的电位继续保持处于低电位。因为N2＝0，所以第四晶体管M4保持开启，而因为CLKA＝1，所以第三晶体管M3关断，由此使得保持N3＝1。因为现在第三节点N3＝1，所以第七、第八晶体管M7、M8关断，同时因为第二节点N2＝0，所以第五、第六晶体管M5、M6开启，以使第二时钟信号端CLKB与输出端OUT和传递端CR都导通。此时，因为CLKB＝0，所以输出端OUT和传递端CR的输出也为0。
需要注意的是，在第二时间阶段P2，由于第一、第二电容器C1、C2的作用，所以当输出端OUT和传递端CR的输出从高电位变到低电位时，会使第一节点N1和第二节点N2处的电位变得更低，即低于第二电压端VGL的第二电压，由此导致第十一晶体管M1截止，以将第一节点N1和第二节点N2断开，从而防止第一节点N1处由于电荷的可能泄漏导致的电位变化对第二节点N2的电位造成影响。因此，如图10中清楚所示，在第二时间阶段P2，第二节点N2处的电位比第一节点N1处的电位更低。
此外类似地，对于移位寄存器单元130而言，在第二时间阶段P2时，因为CR＝0，所以第九晶体管M9开启，以将输出端OUT的输出信号输送到调节端FIN作为调节信号，因为OUT＝0，且第一节点N1处于低电位，因而可以减小第一晶体管M1的源漏极间电压差，从而减小了第一节点N1通过第一晶体管M1发生漏电的可能性。此外，因为 第三节点N3＝1，所以第十晶体管M10保持关断。
因此，在第二时间阶段P2，移位寄存器单元130生成输出脉冲。
在第三时间阶段P3，IN＝1，VGH＝1，VGL＝0，CLKA＝0，CLKB＝1。因为CLKA＝0，所以第一、第二晶体管M1、M2开启，但因为IN＝1，所以第一节点N1和第二节点N2的电位处于高电位。第三晶体管M3开启，第四晶体管M4关断，所以现在第三节点N3＝0。因为第二节点N2＝1，所以第五、第六晶体管M5、M6关断，同时因为N3＝0，所以第七、第八晶体管M7、M8开启，以使第一电压端VGH与输出端OUT和传递端CR都导通。此时，因为VGH＝1，所以输出端OUT和传递端CR的输出也为1。
此外，在第三时间阶段P3，因为CR＝1，所以第九晶体管M9关断；而因为第三节点N3＝0，所以第十晶体管M10开启，以将输出端OUT的输出信号输送到第一节点N1，从而给第一节点N1和第二节点N2充电，以维持第一节点N1和第二节点N2的电位稳定。
因此，在第三时间阶段P3，移位寄存器单元130实现复位。此后，移位寄存器单元130将保持输出端OUT和传递端CR的输出信号的电位不变，直到接收下一个输入脉冲时为止。当接收到下一个输入脉冲，移位寄存器单元130重复上述第一、第二、第时间阶段P1、P2、P3中的操作。
图11示出了图1～6所示的移位寄存器单元的另一示例性时序图，其显示了在一次扫描过程中生成多个输出脉冲的情况；类似地，图12示出了图7～8所示的移位寄存器单元的另一示例性时序图，其也显示了在一次扫描过程中多次输出的情况。需要说明的是，图11、图12示出的这种操作是移位寄存器单元处于级联状态中时，因此图11和图12中均示出了扫描信号STU，移位寄存器单元接收到扫描信号STU后(即，该移位寄存器单元是级联中的第一级)，生成两个输出信号脉冲(相应地，还可以包括两个传递信号脉冲)，随后两个输出信号脉冲或两个传递信号脉冲可输送到下一级移位寄存器单元作为输入脉冲，并相应地继续生成被移位的两个输出信号脉冲。
在图11和图12所示的示例性时序图中，在第一、第二时间阶段P2.1、P2.2中，移位寄存器单元的操作与前面关于图9、图10中的第一、第二时间阶段P1、P2描述的操作相同。因此，这里不再赘述。在 第三、第四时间阶段P2.3、P2.4中，移位寄存器单元重复第一、第二时间阶段P2.1、P2.2中的操作。在第五时间阶段P2.5中，移位寄存器单元的操作与前面关于图9、图10中的第三时间阶段P3描述的操作相同。因此，这里也不再赘述。
如图11和图12中所示，移位寄存器单元在一次扫描过程中可以生成两个输出信号脉冲。容易理解的是，根据本公开示例性实施例的移位寄存器单元根据需要，可以在一次扫描过程中可以生成更多的输出信号脉冲。
图13显示了由图1～图8的移位寄存器单元构成的栅极驱动器300的结构示意图，并且也显示了该栅极驱动器300在示意性的显示面板中的示例性连接情况。
如图13所示，栅极驱动器300包括2N个级联的移位寄存器单元SR(1)，SR(2)，...，SR(2N-1)和SR(2N)，其每一个可以采取如上面关于图1～图5描述的移位寄存器单元的形式。N可以是大于或等于1的整数。在栅极驱动器300中，除了第一个移位寄存器单元SR(1)之外，各移位寄存器单元中的每一个的输入端IN连接到相邻上一个移位寄存器单元的传递端CR。
当栅极驱动器300被布置在显示面板中时，栅极驱动器300中的2N个移位寄存器单元SR(1)，SR(2)，...，SR(2N-1)和SR(2N)可以相应地连接到2N条栅线G[1]，G[2]，...，G[2N-1]和G[2N]。此外，对于各移位寄存器单元SR(1)，SR(2)，...，SR(2N-1)和SR(2N)中的每一个而言，其第一电压端VH连接到第一电压线vgh，其第二电压端连接到第二电压线vgl，其中第一电压线vgh配置成传送第一电压线电压，第二电压线vgl配置成传送第二电压线电压。此外，各移位寄存器单元SR(1)，SR(2)，...，SR(2N-1)和SR(2N)中的第奇数个移位寄存器单元的第一时钟信号端CLKA连接到第一时钟线clk1，其第二时钟信号端CLKB连接到第二时钟线clk2；并且第偶数个移位寄存器单元的第一时钟信号端CLKA连接到第二时钟线clk2，其第二时钟信号端CLKB连接到第一时钟线clk1。
图14是根据本公开的示例性实施例的显示装置500的结构示意图。参考图14，显示装置500包括显示面板510、时序控制器520、栅极驱动器530、数据驱动器540和电压生成器550。栅极驱动器530可以采 取上面关于图13所示的栅极驱动器300的形式。另外，在图13中示出的第一时钟线clk1、第二时钟线clk2、第一电压线vgh、第二电压线vgl在图14中为了图示的方便被省略。
显示面板510用于显示接收到的图像数据。显示面板510可以具有各种类型的结构，例如add-on、in-cell、on-cell、OGS等等。显示面板510包括连接至在第一方向D1上延伸的多个栅极线GL和在与第一方向D1交叉(例如，基本垂直)的第二方向D2上延伸的多个数据线DL。显示面板510的显示面板包括以矩阵形式排列的多个像素(未示出)。所述像素中的每一个可电连接至栅极线GL中的对应一条栅极线和数据线DL中的对应一条数据线。显示面板510的显示面板可以是液晶显示面板、有机发光二极管(OLED)显示面板或任何其他合适类型的显示面板。
时序控制器520控制显示面板510、栅极驱动器530、数据驱动器540、电压生成器550的操作。时序控制器520从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器520基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。时序控制器520的实现方式是本领域已知的。时序控制器520可以以许多方式(例如诸如利用专用硬件)实现以便执行本文讨论的各种不同的功能。“处理器”是采用一个或多个微处理器的时序控制器520的一个示例，所述微处理器可以使用软件(例如微代码)进行编程以便执行本文讨论的各种不同的功能。时序控制器520可以在采用或者在不采用处理器的情况下实现，并且也可以实现为执行一些功能的专用硬件和执行其他功能的处理器的组合。时序控制器520的示例包括但不限于常规的微处理器、专用集成电路(ASIC)以及现场可编程门阵列(FPGA)。
栅极驱动器530从时序控制器520接收第一控制信号CONT1。第一控制信号CONT1可以包括经由在图7中示出的第一、第二时钟线clk1和clk2传送的第一、第二时钟线时钟信号。栅极驱动器530基于 第一控制信号CONT1生成用于输出到栅极线GL的多个栅极驱动信号。栅极驱动器530可顺序地将多个栅极驱动信号施加至栅极线GL。
数据驱动器540从时序控制器520接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动器940基于第二控制信号CONT2和输出图像数据RGBD’生成多个数据电压。数据驱动器540可将生成的多个数据电压施加至数据线DL。
电压生成器550向显示面板510、时序控制器520、栅极驱动器530、数据驱动器540以及潜在地另外的组件供应电力。具体地，电压生成器550被配置成在时序控制器520的控制下供应分别经由在图7中示出的第一电压线vgh和第二电压线vgl传送的第一电压线电压和第二电压线电压。电压生成器550的配置可以是本领域已知的。在一个实现方式中，电压生成器550可以包括例如DC/DC转换器之类的电压转换器和交叉开关(crossbar switch)。所述电压转换器从输入电压生成具有不同电压水平的多个输出电压。然后，所述交叉开关可以在时序控制器520的控制下将这些输出电压选择性地耦合到第一电压线vgh和第二电压线vgl，以便供应所需的第一、第二电压。
在各实施例中，栅极驱动器530和/或数据驱动器540可被设置在显示面板510上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)而连接至触控显示面板510。例如，栅极驱动器530可被集成在显示面板510中作为阵列基板行驱动(gate driver on array，GOA)电路。
显示装置500的示例包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪。
参见图15，其示出了用于驱动根据本公开的示例性实施例的移位寄存器单元的示例性方法700。需要指出的是，以下描述的方法中的步骤都是示例性的，它们不一定必须按照所列出的顺序执行，而是这些步骤中的一个或多个根据实际情况可以以不同的顺序或者同时被执行，此外根据实际情况，还可以包括其他的附加步骤。
方法700包括以下步骤：
步骤S701：向第一电压端VGH提供第一电压，向第二电压端VGL提供第二电压，其中，所述第一电压处于有效电位，所述第二电压处于无效电位；
步骤S702：向第一时钟信号端CLKA提供第一时钟信号，以及向第二时钟信号端CLKB提供第二时钟信号，其中，所述第一时钟信号与所述第二时钟信号具有相同的周期和占空比，并且在时序上彼此相差半个周期；以及
步骤S703：向输入端IN提供输入脉冲，所述输入脉冲的脉宽与所述第一时钟信号为无效的持续时间同步。
可选地，从第一时钟信号端CLKA接收的第一时钟信号和从第二时钟信号端CLKB接收的第二时钟信号各自具有50％的占空比。
需要说明的是，根据本公开的示例性实施例的上述移位寄存器单元以及包括其的栅极驱动器均是以2相时钟信号为例进行说明，但是容易理解的是，也可以为4相时钟、6相时钟等等来实现根据本公开的示例性实施例的上述移位寄存器单元以及包括其的栅极驱动器。
如上所述，由于根据本公开的示例性实施例的移位寄存器单元可以通过输出端OUT和传递端CR来分离输出信号和传递信号，从而可以降低与输出端OUT和传递端CR连接的晶体管的尺寸，进而可以节省移位寄存器单元的版图面积，同时可以降低其功耗。此外，还可以避免在移位寄存器单元正常输出时由于第一节点N11的电荷异常泄漏导致第二节点N2的电位不稳定，使得移位寄存器单元的输出信号不稳定，甚至导致移位寄存器单元失效的问题。因此，当构成上述移位寄存器单元的晶体管均为P型晶体管时，在有较大的工艺波动或者PMOS器件性能在使用中严重漂移变化的条件下，该移位寄存器单元的稳定性较高。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括：
    输入端，其配置成接收输入脉冲；
    第一电压端，其配置成被施加第一电压；
    第二电压端，其配置成被施加第二电压；
    第一时钟信号端，其配置成接收第一时钟信号；
    第二时钟信号端，其配置成接收第二时钟信号；
    调节端，其配置成接收调节信号；
    输出端，其配置成输出输出信号；
    传递端，其配置成输出传递信号；
    输入电路，其配置成：响应于在所述第一时钟信号端接收的所述第一时钟信号有效，使所述输入端、所述调节端和第一节点彼此导通，以及响应于所述第一时钟信号无效，使所述输入端、所述调节端和所述第一节点彼此断开；
    第一控制电路，其配置成：响应于所述第二节点的电位处于有效电位，使所述第一电压端与第三节点导通，响应于在所述第一时钟信号端接收的所述第一时钟信号有效，使所述第二电压端与所述第三节点导通；
    输出电路，其配置成：响应于所述第二节点的电位处于有效电位，使所述第二时钟信号端与所述输出端和所述传递端导通，响应于所述第三节点的电位处于有效电位，使所述第一电压端与所述输出端和所述传递端导通；
    其中，所述第一节点与所述第二节点导通，其中，当所述输入端、所述调节端和所述第一节点彼此断开时，所述调节信号减小所述调节端与所述第一节点之间的电压差。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路包括：
    第一晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述第一节点，其第二电极连接到所述调节端；以及
    第二晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述调节端，其第二电极连接到所述输入端。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第一控制电路包括：
    第三晶体管，其控制极连接到所述第一时钟信号端，其第一电极连接到所述第三节点，其第二电极连接到所述第二电压端；以及
    第四晶体管，其控制极连接到所述第二节点，其第一电极连接到所述第三节点，其第二电极连接到所述第一电压端。
  4. 根据权利要求1至3中任一项所述的移位寄存器单元，其中，所述输出电路包括：
    第五晶体管，其控制极连接到所述第二节点，其第一电极连接到所述传递端，其第二电极连接到所述第二时钟信号端；
    第六晶体管，其控制极连接到所述第二节点，其第一电极连接到所述输出端，其第二电极连接到所述第二时钟信号端；
    第七晶体管，其控制极连接到所述第三节点，其第一电极连接到所述第一电压端，其第二电极连接到所述输出端；
    第八晶体管，其控制极连接到所述第三节点，其第一电极连接到所述第一电压端，其第二电极连接到所述传递端。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述输出电路还包括：
    第一电容器，其第一电极连接到所述第六晶体管的控制极，其第二电极连接到所述输出端；以及
    第二电容器，其第一电极连接到所述第五晶体管的控制极，其第二电极连接到所述传递端。
  6. 根据权利要求4或5所述的移位寄存器单元，其中，所述输出电路还包括：
    第三电容器，其第一电极连接到所述第八晶体管的控制极，其第二电极连接到所述第一电压端；和/或
    第四电容器，其第一电极连接到所述第七晶体管的控制极，其第二电极连接到所述第一电压端。
  7. 根据权利要求5所述的移位寄存器单元，其中，所述移位寄存器单元还包括第二控制电路，所述第二控制电路构造成：响应于所述第一节点的电位低于所述第二电压时，使所述第一节点和所述第二节点断开。
  8. 根据权利要求7所述的移位寄存器单位，其中，所述第二控制电路包括第十一晶体管，所述第十一晶体管的控制极连接到所述第二电压端，其第一电极连接到所述第一节点，其第二电极连接到所述第二节点。
  9. 根据权利要求1至8中任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括第一反馈电路，所述第一反馈电路构造成：响应于所述传递端的传递信号处于有效电位，使所述输出端与所述调节端导通。
  10. 根据权利要求9所述的移位寄存器单位，其中，所述第一反馈电路包括第九晶体管，所述第九晶体管的控制极连接到所述传递端，其第一电极连接到所述调节端，其第二电极连接到所述输出端。
  11. 根据权利要求1至8中任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括第一反馈电路，所述第一反馈电路构造成：响应于所述输出端的输出信号处于有效电位，使所述传递端与所述调节端导通。
  12. 根据权利要求11所述的移位寄存器单位，其中，所述第一反馈电路包括第九晶体管，所述第九晶体管的控制极连接到所述输出端，其第一电极连接到所述调节端，其第二电极连接到所述传递端。
  13. 根据权利要求1至12中任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括第二反馈电路，所述第二反馈电路构造成：响应于所述第三节点的电位处于有效电位，使所述输出端和所述传递端中的至少一个与所述第一节点导通。
  14. 根据权利要求13所述的移位寄存器单位，其中，所述第一反馈电路包括第十晶体管，所述第十晶体管的控制极连接到所述第三节点，其第一电极连接到所述输出端和所述传递端中的至少一个，其第二电极连接到所述第一节点。
  15. 一种栅极驱动驱动器，包括N个级联的如权利要求1至14中任一项所述的移位寄存器单元，N为大于等于2的整数，其中N个移位寄存器单元中的第m个移位寄存器单元的传递端连接到N个移位寄存器单元中的第m+1个移位寄存器单元的输入端，m为整数且1≤m＜N。
  16. 一种显示面板，包括：
    第一电压线，其配置成传送第一电压线电压；
    第二电压线，其配置成传送第二电压线电压；
    第一时钟线，其配置成传送第一时钟线时钟信号；
    第二时钟线，其配置成传送第二时钟线时钟信号；以及
    根据权利要求15所述的栅极驱动器，其中：
    所述N个移位寄存器单元的各第一电压端连接到所述第一电压线，
    所述N个移位寄存器单元的各第二电压端连接到所述第二电压线，
    所述N个移位寄存器单元中的第2k-1个移位寄存器单元的第一时钟信号端连接到所述第一时钟线，其第二时钟信号端连接到所述第二时钟线，并且所述N个移位寄存器单元中的第2k个移位寄存器单元的第一时钟信号端连接到所述第二时钟线，其第二时钟信号端连接到所述第一时钟线，并且其中，k为正整数且2k≤N。
  17. 一种显示装置，包括：
    根据权利要求16所述的显示面板；
    时序控制器，其被配置成控制所述显示面板的操作，其中，所述时序控制器被配置成至少向所述第一时钟线和所述第二时钟线分别供应所述第一线时钟线时钟信号和所述第二时钟线时钟信号，其中，所述第一时钟线时钟信号与所述第二时钟线时钟信号具有相同的周期和占空比，并且在时序上彼此相差半个周期；
    电压生成器，其被配置成至少向所述第一电压线和所述第二电压线分别供应所述第一电压线电压和所述第二电压线电压，其中，所述第一电压线电压处于有效电压水平，所述第二电压线电压处于无效电压水平。
  18. 根据权利要求17所述的显示装置，其中，所述第一时钟线时钟信号和所述第二时钟线时钟信号各自具有50％的占空比。
  19. 一种用于驱动如权利要求1至14中任一项所述的移位寄存器单元的方法，包括：
    向所述第一电压端提供所述第一电压，向所述第二电压端提供所述第二电压，其中，所述第一电压处于有效电压水平，所述第二电压处于无效电压水平；
    向所述第一时钟信号端提供所述第一时钟信号，以及向所述第二时钟信号端提供所述第二时钟信号，其中，所述第一时钟信号与所述第二时钟信号具有相同的周期和占空比，并且在时序上彼此相差半个 周期；以及
    向所述输入端提供所述输入脉冲，所述输入脉冲的脉宽与所述第一时钟信号为无效的持续时间同步。
  20. 根据权利要求19所述的方法，其中，所述第一时钟信号和所述第二时钟信号各自具有50％的占空比。
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