WO2017148029A1 - 显示面板、显示装置及显示面板的制造方法 - Google Patents

显示面板、显示装置及显示面板的制造方法 Download PDF

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Publication number
WO2017148029A1
WO2017148029A1 PCT/CN2016/084243 CN2016084243W WO2017148029A1 WO 2017148029 A1 WO2017148029 A1 WO 2017148029A1 CN 2016084243 W CN2016084243 W CN 2016084243W WO 2017148029 A1 WO2017148029 A1 WO 2017148029A1
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Prior art keywords
layer
conductive layer
display panel
region
data line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/084243
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English (en)
French (fr)
Inventor
王贺卫
韩磊
江鹏
郭栋
张南红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/542,000 priority Critical patent/US10606132B2/en
Publication of WO2017148029A1 publication Critical patent/WO2017148029A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel, a display device, and a method of manufacturing the display panel.
  • liquid crystal panels is roughly divided into four processes: array process, CF (color filter) process, cell process and module process.
  • array process CF (color filter) process
  • cell process cell process
  • module process The coating of the electrode area is completed in the array process, and the attachment process of the COF and the PCB is completed in the module process.
  • the cleaning zone is used for pressure cleaning of the electrode zone (Pad) before the bonding process of the module process.
  • the data line layer is higher in height than the adjacent insulating layer, foreign matter may accumulate in the insulating layer when the electrode region is cleaned, and when there is too much accumulation, a short circuit between the data line and the data line is caused.
  • the data line layer is higher than the adjacent insulating layer, when the electrode area is cleaned, the data line layer may be dumped toward the insulating layer due to pressure or the array coating is not strong, etc., when excessively stacked, causing Short circuit between data line and data line.
  • the product is judged as a scrapped (NG) product, and the short-circuited data line needs to be cut by the maintenance equipment to separate the short-circuited data line.
  • NG scrapped
  • Embodiments of the present disclosure provide a display panel, a display device, and a manufacturing method of the display panel, which can solve the problem that the data lines in the existing display technology are easily short-circuited and the product rejection rate is high. The problem.
  • a first aspect of the present disclosure provides a display panel having an electrode region including: a substrate, data disposed on the substrate alternating with each other in a direction parallel to an upper surface of the substrate a line layer and an isolation layer, wherein a height of the data line layer is equal to a height of the isolation layer.
  • the data line layer includes: a first conductive layer disposed on the substrate; and a second conductive layer disposed on the first conductive layer.
  • the data line layer further includes: a spacer layer disposed between the first conductive layer and the second conductive layer; a via disposed in the spacer layer, A via is used to electrically connect the first conductive layer and the second conductive layer.
  • the first conductive layer further extends into the array region of the display panel as a source electrode or a drain electrode of the thin film transistor.
  • the spacer layer comprises a first passivation layer; the isolation layer comprises a second passivation layer.
  • the first conductive layer further extends into the array region of the display panel as a gate electrode of the thin film transistor.
  • the isolation layer comprises a passivation layer.
  • the spacer layer comprises a first insulating layer; the isolation layer comprises a second insulating layer on the substrate and a third passivation layer on the second insulating layer.
  • a ratio of a height of the second conductive layer to a height of the first insulating layer is 1:39.
  • the spacer layer further includes a fourth passivation layer on the first insulating layer.
  • the first conductive layer comprises a metal
  • the second conductive layer comprises a transparent conductive layer
  • the substrate comprises glass
  • the display panel comprises a liquid crystal display panel
  • Another object of the present disclosure is to provide a display device.
  • a second aspect of the present disclosure provides a display device including the above display panel.
  • Still another object of the present disclosure is to provide a method of manufacturing a display panel.
  • a third aspect of the present disclosure provides a method of manufacturing a display panel, including: providing a substrate on which a data line layer and an isolation layer alternate with each other in a direction parallel to an upper surface of the substrate are disposed to form an electrode region of the display panel, wherein a height of the data line layer is set equal to The height of the isolation layer.
  • the data line layer comprises: a first conductive layer disposed on the substrate; and a second conductive layer disposed on the first conductive layer.
  • the data line layer further includes: a spacer layer disposed between the first conductive layer and the second conductive layer; a via disposed in the spacer layer, A via is used to electrically connect the first conductive layer and the second conductive layer.
  • the first conductive layer further extends into the array region of the display panel as a source electrode or a drain electrode of the thin film transistor, the method further comprising: forming the first on the substrate Conducting a layer and patterning it to form a first conductive layer removal region and a first conductive layer retention region that alternate with each other; and providing passivation on the first conductive layer removal region and the first conductive layer retention region a layer; removing the passivation layer on the first conductive layer retention region; disposing the second conductive layer on the first conductive layer removal region and the first conductive layer retention region; and placing the first conductive layer The second conductive layer of the layer removal region is removed.
  • the passivation layer on the first conductive layer retention region is partially removed, the method further comprising: providing a via hole in the passivation layer on the first conductive layer retention region, the via hole being used for The first conductive layer and the second conductive layer are electrically connected.
  • the first conductive layer further extends into the array region of the display panel as a gate electrode of the thin film transistor, the method further comprising: forming the first conductive layer on the substrate and Forming the first conductive layer removal region and the first conductive layer retention region alternately with each other; providing an insulating layer on the first conductive layer removal region and the first conductive layer retention region; Providing a passivation layer on the insulating layer; at least partially removing the passivation layer of the first conductive layer remaining region; and connecting the insulating layer and the passivation layer in the first conductive layer remaining region a via hole of the first conductive layer; the second conductive layer being disposed on the first conductive layer removal region and the first conductive layer retention region; and the removing the first conductive layer removal region The second conductive layer is removed, wherein the via is used to electrically connect the first conductive layer and the second conductive layer.
  • the passivation layer of the first conductive layer retention region is completely removed, the method further comprising: partially removing the insulating layer of the first conductive layer retention region.
  • the height of the insulating layer of the first conductive layer retention region is removed by one tenth.
  • the first conductive layer comprises a metal
  • the second conductive layer comprises a transparent conductive layer
  • the substrate comprises glass
  • the display panel comprises a liquid crystal display panel
  • the step of cleaning the electrode region is further included.
  • the step of cleaning the electrode region comprises: pressure cleaning the electrode region with a cleaning tape.
  • the display panel, the display device, and the method of manufacturing the display panel provided by the embodiments of the present disclosure alternate with each other by providing a substrate in an electrode region of the display panel, disposed on the substrate, and in a direction parallel to an upper surface of the substrate.
  • the data line layer and the isolation layer make the height of the data line layer equal to the height of the isolation layer, which can effectively prevent the short circuit caused by the inclination of the data line, reduce equipment investment and personnel expenses, and improve the yield of the primary product.
  • FIG. 1 is a schematic view showing a manufacturing process of an electrode region of a display panel of the prior art, in which a gate metal layer is used as a part of a data line layer of an electrode region;
  • FIG. 2 is a schematic view showing a manufacturing process of an electrode region of a display panel of the prior art, in which a source/drain metal layer is used as a part of a data line layer of an electrode region;
  • FIG. 3(a) is a schematic diagram of an electrode region fabrication process of a display panel in which a gate electrode is used as a portion of a data line layer, in accordance with an embodiment of the present disclosure
  • 3(b) is a partial enlarged view of an electrode region of a display panel manufactured according to the manufacturing process of FIG. 3(a);
  • FIG. 4(a) is a schematic diagram of an electrode region fabrication process of a display panel in which a gate electrode is used as a part of a data line layer, according to another embodiment of the present disclosure
  • FIG. 4(b) is a partial enlarged view of an electrode region of a display panel manufactured according to the manufacturing process of FIG. 4(a);
  • FIG. 5(a) is a schematic diagram of an electrode region fabrication process of a display panel in which a source/drain electrode is used as a part of a data line layer, according to still another embodiment of the present disclosure
  • Figure 5 (b) is a partial enlarged view of an electrode region of the display panel manufactured according to the manufacturing process of Figure 5 (a);
  • FIG. 6(a) is a schematic diagram of an electrode region fabrication process of a display panel in which a source/drain electrode is used as a part of a data line layer, according to still another embodiment of the present disclosure
  • Figure 6 (b) is a partial enlarged view of an electrode region of a display panel manufactured according to the manufacturing process of Figure 6 (a);
  • Figure 7 is a flow chart of a method of one embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and The derivative should refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • Terminology “Touch” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • Figure 1 shows a schematic diagram of a scheme using a gate metal layer as part of a data line layer, the fabrication steps being as follows:
  • the gate layer metal is patterned into a specific shape by a process such as exposure and development peeling.
  • PVX passivation layer
  • ITO indium tin oxide
  • Figure 2 shows another schematic diagram using a source/drain metal layer as part of the data line layer.
  • the fabrication steps are as follows:
  • the source/drain metal electrode layer is coated.
  • the source/drain metal electrode layer is patterned into a specific shape by a process such as exposure and development peeling.
  • PVX passivation layer
  • the ITO metal layer is coated, and the ITO above the source/drain layer is connected to the source/drain through the via.
  • the present disclosure provides a scheme capable of setting a data line layer and an isolation layer disposed between data line layers to have the same height.
  • the electrode region of the display panel of the present disclosure includes a substrate, a data line layer on the substrate, and an isolation layer, wherein the data line layer and the isolation layer alternate with each other in a direction parallel to an upper surface of the substrate, the data line layer The height is equal to the height of the isolation layer.
  • the data line layer includes a first conductive layer on the substrate and a second conductive layer on the first conductive layer.
  • a gate electrode (eg, metal) is used as part of the data line layer in the electrode region of the display panel, ie, the first conductive layer also extends into the array region of the display panel as the gate of the thin film transistor electrode.
  • a spacer layer is disposed between the first conductive layer and the second conductive layer, and a via hole for electrically connecting the first conductive layer and the second conductive layer is disposed in the spacer layer, which is preferably located at a center of the spacer layer, and preferably, the The via is filled with a material of the second conductive layer.
  • the spacer layer includes a gate insulating layer (first insulating layer) on the gate layer.
  • the spacer layer further includes a passivation layer (fourth passivation layer) on the gate insulating layer.
  • the isolation layer includes an insulating layer (second insulating layer) on the gate side and a passivation layer (third passivation layer) on the insulating layer.
  • second passivation layer does not mean that there are two passivation layers required; it can mean that there is only one passivation layer, which is referred to as a "second passivation layer.”
  • one end of the via hole shown in the drawing extends into the first conductive layer, it may contact only the upper surface of the first conductive layer without extending into the first conductive layer as long as the via hole can be formed An electrically conductive connection of the first electrically conductive layer.
  • the data line layer includes a first conductive layer 311 (gate electrode layer), a first insulating layer 313, a second conductive layer 312, and a via 314.
  • the first insulating layer 313 is located between the first conductive layer 311 and the second conductive layer 312, and the via 314 is disposed in the spacer layer formed by the first insulating layer 313.
  • the via 314 is worn from the second conductive layer 312.
  • the first conductive layer 313 is passed through the first insulating layer 313, preferably at the center of the first insulating layer 313.
  • the isolation layer includes a second insulating layer 321 and a third passivation layer 322 disposed on the second insulating layer.
  • the data line layer includes a first conductive layer 411, a first insulating layer 413, a fourth passivation layer 415, a second conductive layer 412, and a via. 414, wherein the via 414 is disposed in the spacer layer formed by the first insulating layer 413 and the fourth passivation layer 415, preferably at the center of the spacer layer.
  • the isolation layer includes a second insulating layer 421 and a third passivation layer 422.
  • the source or drain layer metal is used as part of the data line layer, ie, the first conductive layer also extends into the array region of the display panel as the source or drain electrode of the thin film transistor.
  • the first conductive layer and the second conductive layer may be in direct contact, or a spacer layer may be disposed therebetween.
  • the spacer layer may be a passivation layer (first passivation layer), and a via hole for electrically connecting the first conductive layer and the second conductive layer is disposed therein, and preferably, the via hole is filled with a material of the second conductive layer.
  • the isolation layer also includes a passivation layer (second passivation layer).
  • the data line layer includes a first conductive layer 511 and a second conductive layer 512.
  • the isolation layer includes a second passivation layer 521.
  • the data line layer includes a first conductive layer 611, a first passivation layer 613, a second conductive layer 612, and a via 614.
  • the via 614 is disposed in the first passivation layer 613.
  • the isolation layer includes a second passivation layer 621.
  • the display panel of the present disclosure includes, but is not limited to, a liquid crystal display panel.
  • the substrate may be a glass substrate or other suitable material.
  • the first conductive layer may be a metal layer suitable for electrodes of the source, drain or gate of the thin film transistor, or may be other suitable materials.
  • the second conductive layer may be an ITO layer or other suitable transparent conductive layer.
  • the method of the present disclosure provides a substrate on which a data line layer and an isolation layer which alternate with each other in a direction parallel to an upper surface of the substrate are disposed, and a height of the data line layer is set equal to a height of the isolation layer.
  • the gate layer metal is used as the first conductive layer, that is, when the first conductive layer also extends into the array region of the display panel as the gate electrode of the thin film transistor, see FIG. (a) and Figure 4(a), the following exemplary methods can be used:
  • the substrate material may be any suitable substrate material in the art, for example, glass.
  • step S2 providing a gate metal layer as a first conductive layer on the substrate (as shown in step S302 or S402).
  • step S3 patterning the gate metal layer to form a first conductive layer removal region and a first conductive layer retention region that alternate with each other (as shown in step S303 or S403).
  • the patterning process may take any suitable process known to those skilled in the art, for example, a photolithography process including exposure, development, and etching.
  • step S4 providing an insulating layer on the first conductive layer removal region and the first conductive layer retention region (as shown in step S304 or S404).
  • step S5 providing a passivation layer on the insulating layer (as shown in step S305 or S405).
  • a via hole for electrically connecting the first conductive layer and the second conductive layer is disposed (as shown in step S306 or S406).
  • Via holes can be formed by processes such as dry etching. For the case where the passivation layer on the remaining region of the first conductive layer is completely removed, as shown in FIG. 3, a via hole is provided in the insulating layer. For the case where the passivation layer on the remaining portion of the first conductive layer is partially removed, as shown in FIG. 4, via holes are provided in the passivation layer and the insulating layer.
  • a second conductive layer such as a transparent conductive oxide.
  • Transparent conductive oxides include, but are not limited to, ITO.
  • a second conductive layer is integrally deposited over the data line layer and the spacer layer (as shown in step S307 or S407), and then the second conductive layer is patterned (eg, using a photolithography process) such that Forming a second conductive layer removal region and a second conductive alternating with each other The layer reserved area (as shown in step S308 or S408).
  • the second conductive layer removal region and the second conductive layer retention region respectively correspond to the first conductive layer removal region and the first conductive layer retention region.
  • the spacer layer between the first conductive layer and the second conductive layer is composed of an insulating layer in which via holes are formed.
  • the spacer layer between the first conductive layer and the second conductive layer is composed of an insulating layer and a passivation layer, and via holes are formed in In the insulating layer and the passivation layer.
  • the source/drain layer metal is used as the first conductive layer, that is, when the first conductive layer also extends into the array region of the display panel as the source/drain electrodes of the thin film transistor
  • the following exemplary methods can be employed:
  • the substrate material may be any suitable substrate material in the art, for example, glass.
  • a gate metal layer may also be disposed on the substrate of the display panel (as shown in step S502- or step S602-), and then the patterning process is utilized.
  • the gate metal layer of the electrode region is removed (for example, by photolithography) (as shown in step S503 or step S603).
  • the gate insulating layer may be further disposed (as shown in step S504 or step S604). It should be noted that in the case where the source/drain layer metal is used as a part of the data line layer, the arrangement of the gate and the gate insulating layer is not necessary for the electrode region.
  • step S2 providing a source/drain metal layer as the first conductive layer on the substrate (as shown in step S505 or step S605).
  • step S3 patterning the source/drain metal layer (as shown in step S506 or step S606) to form a first conductive layer removal region and a first conductive layer retention region that alternate with each other.
  • the patterning process can take any suitable process known to those skilled in the art, such as a photolithography process.
  • step S4 providing a passivation layer on the first conductive layer removal region and the first conductive layer retention region (as shown in step S507 or step S607).
  • step S5 According to the specific case of the layer height, the passivation layer on the remaining region of the first conductive layer is completely removed (see S508 of FIG. 5(a)) or partially removed (see S608 of FIG. 6(a)). For the case shown in FIG. 6, step S5 further includes providing via holes in the remaining passivation layers to electrically connect the first conductive layer and the second conductive layer (see step S608).
  • a second conductive layer such as an ITO layer.
  • a second conductive layer is integrally deposited at the data line layer and the spacer layer (as shown in step S509 or step S609), and then the second conductive layer is patterned (eg, using a photolithography process) such that It forms a second conductive layer removal region and a second conductive layer retention region that alternate with each other (as shown in step S510 or step S610). And the second conductive layer removal region and the second conductive layer retention region respectively correspond to the first conductive layer removal region and the first conductive layer retention region.
  • the spacer layer between the first conductive layer and the second conductive layer is composed of a passivation layer, and via holes are formed in passivation In the layer, it is preferably located at the center of the passivation layer.
  • FIG. 7 shows a flow chart of an illustrative method of one embodiment of the present disclosure.
  • a substrate is provided.
  • a first conductive layer is disposed.
  • the first conductive layer may be patterned to form a first conductive layer retention region and a first conductive layer removal region to form a first conductive layer at the data line layer and no first conductive layer at the isolation layer.
  • an insulating layer and a passivation layer are provided when the first conductive layer also extends into the array region of the display panel as a gate electrode of the thin film transistor.
  • a passivation layer is provided when the first conductive layer also extends into the array region of the display panel as a source/drain electrode of the thin film transistor.
  • the passivation layer on the first conductive layer retention region (corresponding to the data line layer) is partially or completely removed as needed for the layer height.
  • the insulating layer on the first conductive layer retention region is further partially removed.
  • a first guide for electrical connection is provided Vias of the electrical layer and the second conductive layer.
  • a second conductive layer is disposed at the data line layer.
  • the scheme of the present disclosure when the array coating process is performed, adjusts the relationship between the height of the data line layer and the isolation layer without increasing the existing mask, so that the height of the isolation layer is finally The height of the data line layer is consistent, keeping the data line and the insulating layer in a horizontal plane.
  • the step of cleaning the electrode region is performed, for example, when the electrode region is pressure-washed by the cleaning tape, there is no height difference between the data line layer and the isolation layer, and there is no groove.
  • the possibility that the isolation layer accumulates conductive foreign matter at this time is greatly reduced, and the smooth surface is more favorable for the movement of foreign matter, and the cleaning tape can remove foreign matter.
  • the cleaning tape cleans the data line of the electrode region with a certain pressure, it is possible to prevent the cleaning tape from causing the data line of the electrode region to be dumped.
  • the solution of the present disclosure can greatly provide the cleaning rate of the electrode area, reduce the foreign matter in the electrode area, greatly reduce the incidence of the short circuit of the data line short circuit after the module attaching process, reduce equipment investment and personnel expenses, and improve the primary product. Yield.

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Abstract

一种显示面板、显示装置及显示面板的制造方法。所述显示面板具有电极区，电极区包括：基板，设置在基板上的并在平行于基板的上表面的方向上彼此交替的数据线层和隔离层，其中，数据线层的高度等于隔离层的高度。由于数据线层与隔离层之间没有高度差，不存在沟槽，隔离层此时堆积导电异物的可能性大大降低，并且平滑的表面更有利于异物的移动，清洗带可以移除异物。此外，当清洗带以一定压力来清洗电极区的数据线时，可以防止清洗带使电极区数据线倾倒的情况的发生，从而可以提高电极区的清洗率，减少电极区的异物，降低了模组贴附工艺后的数据线短路的不良发生率，减少设备投资与人员费用，提高一次产品良率。

Description

显示面板、显示装置及显示面板的制造方法
相关申请的交叉引用
本申请要求于2016年03月02日递交的中国专利申请第201610117900.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域，特别涉及一种显示面板、显示装置及显示面板的制造方法。
背景技术
液晶面板的生产大致分为四个工艺：阵列工艺、CF(彩色滤光片)工艺、成盒(cell)工艺以及模组工艺。电极区的镀膜在阵列工艺中完成，COF与PCB的贴附工艺在模组工艺完成。在进行模组工艺的贴附工艺之前会对电极区(Pad)使用清洗带进行压力清洗。
现有技术条件下，有以下两种情况最终导致电极区数据线短路：
第一、由于数据线层比相邻的绝缘层高度高，造成在电极区清洗时，异物会堆积在绝缘层，当堆积过多时，造成数据线与数据线之间短路。
第二、由于数据线层比相邻的绝缘层高度高，在电极区清洗时，由于压力原因或阵列镀膜不牢固等原因，可能导致数据线层向绝缘层处倾倒，当堆积过多时，造成数据线与数据线之间短路。
当电极区的数据线之间短路后，该产品就会被判定为报废(NG)品，需要经过维修设备对短路的数据线进行切割，分离开短路的数据线。
发明内容
本公开文本的实施例提供一种显示面板、显示装置和显示面板的制造方法，能够解决现有显示技术中的数据线之间容易短路、产品报废率较高 的问题。
本公开文本的一个目的在于提供一种显示面板。
本公开文本的第一方面提供了一种显示面板，其具有电极区，所述电极区包括：基板，设置在所述基板上的在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层，其中，所述数据线层的高度等于所述隔离层的高度。
在一种实施方式中，所述数据线层包括：设置在所述基板上的第一导电层；和设置在所述第一导电层上的第二导电层。
可选地，所述数据线层还包括：间隔层，其被设置在所述第一导电层和所述第二导电层之间；过孔，其被设置在所述间隔层中，所述过孔用于电连接所述第一导电层和所述第二导电层。
可选地，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极电极或漏极电极。
可选地，所述间隔层包括第一钝化层；所述隔离层包括第二钝化层。
在一种实施方式中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的栅极电极。
可选地，所述隔离层包括钝化层。
可选地，所述间隔层包括第一绝缘层；所述隔离层包括在所述基板上的第二绝缘层和在所述第二绝缘层上的第三钝化层。
可选地，所述第二导电层的高度和所述第一绝缘层的高度的比为1:39。
可选地，所述间隔层还包括在所述第一绝缘层上的第四钝化层。
可选地，所述第一导电层包括金属；所述第二导电层包括透明导电层；所述基板包括玻璃；所述显示面板包括液晶显示面板。
本公开文本的另一个目的在于提供一种显示装置。
本公开文本的第二方面提供了一种显示装置，其包括上述的显示面板。
本公开文本的又一个目的在于提供一种显示面板的制造方法。
本公开文本的第三方面提供了一种显示面板的制造方法，包括：提供 基板，在所述基板上设置在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层以形成显示面板的电极区，其中，所述数据线层的高度被设置为等于所述隔离层的高度。
可选地，所述数据线层包括：设置在所述基板上的第一导电层；和设置在所述第一导电层上第二导电层。
可选地，所述数据线层还包括：间隔层，其被设置在所述第一导电层和所述第二导电层之间；过孔，其被设置在所述间隔层中，所述过孔用于电连接所述第一导电层和所述第二导电层。
在一种实施方式中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极电极或漏极电极，所述方法进一步包括：在基板上形成所述第一导电层并对其进行构图，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域；在所述第一导电层去除区域和所述第一导电层保留区域上设置钝化层；将第一导电层保留区域上的钝化层去除；在所述第一导电层去除区域和所述第一导电层保留区域上设置所述第二导电层；以及将所述第一导电层去除区域的所述第二导电层去除。
可选地，所述第一导电层保留区域上的钝化层被部分去除，所述方法进一步包括：在第一导电层保留区域上的钝化层中设置过孔，所述过孔用于电连接所述第一导电层和所述第二导电层。
在一种实施方式中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的栅极电极，所述方法进一步包括：在基板上形成所述第一导电层并对其进行构图，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域；在所述第一导电层去除区域和所述第一导电层保留区域上设置绝缘层；在所述绝缘层上设置钝化层；将所述第一导电层保留区域的钝化层至少部分去除；在所述第一导电层保留区域的所述绝缘层和所述钝化层中设置连接到所述第一导电层的过孔；在所述第一导电层去除区域和所述第一导电层保留区域上设置所述第二导电层；以及将所述第一导电层去除区域上的所述第二导电层去除，其中所述过孔用于电连接所述第一导电层和所述第二导电层。
可选地，所述第一导电层保留区域的钝化层被完全去除，所述方法进一步包括：将所述第一导电层保留区域的绝缘层部分地去除。
可选地，所述第一导电层保留区域的绝缘层的高度被去除掉四十分之一。
可选地，所述第一导电层包括金属；所述第二导电层包括透明导电层；所述基板包括玻璃；所述显示面板包括液晶显示面板。
进一步，在形成显示面板的电极区后，还包括对所述电极区清洗的步骤。
进一步，对所述电极区清洗的步骤包括：利用清洗带对所述电极区进行压力清洗。
本公开文本的实施例提供的显示面板、显示装置和显示面板的制造方法，通过在显示面板的电极区提供基板、设置在基板上的并在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层，使数据线层的高度等于隔离层的高度，能够有效防止数据线倾斜带来的短路，减少设备投资与人员费用，提高一次产品良率。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1为现有技术的显示面板的电极区的制造工艺的示意图，其中使用栅极金属层作为电极区的数据线层的一部分；
图2为现有技术的显示面板的电极区的制造工艺的示意图，其中使用源极/漏极金属层作为电极区的数据线层的一部分；
图3(a)为根据本公开文本的一个实施例的显示面板的电极区制造工艺的示意图，其中使用栅极电极作为数据线层的一部分；
图3(b)为根据图3(a)的制造工艺制造的显示面板的电极区的局部放大图；
图4(a)为根据本公开文本的另一个实施例的显示面板的电极区制造工艺的示意图，其中使用栅极电极作为数据线层的一部分；
图4(b)为根据图4(a)的制造工艺制造的显示面板的电极区的局部放大图；
图5(a)为根据本公开文本的又一个实施例的显示面板的电极区制造工艺的示意图，其中使用源极/漏极电极作为数据线层的一部分；
图5(b)为根据图5(a)的制造工艺制造的显示面板的电极区的局部放大图；
图6(a)为根据本公开文本的再一个实施例的显示面板的电极区制造工艺的示意图，其中使用源极/漏极电极作为数据线层的一部分；
图6(b)为根据图6(a)的制造工艺制造的显示面板的电极区的局部放大图；
图7为本公开文本的一个实施例的方法的流程图。
具体实施方式
为了使本公开文本的实施例的目的、技术方案和优点更加清楚，下面将接合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接 触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
图1示出了一种使用栅极金属层作为数据线层的一部分的方案的示意图，制造步骤如下：
S101、提供玻璃基板。
S102、在玻璃基板上沉积栅极金属层。
S103、通过曝光显影剥离等工艺，将栅极层金属构图为特定形状。
S104、栅极绝缘(GI)层镀膜。
S105、钝化层(PVX)镀膜。
S106、通过干刻工艺，制造过孔，该过孔穿过钝化层到达栅极层。此时，PVX层与GI层高度不变。经此工艺后，数据线层的高度已经高出绝缘层高度，二者的高度差为栅极金属层的高度。
S107、氧化铟锡(ITO)层镀膜，栅极层上方的ITO通过过孔与栅极相连接。
S108、进行曝光显影剥离等工艺，使得栅极层上方的ITO保留，其它位置的ITO去除。此时数据线处膜层的高度已经高出绝缘层高度，高度差为栅极层的高度加上ITO层的高度之和。
图2示出了另一种使用源极/漏极金属层作为数据线层的一部分的示意图，制造步骤如下：
S201、提供玻璃基板。
S202、栅极金属层镀膜。
S203、通过曝光显影剥离等工艺，在电极区将栅极层金属全部去除。
S204、栅极绝缘(GI)层镀膜。
S205、源极/漏极金属电极层镀膜。
S206、通过曝光显影剥离等工艺，将源极/漏极金属电极层构图为特定形状。
S207、钝化层(PVX)绝缘层镀膜。
S208、通过干刻工艺，制造过孔，该过孔穿过PVX层到达源极/漏极 金属层。此时PVX层高度不变。进过此工艺后，数据线处膜层的高度已经高出绝缘层高度，二者的高度差为源极/漏极金属层的高度。
S209、ITO金属层镀膜，源极/漏极层上方的ITO通过过孔与源极/漏极相连接。
S210、进行曝光显影剥离等工艺，使得源极/漏极层上方的ITO保留，其它位置处的ITO去除。此时数据线层的高度已经高出绝缘层高度，高度差为源极/漏极电极层的高度加上ITO层的高度之和。
经过图1或图2所示的以上工艺步骤之后，例如，达到模组工艺的电极区清洗时，就存在数据线与数据线短路的风险。
针对上述潜在问题，本公开文本提供了能够将数据线层和设置在数据线层之间的隔离层设置为具有相同高度的方案。
本公开文本的显示面板的电极区包括基板、位于基板上的数据线层和隔离层，其中，数据线层和隔离层在平行于所述基板的上表面的方向上彼此交替，数据线层的高度等于隔离层的高度。数据线层包括位于基板上的第一导电层和位于第一导电层上的第二导电层。
在一种实施方式中，使用栅极电极(例如，金属)作为显示面板电极区中的数据线层的一部分，即，第一导电层还延伸到显示面板的阵列区中作为薄膜晶体管的栅极电极。第一导电层和第二导电层之间设置有间隔层，间隔层中设置有用于电连接第一导电层和第二导电层的过孔，其优选位于间隔层的中心，以及优选地，该过孔由第二导电层的材料填充。间隔层包括在栅极层上的栅极绝缘层(第一绝缘层)。可选地，间隔层还包括在栅极绝缘层上的钝化层(第四钝化层)。在这种情况下，隔离层包括栅极侧的绝缘层(第二绝缘层)和在该绝缘层上的钝化层(第三钝化层)。
需要指出，本公开文本的诸如“第四层”的表达仅仅是特定层的称谓，并非用于限制层的种类数目。例如，“第二钝化层”并非意味着需要有两个钝化层；其可以意味着，只有一个钝化层，该钝化层被称为“第二钝化层”。此外，虽然图中所示的过孔的一端延伸到第一导电层中，其也可以仅接触第一导电层的上表面，而不延伸到第一导电层中，只要该过孔能够形成到 第一导电层的导电连接。
具体地，在一个实施例中，如图3(b)所示，数据线层包括第一导电层311(栅极电极层)、第一绝缘层313、第二导电层312和过孔314。其中，第一绝缘层313位于第一导电层311和第二导电层312之间，过孔314被设置在第一绝缘层313构成的间隔层中，该过孔314从第二导电层312穿过第一绝缘层313而到达第一导电层311，优选位于第一绝缘层313的中心。隔离层包括第二绝缘层321和设置在第二绝缘层上的第三钝化层322。
具体地，在另一个实施例中，如图4(b)所示，数据线层包括第一导电层411、第一绝缘层413、第四钝化层415、第二导电层412和过孔414，其中，过孔414设置在第一绝缘层413和第四钝化层415构成的间隔层中，优选位于间隔层的中心。隔离层包括第二绝缘层421和第三钝化层422。
在一种实施方式中，使用源极或漏极层金属作为数据线层的一部分，即，第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极或漏极电极。第一导电层和第二导电层可以直接接触，或者，在二者之间可以设置有间隔层。间隔层可以为钝化层(第一钝化层)，并且其中设置有用于电连接第一导电层和第二导电层的过孔，优选地，该过孔由第二导电层的材料填充。在此实施例中，隔离层也包括钝化层(第二钝化层)。
具体地，在一个实施例中，如图5(b)所示，数据线层包括第一导电层511和第二导电层512。隔离层包括第二钝化层521。
具体地，在另一个实施例中，如图6(b)所示，数据线层包括第一导电层611、第一钝化层613、第二导电层612和过孔614。其中，过孔614被设置在由第一钝化层613中。隔离层包括第二钝化层621。
本公开文本的显示面板包括但不限于液晶显示面板。基板可以为玻璃基板，也可以为其它合适的材料。第一导电层可以为适用于薄膜晶体管的源极、漏极或者栅极的电极的金属层，也可以为其它合适的材料。第二导电层可以为ITO层，也可以为其它合适的透明导电层。
图3-6还示例性示出了本公开文本的不同实施例的显示面板的电极区 制造工艺。本公开文本的方法提供了基板，在基板上设置在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层，并且将数据线层的高度设置为等于隔离层的高度。
具体地，在一种实施方式中，当使用栅极层金属作为第一导电层时,即，第一导电层还延伸到显示面板的阵列区中作为薄膜晶体管的栅极电极时，参见图3(a)和图4(a)，可以采用如下示例性方法：
S1：提供基板(如步骤S301或步骤S401所示)，基板材料可以本领域的任何适宜的基板材料，例如，玻璃。
S2：在基板上设置作为第一导电层的栅极金属层(如步骤S302或S402所示)。
S3：对栅极金属层进行构图，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域(如步骤S303或S403所示)。其中，构图工艺可以采取本领域技术人员所知晓的任何合适的工艺，例如，包括曝光、显影和刻蚀的光刻工艺等工艺。
S4：在第一导电层去除区域和第一导电层保留区域上设置绝缘层(如步骤S304或S404所示)。
S5：在绝缘层上设置钝化层(如步骤S305或S405所示)。
S6：根据层高度的具体情况，将第一导电层保留区域上的钝化层全部(见图3(a)的S306)或者部分去除(见图4(a)的S406)。
S7：设置用于电连接第一导电层和第二导电层的过孔(如步骤S306或S406所示)。可以利用干刻等工艺来形成过孔。对于第一导电层保留区域上的钝化层全部去除的情况，如图3所示，在绝缘层中设置过孔。对于第一导电层保留区域上的钝化层部分去除的情况，如图4所示，在钝化层和绝缘层中设置过孔。
S8：设置诸如透明导电氧化物的第二导电层。透明导电氧化物包括但不限于ITO。在一个实施例中，在数据线层和间隔层之上整体地沉积第二导电层(如步骤S307或S407所示)，然后对第二导电层进行构图(例如，采用光刻工艺)，使得其形成彼此交替的第二导电层去除区域和第二导电 层保留区域(如步骤S308或S408所示)。并且第二导电层去除区域和第二导电层保留区域分别与第一导电层去除区域和第一导电层保留区域相对应。从而，在隔离层处没有第二导电层，而数据线层位置处具有第二导电层。
可以看出，对于图3所示的第一导电层保留区域上的钝化层全部去除的情况，还可以进一步地去除第一导电层保留区域上的绝缘层的一部分(例如，将其高度去除大约四十分之一)去除。在此情况中，第一导电层和第二导电层之间的间隔层由绝缘层构成，过孔被形成在该绝缘层中。
对于图4所示的第一导电层保留区域上的钝化层部分去除的情况，第一导电层和第二导电层之间的间隔层由绝缘层和钝化层构成，过孔被形成在该绝缘层和钝化层中。
在另一种实施方式中，当使用源极/漏极层金属作为第一导电层时，即，第一导电层还延伸到显示面板的阵列区中作为薄膜晶体管的源极/漏极电极时，参见图5(a)和图6(a)，可以采用如下示例性方法：
S1：提供基板(如步骤S501或步骤S601所示)，基板材料可以本领域的任何适宜的基板材料，例如，玻璃。可选地，考虑到包括电极区和阵列区的显示面板的实际生产需要，还可以在显示面板的基板上设置栅极金属层(如步骤S502-或步骤S602-所示)，然后利用构图工艺(例如，通过光刻)，将电极区的栅极金属层去除(如步骤S503或步骤S603所示)。在去除电极区的栅极金属层之后，可以进一步设置栅极绝缘层(如步骤S504或步骤S604所示)。需要说明，在使用源极/漏极层金属作为数据线层的一部分的情况，对于电极区，栅极和栅极绝缘层的设置并非是必需的。
S2：在基板上设置作为第一导电层的源极/漏极金属层(如步骤S505或步骤S605所示)。
S3：对源极/漏极金属层进行构图(如步骤S506或步骤S606所示)，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域。其中，构图工艺可以采取本领域技术人员所知晓的任何合适的工艺，例如，光刻工艺。
S4：在第一导电层去除区域和第一导电层保留区域上设置钝化层(如步骤S507或步骤S607所示)。
S5：根据层高度的具体情况，将第一导电层保留区域上的钝化层全部(见图5(a)的S508)或者部分去除(见图6(a)的S608)。对于图6所示的情况，步骤S5还包括，在剩余的钝化层中设置过孔，以电连接第一导电层和第二导电层(见步骤S608)。
S6：设置诸如ITO层的第二导电层。在一个实施例中，在数据线层和间隔层处整体地沉积第二导电层(如步骤S509或步骤S609所示)，然后对第二导电层进行构图(例如，采用光刻工艺)，使得其形成彼此交替的第二导电层去除区域和第二导电层保留区域(如步骤S510或步骤S610所示)。并且第二导电层去除区域和第二导电层保留区域分别与第一导电层去除区域和第一导电层保留区域相对应。从而，在隔离层处没有第二导电层，而数据线层位置处具有第二导电层。
可以看出，对于图5所示的将第一导电层保留区域上的钝化层全部除去的情况，第一导电层和第二导电层之间不存在间隔层。对于图6所示的将第一导电层保留区域上的钝化层部分去除的情况，第一导电层和第二导电层之间的间隔层由钝化层构成，过孔被形成在钝化层中，优选位于钝化层的中心。
图7示出了本公开文本的一个实施例的示意性方法的流程图。在框101中，提供了基板。在框201中，设置了第一导电层。可以对第一导电层进行构图，来形成第一导电层保留区域和第一导电层去除区域，以在数据线层处形成有第一导电层，而在隔离层处没有第一导电层。在框301中，当第一导电层还延伸到显示面板的阵列区中作为薄膜晶体管的栅极电极时，设置绝缘层和钝化层。在框302中，当第一导电层还延伸到显示面板的阵列区中作为薄膜晶体管的源/漏极电极时，设置钝化层。在框401、402、403和404中，根据层高度的需要，将第一导电层保留区域(对应于数据线层)上的钝化层部分或者全部去除。在框412中，进一步地将第一导电层保留区域上的绝缘层部分地去除。在框501中，设置用于电连接第一导 电层和第二导电层的过孔。在框601中，在数据线层处设置第二导电层。
本公开文本中描绘的流程图仅仅是一个例子。在不脱离本公开文本精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
由上述描述可以知道，本公开文本的方案在阵列镀膜工艺时，在不增加现有掩模的情况下，通过调整数据线层与隔离层的高度之间的关系，使得隔离层的高度最终与数据线层的高度保持一致，能够使得数据线与绝缘层保持在一个水平面。
在形成显示面板的电极区后，执行对电极区清洗的步骤时，例如利用清洗带对所述电极区进行压力清洗时，由于数据线层与隔离层之间没有高度差，不存在沟槽，隔离层此时堆积导电异物的可能性大大降低，并且平滑的表面更有利于异物的移动，清洗带可以移除异物。此外，当清洗带以一定压力来清洗电极区的数据线时，可以防止清洗带使电极区数据线倾倒的情况的发生。从而，本公开文本的方案可以大大提供电极区的清洗率，减少电极区的异物，大大降低了模组贴附工艺后的数据线短路的不良发生率，减少设备投资与人员费用，提高一次产品良率。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开文本的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开文本的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开文本范围和精神内的此类形式或者修改。

Claims (24)

  1. 一种显示面板，其具有电极区，所述电极区包括：基板，设置在所述基板上的并在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层，其中，
    所述数据线层的高度等于所述隔离层的高度。
  2. 根据权利要求1所述的显示面板，其中，所述数据线层包括：
    设置在所述基板上的第一导电层；和
    设置在所述第一导电层上的第二导电层。
  3. 根据权利要求2所述的显示面板，其中，所述数据线层还包括：间隔层，其被设置在所述第一导电层和所述第二导电层之间；
    过孔，其被设置在所述间隔层中，所述过孔用于电连接所述第一导电层和所述第二导电层。
  4. 根据权利要求3所述的显示面板，其中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极电极或漏极电极。
  5. 根据权利要求4所述的显示面板，其中，所述间隔层包括第一钝化层；
    所述隔离层包括第二钝化层。
  6. 根据权利要求2所述的显示面板，其中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极电极或漏极电极。
  7. 根据权利要求6所述的显示面板，其中，所述隔离层包括钝化层。
  8. 根据权利要求3所述的显示面板，其中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的栅极电极。
  9. 根据权利要求8所述的显示面板，其中，所述间隔层包括第一绝缘层；
    所述隔离层包括在所述基板上的第二绝缘层和在所述第二绝缘层上的第三钝化层。
  10. 根据权利要求9所述的显示面板，其中，所述第二导电层的高度和所述第一绝缘层的高度的比为1:39。
  11. 根据权利要求9所述的显示面板，其中，所述间隔层还包括在所述第一绝缘层上的第四钝化层。
  12. 根据权利要求1-11中任一项所述的显示面板，其中，
    所述第一导电层包括金属；
    所述第二导电层包括透明导电层；
    所述基板包括玻璃；
    所述显示面板包括液晶显示面板。
  13. 一种显示装置，其中，包括权利要求1-12中任一项所述的显示面板。
  14. 一种显示面板的制造方法，包括：提供基板，在所述基板上设置在平行于所述基板的上表面的方向上彼此交替的数据线层和隔离层以形成显示面板的电极区，其中，
    将所述数据线层的高度设置为等于所述隔离层的高度。
  15. 根据权利要求14所述的制造方法，其中，所述数据线层包括：
    设置在所述基板上的第一导电层；和
    设置在所述第一导电层之上的第二导电层。
  16. 根据权利要求15所述的制造方法，其中，所述数据线层还包括：间隔层，其被设置在所述第一导电层和所述第二导电层之间；
    过孔，其被设置在所述间隔层中，所述过孔用于电连接所述第一导电层和所述第二导电层。
  17. 根据权利要求15所述的制造方法，其中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的源极电极或漏极电极，其中，所述方法进一步包括：
    在所述基板上形成所述第一导电层并对其进行构图，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域；
    在所述第一导电层去除区域和所述第一导电层保留区域上设置钝化层；
    将所述第一导电层保留区域上的所述钝化层去除；
    在所述第一导电层去除区域和所述第一导电层保留区域上设置所述第二导电层；以及
    将所述第一导电层去除区域的所述第二导电层去除。
  18. 根据权利要求17所述的制造方法，其中，所述第一导电层保留区域上的钝化层被部分去除，所述方法进一步包括：
    在第一导电层保留区域上的所述钝化层中设置过孔，所述过孔用于电连接所述第一导电层和所述第二导电层。
  19. 根据权利要求15所述的制造方法，其中，所述第一导电层还延伸到所述显示面板的阵列区中作为薄膜晶体管的栅极电极，其中，所述方法进一步包括：
    在所述基板上形成所述第一导电层并对其进行构图，使其形成彼此交替的第一导电层去除区域和第一导电层保留区域；
    在所述第一导电层去除区域和所述第一导电层保留区域上设置绝缘层；
    在所述绝缘层上设置钝化层；
    将所述第一导电层保留区域的所述钝化层至少部分去除；
    在所述第一导电层保留区域的所述绝缘层和所述钝化层中设置连接到所述第一导电层的过孔；
    在所述第一导电层去除区域和所述第一导电层保留区域上设置所述第二导电层；以及
    将所述第一导电层去除区域上的所述第二导电层去除，
    其中所述过孔用于电连接所述第一导电层和所述第二导电层。
  20. 根据权利要求19所述的制造方法，其中，所述第一导电层保留区域的所述钝化层被完全去除，所述方法进一步包括：
    将所述第一导电层保留区域的所述绝缘层部分地去除。
  21. 根据权利要求20所述的制造方法，其中，所述第一导电层保留区域的所述绝缘层的高度被去除掉四十分之一。
  22. 根据权利要求14-21中任一项所述的方法，其中，
    所述第一导电层包括金属；
    所述第二导电层包括透明导电层；
    所述基板包括玻璃；
    所述显示面板包括液晶显示面板。
  23. 根据权利要求22所述的方法，其中，在形成显示面板的电极区后，还包括对所述电极区清洗的步骤。
  24. 根据权利要求23所述的方法，其中，对所述电极区清洗的步骤包括：利用清洗带对所述电极区进行压力清洗。
PCT/CN2016/084243 2016-03-02 2016-06-01 显示面板、显示装置及显示面板的制造方法 Ceased WO2017148029A1 (zh)

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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6466289B1 (en) * 1997-10-21 2002-10-15 Samsung Electronics Co., Ltd. Liquid crystal displays having common electrode overlap with one or more data lines
CN103296033A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板及其制作方法
CN103489878A (zh) * 2013-10-09 2014-01-01 合肥京东方光电科技有限公司 一种阵列基板及其制备方法和显示装置
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN103984171A (zh) * 2013-02-22 2014-08-13 上海天马微电子有限公司 一种阵列基板及其制造方法、液晶显示器
CN105549286A (zh) * 2016-03-02 2016-05-04 京东方科技集团股份有限公司 显示面板、显示装置及显示面板的制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100655276B1 (ko) * 1999-08-30 2006-12-08 삼성전자주식회사 박막트랜지스터 액정표시장치 및 그 제조 방법
KR101111995B1 (ko) * 2003-12-02 2012-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터, 디스플레이 장치 및 액정 디스플레이장치, 그리고 그 제조방법
CN101221926A (zh) * 2008-01-18 2008-07-16 友达光电股份有限公司 液晶显示单元结构及其制造方法
JP2012078459A (ja) * 2010-09-30 2012-04-19 Fujitsu Semiconductor Ltd 反射型液晶表示装置、アクティブマトリックス反射基板、及びその製造方法
KR20130109586A (ko) * 2012-03-28 2013-10-08 삼성디스플레이 주식회사 도전 패턴의 형성 방법, 이를 이용한 표시 기판의 제조 방법 및 표시 기판
CN103500746A (zh) * 2013-09-29 2014-01-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6466289B1 (en) * 1997-10-21 2002-10-15 Samsung Electronics Co., Ltd. Liquid crystal displays having common electrode overlap with one or more data lines
CN103984171A (zh) * 2013-02-22 2014-08-13 上海天马微电子有限公司 一种阵列基板及其制造方法、液晶显示器
CN103296033A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板及其制作方法
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN103489878A (zh) * 2013-10-09 2014-01-01 合肥京东方光电科技有限公司 一种阵列基板及其制备方法和显示装置
CN105549286A (zh) * 2016-03-02 2016-05-04 京东方科技集团股份有限公司 显示面板、显示装置及显示面板的制造方法

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