WO2017143642A1 - 一种基于fpga实现pcm音频采集装置及系统及方法 - Google Patents

一种基于fpga实现pcm音频采集装置及系统及方法 Download PDF

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Publication number
WO2017143642A1
WO2017143642A1 PCT/CN2016/078008 CN2016078008W WO2017143642A1 WO 2017143642 A1 WO2017143642 A1 WO 2017143642A1 CN 2016078008 W CN2016078008 W CN 2016078008W WO 2017143642 A1 WO2017143642 A1 WO 2017143642A1
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data
port ram
acquisition
counter
dual
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French (fr)
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盛利
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邦彦技术股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16—Sound input; Sound output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16—Sound input; Sound output
    • G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/64—Automatic arrangements for answering calls; Automatic arrangements for recording messages for absent subscribers; Arrangements for recording conversations
    • H04M1/65—Recording arrangements for recording a message from the calling party

Definitions

  • the present invention relates to the field of digital audio collection, and in particular, to a PCM audio collection device, system and method.
  • PCM Pulse Code Modulation, pulse code modulation.
  • pulse code modulation coding that is, PCM coding.
  • the PCM converts continuously changing analog signals into digital codes through three steps of sampling, quantization, and encoding.
  • the recording system provided on the market usually adds a recording device on the telephone line, and stores and listens to the audio recording after the audio is collected.
  • the scheme has the following defects:
  • the recording channel has a single function, which causes waste of channel resources
  • an object of the present invention is to provide a low-cost, high-efficiency, large-capacity audio collection device, system, and method.
  • a PCM audio collection device based on FPGA, comprising an audio data acquisition module, an acquisition selection controller, a channel data register, a first dual port RAM and a second dual port RAM;
  • the audio data acquisition module is used in the acquisition selection controller Controlling, compressing and sampling data from the broadband bus to the channel data register of the corresponding channel;
  • the acquisition selection controller is configured to control the audio data acquisition module to collect the broadband bus data and forward the data to the channel data register;
  • the channel data register is used to buffer the multi-channel data, and the multi-channel data is written in two dual-port RAMs; the first dual-port RAM and the second dual-port RAM are interleaved and read channels The data, that is, when the first dual port RAM is written with data, the second dual port RAM is read out of data, and when the second dual port RAM is written with data, the first dual port RAM is read out of data.
  • the acquisition selection controller includes a clock module, 32 acquisition control registers, a 12-bit counter, and an equal comparator, and each of the acquisition control registers corresponds to control information of a call information that needs to be collected, and the control information includes Acquisition enable information, bus selection information, start time slot information, the audio data acquisition module includes a bus selector, a latch control register, and the clock module is configured to provide a clock signal for the 12-bit counter and the latch control register,
  • the bus selector selects to collect corresponding broadband bus data according to the bus selection information, and the start slot information and the 12-bit counter value are compared by the equal comparator, and then the control latch register samples the corresponding data of the broadband bus from the broadband bus to the channel. In the data register.
  • the channel data register includes 32 acquisition buffer registers, and each acquisition buffer register is used to store data for buffering a preset period.
  • the apparatus further includes a start control module, a self-locking counter, an address counter, and a multiplexer, the start control module for generating a start control pulse to the self-locking counter based on the clock signal, the self-locking counter being used And generating an enable pulse to the address counter after receiving the start control pulse according to the clock signal, wherein the address counter is configured to respectively generate address information according to the clock signal to the multiplexer, the first dual port RAM, and the second dual port RAM,
  • the input of the multiplexer is connected to the output of 32 acquisition buffer registers, and the outputs of the multiplexer are respectively connected to the first dual port RAM and the second dual port RAM.
  • the clock signal is 19.44M clock signal
  • the self-locking counter counts from 0x00 to 0x20, when the count value reaches 0x20, the counter stops working, and restarts counting until receiving a start signal from the start control module
  • An enable pulse having a length of 32 19.44 M clock cycles is generated when the count value is between 0x00 and 0x1F, and the enable pulse is used to control the address counter to generate address information
  • the address counter is used to receive self-locking The address is incremented when the enable signal of the counter is valid; the address counter generates 12-bit address information, the lower 11-bit address information is the write address of the dual-port RAM, and the highest bit is used for the first dual-port RAM and the second dual-port RAM.
  • the chip select signal, the chip select signals of the two dual port RAMs are always alternately valid.
  • An PCM audio acquisition system based on FPGA comprising a broadband bus, an audio collection device, a CPU, an audio server, an output end of the broadband bus is connected to an audio collection device, and an output end of the audio collection device is connected to a CPU.
  • the output of the CPU is connected to the audio server.
  • the audio data acquisition module is controlled by the acquisition controller to collect the data of the broadband bus, and the data is compressed and sampled, and sent to the channel data register of the corresponding channel;
  • the channel data register buffers the corresponding channel data into the two dual-port RAMs after the preset period
  • the acquisition selection controller in step S1 includes a clock module, 32 acquisition control registers, a 12-bit counter, and an equal comparator, and each of the acquisition control registers corresponds to control information of a call information that needs to be collected.
  • the control information includes acquisition enable information, bus selection information, and start slot information.
  • the audio data collection module includes a bus selector and a latch control register.
  • the bus selector selects to collect corresponding broadband bus data according to bus selection information
  • the start time slot information and the 12-bit counter value are compared by the equal comparator, and then the control latch register samples the corresponding data of the broadband bus from the broadband bus into the channel data register.
  • the step S2 specifically includes the sub-steps:
  • the start control module generates a pulse having a length of 19.44 M clock cycle when the counter counts up to 2100;
  • the self-locking counter starts counting after receiving a start signal from the start control module, and the counting range is from 0x00 to 0x20, and generates a length of 32 19.44M clock cycles when its counting value is between 0x00 and 0x1F.
  • Width enable pulse the pulse signal is used to control the address counter to generate address information, when the count value reaches 0x20, the counter stops working, and restarts counting until receiving the start signal from the start control module;
  • the address counter starts to increment the address when the enable signal from the self-locking counter is valid, otherwise the address does not change, the address counter generates 12-bit address information, and the lower 11-bit address information is the write address of the dual-port RAM.
  • the highest bit is used for the chip select signal of the first dual port RAM and the second dual port RAM, and the chip select signals of the two dual port RAMs are always alternately valid.
  • the step S3 specifically includes the sub-steps:
  • the CPU reads data from the dual port RAM by using an interrupt mode or a timing query manner; if the interrupt mode is used, after the FPGA logic generates an interrupt, the dual port RAM is full, and the read operation is performed, and then the CPU directly Read data; if the query mode is used, the interrupt enable bit of the interrupt status control register must be disabled first, and the dual-port RAM status flag in the interrupt status control register must be determined before reading the data, if the dual-port RAM is full Data can be read, otherwise the dual port RAM cannot be read.
  • the invention mainly completes the acquisition of the audio signal on the broadband bus, and after the acquisition signal is processed by the logic of the FPGA, the collected data is sent to the audio collection server, and the audio collection server realizes the storage.
  • the invention reduces the complexity of the composition of the recording system, and the recording channel can be reused, the system cost is reduced, the system capacity is large, and the 32-channel acquisition capability is provided, which has good economic and social benefits.
  • the invention is widely applicable to various PCM audio collection systems.
  • Figure 1 is a logic block diagram of an embodiment of the apparatus of the present invention.
  • Figure 2 is a schematic view showing the operation of an embodiment of an acquisition channel in the apparatus of the present invention
  • FIG. 3 is a logic diagram of an embodiment of the acquisition of channel data into a dual port RAM in the apparatus of the present invention.
  • the audio collection takes the audio acquisition function module provided by the existing program-controlled switch platform as an example.
  • the program-controlled switch provides a consistent card slot and accesses the required board.
  • the audio collection exists on the acquisition board.
  • the system supports the insertion of multiple acquisition boards to provide application requirements based on 32-channel acquisition and 32-channel playback multiplier.
  • the design principle of the audio acquisition module which is purely designed and invented, has universality and is not limited to any application platform.
  • an FPGA-based PCM audio acquisition system includes a broadband bus, an audio collection device, a CPU, and an audio server.
  • the output of the broadband bus is connected to an audio collection device, and the audio collection is performed.
  • the output of the device is connected to the CPU, and the output of the CPU is connected to the audio server.
  • the data collected and processed by the FPGA logic must be read by the CPU into the system RAM, then processed by the CPU and sent to the audio collection server.
  • the audio collection device is implemented in the FPGA, receives the input of the broadband bus (the program-controlled switch platform definition bus), completes the acquisition and processing of the broadband bus data in the acquisition unit inside the audio collection device, and realizes the PCM audio collection function.
  • the audio data is collected under the control of the acquisition selection controller, and the data is compressed and sampled, and sent to the channel data register of the corresponding channel, and the channel data register is used as the first level buffer to copy the data to the collection processing after a preset period.
  • the audio data is dumped by the CPU reading, and the acquisition of the PCM audio is completed.
  • a PCM audio collection device based on FPGA, comprising an audio data acquisition module, an acquisition selection controller, a channel data register, a first dual port RAM and a second dual port RAM;
  • the audio data acquisition module is used in the acquisition selection controller Controlling, compressing and sampling data from the broadband bus to the channel data register of the corresponding channel;
  • the acquisition selection controller is configured to control the audio data acquisition module to collect the broadband bus data and forward the data to the channel data register;
  • the channel data register is used to buffer the multi-channel data, and the multi-channel data is written in two dual-port RAMs; the first dual-port RAM and the second dual-port RAM are interleaved and read channels The data, that is, when the first dual port RAM is written with data, the second dual port RAM is read out of data, and when the second dual port RAM is written with data, the first dual port RAM is read out of data.
  • the acquisition selection controller includes a clock module, 32 acquisition control registers, a 12-bit counter, and an equal comparator, and each of the acquisition control registers corresponds to control information of a call information that needs to be collected, and the control information includes Acquisition enable information, bus selection information, start time slot information, the audio data acquisition module includes a bus selector, a latch control register, and the clock module is configured to provide a clock signal for the 12-bit counter and the latch control register,
  • the bus selector selects to collect corresponding broadband bus data according to the bus selection information, and the start slot information and the 12-bit counter value are compared by the equal comparator, and then the control latch register samples the corresponding data of the broadband bus from the broadband bus to the channel.
  • the embodiment further includes an enable control signal, and the enable control signal and the signal output by the equal comparator are combined with the control latch register to sample the corresponding data of the wideband bus from the wideband bus into the channel data register.
  • the audio collection device collects the audio coded data on the broadband bus into the FPGA logic according to the configuration data.
  • the acquisition module uses 32 acquisition control registers, each of which corresponds to the relevant control information of the call information that needs to be collected, including the acquisition enable information, the bus selection information, and the start time slot information.
  • the channel's acquisition buffer registers are used to sample the audio coded data on the broadband bus into the FPGA logic according to the configuration data.
  • the channel data register includes 32 acquisition buffer registers (Reg0 to Reg31), and each acquisition buffer register is used to store data for buffering a preset period.
  • the device further includes a start control module, a self-locking counter, an address counter, and a multiplexer (32-select 1 multiplexer), and the start control module is configured to generate a start control pulse to the self-lock according to the clock signal.
  • a counter the self-locking counter is configured to generate an enable pulse to an address counter after receiving the start control pulse according to the clock signal, where the address counter is used to generate address information according to the clock signal and respectively provide the multiplexer, the first pair Port RAM and second dual port RAM, the input of the multiplexer is connected to the output of 32 acquisition buffer registers, and the outputs of the multiplexer are respectively connected to the first dual port RAM and the second pair Port RAM.
  • the collected data must be stored in the dual-port RAM so that the system can read data from it.
  • the system uses 2 pieces of 2K Byte's dual-port RAM, the combined data is written to the dual-port RAM and the read data from the dual-port RAM is alternately performed, and when the combined data is written to the first dual-port RAM, the read operation cannot be performed, but Another piece of dual-port RAM is read. Similarly, when reading one piece of dual-port RAM, it cannot be written, and only another piece of dual-port RAM can be written.
  • the useful time slot in the broadband bus is in the range of 0-2047. In this time range, it is possible to process the data of a certain channel, but in the time slot range after 2048, the data processing of all the channels has been completed, the system In this time range, the data in the temporary buffer register of the 32 channels is written into the dual port RAM, and the number of bytes written into the dual port RAM is 32 each time, so after every 64 writes (ie, 64 frames), The written dual-port RAM is full, then an interrupt flag is generated, and the write-select signal of the dual-port RAM is switched.
  • the clock signal is 19.44M clock signal
  • the self-locking counter counts from 0x00 to 0x20, when the count value reaches 0x20, the counter stops working, and restarts counting until receiving a start signal from the start control module
  • An enable pulse having a length of 32 19.44 M clock cycles is generated when the count value is between 0x00 and 0x1F, and the enable pulse is used to control the address counter to generate address information
  • the address counter is used to receive self-locking The address is incremented when the enable signal of the counter is valid; the address counter generates 12-bit address information, the lower 11-bit address information is the write address of the dual-port RAM, and the highest bit is used for the first dual-port RAM and the second dual-port RAM.
  • the chip select signal, the chip select signals Cs0/Cs1 of the two dual-port RAMs are always alternately valid.
  • the 19.44M clock signal is counted, and when the count reaches 2100, a pulse with a length of 19.44M clock cycle is generated.
  • the self-locking counter counts only from 0x00 to 0x20 (32). When the count reaches 0x20, the counter stops working and restarts counting until it receives a start signal from the start control module. Its initial value is 0x20. And when its count value is between 0x00 and 0x1F, an enable pulse having a length of 32 19.44M clock cycle width is generated, and the pulse signal is used to control the address counter to generate address information.
  • the address counter begins to increment the address when the enable signal from the self-locking counter is active, otherwise the address does not change.
  • the initial value is 0x0000; the address counter is 12 bits, the lower 11 bits address is the write address of the dual port RAM, the highest bit is used for the chip selection signal, and the chip select signals Cs0/Cs1 of the two dual port RAMs are always alternately valid.
  • the data written to the dual-port RAM varies according to the lowest five-bit address information, because the time for actually writing to the dual-port RAM is after 2100 time slots, at which time the data in the register is stable, and the data is guaranteed to be consistent with the address according to the address change. Sex.
  • the write enable WrEn of the dual port RAM is always valid. Because when writing at other times, the data of 0 channel is actually written continuously (the lowest five bits of the address are 0), and only the 0 channel data of the last write (when the time slot is 2100) can be saved in the dual port. In RAM, other data is invalid. The address and data at this time are stable data after the channel is collected. Therefore, even if the write enable is always valid, the written data will not be wrong.
  • the audio data acquisition module is controlled by the acquisition controller to collect the data of the broadband bus, and the data is compressed and sampled, and sent to the channel data register of the corresponding channel;
  • the acquisition selection controller in step S1 includes a clock module, 32 acquisition control registers, a 12-bit counter, and an equal comparator, and each of the acquisition control registers corresponds to control information of a call information that needs to be collected.
  • the control information includes acquisition enable information, bus selection information, and start time slot information
  • the audio data collection module includes a bus selector and a latch control register.
  • the step S1 specifically includes the sub-step: S11, the bus selector Selecting and collecting corresponding broadband bus data according to the bus selection information; S12, the start time slot information and the 12-bit counter value are compared by the equal comparator, and then the control latch register samples the corresponding data of the broadband bus from the broadband bus to the channel data register. .
  • the channel data register buffers the corresponding channel data into the two dual-port RAMs after the preset period
  • the step S2 specifically includes the sub-step: S21, the start control module generates a pulse having a length of 19.44 M clock cycle when the counter count reaches 2100; S22, the self-locking counter is The count is started after receiving the start signal from the start control module, the count range is from 0x00 to 0x20, and an enable pulse of 32 19.44M clock cycle width is generated when its count value is between 0x00 and 0x1F. The signal is used to control the address counter to generate address information. When the count value reaches 0x20, the counter stops working until the start signal is received from the start control module, and the counting is restarted; S23, the address counter is subjected to an enable signal from the self-locking counter.
  • the address counter When valid, the address is incremented, otherwise the address is unchanged.
  • the address counter generates 12-bit address information, the lower 11-bit address information is the write address of the dual-port RAM, and the highest bit is used for the first dual-port RAM and the second dual-port RAM.
  • the chip select signal, the chip select signals of the two dual-port RAMs are always alternately active (by the two dual-port RAM chip select signals being inverted for each other).
  • the step S3 specifically includes the sub-step: S31, the CPU reads data from the dual-port RAM by using an interrupt mode or a timing query manner; if the interrupt mode is used, after the FPGA logic generates an interrupt, the dual-port RAM is represented. Full, it can be read, and then the CPU directly reads the data; if the query mode is used, the interrupt enable bit of the interrupt status control register must be disabled first, and the double in the interrupt status control register must be determined before reading the data.
  • Port RAM status flag if the dual port RAM is full, the data can be read. Otherwise, the dual port RAM cannot be read.
  • the data collected and processed by the FPGA logic must be read by the CPU into the system RAM, and then processed by the CPU and sent to the audio collection server.
  • the CPU reads data from the dual-port RAM through the interrupt mode (when the full-port RAM is written, the hardware generates an interrupt flag) or the timing query mode. If the interrupt mode is used, after the FPGA logic generates an interrupt, the internal acquisition buffer (dual-port RAM) of the logic is full, it can be read, and then the CPU directly reads the data; if the query mode is used, the interrupt must be disabled first.
  • the interrupt enable bit of the status control register, and the buffer status flag in the interrupt status control register must be determined before reading the data. If the buffer is full, the data can be read. Otherwise, the buffer cannot be read.
  • the CPU reads 2K from the dual port RAM each time. Bytes of data, containing 32 channels, 64 bytes per channel. The read data is stored in the buffer in the system RAM space, and then the data of each channel is extracted and written into the buffer linked list of each channel.
  • the audio signal on the broadband bus is mainly collected, and after the signal is processed by the logic of the FPGA, the collected data is sent to the audio collection server, and the audio collection server realizes storage.
  • the FPGA in this scheme uses the XC2S200 of XILINX.
  • the audio collection server mainly records the data information of the call sent by the acquisition board (such as the call start time, the end time, the telephone number of the call party, etc.) and the voice information of both parties (the encoded voice signal), and then dispatched as needed. Or the relevant administrator to query and listen.

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Abstract

一种基于FPGA实现PCM音频采集的装置及方法。该方法首先采集宽带总线上的音频信号，采集的音频信号经过FPGA的逻辑处理后，被发送至音频采集服务器进行存储。该方法降低了录音系统组成的复杂度，系统容量大，具备32路采集能力，而且录音通道可复用，降低了系统的开发成本。

Description

一种基于FPGA实现PCM音频采集装置及系统及方法
技术领域
本发明涉及数字化音频采集领域，尤其涉及一种PCM音频采集装置及系统及方法。
背景技术
PCM：Pulse Code Modulation，脉冲编码调制。对于声音波形的处理通常采用的是脉冲代码调制编码，即PCM编码。PCM通过抽样、量化、编码三个步骤将连续变化的模拟信号转换为数字编码。
目前，市面上提供的录音系统通常是在电话线路上增加录音设备，对音频采集后在录音服务器上存储及供回放调听，该方案存在以下缺陷：
1.录音系统设备多，系统复杂；
2.录音通道功能单一，造成通道资源浪费；
3.且只能对固定线路进行录音，应用局限，系统容量小。
发明内容
为了解决上述技术问题，本发明的目的是提供一种低成本、高效率、大容量的音频采集装置及系统及方法。
本发明所采用的技术方案是：
一种基于FPGA实现PCM音频采集装置，包括音频数据采集模块、采集选择控制器、通道数据寄存器、第一双口RAM和第二双口RAM；所述音频数据采集模块用于在采集选择控制器的控制下，将来自宽带总线的数据压缩采样，送到对应通道的通道数据寄存器中；所述采集选择控制器用于控制音频数据采集模块采集宽带总线数据并将数据转送到通道数据寄存器；所述通道数据寄存器用于缓存多路通道数据，并将多路通道数据轮流写入到两个双口RAM中；所述第一双口RAM和第二双口RAM中交错被写入和读出通道数据，即当第一双口RAM被写入数据时，第二双口RAM被读出数据，当第二双口RAM被写入数据时，第一双口RAM被读出数据。
优选的，所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器，所述时钟模块用于为12位计数器和锁存控制寄存器提供时钟信号，所述总线选择器根据总线选择信息选择采集对应宽带总线数据，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
优选的，所述通道数据寄存器包括32个采集缓冲寄存器，每个采集缓冲寄存器用于存储用于缓存一路预先设定的周期的数据。
优选的，所述装置还包括开始控制模块、自锁计数器、地址计数器和多路选择器，所述开始控制模块用于根据时钟信号产生开始控制脉冲到自锁计数器，所述自锁计数器用于根据时钟信号在接收到开始控制脉冲后产生使能脉冲到地址计数器，所述地址计数器用于根据时钟信号产生地址信息分别提供给多路选择器、第一双口RAM和第二双口RAM，所述多路选择器的输入端连接到32个采集缓冲寄存器的输出端，所述多路选择器的输出端分别连接到第一双口RAM和第二双口RAM。
优选的，所述时钟信号为19.44M时钟信号，所述自锁计数器从0x00到0x20计数，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，所述使能脉冲用于控制地址计数器产生地址信息；所述地址计数器用于接收来自自锁计数器的使能信号有效时开始递加地址；所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号始终交替有效。
一种基于FPGA实现PCM音频采集系统，其包括宽带总线、音频采集装置、CPU、音频服务器，所述宽带总线的输出端与音频采集装置连接，所述音频采集装置的输出端与CPU连接，所述CPU的输出端与音频服务器连接。
一种基于FPGA实现PCM音频采集方法，其应用于音频采集系统，其特征在于，所述方法包括步骤：
S1，通过采集控制器控制音频数据采集模块采集宽带总线的数据，将数据压缩采样，送到对应通道的通道数据寄存器中；
S2，通道数据寄存器将对应通道数据缓存在预先设定的周期后将数据轮流写入到两个双口RAM中；
S3，通过CPU轮流读取两个双口RAM中音频数据，并转储到音频服务器中。
优选的，步骤S1中所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器；所述步骤S1具体包括子步骤：
S11，所述总线选择器根据总线选择信息选择采集对应宽带总线数据；
S12，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
优选的，所述步骤S2具体包括子步骤：
S21,所述开始控制模块在当12为计数器计数达到2100时产生一个长度为1个19.44M时钟周期宽度的脉冲；
S22，所述自锁计数器在收到来自开始控制模块的开始信号后开始计数，计数范围从0x00到0x20，并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，该脉冲信号用于控制地址计数器产生地址信息，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；
S23，所述地址计数器在受到来自自锁计数器的使能信号有效时开始递加地址，否则地址不变，所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号始终交替有效。
优选的，所述步骤S3具体包括子步骤：
S31，所述CPU通过中断方式或者定时查询方式从双口RAM中读取数据；如果使用中断方式，当FPGA逻辑产生中断之后，代表双口RAM已满，可以对其进行读操作，然后CPU直接读取数据；如果采用查询方式，必须首先禁止中断状态控制寄存器的中断使能位，并且在读取数据之前需要先判断中断状态控制寄存器中的双口RAM状态标志位，如果双口RAM满则可以读取数据，否则不能对双口RAM进行读操作。
本发明的有益效果是：
本发明主要完成采集宽带总线上的音频信号，采集信号经FPGA的逻辑处理后，将采集到的数据发送到音频采集服务器，音频采集服务器实现存储。本发明降低录音系统组成的复杂度、而且录音通道可复用，降低系统成本，系统容量大，具备32路采集能力，具有良好的经济和社会效益。
本发明可广泛应用于各种PCM音频采集系统。
附图说明
下面结合附图对本发明的具体实施方式作进一步说明：
图1是本发明装置一种实施例的逻辑框图；
图2是本发明装置中采集通道一种实施例的工作原理图；
图3是本发明装置中采集通道数据写入双口RAM一种实施例的逻辑图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本设计中音频采集以已有的程控交换机平台提供音频采集功能模块为例。程控交换机提供一致的卡槽，接入需要的板卡，音频采集存在于采集板上，系统支持插入多块采集板，提供基于32路采集和32路放音倍数能力的应用需求。
单纯从设计发明的音频采集模块，其设计原理具有通用性，不受限制于任何应用平台，为便于介绍设计发明的原理，我们以在程控交换机平台实现的场景进行说明。
如图1至图3所示，一种基于FPGA实现PCM音频采集系统，其包括宽带总线、音频采集装置、CPU、音频服务器，所述宽带总线的输出端与音频采集装置连接，所述音频采集装置的输出端与CPU连接，所述CPU的输出端与音频服务器连接。经过FPGA逻辑采集和处理之后的数据必须由CPU读取到系统RAM中，然后由CPU处理之后发送到音频采集服务器。
其中，音频采集装置在FPGA内部实现，接收宽带总线（程控交换机平台定义总线）的输入，在音频采集装置内部的采集单元中完成宽带总线数据的采集处理，实现PCM音频采集功能。其中，音频数据采集在采集选择控制器的控制下，将数据压缩采样，送到对应通道的通道数据寄存器中，通道数据寄存器作为一级缓存在预先设定的周期后将数据复制到采集处理的双口RAM中，通过CPU的读取将音频数据转储，完成对PCM音频的采集。
一种基于FPGA实现PCM音频采集装置，包括音频数据采集模块、采集选择控制器、通道数据寄存器、第一双口RAM和第二双口RAM；所述音频数据采集模块用于在采集选择控制器的控制下，将来自宽带总线的数据压缩采样，送到对应通道的通道数据寄存器中；所述采集选择控制器用于控制音频数据采集模块采集宽带总线数据并将数据转送到通道数据寄存器；所述通道数据寄存器用于缓存多路通道数据，并将多路通道数据轮流写入到两个双口RAM中；所述第一双口RAM和第二双口RAM中交错被写入和读出通道数据，即当第一双口RAM被写入数据时，第二双口RAM被读出数据，当第二双口RAM被写入数据时，第一双口RAM被读出数据。
优选的，所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器，所述时钟模块用于为12位计数器和锁存控制寄存器提供时钟信号，所述总线选择器根据总线选择信息选择采集对应宽带总线数据，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。该实施例中还包括使能控制信号，所述使能控制信号和相等比较器输出的信号进行与运算后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
其中，如图2所示，音频采集装置根据配置数据将宽带总线上音频编码数据采集到FPGA逻辑内部, 采集模块使用32个采集控制寄存器，每个寄存器对应1路需要采集的通话信息的相关控制信息，包括采集使能信息、总线选择信息、起始时隙信息。系统内存在一个12位计数器，该计数器计数值与32个控制寄存器内的总线起始时隙进行比较，如果相等，则指定总线上连续两个时隙的数据被采样到FPGA逻辑内部相应的32个通道的采集缓冲寄存器中。
优选的，所述通道数据寄存器包括32个采集缓冲寄存器（Reg0～Reg31），每个采集缓冲寄存器用于存储用于缓存一路预先设定的周期的数据。
优选的，所述装置还包括开始控制模块、自锁计数器、地址计数器和多路选择器（32选1多路选择器），所述开始控制模块用于根据时钟信号产生开始控制脉冲到自锁计数器，所述自锁计数器用于根据时钟信号在接收到开始控制脉冲后产生使能脉冲到地址计数器，所述地址计数器用于根据时钟信号产生地址信息分别提供给多路选择器、第一双口RAM和第二双口RAM，所述多路选择器的输入端连接到32个采集缓冲寄存器的输出端，所述多路选择器的输出端分别连接到第一双口RAM和第二双口RAM。
其中，采集到的数据必须被存入双口RAM，以便系统从中读取数据。系统使用2片2K Byte的双口RAM，合路数据写入双口RAM以及从双口RAM中读数据分别交替进行，及当向第一片双口RAM写入合路数据时不能对其进行读操作，而是读取另外一片双口RAM，同样，读取其中一片双口RAM时也不能对其进行写操作，只能写入另外一片双口RAM。
宽带总线中有用时隙为0－2047范围之内，在此时间范围内有可能正对某通道的数据进行处理，但是在2048之后的时隙范围内，所有的通道的数据处理已经完成，系统在此时间范围内将32路通道的临时缓冲寄存器中的数据写入双口RAM，每次写入双口RAM的字节数为32，这样每写入64次以后（即64帧），被写入的双口RAM写满，这时便产生一个中断标志位，并且切换双口RAM的写入片选信号。
优选的，所述时钟信号为19.44M时钟信号，所述自锁计数器从0x00到0x20计数，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，所述使能脉冲用于控制地址计数器产生地址信息；所述地址计数器用于接收来自自锁计数器的使能信号有效时开始递加地址；所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号Cs0/Cs1始终交替有效。
其中，对19.44M时钟信号计数，当计数达到2100时便产生一个长度为1个19.44M时钟周期宽度的脉冲。
自锁计数器只从0x00到0x20（32个）计数，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数。其初始值为0x20。并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，该脉冲信号用于控制地址计数器产生地址信息。
地址计数器在来自自锁计数器的使能信号有效时开始递加地址，否则地址不变。其初始值为0x0000；地址计数器为12位，低11位地址为双口RAM的写地址，最高位用于芯片选择信号，两片双口RAM的片选信号Cs0/Cs1始终交替有效。
写入双口RAM的数据根据最低五位地址信息变化，因为真正写入双口RAM的时间在2100时隙以后，此时寄存器中的数据已经稳定，并且数据根据地址变化保证地址和数据的一致性。
该实施例中，双口RAM的写使能WrEn一直有效。因为在其它时间写时，实际上是不断写入0通道的数据（地址最低五位均为0），而只有最后一次写入（在时隙为2100时）的0通道数据才能保存在双口RAM中，其它数据均无效，此时的地址和数据均是该通道采集之后的稳定数据，因此，即使写使能一直有效，写入的数据也不会发生错误。
一种基于FPGA实现PCM音频采集方法，其应用于音频采集系统，其特征在于，所述方法包括步骤：
S1，通过采集控制器控制音频数据采集模块采集宽带总线的数据，将数据压缩采样，送到对应通道的通道数据寄存器中；
优选的，步骤S1中所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器；所述步骤S1具体包括子步骤：S11，所述总线选择器根据总线选择信息选择采集对应宽带总线数据；S12，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
S2，通道数据寄存器将对应通道数据缓存在预先设定的周期后将数据轮流写入到两个双口RAM中；
优选的，所述步骤S2具体包括子步骤：S21,所述开始控制模块在当12为计数器计数达到2100时产生一个长度为1个19.44M时钟周期宽度的脉冲；S22，所述自锁计数器在收到来自开始控制模块的开始信号后开始计数，计数范围从0x00到0x20，并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，该脉冲信号用于控制地址计数器产生地址信息，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；S23，所述地址计数器在受到来自自锁计数器的使能信号有效时开始递加地址，否则地址不变，所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号始终交替有效(通过两个双口RAM片选信号互为取反实现)。
S3，通过CPU轮流读取两个双口RAM中音频数据，并转储到音频服务器中。
优选的，所述步骤S3具体包括子步骤：S31，所述CPU通过中断方式或者定时查询方式从双口RAM中读取数据；如果使用中断方式，当FPGA逻辑产生中断之后，代表双口RAM已满，可以对其进行读操作，然后CPU直接读取数据；如果采用查询方式，必须首先禁止中断状态控制寄存器的中断使能位，并且在读取数据之前需要先判断中断状态控制寄存器中的双口RAM状态标志位，如果双口RAM满则可以读取数据，否则不能对双口RAM进行读操作。
其中，经过FPGA逻辑采集和处理之后的数据必须由CPU读取到系统RAM中，然后由CPU处理之后发送到音频采集服务器。
CPU通过中断方式（在写满一个双口RAM时有，硬件会产生一个中断标志位）或者定时查询方式从双口RAM中读取数据。如果使用中断方式，当FPGA逻辑产生中断之后，代表逻辑内部的采集缓冲区（双口RAM）已满，可以对其进行读操作，然后CPU直接读取数据；如果采用查询方式，必须首先禁止中断状态控制寄存器的中断使能位，并且在读取数据之前需要先判断中断状态控制寄存器中的缓冲区状态标志位，如果缓冲区满则可以读取数据，否则不能对缓冲区进行读操作。
CPU每次从双口RAM中读取2K 字节的数据，包含32个通道，每通道64字节。读取的数据存入系统RAM空间中缓冲区内，然后提取各个通道的数据并写入各个通道的缓冲链表中。
本发明中主要完成采集宽带总线上的音频信号，采集信号经FPGA的逻辑处理后，将采集到的数据发送到音频采集服务器，音频采集服务器实现存储。本方案中的FPGA选用的是XILINX的XC2S200。音频采集服务器主要记录采集板发送上来的通话的数据信息（譬如通话起始时间，结束时间，通话双方电话号码等）和通话双方的声音信息（经过编码之后的语音信号），然后根据需要由调度员或者相关管理员查询和调听。
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (10)

  1. 一种基于FPGA实现PCM音频采集装置，其特征在于，包括音频数据采集模块、采集选择控制器、通道数据寄存器、第一双口RAM和第二双口RAM；
    所述音频数据采集模块用于在采集选择控制器的控制下，将来自宽带总线的数据压缩采样，送到对应通道的通道数据寄存器中；
    所述采集选择控制器用于控制音频数据采集模块采集宽带总线数据并将数据转送到通道数据寄存器；
    所述通道数据寄存器用于缓存多路通道数据，并将多路通道数据轮流写入到两个双口RAM中；
    所述第一双口RAM和第二双口RAM中交错被写入和读出通道数据，即当第一双口RAM被写入数据时，第二双口RAM被读出数据，当第二双口RAM被写入数据时，第一双口RAM被读出数据。
  2. 根据权利要求1所述的一种基于FPGA实现PCM音频采集装置，其特征在于，所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器，所述时钟模块用于为12位计数器和锁存控制寄存器提供时钟信号，所述总线选择器根据总线选择信息选择采集对应宽带总线数据，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
  3. 根据权利要求2所述的一种基于FPGA实现PCM音频采集装置，其特征在于，其特征在于，所述通道数据寄存器包括32个采集缓冲寄存器，每个采集缓冲寄存器用于存储用于缓存一路预先设定的周期的数据。
  4. 根据权利要求3所述的一种基于FPGA实现PCM音频采集装置，其特征在于，所述装置还包括开始控制模块、自锁计数器、地址计数器和多路选择器，所述开始控制模块用于根据时钟信号产生开始控制脉冲到自锁计数器，所述自锁计数器用于根据时钟信号在接收到开始控制脉冲后产生使能脉冲到地址计数器，所述地址计数器用于根据时钟信号产生地址信息分别提供给多路选择器、第一双口RAM和第二双口RAM，所述多路选择器的输入端连接到32个采集缓冲寄存器的输出端，所述多路选择器的输出端分别连接到第一双口RAM和第二双口RAM。
  5. 根据权利要求4所述的一种基于FPGA实现PCM音频采集装置，其特征在于，所述时钟信号为19.44M时钟信号，所述自锁计数器从0x00到0x20计数，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，所述使能脉冲用于控制地址计数器产生地址信息；所述地址计数器用于接收来自自锁计数器的使能信号有效时开始递加地址；所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号始终交替有效。
  6. 一种基于FPGA实现PCM音频采集系统，其特征在于，其包括宽带总线、如权利要求1至5任一项所述的音频采集装置、CPU、音频服务器，所述宽带总线的输出端与音频采集装置连接，所述音频采集装置的输出端与CPU连接，所述CPU的输出端与音频服务器连接。
  7. 一种基于FPGA实现PCM音频采集方法，其应用于如权利要求6所述的音频采集系统，其特征在于，所述方法包括步骤：
    S1，通过采集控制器控制音频数据采集模块采集宽带总线的数据，将数据压缩采样，送到对应通道的通道数据寄存器中；
    S2，通道数据寄存器将对应通道数据缓存在预先设定的周期后将数据轮流写入到两个双口RAM中；
    S3，通过CPU轮流读取两个双口RAM中音频数据，并转储到音频服务器中。
  8. 根据权利要求7所述的一种基于FPGA实现PCM音频采集方法，其特征在于，步骤S1中所述采集选择控制器包括时钟模块、32个采集控制寄存器、12位计数器和相等比较器，所述每个采集控制寄存器对应一路需要采集的通话信息的控制信息，所述控制信息包括采集使能信息、总线选择信息、起始时隙信息，所述音频数据采集模块包括总线选择器、锁存控制寄存器；所述步骤S1具体包括子步骤：
    S11，所述总线选择器根据总线选择信息选择采集对应宽带总线数据；
    S12，所述起始时隙信息和12位计数器数值经过相等比较器比较后控制锁存寄存器从宽带总线中采样宽带总线的相应数据到通道数据寄存器中。
  9. 根据权利要求8所述的一种基于FPGA实现PCM音频采集方法，其特征在于，所述步骤S2具体包括子步骤：
    S21,所述开始控制模块在当12为计数器计数达到2100时产生一个长度为1个19.44M时钟周期宽度的脉冲；
    S22，所述自锁计数器在收到来自开始控制模块的开始信号后开始计数，计数范围从0x00到0x20，并且在其计数值为0x00到0x1F之间时产生一个长度为32个19.44M时钟周期宽度的使能脉冲，该脉冲信号用于控制地址计数器产生地址信息，当计数值达到0x20计数器停止工作，直到收到来自开始控制模块的开始信号后重新开始计数；
    S23，所述地址计数器在受到来自自锁计数器的使能信号有效时开始递加地址，否则地址不变，所述地址计数器产生12位地址信息，低11位地址信息为双口RAM的写地址，最高位用于第一双口RAM和第二双口RAM的片选信号，两个双口RAM的片选信号始终交替有效。
  10. 根据权利要求9所述的一种基于FPGA实现PCM音频采集方法，其特征在于，所述步骤S3具体包括子步骤：
    S31，所述CPU通过中断方式或者定时查询方式从双口RAM中读取数据；如果使用中断方式，当FPGA逻辑产生中断之后，代表双口RAM已满，可以对其进行读操作，然后CPU直接读取数据；如果采用查询方式，必须首先禁止中断状态控制寄存器的中断使能位，并且在读取数据之前需要先判断中断状态控制寄存器中的双口RAM状态标志位，如果双口RAM满则可以读取数据，否则不能对双口RAM进行读操作。
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