WO2017141811A1 - 保護回路、および保護回路の動作方法、および半導体集積回路装置 - Google Patents
保護回路、および保護回路の動作方法、および半導体集積回路装置 Download PDFInfo
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- WO2017141811A1 WO2017141811A1 PCT/JP2017/004743 JP2017004743W WO2017141811A1 WO 2017141811 A1 WO2017141811 A1 WO 2017141811A1 JP 2017004743 W JP2017004743 W JP 2017004743W WO 2017141811 A1 WO2017141811 A1 WO 2017141811A1
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- nmos transistor
- power supply
- protection circuit
- zener diode
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims description 16
- 230000001681 protective effect Effects 0.000 title abstract description 7
- 230000015556 catabolic process Effects 0.000 claims abstract description 23
- 230000002441 reversible effect Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 230000006378 damage Effects 0.000 claims description 19
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 11
- 230000003068 static effect Effects 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 2
- 229910052744 lithium Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/003—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to reversal of power transmission direction
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
- H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
- H02H11/003—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection using a field effect transistor as protecting element in one of the supply lines
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0034—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using reverse polarity correcting or protecting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/042—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage comprising means to limit the absorbed power or indicate damaged over-voltage protection device
Definitions
- the present embodiment relates to a protection circuit, an operation method of the protection circuit, and a semiconductor integrated circuit device.
- IC integrated circuit
- in-vehicle IC a protection function is required to prevent the IC from being destroyed even when the in-vehicle battery is reversely connected.
- an external diode is generally used as a reverse connection measure.
- This embodiment provides a protection circuit capable of protecting a semiconductor integrated circuit from destruction due to reverse connection of an external power supply and capable of reducing the applied voltage, and a method for operating the protection circuit.
- This embodiment provides a protection circuit and a semiconductor integrated circuit device that can protect a semiconductor integrated circuit from electrostatic breakdown and can also protect the semiconductor integrated circuit from breakdown due to reverse connection of an external power supply.
- a semiconductor integrated circuit connected to a power supply terminal to which a predetermined power supply voltage is supplied from an external power supply, and the external power supply connected to the semiconductor integrated circuit to the power supply terminal And a switch for preventing energization of the semiconductor integrated circuit at the time of reverse connection, and a protection circuit for protecting the semiconductor integrated circuit from destruction.
- a method for operating a protection circuit that protects a semiconductor integrated circuit connected to a power supply terminal to which a predetermined power supply voltage is supplied from an external power supply, from being destroyed.
- a method of operating a protection circuit is provided in which a current path between a ground terminal and the power supply terminal is interrupted by a switch when the external power supply is reversely connected to the terminal.
- the clamp circuit unit is connected to the clamp circuit unit inserted between the power supply terminal and the ground terminal, and when the external power supply is reversely connected to the power supply terminal, There is provided a protection circuit as described above that protects against destruction.
- the protection circuit for protecting a semiconductor integrated circuit connected between a power supply terminal to which a predetermined power supply voltage is supplied from an external power supply and a ground terminal from electrostatic breakdown. A semiconductor integrated circuit device is provided.
- the present embodiment it is possible to provide a protection circuit capable of protecting a semiconductor integrated circuit from destruction due to reverse connection of an external power supply and capable of reducing the applied voltage, and a method for operating the protection circuit.
- a protection circuit and a semiconductor integrated circuit device that can protect the semiconductor integrated circuit from electrostatic breakdown and can also protect the semiconductor integrated circuit from breakdown due to reverse connection of an external power supply.
- FIG. 2 is a circuit configuration diagram illustrating a specific example of the protection circuit illustrated in FIG. 1.
- FIG. 3 is a circuit configuration diagram showing a specific example of the high-side switch shown in FIGS. 1 and 2.
- FIG. 1 A schematic configuration of an in-vehicle IC (integrated circuit) on which the protection circuit according to this embodiment can be mounted is expressed as shown in FIG.
- FIG. 1 A schematic configuration of an in-vehicle IC on which a protection circuit according to a comparative example can be mounted is expressed as shown in FIG.
- the in-vehicle IC on which the protection circuit according to this embodiment can be mounted includes a high-side switch 10 as a semiconductor integrated circuit connected to the power supply terminal 102 and an external power supply as shown in FIG. And a protection circuit 12 that prevents energization of the high-side switch 10 when a vehicle battery (not shown) is reversely connected.
- the protection circuit 12 includes a semiconductor integrated circuit (high-side switch) 10 connected to a power supply terminal 102 to which a predetermined power supply voltage is supplied from an external power supply, and a semiconductor integrated circuit.
- a switch MT1 that is connected to the circuit 10 and prevents energization of the semiconductor integrated circuit 10 when an external power supply is reversely connected to the power supply terminal 102 is provided to protect the semiconductor integrated circuit 10 from destruction.
- the semiconductor integrated circuit 10 is a high-side switch (10) provided with an N-type semiconductor substrate (N-sub), and the external power source is an in-vehicle battery.
- the high side switch 10 is provided between a vehicle battery (power supply terminal 102) and a load (corresponding to 100 in FIG. 3) connected to the output terminal 104.
- the high-side switch 10 has, for example, a power supply voltage (applied voltage) VBB from an in-vehicle battery as an operating voltage in response to the supply of a high level signal (control signal) to the input terminal (IN) 106, and an output terminal (OUT). Output from 104.
- the general high-side switch 10 is used for protection against static electricity (ESD: Electro Static Static Discharge), for example, by a surge current absorbing clamp circuit (described later) inserted between a power supply terminal 102 and a ground (GND) terminal.
- ESD Electro Static Static Discharge
- the switch 10 is protected from failure or destruction against overcurrent.
- the high-side switch 10 may include a functional block for protecting against breakdown or destruction when an output negative voltage is detected.
- the protection circuit 12 is a circuit for preventing the high-side switch 10 from being destroyed even when the in-vehicle battery is reversely connected to the power supply terminal 102. Although details will be described later, the protection circuit 12 is grounded at the time of reverse connection.
- an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) MT1 that functions as a switch for cutting off a current path between the terminal and the power supply terminal 102 is provided.
- the vehicle-mounted battery supplies a power supply voltage VBB of about 12V to 14V from the power supply terminal 102 at normal times.
- the in-vehicle battery is reversely connected so that the power supply voltage VBB to be applied to the power supply terminal 102 is erroneously applied to the ground terminal side.
- the protection circuit 12 blocks the current path from the ground terminal side to the power supply terminal side to prevent the high-side switch 10 from being destroyed.
- the in-vehicle IC according to the comparative example is a current limiting circuit between the high side switch 10 and the ground terminal as a protection circuit for protecting the high side switch 10 as shown in FIG.
- a resistance element 20 and a voltage clamping diode 22 are connected in parallel.
- the circuit current flowing in the in-vehicle IC and the resistance value of the resistance element 20 (for example, about 100 ⁇ ) Accordingly, since the GND potential rises, the applied voltage range is narrow and is not suitable for lowering the applied voltage.
- the protection circuit 12 can reduce the on-resistance of the switch by adopting the MOSFET, so that the applied voltage can be easily lowered. .
- the in-vehicle IC on which the protection circuit 12 according to the present embodiment can be mounted employs a so-called N-sub that employs a semiconductor substrate (N-sub) whose conductivity type is N-type. Formed by the process.
- FIG. 2 shows a configuration example of the protection circuit 12 according to the present embodiment, which can be applied to an in-vehicle IC.
- the protection circuit 12 includes N-channel MOSFETs (MOS transistors) MT1, MT2, MT3, and MT4, and a zener diode ZD1 for withstand voltage clamping.
- MOS transistors MT1, MT2, and MT3 may constitute an output negative voltage protection (hereinafter referred to as NVP (Negative Voltage Protection)) circuit 14.
- NVP Negative Voltage Protection
- the MOS transistors MT1 and MT2 are for high voltage (HV), and both are constituted by enhancement type N-channel MOSFETs (E-NMOS transistors).
- the MOS transistor MT3 is for low voltage (LV)
- the MOS transistor MT4 is for HV, both of which are constituted by a depletion type N-channel MOSFET (D-NMOS transistor).
- the D-NMOS transistor MT4 may be replaced by a resistance element (resistor).
- the protection circuit 12 includes a first D-NMOS transistor MT4 having a drain (D) connected to the power supply terminal 102, and a gate (G) and a source (S) of the first D-NMOS transistor MT4.
- a second E-NMOS transistor (switch) MT1 having a drain connected to the ground terminal and a source connected to the ground connection terminal GND_REF of the high-side switch 10, and a gate of the first D-NMOS transistor MT4
- a third E-NMOS transistor MT2 having a gate connected to the source, a drain connected to the ground terminal, and a drain connected to the back gate (B) which is the body terminal of the second E-NMOS transistor MT1;
- the gate and source of the second E-NMOS transistor MT1 are backed up.
- a fourth D-NMOS transistor MT3 connected to the gate, a drain connected to the source of the second E-NMOS transistor MT1, an anode connected to the source of the second E-NMOS transistor MT1, and a cathode connected to the first And a Zener diode ZD1 connected to the gate and source of one D-NMOS transistor MT4.
- the switch MT1 has a gate connected to the gate and source of the first NMOS transistor MT4 whose drain is connected to the power supply terminal 102, a drain connected to the ground terminal, and a source connected to the semiconductor integrated circuit (high-side switch )
- a second NMOS transistor MT1 connected to the transistor 10.
- the back gate (B) of the second NMOS transistor MT1 has a gate connected to the gate and source of the first NMOS transistor MT4 and a third NMOS transistor MT2 whose source is connected to the ground terminal.
- the drain is connected to the gate and source of the fourth NMOS transistor MT3 whose drain is connected to the source of the second NMOS transistor MT1.
- the E-NMOS transistor MT1 is turned on / off in accordance with the state of the vehicle-mounted battery, the gate voltage is pulled up to the power supply voltage VBB.
- the gate voltage of the E-NMOS transistor MT1 becomes equal to or higher than a predetermined voltage (drain voltage + Vth), and the E-NMOS transistor MT2 is turned on. To do.
- the back gate of the E-NMOS transistor MT1 becomes the same potential as the drain, and the E-NMOS transistor MT1 is turned on (the source and drain are short-circuited).
- the gate voltage of the E-NMOS transistor MT1 becomes lower than a predetermined voltage, and the E-NMOS transistor MT2 is turned off. Then, the D-NMOS transistor MT3 causes the back gate of the E-NMOS transistor MT1 to have the same potential as the source, so that the E-NMOS transistor MT1 is turned off.
- the E-NMOS transistor MT2 or D-NMOS connected to the back gate of the E-NMOS transistor MT1 in the NVP circuit 14 in accordance with the connection state of the on-vehicle battery.
- One of the transistors MT3 is selectively turned on.
- the D-NMOS transistor MT3 is selectively turned on and the E-NMOS transistor MT1 is turned off.
- the current path from the ground terminal (drain) side to the power supply terminal (source) 102 side is cut off, and energization to the high-side switch 10 is blocked.
- FIG. 3 shows an example of the configuration of the high-side switch 10.
- the high-side switch 10 includes a PMOS transistor (first PMOS transistor) 108, a Zener diode 110, an OSC (Oscillator) 112, a charge pump (CP) 114, and gate drive circuits (DRV) 116 and 120.
- PMOS transistor first PMOS transistor
- Zener diode 110 an OSC (Oscillator) 112
- CP charge pump
- DDRV gate drive circuits
- the Zener diode 110, OSC (oscillation circuit) 112, CP (boost circuit) 114, and DRV 116 may constitute the drive control unit 140 of the NMOS transistor 118.
- the high side switch 10 may include a power supply terminal (VBB) 102, an output terminal (OUT) 104, and an input terminal (IN) 106.
- the fifth NMOS transistor 118 is connected between the power supply terminal 102 and the output terminal 104 to which a load to which an operating voltage is to be supplied is connected.
- the drive control unit 140 is connected to the gate of the fifth NMOS transistor 118.
- the sixth NMOS transistor 122 is provided between the drive control unit 140 and the input terminal 106 to which a control signal is input, and the source is connected to the protection circuit (switch) 12 via the ground connection terminal GND_REF.
- the negative voltage control unit 126 is provided between the sixth NMOS transistor 122 and the drive control unit 140.
- the first PMOS transistor MT4 is provided between the drive control unit 140 and the power supply terminal 102, and a control signal is input to the gate.
- the clamp circuit 130 is provided between the power supply terminal 102 and the gate of the fifth NMOS transistor 118.
- a predetermined power supply voltage VBB (for example, about 14 V) is applied to the power supply terminal 102 as an applied voltage from a vehicle-mounted battery (not shown) during normal operation.
- the power supply terminal 102 is connected to the source of the PMOS transistor 108 and the drain of the NMOS transistor 118.
- a high-level control signal for setting the high-side switch 10 to an enable state is supplied to the input terminal 106 from an external control circuit (not shown).
- the external control circuit may be configured by, for example, an ECU (Engine Control Unit).
- the DRV 120 is connected to the gate of the PMOS transistor 108 and the gate of the MOS transistor 122.
- the source of the NMOS transistor 122 is connected to the protection circuit 12 via the ground connection terminal GND_REF, and the drain is connected to the negative voltage control unit 126.
- the NMOS transistor 122 includes a body diode 124 between the source and the drain.
- the protection circuit 12 By connecting the protection circuit 12 to the ground connection terminal GND_REF, the ground of the high-side switch 10 becomes the ground of the protection circuit 12.
- the DRV 120 supplies a high level output voltage to the gate of the NMOS transistor 122 and supplies a low level output voltage to the gate of the PMOS transistor 108 when the signal of the input terminal 106 is high level.
- the DRV 120 supplies a low-level output voltage to the gate of the NMOS transistor 122 and supplies a high-level output voltage to the gate of the PMOS transistor 108 when the signal at the input terminal 106 is low level.
- the gate of the PMOS transistor 108 is at a low level, the PMOS transistor 108 is turned on, the gate of the NMOS transistor 122 is at a high level, and the NMOS transistor 122 is also turned on.
- the gate of the PMOS transistor 108 is at high level, the PMOS transistor 108 is off, the gate of the NMOS transistor 122 is at low level, and the NMOS transistor 122 is also off.
- the PMOS transistor 108 is turned on and the NMOS transistor 122 is also turned on.
- the PMOS transistor 108 When the signal at the input terminal 106 of the DRV 120 is at a low level, the PMOS transistor 108 is turned off and the NMOS transistor 122 is also turned off.
- the negative voltage control unit 126 is a functional block for protecting the high-side switch 10 from destruction when an output negative voltage is detected.
- the negative voltage control unit 126 includes MOS transistors MT1, MT2, and MT3. It may have the same configuration as the NVP circuit 14.
- a Zener diode 110 Between the negative voltage control unit 126 and the drain of the PMOS transistor 108, a Zener diode 110, an OSC 112, and a CP 114 constituting the drive control unit 140 are connected in parallel. Further, the DR 114 of the drive control unit 140 is connected to the CP 114, and the gate and source of the NMOS transistor 118 and the output terminal 104 are connected to the DRV 116. That is, the DRV (drive circuit) 116 is connected between the OSC (boost circuit) 112 and the gate of the fifth NMOS transistor 118 and the output terminal 104. The DRV 116 outputs the input as it is without inverting the input.
- the drive control unit 140 supplies the voltage boosted by the CP 114 to the DRV 116 based on the oscillation output of the OSC 112, thereby turning on the NMOS transistor 118.
- the oscillation output of the OSC 112 and the degree of boosting of the CP 114 may be determined by the Zener diode 110.
- a clamp circuit 130 is connected between the gate of the NMOS transistor 118 and the power supply terminal 102.
- the clamp circuit 130 is an ESD protection device for absorbing a surge current. Further, the clamp circuit 130 temporarily clamps the gate voltage when the NMOS transistor 118 is driven, thereby preventing the operating voltage supplied from the output terminal 104 from drastically decreasing (for example, about ⁇ 30V). ing.
- the load 100 is connected to the output terminal 104.
- electronic parts such as various in-vehicle accessories that operate by supplying an operating voltage corresponding to the power supply voltage VBB are assumed.
- the negative voltage control unit 126 is provided, so that the high side switch 10 is destroyed even when an output negative voltage is detected except when the vehicle battery is reversely connected. Can be protected from.
- FIG. 4 is a diagram schematically showing a part of the element structure in the protection circuit 12 according to the embodiment, and is a diagram for explaining the operation of the protection circuit 12.
- FIG. At the time of connection, (b) corresponds to the case of reverse connection of the vehicle battery.
- FIGS. 4A and 4B only the cross-sectional structure of the E-NMOS transistor MT2 is illustrated for convenience.
- the operation of the protection circuit 12 is an operation for protecting the semiconductor integrated circuit 10 connected to the power supply terminal 102 to which a predetermined power supply voltage is supplied from an external power supply from being destroyed.
- the switch MT1 is a MOS transistor (MT1), and the MOS transistor (MT1) is turned off when an external power supply is reversely connected to the power supply terminal 102 to prevent the semiconductor integrated circuit 10 from being energized.
- the switch MT1 has a gate connected to the gate and source of a depletion type first NMOS transistor MT4 whose drain is connected to the power supply terminal 102, a drain connected to the ground terminal, and a source connected to the semiconductor integrated circuit 10.
- An enhanced second NMOS transistor may be used.
- the back gate of the second NMOS transistor MT1 is connected to the gate and source of the first NMOS transistor MT4, and the enhancement type third NMOS transistor MT2 whose source is connected to the ground terminal.
- the third NMOS transistor MT2 and the fourth NMOS transistor MT3 connected to the back gate of the second NMOS transistor MT1 are connected to the power supply terminal 102 from the third NMOS transistor MT2 when the external power supply is reversely connected.
- the protection circuit 12 includes an N + type semiconductor substrate 30, an N type semiconductor layer 32 formed on the N + type semiconductor substrate 30, and a high voltage P formed on the N type semiconductor layer 32.
- a gate electrode 40G is provided on the P-type well region 34 via a gate oxide film. The gate electrode 40G is connected to the gate and source of the D-NMOS transistor MT4.
- N + -type diffusion regions 36S and 42D and a P + -type diffusion region 46B are formed on the surface of the P-type well region 34.
- the N + type diffusion region 36S is connected to the ground terminal and the drain of the E-NMOS transistor MT1 via the source electrode 38S.
- the N + type diffusion region 42D is connected to the source of the E-NMOS transistor MT1 via the drain electrode 44D and the D-NMOS transistor MT3 (not shown).
- the P + -type diffusion region 46B is connected to the back gate of the E-NMOS transistor MT1 through the back gate electrode 48B.
- a back electrode 50 to which the power supply voltage VBB is applied is provided.
- the protection circuit 12 having such a configuration can be formed on an N-type semiconductor substrate (N-sub) on which the high-side switch 10 is formed. That is, the first NMOS transistor MT4, the second NMOS transistor MT1, the third NMOS transistor MT2, and the fourth NMOS transistor MT3 can be formed on an N-type semiconductor substrate (N-sub).
- the N + type diffusion region 36S and the P + type diffusion region 46B are connected via the back gate of the E-NMOS transistor MT1 as the E-NMOS transistor MT2 is turned on. Connected to the ground terminal. As a result, the E-NMOS transistor MT1 is turned on and the source and the drain are short-circuited, whereby the high-side switch 10 can be energized by the E-NMOS transistor MT1.
- the power supply voltage VBB is applied to the N + type diffusion region 36S as shown in FIG. MT2 is turned off, and accordingly, the back gate of the E-NMOS transistor MT1 is connected to the source via the D-NMOS transistor MT3.
- the current path for energizing the high-side switch 10 is interrupted by turning off the E-NMOS transistor MT1.
- the high-side switch 10 can be prevented from being destroyed even when the vehicle-mounted battery is reversely connected.
- the E-NMOS transistor MT2 normally connected to the back gate of the E-NMOS transistor MT1 is switched to the D-NMOS transistor MT3 when the battery is reversely connected.
- the E-NMOS transistor MT1 can be turned off to cut off the current path from the ground terminal side to the power supply terminal 102 side. Therefore, even when a predetermined power supply voltage VBB is applied to the terminal G102 from the vehicle-mounted battery, the high-side switch 10 can be prevented from being destroyed.
- the E-NMOS transistor MT1 can be turned on / off according to the selection of the back gate (selection of the NMOS transistors MT2 and MT3), the on-resistance of the switch can be reduced.
- the on-resistance can be reduced as compared with the case where a resistance element is used, so the setting of the applied voltage range is expanded. become able to. Therefore, the applied voltage can be easily lowered, and for example, a microcomputer having an operating voltage of 5V (hereinafter referred to as a microcomputer) can be switched to a 3.3V microcomputer.
- the protection circuit according to the present embodiment is not limited to an in-vehicle IC, and can be used for all ICs to which an external power source is connected.
- various storage batteries represented by lithium batteries are used as an external power source. It can be widely applied to various fields to be used.
- a protection circuit capable of protecting a semiconductor integrated circuit from destruction due to reverse connection of an external power supply and a voltage applied to the circuit can be reduced, and a method for operating the protection circuit is provided. it can.
- the ESD protection device 130 is inserted, for example, between the power supply terminal 102 and the ground terminal, and an ESD clamp circuit as an original clamp circuit for protecting the high-side switch 10 from electrostatic breakdown.
- the protection circuit unit 88 may be the protection circuit 12 illustrated in FIG. 1A, FIG. 2, FIG. 4, etc.
- the protection circuit 12 includes, for example, a power supply terminal 102, a ground terminal, and the like.
- the ESD clamp circuit unit 131 is connected to the power supply terminal 102 so that the ESD clamp circuit unit 131 is protected from destruction (as a protection circuit unit 88) when the external power supply is reversely connected to the power supply terminal 102. .
- the electrostatic protection device 130 includes a semiconductor integrated circuit (high-side switch) 10 (FIG. 1A) connected between a power supply terminal 102 to which a predetermined power supply voltage is supplied from an external power supply and a ground terminal. 3, FIG. 4), a clamp circuit portion 131 inserted between the power supply terminal 102 and the ground terminal, and connected to the clamp circuit portion 131 so that the external power supply to the power supply terminal 102 is reversely connected.
- a protection circuit unit 88 that protects the clamp circuit unit 131 from destruction, and protects the semiconductor integrated circuit 10 from electrostatic breakdown.
- the semiconductor integrated circuit 10 is a high-side switch (10) including an N-type semiconductor substrate (N-sub).
- the ESD clamp circuit unit 131 is provided in the high side switch 10.
- the ESD clamp circuit unit 131 absorbs a surge current.
- the ESD clamp circuit unit 131 includes an NMOS transistor 84, first to ninth Zener diodes 80 1 , 80 2 , 80 3, ... 80 9 and a tenth Zener diode 81 connected in series, and a resistance element. 82 and eleventh and twelfth Zener diodes 86 1 and 86 2 connected in series. That is, the ESD clamp circuit unit 131 includes an NMOS transistor 84 whose drain is connected to the power supply terminal 102, a first Zener diode 80 1 whose cathode is connected to the drain of the NMOS transistor 84, and a first Zener diode 80 1.
- a second Zener diode 80 2 having a cathode connected to the anode thereof, a third Zener diode 80 3 having a cathode connected to the anode of the second Zener diode 80 2, and an anode of the third Zener diode 80 3 in a fourth Zener diode 80 4 having a cathode connected, a fifth Zener diode 80 5 having a cathode connected to the anode of the fourth Zener diode 80 4, the cathode to the anode of the fifth Zener diode 80 5
- a sixth Zener diode 80 6 connected to Sixth and seventh Zener diode 80 7 of the cathode to the anode of the Zener diode 80 6 is connected to a Zener diode 80 8 eighth having a cathode connected to the anode of a seventh Zener diode 80 7, 8 a ninth zener diode 80 9 Zener diode 80 8 cathode to the anode
- the first to ninth Zener diodes 80 1 , 80 2 , 80 3, ... 80 9 are in the same direction, and the tenth Zener diode 81 is the first to ninth Zener diodes 80 1.
- 80 2 , 80 3, ... 80 9 are connected in different directions.
- the anode of the ninth Zener diode 809 and the anode of the tenth Zener diode 81 are connected, and the power supply terminal 102 is connected to the cathode of the first Zener diode 801, so that the tenth Zener
- the gate of the NMOS transistor 84 (G) is connected to the cathode of the diode 81.
- the power supply terminal 102 is connected to the drain (D) of the NMOS transistor 84, and the protection circuit unit 88 is connected in series to the source (S).
- a resistance element 82 and eleventh and twelfth Zener diodes 86 1 and 86 2 are connected between the gate and source of the NMOS transistor 84.
- the eleventh and twelfth Zener diodes 86 1 and 86 2 are connected in the same direction, with the cathode of the eleventh Zener diode 86 1 being the gate of the NMOS transistor 84 and the anode of the twelfth Zener diode 86 2 being the anode.
- Each is connected to the source of the NMOS transistor 84.
- the protection circuit unit 88 has a configuration in which a plurality of (for example, three) Zener diodes 88 1 , 88 2, and 88 3 are connected in series.
- the Zener diodes 88 1 , 88 2, and 88 3 may be configured by, for example, bipolar transistors (npn transistors) in which the base (B) and the collector (C) are connected. That is, the protection circuit unit 88 may be configured by a series stage of a plurality of bipolar transistors in which a plurality of Zener diodes 88 1 , 88 2, and 88 3 are short-circuited at the base and collector.
- the protection circuit unit 88 is set so that the reverse breakdown voltage by the Zener diodes 88 1 , 88 2, and 88 3 is set to be equal to or higher than the power supply voltage VBB (for example, about 24 V) of the vehicle battery (external power supply).
- VBB the power supply voltage of the vehicle battery (external power supply).
- the NMOS transistor 84 can be prevented from being destroyed when the battery for battery is reversely connected.
- the protection circuit unit 88 in which the Zener diodes 88 1 , 88 2, and 88 3 are connected in series so that the reverse breakdown voltage is equal to or higher than the battery voltage (VBB) in series with the ESD clamp circuit unit 131,
- the body diode (not shown) of the NMOS transistor 84 existing from the terminal side toward the power supply terminal 102 side can be protected from destruction due to reverse connection of the in-vehicle battery.
- the protection circuit unit 88 can be formed on an N-type semiconductor substrate (N-sub).
- Zener diode 80 1, 80 2, 80 3 ... 80 9 - 81 - 86 1 - 86 2 was configured from the npn transistor can be protected from breakdown due to the reverse connection of the vehicle battery.
- the electrostatic protection device 130 can not only protect the high-side switch 10 from electrostatic breakdown by a relatively simple configuration in which the protection circuit unit 88 is added to the existing clamp circuit, but also by reverse connection of the in-vehicle battery.
- the high side switch 10 can be protected from destruction.
- the circuit configuration of the protection circuit unit 88 is represented as shown in FIG. 6A, and the schematic cross-sectional structure of the protection circuit unit 88 is represented as shown in FIG.
- the protection circuit unit 88 forms Zener diodes 88 1 , 88 2, and 88 3 together with, for example, the ESD clamp circuit unit 131 on the N + type semiconductor substrate 30 on which the protection circuit 12 is formed. It is also good to include.
- the Zener diodes 88 1 , 88 2, and 88 3 of the protection circuit unit 88 are formed on the N-type semiconductor layer 32 formed on the N + -type semiconductor substrate 30 and on the surface portion of the N-type semiconductor layer 32, respectively. have been a P-type well region 52, the N + -type diffusion region 54E and the P + -type diffusion region 54B formed in a surface portion of the P-type well region 52, formed on the surface portion of the N-type semiconductor layer 32 N + And a mold diffusion region 54C.
- the N + -type diffusion region 54C is taken out via the collector electrode 56C and becomes the collector of each Zener diode 88 1 , 88 2 , 88 3 .
- the N + -type diffusion regions 54E are taken out through the emitter electrode 56E and become the emitters of the respective Zener diodes 88 1 , 88 2, and 88 3 .
- the P + -type diffusion regions 54B are respectively taken out via the base electrodes 56B and become the bases of the Zener diodes 88 1 , 88 2, and 88 3 .
- the base electrode 56B and the collector electrode 56C are connected to each other via the connection electrode 56T.
- the base and collector of the Zener diode 88 1 is connected to the ESD clamp circuit 131, the emitter of the Zener diode 88 1 is connected to the base and collector of the Zener diode 88 2, an emitter of the Zener diode 88 2, Zener is connected to the base and collector of the diode 88 3, the emitter of the Zener diode 88 3, for example, is connected to the ground terminal, N + -type semiconductor substrate 30 protective circuit section 88 can be mounted on is formed.
- the circuit configuration of the NMOS transistor 84 is expressed as shown in FIG. 7A, and the schematic cross-sectional structure of the NMOS transistor 84 is shown in FIG. It is expressed as shown in (b).
- the NMOS transistor 84 may be formed on the N + type semiconductor substrate 30 on which the protection circuit 12 is formed, for example, as a part of the ESD clamp circuit unit 131.
- the NMOS transistor 84 includes an N-type semiconductor layer 32 formed on the N + -type semiconductor substrate 30, a P-type well region 52 formed on the surface of the N-type semiconductor layer 32, and a P-type well region 52.
- the gate electrode 64G is connected to the source of the NMOS transistor 84, the cathode of the tenth Zener diode 81, and the like.
- N + -type diffusion region 60S is connected to protection circuit unit 88 via source electrode 62S.
- N + -type diffusion region 60D is connected to power supply terminal 102 via drain electrode 62D.
- P + -type diffusion region 60B is connected to source electrode 62S through back gate electrode 62B.
- the high-side switch 10 can be prevented from being broken even when the in-vehicle battery is reversely connected.
- the protection circuit unit 88 set so that the reverse withstand voltage is equal to or higher than the power supply voltage VBB of the vehicle-mounted battery is connected in series to the ESD clamp circuit unit 131.
- the high-side switch 10 can be protected from damage due to static electricity
- the NMOS transistor 84 which is an ESD protection element for protecting the static electricity, can be protected from being destroyed when the on-vehicle battery is reversely connected.
- the protection circuit portion that constitutes a part of the electrostatic protection device according to this embodiment can be applied to various ICs that require ESD protection between the power supply terminal and the ground terminal.
- it can be used not only for in-vehicle ICs but also for all ICs to which an external power supply is connected, and particularly widely applied to various fields in which various storage batteries represented by lithium batteries are used as external power supplies. Is possible.
- a semiconductor integrated circuit device (not shown) according to the present embodiment includes a semiconductor integrated circuit (high-side switch) 10 (connected between a power supply terminal 102 to which a predetermined power supply voltage is supplied from an external power supply and a ground terminal. 1 (a), FIG. 3, and FIG. 4) and an electrostatic protection device 130 (see FIGS. 5 to 6) that protects the semiconductor integrated circuit 10 from electrostatic breakdown.
- the electrostatic protection device 130 is connected to the ESD clamp circuit unit 131 and the ESD clamp circuit unit 131 inserted between the power supply terminal 102 and the ground terminal.
- a protection circuit unit 88 that protects the circuit unit 131 from destruction.
- the protection circuit unit 88 may be the protection circuit 12 illustrated in FIG. 1A, FIG. 2, FIG. 4, and the like. In that case, the semiconductor integrated circuit device according to the present embodiment (not shown).
- the semiconductor integrated circuit 10 is a high-side switch (10) including an N-type semiconductor substrate (N-sub).
- the ESD clamp circuit unit 131 is provided in the high side switch 10.
- the ESD clamp circuit unit 131 absorbs a surge current.
- the ESD clamp circuit 131 includes an NMOS transistor 84 having a drain connected to the power supply terminal 102, a first Zener diode 80 1 having a cathode connected to the drain of the NMOS transistor 84, and a first Zener diode 80 1.
- a second Zener diode 80 2 having a cathode connected to the anode thereof, a third Zener diode 80 3 having a cathode connected to the anode of the second Zener diode 80 2, and an anode of the third Zener diode 80 3 in a fourth Zener diode 80 4 having a cathode connected, a fifth Zener diode 80 5 having a cathode connected to the anode of the fourth Zener diode 80 4, the cathode to the anode of the fifth Zener diode 80 5 6 and Zener diode 80 6, 6 but connected Zener seventh Zener diode 80 7 of the diode 80 6 cathode to the anode of which is connected, with the eighth Zener diode 80 8 having a cathode connected to the anode of a seventh Zener diode 80 7, 8 Zener of A ninth Zener diode 80 9 whose cathode is connected to the anode of the diode 80
- Zener diode 80 10 resistance element 82 connected between the gate and source of NMOS transistor 84, eleventh Zener diode 80 11 whose cathode is connected to the gate of NMOS transistor 84, and eleventh Zener diode 80 11 the cathode is connected to the anode of the And a second Zener diode 80 12.
- the protection circuit unit 88 is connected in series to the source (S) of the NMOS transistor 84.
- the protection circuit unit 88 has a configuration in which a plurality of (for example, three) Zener diodes 88 1 , 88 2, and 88 3 are connected in series. Further, the protection circuit unit 88 is set so that the reverse breakdown voltage by the plurality of Zener diodes 88 1 , 88 2, and 88 3 is equal to or higher than the power supply voltage VBB (for example, about 24 V) of the vehicle battery (external power supply). .
- VBB power supply voltage
- the protection circuit unit 88 is constituted by a series stage of a plurality of bipolar transistors in which a plurality of Zener diodes 88 1 , 88 2, and 88 3 are short-circuited at the base and collector.
- protection circuit unit 88 can be formed on an N-type semiconductor substrate (N-sub).
- the semiconductor integrated circuit can be protected from electrostatic breakdown, and the semiconductor integrated circuit can be protected from breakdown due to reverse connection of an external power supply, and the electrostatic protection apparatus is provided.
- a semiconductor integrated circuit can be provided.
- the protection circuit according to this embodiment can be applied to an in-vehicle IC. Further, such a protection circuit can be used other than an in-vehicle IC, and in particular, can be applied to various semiconductor integrated circuits having a possibility that an external power supply is reversely connected.
- the electrostatic protection device according to this embodiment can be applied to an in-vehicle IC. Further, such an electrostatic protection device can be used other than an in-vehicle IC, and in particular, can be applied to various semiconductor integrated circuits having a possibility that an external power source is reversely connected.
- PMOS transistor 110 Zener diode 112 ... OSC (oscillation circuit) 114 ... Charge pump (boost circuit) 116, 120, gate drive 118, 122, NMOS transistor 124, body diode 126, negative voltage control unit 130, clamp circuit 131, ESD clamp circuit unit 140, drive control unit VBB, power supply voltage (applied voltage) MT1... E-N channel type MOSFET (second NMOS transistor, switch that cuts off the current path) MT2 ... E-N channel type MOSFET (third NMOS transistor) MT3 ... DN channel type MOSFET (fourth NMOS transistor) MT4... DN channel type MOSFET (first NMOS transistor) ZD1 ... Zener diode G102 ... terminal GND_REF ... ground connection terminal
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Abstract
Description
本実施の形態に係る保護回路を搭載可能な車載用IC(集積回路)の概略構成は、図1(a)に示すように表される。なお、比較例に係る保護回路を搭載可能な車載用ICの概略構成は、図1(b)に示すように表される。
図4は、実施の形態に係る保護回路12における素子構造の一部を模式的に示すと共に、保護回路12の動作を説明するために示す図であって、(a)は車載用バッテリの通常接続時に、(b)は車載用バッテリの逆接続時に、それぞれ対応する。ただし、図4(a),(b)では、便宜上、E-NMOSトランジスタMT2の断面構造のみを例示している。
次に、本実施の形態に係る静電気保護装置130の構成について説明する。静電気保護装置130の具体的な回路構成は、図5に示すように表わされる。
本実施の形態に係る半導体集積回路装置(図示省略)は、外部電源から所定の電源電圧が供給される電源端子102とグランド端子との間に接続される半導体集積回路(ハイサイドスイッチ)10(図1(a)、図3、図4参照)と、半導体集積回路10を静電気破壊から保護する静電気保護装置130(図5~図6参照)とを備える。静電気保護装置130は、電源端子102とグランド端子との間に挿入されたESDクランプ回路部131と、ESDクランプ回路部131に接続されて、電源端子102への外部電源の逆接続時に、ESDクランプ回路部131を破壊から保護する保護回路部88とを有する。
上記のように、いくつかの実施の形態を記載したが、開示の一部をなす論述および図面は例示的なものであり、各実施の形態を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。このように、本実施の形態は、ここでは記載していない様々な形態などを含む。
12…保護回路
14…NVP回路
30…N+ 型半導体基板
32…N型半導体層
34…P型ウェル領域(HVPW)
36S・42D…N+ 型拡散領域
38S…ソース電極
40G…ゲート電極
44D…ドレイン電極
46B…P+ 型拡散領域
48B…バックゲート電極
50…裏面電極
52…P型ウェル領域
54B…P+ 型拡散領域
54C・54E…N+ 型拡散領域
56B…ベース電極
56C…コレクタ電極
56E…エミッタ電極
56T…接続電極
60B…P+ 型拡散領域
60D・60S…N+ 型拡散領域
62B…バックゲート電極
62D…ドレイン電極
62S…ソース電極
64G…ゲート電極
801 ・802 ・803 …809 …第1~第9のツェナーダイオード
81…第10のツェナーダイオード
82…抵抗素子
84…NMOSトランジスタ
861 ・862 …第11・第12のツェナーダイオード
88…保護回路部
881 ・882 ・883 …ツェナーダイオード(npnトランジスタ)
100…負荷
102…電源端子
104…出力端子(OUT)
106…入力端子(IN)
108…PMOSトランジスタ
110…ツェナーダイオード
112…OSC(発振回路)
114…チャージポンプ(昇圧回路)
116・120…ゲートドライブ
118・122…NMOSトランジスタ
124…ボディダイオード
126…負電圧制御部
130…クランプ回路
131…ESDクランプ回路部
140…駆動制御部
VBB…電源電圧(印加電圧)
MT1…E-Nチャネル型MOSFET(第2のNMOSトランジスタ、電流経路を遮断するスイッチ)
MT2…E-Nチャネル型MOSFET(第3のNMOSトランジスタ)
MT3…D-Nチャネル型MOSFET(第4のNMOSトランジスタ)
MT4…D-Nチャネル型MOSFET(第1のNMOSトランジスタ)
ZD1…ツェナーダイオード
G102…端子
GND_REF…グランド接続用端子
Claims (26)
- 外部電源から所定の電源電圧が供給される電源端子に接続された半導体集積回路と、
前記半導体集積回路に接続されて、前記電源端子への前記外部電源の逆接続時に、前記半導体集積回路への通電を阻止するスイッチと
を備え、
前記半導体集積回路を破壊から保護することを特徴とする保護回路。 - 前記スイッチは、グランド端子側から前記電源端子側への電流経路を遮断するMOSトランジスタを備えることを特徴とする請求項1に記載の保護回路。
- 前記スイッチは、前記電源端子にドレインが接続された第1のNMOSトランジスタのゲートおよびソースにゲートが接続され、ドレインがグランド端子に接続され、ソースが前記半導体集積回路に接続された第2のNMOSトランジスタであって、
前記第2のNMOSトランジスタのバックゲートには、前記第1のNMOSトランジスタの前記ゲートおよび前記ソースにゲートが接続され、ソースが前記グランド端子に接続された第3のNMOSトランジスタのドレイン、およびドレインが前記第2のNMOSトランジスタの前記ソースに接続された第4のNMOSトランジスタのゲートおよびソースが接続されていることを特徴とする請求項2に記載の保護回路。 - 前記第1のNMOSトランジスタおよび前記第4のNMOSトランジスタは、デプレッション型のNチャネル型MOSFETであり、前記第2のNMOSトランジスタおよび前記第3のNMOSトランジスタは、エンハンスメント型のNチャネル型MOSFETであることを特徴とする請求項3に記載の保護回路。
- 前記第2のNMOSトランジスタ、前記第3のNMOSトランジスタ、および前記第4のNMOSトランジスタによって、出力負電圧保護回路が構成されてなることを特徴とする請求項3または4に記載の保護回路。
- 前記第1のNMOSトランジスタは、抵抗体によって代用可能であることを特徴とする請求項3~5のいずれか1項に記載の保護回路。
- 前記外部電源が、車載用バッテリであることを特徴とする請求項1~6のいずれか1項に記載の保護回路。
- 前記半導体集積回路が、N型半導体基板を備えたハイサイドスイッチであることを特徴とする請求項1~7のいずれか1項に記載の保護回路。
- 前記ハイサイドスイッチは、
前記電源端子と動作電圧を供給すべき負荷が接続される出力端子との間に接続された第5のNMOSトランジスタと、
前記第5のNMOSトランジスタのゲートに接続された駆動制御部と、
前記駆動制御部と制御信号が入力される入力端子との間に設けられ、ソースがグランド接続用端子を介して前記スイッチに接続される第6のNMOSトランジスタと、
前記第6のNMOSトランジスタと前記駆動制御部との間に設けられた負電圧制御部と、
前記駆動制御部と前記電源端子との間に設けられ、ゲートに前記制御信号が入力される第1のPMOSトランジスタと、
前記電源端子と前記第5のNMOSトランジスタのゲートとの間に設けられたクランプ回路と
を備えることを特徴とする請求項8に記載の保護回路。 - 前記駆動制御部は、
前記第1のPMOSトランジスタと前記負電圧制御部との間に並列に接続されたダイオード、発振回路、および昇圧回路と、
前記昇圧回路と前記第5のNMOSトランジスタのゲートおよび前記出力端子との間に接続されたドライブ回路と
を備えることを特徴とする請求項9に記載の保護回路。 - 前記第1のNMOSトランジスタ、前記第2のNMOSトランジスタ、前記第3のNMOSトランジスタ、および前記第4のNMOSトランジスタが、前記N型半導体基板上に形成されてなることを特徴とする請求項8に記載の保護回路。
- 外部電源から所定の電源電圧が供給される電源端子に接続される半導体集積回路を破壊から保護する保護回路の動作方法であって、
前記電源端子への前記外部電源の逆接続時に、スイッチによってグランド端子と前記電源端子との間の電流経路を遮断することを特徴とする保護回路の動作方法。 - 前記スイッチは、MOSトランジスタであって、
前記MOSトランジスタが、前記電源端子への前記外部電源の逆接続時にオフされて、前記半導体集積回路への通電を阻止することを特徴とする請求項12に記載の保護回路の動作方法。 - 前記スイッチは、
前記電源端子にドレインが接続されたデプレッション型の第1のNMOSトランジスタのゲートおよびソースにゲートが接続され、ドレインがグランド端子に接続され、ソースが前記半導体集積回路に接続されたエンハンスメント型の第2のNMOSトランジスタであって、
前記第2のNMOSトランジスタのバックゲートには、
前記第1のNMOSトランジスタの前記ゲートおよび前記ソースにゲートが接続され、ソースが前記グランド端子に接続されたエンハンスメント型の第3のNMOSトランジスタのドレイン、およびドレインが前記第2のNMOSトランジスタの前記ソースに接続されたデプレッション型の第4のNMOSトランジスタのゲートおよびソースが接続されると共に、
前記第2のNMOSトランジスタのバックゲートに接続された前記第3のNMOSトランジスタおよび前記第4のNMOSトランジスタが、前記電源端子への前記外部電源の逆接続時に、前記第3のNMOSトランジスタから前記第4のNMOSトランジスタに切り換えられることを特徴とする請求項12または13に記載の保護回路の動作方法。 - 前記電源端子とグランド端子との間に挿入されたクランプ回路部
に接続されて、前記電源端子への前記外部電源の逆接続時に、前記クランプ回路部を破壊から保護する請求項1に記載の保護回路。 - 前記外部電源が、車載用バッテリであることを特徴とする請求項15に記載の保護回路。
- 前記半導体集積回路が、N型半導体基板を備えたハイサイドスイッチであることを特徴とする請求項15または16に記載の保護回路。
- 前記クランプ回路部は、前記ハイサイドスイッチ内に設けられることを特徴とする請求項17に記載の保護回路。
- 前記クランプ回路部は、サージ電流を吸収することを特徴とする請求項18に記載の保護回路。
- 前記クランプ回路部は、
前記電源端子にドレインが接続されたNMOSトランジスタと、
前記NMOSトランジスタの前記ドレインにカソードが接続された第1のツェナーダイオードと、
前記第1のツェナーダイオードのアノードにカソードが接続された第2のツェナーダイオードと、
前記第2のツェナーダイオードのアノードにカソードが接続された第3のツェナーダイオードと、
前記第3のツェナーダイオードのアノードにカソードが接続された第4のツェナーダイオードと、
前記第4のツェナーダイオードのアノードにカソードが接続された第5のツェナーダイオードと、
前記第5のツェナーダイオードのアノードにカソードが接続された第6のツェナーダイオードと、
前記第6のツェナーダイオードのアノードにカソードが接続された第7のツェナーダイオードと、
前記第7のツェナーダイオードのアノードにカソードが接続された第8のツェナーダイオードと、
前記第8のツェナーダイオードのアノードにカソードが接続された第9のツェナーダイオードと、
前記第9のツェナーダイオードのアノードにアノードが接続され、カソードが前記NMOSトランジスタのゲートに接続された第10のツェナーダイオードと、
前記NMOSトランジスタの前記ゲートとソースとの間に接続された抵抗素子と、
前記NMOSトランジスタの前記ゲートにカソードが接続された第11のツェナーダイオードと、
前記第11のツェナーダイオードのアノードにカソードが接続された第12のツェナーダイオードと
を備えることを特徴とする請求項19に記載の保護回路。 - 前記保護回路部は、前記NMOSトランジスタの前記ソースに直列に接続されることを特徴とする請求項15~20のいずれか1項に記載の保護回路。
- 前記保護回路部は、複数のツェナーダイオードが直列に接続された構成を備えることを特徴とする請求項21に記載の保護回路。
- 前記保護回路部は、前記複数のツェナーダイオードによる逆耐圧が、前記外部電源の電源電圧以上となるように設定されることを特徴とする請求項22に記載の保護回路。
- 前記保護回路部は、前記複数のツェナーダイオードがベース・コレクタを短絡した複数のバイポーラトランジスタの直列段によって構成されていることを特徴とする請求項22または23に記載の保護回路。
- 前記保護回路部は、前記N型半導体基板上に形成されてなることを特徴とする請求項17に記載の保護回路。
- 外部電源から所定の電源電圧が供給される電源端子とグランド端子との間に接続される半導体集積回路を静電気破壊から保護する請求項15~25のいずれか1項に記載の保護回路を有することを特徴とする半導体集積回路装置。
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