WO2017128470A1 - 一种基于栅极驱动电路及其液晶显示器 - Google Patents

一种基于栅极驱动电路及其液晶显示器 Download PDF

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Publication number
WO2017128470A1
WO2017128470A1 PCT/CN2016/074558 CN2016074558W WO2017128470A1 WO 2017128470 A1 WO2017128470 A1 WO 2017128470A1 CN 2016074558 W CN2016074558 W CN 2016074558W WO 2017128470 A1 WO2017128470 A1 WO 2017128470A1
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Prior art keywords
switch tube
type switch
control
transmission end
signal
Prior art date
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Ceased
Application number
PCT/CN2016/074558
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/023,380 priority Critical patent/US9906222B2/en
Publication of WO2017128470A1 publication Critical patent/WO2017128470A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a liquid crystal display thereof.
  • Gate Driver On Array is a technology that uses the existing thin film transistor liquid crystal display Array process to make the Gate scan drive signal circuit on the Array substrate to realize the drive mode of Gate progressive scan.
  • the module design of the GOA function including: Latch latch unit, for the latching of the level signal, is the core part of the GOA circuit design, mainly composed of two clocked inverters and two inverters;
  • the NAND gate signal processing unit performs NAND processing by the CK control signal line and the latched data for generating the control terminal driving signal of the current stage;
  • the output Buffer of the CMOS circuit is used for increasing the driving capability of the control terminal driving signal, Reduce the RC of the transmitted signal Loading.
  • the circuit connection manner of the above two modules is relatively simple, wherein the first and second transistors need to bear different degrees of Stress during long-term operation, so the degree of variation of the first and second transistors is also different.
  • This transistor non-uniformity may cause variations in signal latching and NAND gate logic errors, which can affect the normal operation of the circuit and cause the entire circuit to fail.
  • the technical problem to be solved by the present invention is to provide a gate driving circuit and a liquid crystal display thereof, which can effectively improve the uniformity of circuit design and the stability of circuit operation.
  • a technical solution adopted by the present invention is to provide a gate driving circuit including: an input and a latch circuit, a signal processing circuit electrically connected to the input and latch circuit, and an electrical connection signal.
  • An output buffer circuit of the processing circuit including:
  • the input and latch circuit outputs a first control signal according to the upper scan driving signal, the first clock signal, and the second clock signal inverted from the first clock signal, and the signal processing circuit outputs the second according to the first control signal and the third clock signal a control signal, the output buffer circuit outputs a scan drive signal of the current stage according to the second control signal;
  • the input and latch circuit or the signal processing circuit comprises two switch components arranged in parallel, wherein each switch component comprises two switch tubes arranged in series, and two switch tubes of one switch assembly of the two switch components are controlled The end is cross-connected with the control ends of the two switch tubes of the other switch assembly of the two switch assemblies.
  • the input and latch circuit includes: a first clocked inverter, a second clocked inverter, and a first inverter, wherein the positive phase control terminal of the first clocked inverter is connected to the first clock signal,
  • the inverting control end of the first clocked inverter is connected to the second clock signal, the input of the first clocked inverter is connected to the upper scan driving signal, and the output of the first clocked inverter is connected to the second clock Controlling the output end of the inverter, the positive phase control end of the second clock control inverter is connected to the second clock signal, and the inverting control end of the second clock control inverter is connected to the first clock signal, the first inversion
  • the input end of the first clock control inverter is connected to the output end of the second clock control inverter, and the output end of the first inverter is connected to the input end of the second clock control inverter, and the output is a control signal, wherein at least one of the first clocked
  • the output buffer circuit includes an odd number of second inverters connected in series, and an input end of the second inverter close to the signal processing circuit is connected to the second control signal, and is output from the second inverter output terminal of the signal processing circuit. This level scans the drive signal.
  • the present invention also adopts a technical solution of providing a gate driving circuit including: an input and a latch circuit, a signal processing circuit electrically connecting the input and the latch circuit, and an electrical connection signal processing.
  • a gate driving circuit including: an input and a latch circuit, a signal processing circuit electrically connecting the input and the latch circuit, and an electrical connection signal processing.
  • Output buffer circuit of the circuit including: an input and a latch circuit, a signal processing circuit electrically connecting the input and the latch circuit, and an electrical connection signal processing.
  • the input and latch circuit outputs a first control signal according to the upper scan driving signal, the first clock signal, and the second clock signal inverted from the first clock signal, and the signal processing circuit outputs the second according to the first control signal and the third clock signal a control signal, the output buffer circuit outputs a scan drive signal of the current stage according to the second control signal;
  • the input and latch circuit or the signal processing circuit comprises two switch components arranged in parallel, wherein each switch component comprises two switch tubes arranged in series, and two switch tubes of one switch assembly of the two switch components are controlled The end is cross-connected with the control ends of the two switch tubes of the other switch assembly of the two switch assemblies.
  • the input and latch circuit includes: a first clocked inverter, a second clocked inverter, and a first inverter, wherein the positive phase control terminal of the first clocked inverter is connected to the first clock signal,
  • the inverting control end of the first clocked inverter is connected to the second clock signal, the input of the first clocked inverter is connected to the upper scan driving signal, and the output of the first clocked inverter is connected to the second clock Controlling the output end of the inverter, the positive phase control end of the second clock control inverter is connected to the second clock signal, and the inverting control end of the second clock control inverter is connected to the first clock signal, the first inversion
  • the input end of the first clock control inverter is connected to the output end of the second clock control inverter, and the output end of the first inverter is connected to the input end of the second clock control inverter, and the output is a control signal, wherein at least one of the first clocked
  • the first clocked inverter includes a first P-type switch tube, a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a first N-type switch tube, and a second N-type switch a tube, a third N-type switch tube, and a fourth N-type switch tube;
  • the control end of the first P-type switch tube is connected to the control end of the fourth P-type switch tube, and is connected to the second clock signal, and the control end of the second P-type switch tube is connected to the control end of the fourth P-type switch tube And accessing the upper-level scan driving signal, the first transmission end of the first P-type switch tube and the first transmission end of the third P-type switch tube are connected to the high reference potential, and the first transmission end of the second P-type switch tube is The second transmission end of the first P-type switch tube is connected, the first transmission end of the fourth P-type switch tube is connected to the second transmission end of the third P-type switch tube, and the second transmission of the second P-type switch tube is connected.
  • the second transmission end of the terminal and the fourth P-type switch tube are connected to the output end of the first clocked inverter;
  • the control end of the first N-type switch tube is connected to the control end of the fourth N-type switch tube, and is connected to the upper scan drive signal, and the second N-type switch tube is connected to the control end of the third N-type switch tube, and Accessing the first clock signal, the first transmission end of the second N-type switch tube and the first transmission end of the fourth N-type switch tube are connected to a low reference potential, and the first transmission end and the second end of the first N-type switch tube
  • the second transmission end of the N-type switch tube is connected, the first transmission end of the third N-type switch tube is connected to the second transmission end of the fourth N-type switch tube, and the second transmission end of the first N-type switch tube is The second transmission end of the fourth N-type switch is connected to the output of the first clocked inverter.
  • the second clock control inverter comprises a fifth P-type switch tube, a sixth P-type switch tube, a seven-P-type switch tube, an eighth P-type switch tube, a fifth N-type switch tube, and a sixth N-type switch tube. a seventh N-type switch tube and an eighth N-type switch tube;
  • the control end of the fifth P-type switch tube is connected with the control end of the eighth P-type switch tube, and is connected to the first control signal, and the control end of the sixth P-type switch tube and the control end of the seventh P-type switch tube Connected to and connected to the first clock signal, wherein the first transmission end of the fifth P-type switch tube and the first transmission end of the seventh P-type switch tube are connected to the high reference point, and the fifth P-type switch tube is The second transmission end is connected to the first transmission end of the sixth P-type switch tube, the first transmission end of the eighth P-type switch tube is connected to the second transmission end of the seventh P-type switch tube, and the eighth P-type switch tube is connected The second transmission end and the second transmission end of the sixth P-type switch tube are connected to the output end of the second clock control inverter;
  • the control end of the fifth N-type switch tube is connected to the control end of the eighth N-type switch tube, and is connected to the second clock signal, and the control end of the sixth N-type switch tube and the control end of the seventh N-type switch tube are Connecting and accessing the first control signal, the first transmission end of the sixth N-type switch tube and the first transmission end of the eighth N-type switch tube are connected to the low reference potential, and the first transmission end of the fifth N-type switch tube Connected to the second transmission end of the sixth N-type switch tube, the second transmission end of the eighth N-type switch tube is connected to the first transmission end of the seventh N-type switch tube, and the second transmission end of the fifth N-type switch tube And connecting a second transmission end of the seventh N-type switch to the output of the second clocked inverter.
  • the signal processing circuit is a NAND gate, the first input end of the NAND gate circuit is connected to the first control signal, the second input end of the NAND gate circuit is connected to the third clock signal, and the output end of the NAND gate circuit is outputted.
  • the second control signal, the NAND circuit includes two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit comprises a ninth P-type switch tube, a tenth P-type switch tube, a ninth N-type switch tube, a tenth N-type switch tube, an eleventh N-type switch tube, and a twelfth N-type switch tube;
  • the control end of the ninth P-type switch tube is connected to the first control signal, the control end of the tenth P-type switch tube is connected to the third clock signal, and the first transmission end of the ninth P-type switch tube and the tenth P-type switch tube
  • the first transmission end is connected to the high reference potential, the second transmission of the ninth P-type switch tube and the second transmission end of the tenth P-type switch tube are connected to the output end of the NAND gate;
  • the control end of the ninth N-type switch tube is connected with the control end of the twelfth N-type switch tube, and is connected to the first control signal, and the control end of the tenth N-type switch tube and the control of the eleventh N-type switch tube
  • the terminal phase is connected, and the third clock signal is connected, the first input end of the tenth N-type switch tube and the first input end of the twelfth N-type switch tube are connected to the low reference potential, and the ninth N-type switch tube is connected a transmission end is connected to the second transmission end of the tenth N-type switch tube, and the first transmission end of the eleventh N-type switch tube is connected to the second transmission end of the twelfth N-type switch tube, and the ninth N type switch
  • the second output of the tube and the second output of the eleventh N-type switch are connected to the output of the NAND gate.
  • the signal processing circuit is a NAND gate
  • the first input end of the NAND gate circuit is connected to the first control signal
  • the second input end of the NAND gate circuit is connected to the third clock signal
  • the output end of the NAND gate circuit A second control signal is output, the NAND gate circuit comprising two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit includes a first P-type switch tube, a second P-type switch tube, a first N-type switch tube, a second N-type switch tube, a third N-type switch tube, and a fourth N-type switch tube;
  • the control end of the first P-type switch tube is connected to the first control signal
  • the control end of the second P-type switch tube is connected to the third clock signal
  • the first transmission end of the first P-type switch tube and the second P-type switch tube The first transmission end is connected to the high reference potential
  • the second transmission of the first P-type switch tube and the second transmission end of the second P-type switch tube are connected to the output end of the NAND gate;
  • the control end of the first N-type switch tube is connected to the control end of the fourth N-type switch tube, and is connected to the first control signal, and the control end of the second N-type switch tube and the control end of the third N-type switch tube Connecting, and accessing the third clock signal, the first input end of the second N-type switch tube and the first input end of the fourth N-type switch tube are connected to the low reference potential, and the first transmission end of the first N-type switch tube Connected to the second transmission end of the second N-type switch tube, the first transmission end of the third N-type switch tube is connected to the second transmission end of the fourth N-type switch tube, and the second output of the first N-type switch tube
  • the second output end of the third N-type switch tube is connected to the output end of the NAND gate.
  • the output buffer circuit includes an odd number of second inverters connected in series, and an input end of the second inverter close to the signal processing circuit is connected to the second control signal, and is output from the second inverter output terminal of the signal processing circuit. This level scans the drive signal.
  • the present invention further provides a liquid crystal display comprising a plurality of gate drive circuits arranged in cascade, the gate drive circuit comprising: an input and a latch circuit, and a signal electrically connecting the input and the latch circuit Processing circuitry and an output buffer circuit electrically coupled to the signal processing circuit;
  • the input and latch circuit outputs a first control signal according to the upper scan driving signal, the first clock signal, and the second clock signal inverted from the first clock signal, and the signal processing circuit outputs the second according to the first control signal and the third clock signal a control signal, the output buffer circuit outputs a scan drive signal of the current stage according to the second control signal;
  • the input and latch circuit or the signal processing circuit comprises two switch components arranged in parallel, wherein each switch component comprises two switch tubes arranged in series, and two switch tubes of one switch assembly of the two switch components are controlled The end is cross-connected with the control ends of the two switch tubes of the other switch assembly of the two switch assemblies.
  • the input and latch circuit includes: a first clocked inverter, a second clocked inverter, and a first inverter, wherein the positive phase control terminal of the first clocked inverter is connected to the first clock signal,
  • the inverting control end of the first clocked inverter is connected to the second clock signal, the input of the first clocked inverter is connected to the upper scan driving signal, and the output of the first clocked inverter is connected to the second clock Controlling the output end of the inverter, the positive phase control end of the second clock control inverter is connected to the second clock signal, and the inverting control end of the second clock control inverter is connected to the first clock signal, the first inversion
  • the input end of the first clock control inverter is connected to the output end of the second clock control inverter, and the output end of the first inverter is connected to the input end of the second clock control inverter, and the output is a control signal, wherein at least one of the first clocked
  • the first clocked inverter includes a first P-type switch tube, a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a first N-type switch tube, and a second N-type switch a tube, a third N-type switch tube, and a fourth N-type switch tube;
  • the control end of the first P-type switch tube is connected to the control end of the fourth P-type switch tube, and is connected to the second clock signal, and the control end of the second P-type switch tube is connected to the control end of the fourth P-type switch tube And accessing the upper-level scan driving signal, the first transmission end of the first P-type switch tube and the first transmission end of the third P-type switch tube are connected to the high reference potential, and the first transmission end of the second P-type switch tube is The second transmission end of the first P-type switch tube is connected, the first transmission end of the fourth P-type switch tube is connected to the second transmission end of the third P-type switch tube, and the second transmission of the second P-type switch tube is connected.
  • the second transmission end of the terminal and the fourth P-type switch tube are connected to the output end of the first clocked inverter;
  • the control end of the first N-type switch tube is connected to the control end of the fourth N-type switch tube, and is connected to the upper scan drive signal, and the second N-type switch tube is connected to the control end of the third N-type switch tube, and Accessing the first clock signal, the first transmission end of the second N-type switch tube and the first transmission end of the fourth N-type switch tube are connected to a low reference potential, and the first transmission end and the second end of the first N-type switch tube
  • the second transmission end of the N-type switch tube is connected, the first transmission end of the third N-type switch tube is connected to the second transmission end of the fourth N-type switch tube, and the second transmission end of the first N-type switch tube is The second transmission end of the fourth N-type switch is connected to the output of the first clocked inverter.
  • the second clock control inverter comprises a fifth P-type switch tube, a sixth P-type switch tube, a seven-P-type switch tube, an eighth P-type switch tube, a fifth N-type switch tube, and a sixth N-type switch tube. a seventh N-type switch tube and an eighth N-type switch tube;
  • the control end of the fifth P-type switch tube is connected with the control end of the eighth P-type switch tube, and is connected to the first control signal, and the control end of the sixth P-type switch tube and the control end of the seventh P-type switch tube Connected to and connected to the first clock signal, wherein the first transmission end of the fifth P-type switch tube and the first transmission end of the seventh P-type switch tube are connected to the high reference point, and the fifth P-type switch tube is The second transmission end is connected to the first transmission end of the sixth P-type switch tube, the first transmission end of the eighth P-type switch tube is connected to the second transmission end of the seventh P-type switch tube, and the eighth P-type switch tube is connected The second transmission end and the second transmission end of the sixth P-type switch tube are connected to the output end of the second clock control inverter;
  • the control end of the fifth N-type switch tube is connected to the control end of the eighth N-type switch tube, and is connected to the second clock signal, and the control end of the sixth N-type switch tube and the control end of the seventh N-type switch tube are Connecting and accessing the first control signal, the first transmission end of the sixth N-type switch tube and the first transmission end of the eighth N-type switch tube are connected to the low reference potential, and the first transmission end of the fifth N-type switch tube Connected to the second transmission end of the sixth N-type switch tube, the second transmission end of the eighth N-type switch tube is connected to the first transmission end of the seventh N-type switch tube, and the second transmission end of the fifth N-type switch tube And connecting a second transmission end of the seventh N-type switch to the output of the second clocked inverter.
  • the signal processing circuit is a NAND gate
  • the first input end of the NAND gate circuit is connected to the first control signal
  • the second input end of the NAND gate circuit is connected to the third clock signal
  • the output end of the NAND gate circuit A second control signal is output, the NAND gate circuit comprising two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit comprises a ninth P-type switch tube, a tenth P-type switch tube, a ninth N-type switch tube, a tenth N-type switch tube, an eleventh N-type switch tube, and a twelfth N-type switch tube;
  • the control end of the ninth P-type switch tube is connected to the first control signal, the control end of the tenth P-type switch tube is connected to the third clock signal, and the first transmission end of the ninth P-type switch tube and the tenth P-type switch tube
  • the first transmission end is connected to the high reference potential, the second transmission of the ninth P-type switch tube and the second transmission end of the tenth P-type switch tube are connected to the output end of the NAND gate;
  • the control end of the ninth N-type switch tube is connected with the control end of the twelfth N-type switch tube, and is connected to the first control signal, and the control end of the tenth N-type switch tube and the control of the eleventh N-type switch tube
  • the terminal phase is connected, and the third clock signal is connected, the first input end of the tenth N-type switch tube and the first input end of the twelfth N-type switch tube are connected to the low reference potential, and the ninth N-type switch tube is connected a transmission end is connected to the second transmission end of the tenth N-type switch tube, and the first transmission end of the eleventh N-type switch tube is connected to the second transmission end of the twelfth N-type switch tube, and the ninth N type switch
  • the second output of the tube and the second output of the eleventh N-type switch are connected to the output of the NAND gate.
  • the signal processing circuit is a NAND gate
  • the first input end of the NAND gate circuit is connected to the first control signal
  • the second input end of the NAND gate circuit is connected to the third clock signal
  • the output end of the NAND gate circuit A second control signal is output, the NAND gate circuit comprising two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit includes a first P-type switch tube, a second P-type switch tube, a first N-type switch tube, a second N-type switch tube, a third N-type switch tube, and a fourth N-type switch tube;
  • the control end of the first P-type switch tube is connected to the first control signal
  • the control end of the second P-type switch tube is connected to the third clock signal
  • the first transmission end of the first P-type switch tube and the second P-type switch tube The first transmission end is connected to the high reference potential
  • the second transmission of the first P-type switch tube and the second transmission end of the second P-type switch tube are connected to the output end of the NAND gate;
  • the control end of the first N-type switch tube is connected to the control end of the fourth N-type switch tube, and is connected to the first control signal, and the control end of the second N-type switch tube and the control end of the third N-type switch tube Connecting, and accessing the third clock signal, the first input end of the second N-type switch tube and the first input end of the fourth N-type switch tube are connected to the low reference potential, and the first transmission end of the first N-type switch tube Connected to the second transmission end of the second N-type switch tube, the first transmission end of the third N-type switch tube is connected to the second transmission end of the fourth N-type switch tube, and the second output of the first N-type switch tube
  • the second output end of the third N-type switch tube is connected to the output end of the NAND gate.
  • the output buffer circuit includes an odd number of second inverters connected in series, and an input end of the second inverter close to the signal processing circuit is connected to the second control signal, and is output from the second inverter output terminal of the signal processing circuit. This level scans the drive signal.
  • the present invention provides the same degree of pressure by setting two switch components and cross-connecting the control ends of the switch tubes therein. Greatly improve the stability of the circuit work.
  • FIG. 1 is a schematic diagram showing the circuit structure of a first embodiment of a gate driving circuit of the present invention
  • FIG. 2 is a timing chart showing the operation of the gate driving circuit of the present invention.
  • FIG. 3 is a schematic structural diagram of a circuit of a second embodiment of a gate driving circuit of the present invention.
  • FIG. 4 is a schematic structural diagram of a circuit of a third embodiment of a gate driving circuit of the present invention.
  • Fig. 5 is a schematic view showing the structure of an embodiment of a liquid crystal display of the present invention.
  • the gate driving circuit includes: an input and latch circuit 11, a signal processing circuit 12 electrically connected to the input and latch circuit 11, and a circuit.
  • the output buffer circuit 13 of the signal processing circuit 12 is connected;
  • the input and latch circuit 11 outputs the first control signal Q(N) according to the upper scanning drive signal G(N-1), the first clock signal CK1, and the second clock signal CK2 inverted from the first clock signal CK1, and the signal processing
  • the circuit 12 outputs the second control signal A(N) according to the first control signal Q(N) and the third clock signal CK3, and the output buffer circuit 13 outputs the current-level scan driving signal G(N) according to the second control signal A(N). ;
  • the input and latch circuit 11 or the signal processing circuit 12 includes two switch assemblies arranged in parallel, wherein each switch assembly includes two switch tubes arranged in series, and two switch tubes of one switch unit of the two switch units.
  • the control terminal is cross-connected with the control terminals of the two switch tubes of the other switch assembly of the two switch assemblies.
  • the input and latch circuit 11 includes: a first clock control inverter 111, a second clock control inverter 112, and a first inverter F1.
  • the first clock control inverter 111 is connected to the positive phase control terminal.
  • the first clock signal CK1 the inverting control terminal of the first clocked inverter 111 is connected to the second clock signal CK2, and the input of the first clocked inverter 111 is connected to the upper scan driving signal G(N-1).
  • the output of the first clocked inverter 111 is connected to the output of the second clocked inverter 112, and the positive phase of the second clocked inverter 112 is connected to the second clock signal CK2, the second clock is controlled.
  • the inverting control terminal of the inverter 112 is connected to the first clock signal CK1, and the input terminal of the first inverter F1 is connected to the output terminal of the first clocked inverter 111 and the output of the second clocked inverter 112.
  • the output of the first inverter F1 is coupled to the input of the second clocked inverter 112 and outputs a first control signal Q(N), wherein the first clocked inverter 111 and the second clocked control are inverted
  • At least one of the devices 112 is provided with a first clocked inverter 111 and a second connected Switching between the two components of the clocked inverter 112 at least one output terminal and a reference potential.
  • the first clocked inverter 111 includes a first P-type switch TP1, a second P-type switch TP2, a third P-type switch TP3, a fourth P-type switch TP4, and a first N-type switch TN1.
  • the control end of the first P-type switch tube TP1 is connected to the control end of the fourth P-type switch tube TP4, and is connected to the second clock signal CK2, the control end of the second P-type switch tube TP2 and the fourth P-type switch tube TP4
  • the control terminals are connected and connected to the upper scanning drive signal G(N-1)
  • the first transmission end of the first P-type switch tube TP1 and the first transmission end of the third P-type switch tube TP3 are connected to the high reference potential VGH
  • the first transmission end of the second P-type switch tube TP2 is connected to the second transmission end of the first P-type switch tube TP1, the first transmission end of the fourth P-type switch tube TP4 and the third P-type switch tube TP3
  • the second transmission end of the second P-type switch tube TP2 and the second transmission end of the fourth P-type switch tube TP4 are connected to the output end of the first clock control inverter 111;
  • the control end of the first N-type switch tube TN1 is connected to the control end of the fourth N-type switch tube TN4, and is connected to the upper-stage scan drive signal G(N-1), the second N-type switch tube TN2 and the third N-type
  • the control end of the switch tube TN3 is connected to the first clock signal CK1, and the first transmission end of the second N-type switch tube TN2 and the first transmission end of the fourth N-type switch tube TN4 are connected to the low reference potential VGL.
  • the first transmission end of the first N-type switch tube TN1 is connected to the second transmission end of the second N-type switch tube TN2, and the first transmission end of the third N-type switch tube TN3 and the fourth N-type switch tube TN4
  • the two transmission ends are connected, and the second transmission end of the first N-type switch tube TN1 and the second transmission end of the fourth N-type switch tube TN4 are connected to the output end of the first clock control inverter CK1.
  • the second clock control inverter 112 includes a fifth P-type switch tube TP5, a sixth P-type switch tube TP6, a seven-P-type switch tube TP7, an eighth P-type switch tube TP8, and a fifth N-type switch tube TN5. a sixth N-type switch tube TN6, a seventh N-type switch tube TN7, and an eighth N-type switch tube TN8;
  • the control end of the fifth P-type switch tube TP5 is connected with the control end of the eighth P-type switch tube TP8, and is connected to the first control signal Q(N), and the control end of the sixth P-type switch tube TP6 and the seventh
  • the control end of the P-type switch tube TP7 is connected and connected to the first clock signal CK1, wherein the first transmission end of the fifth P-type switch tube TP5 and the first transmission end of the seventh P-type switch tube TP7 are connected to the high reference Point VGH, the second transmission end of the fifth P-type switch tube TP5 is connected to the first transmission end of the sixth P-type switch tube TP6, and the first transmission end and the seventh P-type switch of the eighth P-type switch tube TP8
  • the second transmission end of the tube TP7 is connected, the second transmission end of the eighth P-type switch tube TP8 and the second transmission end of the sixth P-type switch tube TP6 are connected to the output end of the second clock control inverter 112;
  • the control end of the fifth N-type switch tube TN5 is connected to the control end of the eighth N-type switch tube TN8, and is connected to the second clock signal CK2, the control end of the sixth N-type switch tube TN6 and the seventh N-type switch tube
  • the control end of the TN7 is connected to the first control signal Q(N), and the first transmission end of the sixth N-type switch tube TN6 and the first transmission end of the eighth N-type switch tube TN8 are connected to the low reference potential.
  • the first transmission end of the fifth N-type switch tube TN5 is connected to the second transmission end of the sixth N-type switch tube TN6, and the first transmission end of the eighth N-type switch tube TN8 and the first of the seventh N-type switch tube TN7
  • the transmission end is connected, and the second transmission end of the fifth N-type switch tube TN5 and the second transmission end of the seventh N-type switch tube TN7 are connected to the output end of the second clock control inverter 112.
  • the signal processing circuit 12 is a NAND gate.
  • the first input terminal of the NAND gate circuit is connected to the first control signal Q(N), and the second input terminal of the NAND gate circuit is connected to the third clock signal CK3.
  • the output of the NOT circuit outputs a second control signal A(N), and the NAND circuit includes two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit 12 includes a ninth P-type switch tube TP9, a tenth P-type switch tube TP10, a ninth N-type switch tube TN9, a tenth N-type switch tube TN10, an eleventh N-type switch tube TN11, and a twelfth N Type switch tube TN12;
  • the control end of the ninth P-type switch tube TP9 is connected to the first control signal Q(N), the control end of the tenth P-type switch tube TP10 is connected to the third clock signal CK3, and the first transmission of the ninth P-type switch tube TP9
  • the first transmission end of the terminal and the tenth P-type switch tube TP10 is connected to the high reference potential VGH, the second transmission of the ninth P-type switch tube TP9, and the second transmission end of the tenth P-type switch TP10 tube and the NAND gate
  • the outputs are connected;
  • the control end of the ninth N-type switch tube TN9 is connected to the control end of the twelfth N-type switch tube TN12, and is connected to the first control signal Q(N), the control end of the tenth N-type switch tube TN10 and the tenth
  • the control end of an N-type switch tube TN11 is connected and connected to the third clock signal CK3, and the first input end of the tenth N-type switch tube TN10 and the first input end of the twelfth N-type switch tube TN12 are connected low.
  • the first transmission end of the ninth N-type switch tube TN9 is connected to the second transmission end of the tenth N-type switch tube TN10, and the first transmission end of the eleventh N-type switch tube TN11 is connected to the twelfth
  • the second output end of the N-type switch tube TN12, the second output end of the ninth N-type switch tube TN9 and the second output end of the eleventh N-type switch tube TN11 are connected to the output end of the NAND gate.
  • the output buffer circuit 13 includes an odd number of second inverters F2 connected in series, and an input end of the second inverter F2 adjacent to the signal processing circuit 12 is connected to the second control signal A(N), away from the signal processing circuit 12
  • the output of the second inverter F2 outputs the current-level scan driving signal G(N).
  • the switching transistor may be a thin film transistor TFT whose control terminal is a gate of a thin film transistor, and the first transmission end and the second transmission end are respectively a source and a drain.
  • FIG. 2 is a timing chart of operation of the gate driving circuit of the present invention.
  • the first clock signal (CK1) is also a high potential signal.
  • the second clock signal CK2 is a low potential signal, the first P-type switch tube TP1 and the fourth P-type switch tube TP4 are opened, the first N-type switch tube TN1 and the fourth N-type switch tube TN4 are open, and the second N-type switch is opened.
  • the voltage of the connection node of the second transmission end of the fourth P-type switch tube TP4 and the third N-type switch tube TN3 is equal to the voltage value of the constant voltage low potential signal VGL.
  • the first control signal Q(N) is obtained after the inverter F1 is inverted, and the first control signal Q(N) is a high level signal; when the first clock signal CK1 becomes a low level signal, the upper level scan
  • the drive signal G(N-1) also becomes a low level signal, at which time the first clocked inverter 111 does not operate, and the second clock controls the sixth N-type switch TN6 and the seventh N-type in the inverter 112.
  • the switch tube TN7 is opened, the sixth P-type switch tube TP6 and the seventh P-type switch tube TP7 are opened, and the fifth N-type switch tube TN5 and the eighth N-type switch tube TN8 are opened, then
  • the voltage of the connection node of the second transmission terminal of the fourth P-type switch transistor TP4 and the third N-type switch transistor TN3 is latched at the voltage value of the low reference potential VGL; when the third clock signal CK3 of the high potential is generated, the signal processing circuit 12
  • the ninth N-type switch tube TN9 and the tenth N-type switch tube TN10 are turned on, then the second control signal A(N) is a low level signal, and an odd number is sequentially connected in series through the output buffer circuit 13 (Fig. 3 Only three of the second inverters F2 are inverted, and the high-level positive-phase scan drive signal G(N) is output.
  • the original clocked inverter is split into two in the input and latch circuit 11, and the two clocked inverters are cross-connected, so that VGH and VGL are close to each other.
  • the transistor is equivalent to the same voltage as the transistor near the output (equivalent), which effectively improves the uniformity of the circuit design and the stability of the circuit operation.
  • the input and latch circuit 11 further includes a third inverter (F3) through which the second clock signal (CK2) is passed by the first clock signal (CK1). (F3) is obtained by inversion.
  • F3 is obtained by inversion.
  • the input and latch circuit 11 further includes a reset circuit 113.
  • the reset circuit 113 has an eleventh P-type switch tube TP11, and the control end of the eleventh P-type switch tube TP11 is connected.
  • the reset signal Reset the first transmission end is connected to the high reference point VGH, and the second transmission end is connected to the outputs of the first clocked inverter 111 and the second clocked inverter 112.
  • the gate driving circuit includes: an input and latch circuit 31, a signal processing circuit 32 electrically connected to the input and latch circuit 31, and an electric The output buffer circuit 33 of the signal processing circuit 32 is connected.
  • the input and latch circuit 31 outputs the first control signal Q(N) according to the upper-stage scan driving signal G(N-1), the first clock signal CK1, and the second clock signal CK2 inverted from the first clock signal CK1, and the signal processing
  • the circuit 32 outputs the second control signal A(N) according to the first control signal Q(N) and the third clock signal CK3, and the output buffer circuit 33 outputs the current-level scan driving signal G(N) according to the second control signal A(N). ;
  • the signal processing circuit 32 is a NAND gate, the first input end of the NAND gate circuit is connected to the first control signal Q(N), and the second input end of the NAND gate circuit is connected to the third clock signal CK3, and The output of the NOT circuit outputs a second control signal A(N), and the NAND circuit includes two switch components disposed between the output of the NAND circuit and the reference potential.
  • the signal processing circuit 32 includes a first P-type switch tube TP1, a second P-type switch tube TP2, a first N-type switch tube TN1, a second N-type switch tube TN2, a third N-type switch tube TN3, and a fourth N.
  • the control end of the first P-type switch tube TP1 is connected to the first control signal Q(N), the control end of the second P-type switch tube TP2 is connected to the third clock signal CK3, and the first transmission of the first P-type switch tube TP1
  • the first transmission end of the terminal and the second P-type switch tube TP2 is connected to the high reference potential VGH, the second transmission of the first P-type switch tube TP1 and the second transmission end of the second P-type switch tube TP2 and the NAND gate
  • the outputs are connected;
  • the control end of the first N-type switch tube TN1 is connected to the control end of the fourth N-type switch tube TN4, and is connected to the first control signal Q(N), the control end of the second N-type switch tube TN2 and the third N
  • the control end of the type switch tube TN3 is connected, and is connected to the third clock signal CK3.
  • the first input end of the second N-type switch tube TN2 and the first input end of the fourth N-type switch tube TN4 are connected to the low reference potential VGL.
  • the first transmission end of the first N-type switch tube TN1 is connected to the second transmission end of the second N-type switch tube TN2, and the first transmission end of the third N-type switch tube TN3 is connected to the fourth N-type switch tube TN4.
  • the second output end of the first N-type switch tube TN1 and the second output end of the third N-type switch tube TN3 are connected to the output end of the NAND gate.
  • the input and latch circuit 31 includes a first clocked inverter 311, a second clocked inverter 312, and a first inverter F1.
  • the positive phase control terminal of the first clocked inverter 311 is connected to the first The clock signal CK1, the inverting control terminal of the first clocked inverter 311 is connected to the second clock signal CK2, and the input of the first clocked inverter 311 is connected to the upper scan driving signal G(N-1),
  • An output of a clocked inverter 311 is coupled to an output of the second clocked inverter 312, a positive phase control of the second clocked inverter 312 is coupled to the second clock signal CK2, and the second clock is inverted.
  • the inverting control terminal of the device 312 is connected to the first clock signal CK1, and the input end of the first inverter F1 is connected to the output end of the first clocked inverter 311 and the output of the second clocked inverter 312.
  • An output terminal of the inverter F1 is connected to the input terminal of the second clock control inverter 312, and outputs a first control signal CK1;
  • the first clocked inverter 311 includes a third P-type switch TP3, a fourth P-type switch TP4, a fifth N-type switch TN5, and a sixth N-type switch TN6;
  • the control terminal of the third P-type switch tube TP3 is connected to the second clock signal CK2, the first transmission end is connected to the high reference potential VGH, and the second transmission end is connected to the first transmission end of the second P-type switch tube TP2;
  • the control end of the P-type switch tube TP4 is connected to the upper-stage scan driving signal G(N-1), the second transmission end of the fourth P-type switch tube and the second transmission end of the fifth N-type switch tube TN5 and the first clock control
  • the output end of the inverter 311 is connected; the control end of the fifth N-type switch tube TN5 is connected to the upper stage scan drive signal G(N-1), and the second transmission of the first transmission end and the sixth N-type switch tube TN6
  • the terminal end is connected; the control end of the sixth N-type switch tube TN6 is connected to the first clock signal CK1, and the first transmission end of the sixth N-type switch tube TN6 is connected to the low reference potential VGL;
  • the second clock control inverter 312 includes a fifth P-type switch tube TP5, a sixth P-type switch tube TP6, a seventh N-type switch tube TN7, and an eighth N-type switch tube TN8;
  • the control end of the fifth P-type switch tube TP5 is connected to the first clock signal CK1, the first transmission end is connected to the high reference point VGH, and the second transmission end is connected to the first transmission end of the sixth P-type switch tube TP6;
  • the control end of the sixth P-type switch tube TP6 is connected to the first control signal Q(N), the second transmission end of the sixth P-type switch tube TP6, and the second transmission end and the second clock of the seventh N-type switch tube TN7
  • the output end of the control inverter 312 is connected; the control end of the seventh N-type switch tube TN7 is connected to the first control signal Q(N), and the first transmission end is connected to the second transmission end of the eighth N-type switch tube TN8.
  • the control end of the eighth N-type switch tube TN8 is connected to the second clock signal CK2, and the first transmission end is connected to the low reference potential VGL.
  • the output buffer circuit 33 includes an odd number of second inverters F2 connected in series, and an input end of the second inverter F2 adjacent to the signal processing circuit is connected to the second control signal A(N), away from the signal processing circuit 32.
  • the output of the second inverter F2 outputs the current-stage scan driving signal G(N).
  • the third clock control signal CK3 of high potential when the third clock control signal CK3 of high potential is generated, the first control signal Q(N) is also at a high potential, and the first N-type switching transistor TN1, the fourth N in the signal processing circuit 32.
  • the type switch tube TN4, the second N type switch tube TN2, and the third N type switch tube TN3 are all turned on, the output second control signal A(N) is a low level signal.
  • the transistor close to the VGL is close to the second control signal A ( N)
  • the transistor of the output point (equivalent) is subjected to the same degree of pressure, which effectively improves the uniformity of the circuit design and the stability of the circuit operation.
  • the second embodiment of the gate driving circuit of the present invention can also be combined with the first embodiment to form the third embodiment of the gate driving circuit of the present invention.
  • the specific structure and the working principle of the circuit are already in the above embodiment. A detailed description will not be repeated here.
  • the present invention further provides a schematic structural diagram of an embodiment of a liquid crystal display.
  • the liquid crystal display includes a display panel 701 and a backlight 702.
  • the display panel 701 includes a plurality of cascaded gate driving circuits. The implementation is similar and will not be described here.
  • the gate driving circuit in the embodiment of the present invention is not limited to the liquid crystal display, and can be applied to the field of OLED display panels and the like, and is applied to the field of gate driving of mobile phones, displays, and televisions. .

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Abstract

一种栅极驱动电路及液晶显示器，该栅极驱动电路包括：输入与锁存电路(11)、电性连接所述输入与锁存电路(11)的信号处理电路(12)以及电性连接所述信号处理电路(12)的输出缓冲电路(13)。其中，输入与锁存电路(11)或信号处理电路(12)包括并联设置的两个开关组件。每一开关组件分别包括串联设置的两个开关管，该两个开关组件的一开关组件的两个开关管的控制端与另一开关组件的两个开关管的控制端交叉连接。通过设置两个开关组件并将其内部的开关管的控制端进行交叉连接，使得两个开关管所受的压力程度相同，极大的提高了电路工作的稳定性。

Description

一种基于栅极驱动电路及其液晶显示器
【技术领域】
本发明涉及显示技术领域，特别是涉及一种栅极驱动电路及其液晶显示器。
【背景技术】
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
随着低温多晶硅（LTPS）半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到System on Panel（SOP）的相关技术研究，并逐步成为现实。
一般LTPS工艺中普遍采用的CMOS GOA功能的模块设计，其中包括了：Latch锁存器单元，用于级传信号的锁存，是GOA电路设计的核心部分，主要由两个时钟控制反相器和两个反相器组成；与非门信号处理单元，通过CK控制信号线与锁存的数据进行与非处理，用于产生本级的控制端驱动信号；CMOS电路的输出Buffer，用于增加控制端驱动信号的驱动能力，减小传输信号的RC Loading。
对于时钟控制反相器和与非门，我们定义靠近VGH和VGL的晶体管为第一晶体管，靠近输出端的晶体管为第二晶体管。
上述两个模块的电路连接方式较为单一，其中第一和第二晶体管在长时间工作的过程中需要承受的Stress程度不一样，因此第一和第二晶体管的变异程度也不一样。这种晶体管的不均匀性可能会导致信号锁存的变异以及与非门逻辑的错误，严重时会影响电路的正常工作，造成整个电路的失效。
【发明内容】
本发明主要解决的技术问题是提供一种栅极驱动电路及其液晶显示器，能够有效提高电路设计的均匀性以及电路工作的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种栅极驱动电路，包括：输入与锁存电路、电性连接所述输入与锁存电路的信号处理电路以及电性连接信号处理电路的输出缓冲电路；
输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与第一时钟信号反相的第二时钟信号输出第一控制信号，信号处理电路根据第一控制信号以及第三时钟信号输出第二控制信号，输出缓冲电路根据第二控制信号输出本级扫描驱动信号；
其中，输入与锁存电路或信号处理电路包括并联设置的两个开关组件，其中每一开关组件分别包括串联设置的两个开关管，两个开关组件的一开关组件的两个开关管的控制端与两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
其中，输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，第一时钟控制反相器的正相控制端接入第一时钟信号，第一时钟控制反相器的反相控制端接入第二时钟信号，第一时钟控制反相器的输入端接入上级扫描驱动信号，第一时钟控制反相器的输出端连接第二时钟控制反相器的输出端，第二时钟控制反相器的正相控制端接入第二时钟信号，第二时钟控制反相器的反相控制端接入第一时钟信号，第一反相器的输入端连接第一时钟控制反相器的输出端和第二时钟控制反相器的输出端，第一反相器的输出端连接第二时钟控制反相器的输入端，并输出第一控制信号，其中第一时钟控制反相器和第二时钟控制反相器的至少一个内设置有连接于第一时钟控制反相器和第二时钟控制反相器的至少一个的输出端与参考电位之间的两个开关组件。
其中，输出缓冲电路包括依次串联的奇数个第二反相器，接近信号处理电路的第二反向器的输入端接入第二控制信号，远离信号处理电路的第二反相器输出端输出本级扫描驱动信号。
为解决上述技术问题，本发明还采用的一个技术方案是：提供一种栅极驱动电路，包括：输入与锁存电路、电性连接输入与锁存电路的信号处理电路以及电性连接信号处理电路的输出缓冲电路；
输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与第一时钟信号反相的第二时钟信号输出第一控制信号，信号处理电路根据第一控制信号以及第三时钟信号输出第二控制信号，输出缓冲电路根据第二控制信号输出本级扫描驱动信号；
其中，输入与锁存电路或信号处理电路包括并联设置的两个开关组件，其中每一开关组件分别包括串联设置的两个开关管，两个开关组件的一开关组件的两个开关管的控制端与两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
其中，输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，第一时钟控制反相器的正相控制端接入第一时钟信号，第一时钟控制反相器的反相控制端接入第二时钟信号，第一时钟控制反相器的输入端接入上级扫描驱动信号，第一时钟控制反相器的输出端连接第二时钟控制反相器的输出端，第二时钟控制反相器的正相控制端接入第二时钟信号，第二时钟控制反相器的反相控制端接入第一时钟信号，第一反相器的输入端连接第一时钟控制反相器的输出端和第二时钟控制反相器的输出端，第一反相器的输出端连接第二时钟控制反相器的输入端，并输出第一控制信号，其中第一时钟控制反相器和第二时钟控制反相器的至少一个内设置有连接于第一时钟控制反相器和第二时钟控制反相器的至少一个的输出端与参考电位之间的两个开关组件。
其中，第一时钟控制反相器包括第一P型开关管、第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管、第三N型开关管以及第四N型开关管；
第一P型开关管控制端与第四P型开关管的控制端相连接，并接入第二时钟信号，第二P型开关管的控制端和第四P型开关管的控制端相连接，并接入上级扫描驱动信号，第一P型开关管的第一传输端和第三P型开关管的第一传输端接入高参考电位，第二P型开关管的第一传输端与第一P型开关管的第二传输端相连接，第四P型开关管的第一传输端和第三P型开关管的第二传输端相连接，第二P型开关管的第二传输端和第四P型开关管的第二传输端连接第一时钟控制反相器的输出端；
第一N型开关管的控制端与第四N型开关管的控制端相连接，并接入上级扫描驱动信号，第二N型开关管和第三N型开关管的控制端相连接，并接入第一时钟信号，第二N型开关管的第一传输端和第四N型开关管的第一传输端接入低参考电位，第一N型开关管的第一传输端与第二N型开关管的第二传输端相连接，第三N型开关管的第一传输端与第四N型开关管的第二传输端相连接，第一N型开关管的第二传输端和第四N型开关管的第二传输端连接第一时钟控制反相器的输出端。
其中，第二时钟控制反相器包括第五P型开关管、第六P型开关管、七P型开关管、第八P型开关管、第五N型开关管、第六N型开关管，第七N型开关管、第八N型开关管；
第五P型开关管的控制端与和第八P型开关管的控制端相连接，并接入第一控制信号，第六P型开关管的控制端与第七P型开关管的控制端相连接，并接入第一时钟信号，其中第五P型开关管的第一传输端和第七P型开关管的第一传输端接入高参考点位，第五P型开关管的第二传输端与第六P型开关管的第一传输端相连接，第八P型开关管的第一传输端与第七P型开关管的第二传输端相连接，第八P型开关管的第二传输端和第六P型开关管的第二传输端连接第二时钟控制反相器的输出端；
第五N型开关管的控制端与第八N型开关管的控制端相连接，并接入第二时钟信号，第六N型开关管的控制端与第七N型开关管的控制端相连接，并接入第一控制信号，第六N型开关管的第一传输端和第八N型开关管的第一传输端接入低参考电位，第五N型开关管的第一传输端与第六N型开关管的第二传输端相连接，第八N型开关管第二传输端与第七N型开关管的第一传输端相连接，第五N型开关管第二传输端和第七N型开关管的第二传输端连接第二时钟控制反相器的输出端。
信号处理电路为一与非门，与非门电路的第一输入端接入第一控制信号，与非门电路的第二输入端接入第三时钟信号，与非门电路的输出端输出第二控制信号，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
信号处理电路包括第九P型开关管、第十P型开关管、第九N型开关管、第十N型开关管、第十一N型开关管、第十二N型开关管；
第九P型开关管的控制端接入第一控制信号，第十P型开关管的控制端接入第三时钟信号，第九P型开关管的第一传输端和第十P型开关管的第一传输端端接入高参考电位，第九P型开关管的第二传输和第十P型开关管的第二传输端与与非门的输出端相连接；
第九N型开关管的控制端和第十二N型开关管的控制端相连接，并接入第一控制信号，第十N型开关管的控制端和第十一N型开关管的控制端相连接，并接入第三时钟信号，第十N型开关管的第一输入端和第十二N型开关管的第一输入端接入低参考电位，第九N型开关管的第一传输端与第十N型开关管的第二传输端相连接，第十一N型开关管的第一传输端连接于第十二N型开关管的第二传输端，第九N型开关管的第二输出端与第十一N型开关管的第二输出端连接与非门的输出端。
其中，信号处理电路为一与非门，与非门电路的第一输入端接入第一控制信号，与非门电路的第二输入端接入第三时钟信号，与非门电路的输出端输出第二控制信号，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
其中，信号处理电路包括第一P型开关管、第二P型开关管、第一N型开关管、第二N型开关管、第三N型开关管、第四N型开关管；
第一P型开关管的控制端接入第一控制信号，第二P型开关管的控制端接入第三时钟信号，第一P型开关管的第一传输端和第二P型开关管的第一传输端端接入高参考电位，第一P型开关管的第二传输和第二P型开关管的第二传输端与与非门的输出端相连接；
第一N型开关管的控制端和第四N型开关管的控制端相连接，并接入第一控制信号，第二N型开关管的控制端和第三N型开关管的控制端相连接，并接入第三时钟信号，第二N型开关管的第一输入端和第四N型开关管的第一输入端接入低参考电位，第一N型开关管的第一传输端与第二N型开关管的第二传输端相连接，第三N型开关管的第一传输端连接于第四N型开关管的第二传输端，第一N型开关管的第二输出端与第三N型开关管的第二输出端连接与非门的输出端。
其中，输出缓冲电路包括依次串联的奇数个第二反相器，接近信号处理电路的第二反向器的输入端接入第二控制信号，远离信号处理电路的第二反相器输出端输出本级扫描驱动信号。
为了解决上述问题，本发明还提供了一种液晶显示器，包括多个级联设置的的栅极驱动电路，栅极驱动电路包括：输入与锁存电路、电性连接输入与锁存电路的信号处理电路以及电性连接信号处理电路的输出缓冲电路；
输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与第一时钟信号反相的第二时钟信号输出第一控制信号，信号处理电路根据第一控制信号以及第三时钟信号输出第二控制信号，输出缓冲电路根据第二控制信号输出本级扫描驱动信号；
其中，输入与锁存电路或信号处理电路包括并联设置的两个开关组件，其中每一开关组件分别包括串联设置的两个开关管，两个开关组件的一开关组件的两个开关管的控制端与两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
其中，输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，第一时钟控制反相器的正相控制端接入第一时钟信号，第一时钟控制反相器的反相控制端接入第二时钟信号，第一时钟控制反相器的输入端接入上级扫描驱动信号，第一时钟控制反相器的输出端连接第二时钟控制反相器的输出端，第二时钟控制反相器的正相控制端接入第二时钟信号，第二时钟控制反相器的反相控制端接入第一时钟信号，第一反相器的输入端连接第一时钟控制反相器的输出端和第二时钟控制反相器的输出端，第一反相器的输出端连接第二时钟控制反相器的输入端，并输出第一控制信号，其中第一时钟控制反相器和第二时钟控制反相器的至少一个内设置有连接于第一时钟控制反相器和第二时钟控制反相器的至少一个的输出端与参考电位之间的两个开关组件。
其中，第一时钟控制反相器包括第一P型开关管、第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管、第三N型开关管以及第四N型开关管；
第一P型开关管控制端与第四P型开关管的控制端相连接，并接入第二时钟信号，第二P型开关管的控制端和第四P型开关管的控制端相连接，并接入上级扫描驱动信号，第一P型开关管的第一传输端和第三P型开关管的第一传输端接入高参考电位，第二P型开关管的第一传输端与第一P型开关管的第二传输端相连接，第四P型开关管的第一传输端和第三P型开关管的第二传输端相连接，第二P型开关管的第二传输端和第四P型开关管的第二传输端连接第一时钟控制反相器的输出端；
第一N型开关管的控制端与第四N型开关管的控制端相连接，并接入上级扫描驱动信号，第二N型开关管和第三N型开关管的控制端相连接，并接入第一时钟信号，第二N型开关管的第一传输端和第四N型开关管的第一传输端接入低参考电位，第一N型开关管的第一传输端与第二N型开关管的第二传输端相连接，第三N型开关管的第一传输端与第四N型开关管的第二传输端相连接，第一N型开关管的第二传输端和第四N型开关管的第二传输端连接第一时钟控制反相器的输出端。
其中，第二时钟控制反相器包括第五P型开关管、第六P型开关管、七P型开关管、第八P型开关管、第五N型开关管、第六N型开关管，第七N型开关管、第八N型开关管；
第五P型开关管的控制端与和第八P型开关管的控制端相连接，并接入第一控制信号，第六P型开关管的控制端与第七P型开关管的控制端相连接，并接入第一时钟信号，其中第五P型开关管的第一传输端和第七P型开关管的第一传输端接入高参考点位，第五P型开关管的第二传输端与第六P型开关管的第一传输端相连接，第八P型开关管的第一传输端与第七P型开关管的第二传输端相连接，第八P型开关管的第二传输端和第六P型开关管的第二传输端连接第二时钟控制反相器的输出端；
第五N型开关管的控制端与第八N型开关管的控制端相连接，并接入第二时钟信号，第六N型开关管的控制端与第七N型开关管的控制端相连接，并接入第一控制信号，第六N型开关管的第一传输端和第八N型开关管的第一传输端接入低参考电位，第五N型开关管的第一传输端与第六N型开关管的第二传输端相连接，第八N型开关管第二传输端与第七N型开关管的第一传输端相连接，第五N型开关管第二传输端和第七N型开关管的第二传输端连接第二时钟控制反相器的输出端。
其中，信号处理电路为一与非门，与非门电路的第一输入端接入第一控制信号，与非门电路的第二输入端接入第三时钟信号，与非门电路的输出端输出第二控制信号，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
其中，信号处理电路包括第九P型开关管、第十P型开关管、第九N型开关管、第十N型开关管、第十一N型开关管、第十二N型开关管；
第九P型开关管的控制端接入第一控制信号，第十P型开关管的控制端接入第三时钟信号，第九P型开关管的第一传输端和第十P型开关管的第一传输端端接入高参考电位，第九P型开关管的第二传输和第十P型开关管的第二传输端与与非门的输出端相连接；
第九N型开关管的控制端和第十二N型开关管的控制端相连接，并接入第一控制信号，第十N型开关管的控制端和第十一N型开关管的控制端相连接，并接入第三时钟信号，第十N型开关管的第一输入端和第十二N型开关管的第一输入端接入低参考电位，第九N型开关管的第一传输端与第十N型开关管的第二传输端相连接，第十一N型开关管的第一传输端连接于第十二N型开关管的第二传输端，第九N型开关管的第二输出端与第十一N型开关管的第二输出端连接与非门的输出端。
其中，信号处理电路为一与非门，与非门电路的第一输入端接入第一控制信号，与非门电路的第二输入端接入第三时钟信号，与非门电路的输出端输出第二控制信号，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
其中，信号处理电路包括第一P型开关管、第二P型开关管、第一N型开关管、第二N型开关管、第三N型开关管、第四N型开关管；
第一P型开关管的控制端接入第一控制信号，第二P型开关管的控制端接入第三时钟信号，第一P型开关管的第一传输端和第二P型开关管的第一传输端端接入高参考电位，第一P型开关管的第二传输和第二P型开关管的第二传输端与与非门的输出端相连接；
第一N型开关管的控制端和第四N型开关管的控制端相连接，并接入第一控制信号，第二N型开关管的控制端和第三N型开关管的控制端相连接，并接入第三时钟信号，第二N型开关管的第一输入端和第四N型开关管的第一输入端接入低参考电位，第一N型开关管的第一传输端与第二N型开关管的第二传输端相连接，第三N型开关管的第一传输端连接于第四N型开关管的第二传输端，第一N型开关管的第二输出端与第三N型开关管的第二输出端连接与非门的输出端。
其中，输出缓冲电路包括依次串联的奇数个第二反相器，接近信号处理电路的第二反向器的输入端接入第二控制信号，远离信号处理电路的第二反相器输出端输出本级扫描驱动信号。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置两个开关组件并将其内部的开关管的控制端进行交叉连接，使得两个开关管所受的压力程度相同，极大的提高了电路工作的稳定性。
【附图说明】
图1是本发明栅极驱动电路第一实施例的电路结构示意图；
图2是本发明栅极驱动电路的工作时序图；
图3是本发明栅极驱动电路第二实施例的电路结构示意图；
图4是本发明栅极驱动电路第三实施例的电路结构示意图；
图5是本发明液晶显示器一实施例的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应该可以理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
参阅图1，为本发明栅极驱动电路第一实施例的电路结构示意图，该栅极驱动电路包括：输入与锁存电路11、电性连接输入与锁存电路11的信号处理电路12、电性连接信号处理电路12的输出缓冲电路13；
输入与锁存电路11根据上级扫描驱动信号G(N-1)、第一时钟信号CK1以及与第一时钟信号CK1反相的第二时钟信号CK2输出第一控制信号Q(N)，信号处理电路12根据第一控制信号Q(N)以及第三时钟信号CK3输出第二控制信号A(N)，输出缓冲电路13根据第二控制信号A(N)输出本级扫描驱动信号G(N)；
其中，输入与锁存电路11或信号处理电路12包括并联设置的两个开关组件，其中每一开关组件分别包括串联设置的两个开关管，两个开关组件的一开关组件的两个开关管的控制端与两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
其中，输入与锁存电路11包括：第一时钟控制反相器111、第二时钟控制反相器112以及第一反相器F1，第一时钟控制反相器111的正相控制端接入第一时钟信号CK1，第一时钟控制反相器111的反相控制端接入第二时钟信号CK2，第一时钟控制反相器111的输入端接入上级扫描驱动信号G(N-1)，第一时钟控制反相器111的输出端连接第二时钟控制反相器112的输出端，第二时钟控制反相器112的正相控制端接入第二时钟信号CK2，第二时钟控制反相器112的反相控制端接入第一时钟信号CK1，第一反相器F1的输入端连接第一时钟控制反相器111的输出端和第二时钟控制反相器112的输出端，第一反相器F1的输出端连接第二时钟控制反相器112的输入端，并输出第一控制信号Q(N)，其中第一时钟控制反相器111和第二时钟控制反相器112的至少一个内设置有连接于第一时钟控制反相器111和第二时钟控制反相器112的至少一个的输出端与参考电位之间的两个开关组件。
其中，第一时钟控制反相器111包括第一P型开关管TP1、第二P型开关管TP2、第三P型开关管TP3、第四P型开关管TP4、第一N型开关管TN1、第二N型开关管TN2、第三N型开关管TN3以及第四N型开关管TN4；
第一P型开关管TP1控制端与第四P型开关管TP4的控制端相连接，并接入第二时钟信号CK2，第二P型开关管TP2的控制端和第四P型开关管TP4的控制端相连接，并接入上级扫描驱动信号G(N-1)，第一P型开关管TP1的第一传输端和第三P型开关管TP3的第一传输端接入高参考电位VGH，第二P型开关管TP2的第一传输端与第一P型开关管TP1的第二传输端相连接，第四P型开关管TP4的第一传输端和第三P型开关管TP3的第二传输端相连接，第二P型开关管TP2的第二传输端和第四P型开关管TP4的第二传输端连接第一时钟控制反相器111的输出端；
第一N型开关管TN1的控制端与第四N型开关管TN4的控制端相连接，并接入上级扫描驱动信号G(N-1)，第二N型开关管TN2和第三N型开关管TN3的控制端相连接，并接入第一时钟信号CK1，第二N型开关管TN2的第一传输端和第四N型开关管TN4的第一传输端接入低参考电位VGL，第一N型开关管TN1的第一传输端与第二N型开关管TN2的第二传输端相连接，第三N型开关管TN3的第一传输端与第四N型开关管TN4的第二传输端相连接，第一N型开关管TN1的第二传输端和第四N型开关管TN4的第二传输端连接第一时钟控制反相器CK1的输出端。
其中，第二时钟控制反相器112包括第五P型开关管TP5、第六P型开关管TP6、七P型开关管TP7、第八P型开关管TP8、第五N型开关管TN5、第六N型开关管TN6，第七N型开关管TN7、第八N型开关管TN8；
第五P型开关管TP5的控制端与和第八P型开关管TP8的控制端相连接，并接入第一控制信号Q(N)，第六P型开关管TP6的控制端与第七P型开关管TP7的控制端相连接，并接入第一时钟信号CK1，其中第五P型开关管TP5的第一传输端和第七P型开关管TP7的第一传输端接入高参考点位VGH，第五P型开关管TP5的第二传输端与第六P型开关管TP6的第一传输端相连接，第八P型开关管TP8的第一传输端与第七P型开关管TP7的第二传输端相连接，第八P型开关管TP8的第二传输端和第六P型开关管TP6的第二传输端连接第二时钟控制反相器112的输出端；
第五N型开关管TN5的控制端与第八N型开关管TN8的控制端相连接，并接入第二时钟信号CK2，第六N型开关管TN6的控制端与第七N型开关管TN7的控制端相连接，并接入第一控制信号Q(N)，第六N型开关管TN6的第一传输端和第八N型开关管TN8的第一传输端接入低参考电位，第五N型开关管TN5的第一传输端与第六N型开关管TN6的第二传输端相连接，第八N型开关管TN8第二传输端与第七N型开关管TN7的第一传输端相连接，第五N型开关管TN5第二传输端和第七N型开关管TN7的第二传输端连接第二时钟控制反相器112的输出端。
其中，信号处理电路12为一与非门，与非门电路的第一输入端接入第一控制信号Q(N)，与非门电路的第二输入端接入第三时钟信号CK3，与非门电路的输出端输出第二控制信号A(N)，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
信号处理电路12包括第九P型开关管TP9、第十P型开关管TP10、第九N型开关管TN9、第十N型开关管TN10、第十一N型开关管TN11、第十二N型开关管TN12；
第九P型开关管TP9的控制端接入第一控制信号Q(N)，第十P型开关管TP10的控制端接入第三时钟信号CK3，第九P型开关管TP9的第一传输端和第十P型开关管TP10的第一传输端端接入高参考电位VGH，第九P型开关管TP9的第二传输和第十P型开关TP10管的第二传输端与与非门的输出端相连接；
第九N型开关管TN9的控制端和第十二N型开关管TN12的控制端相连接，并接入第一控制信号Q(N)，第十N型开关管TN10的控制端和第十一N型开关管TN11的控制端相连接，并接入第三时钟信号CK3，第十N型开关管TN10的第一输入端和第十二N型开关管TN12的第一输入端接入低参考电位VGL，第九N型开关管TN9的第一传输端与第十N型开关管TN10的第二传输端相连接，第十一N型开关管TN11的第一传输端连接于第十二N型开关管TN12的第二传输端，第九N型开关管TN9的第二输出端与第十一N型开关管TN11的第二输出端连接与非门的输出端。
其中，输出缓冲电路13包括依次串联的奇数个第二反相器F2，接近信号处理电路12的第二反向器F2的输入端接入第二控制信号A(N)，远离信号处理电路12的第二反相器F2输出端输出本级扫描驱动信号G(N)。
其中，开关管可以是薄膜晶体管TFT，其控制端为薄膜晶体管的栅极，第一传输端和第二传输端分别为源极和漏极。
图2为本发明栅极驱动电路的工作时序图，结合图1以及图2，当产生高电位的上级扫描驱动信号G(N-1)时，第一时钟信号(CK1)也为高电位信号，第二时钟信号CK2为低电位信号，第一P型开关管TP1和第四P型开关管TP4打开,第一N型开关管TN1和第四N型开关管TN4打开，第二N型开关管TN2和第三N型开关管TN3打开，则第四P型开关管TP4和第三N型开关管TN3的第二传输端的连接节点的电压等于恒压低电位信号VGL的电压值，经过第一反相器F1反相后得到第一控制信号Q(N)，此时第一控制信号Q(N)为高电平信号；当第一时钟信号CK1变为低电平信号时，上级扫描驱动信号G(N-1)也变为低电平信号，此时第一时钟控制反相器111不工作，第二时钟控制反相器112中第六N型开关管TN6和第七N型开关管TN7打开，第六P型开关管TP6和第七P型开关管TP7打开，第五N型开关管TN5和第八N型开关管TN8打开，则第四P型开关管TP4和第三N型开关管TN3的第二传输端的连接节点的电压被锁存在低参考电位VGL的电压值；当产生高电位的第三时钟信号CK3时，信号处理电路12中的第九N型开关管TN9和第十N型开关管TN10打开，则此时第二控制信号A(N)为低电平信号，经过输出缓冲电路13内依次串联的奇数个(图3中只画出了3个)第二反相器F2的反相作用，输出高电位的本级正相扫描驱动信号G(N)。
在本发明实施例中，由于在输入与锁存电路11中将原先的一个时钟控制反相器拆分成两个，并将这两个时钟控制反相器交叉连接，使得接近VGH和VGL的晶体管与靠近输出端的晶体管(等效)所受的压力程度相同，有效提高电路设计的均匀性以及电路工作的稳定性。
在本发明一个优选的实施例中，输入与锁存电路11还包括一第三反相器(F3)，第二时钟信号(CK2)由第一时钟信号(CK1)经该第三反相器(F3)反相得到。
在本发明一个优选的实施例中，输入与锁存电路11还包括一复位电路113，复位电路113具有一第十一P型开关管TP11，第十一P型开关管TP11的控制端接入复位信号Reset，第一传输端接入高参考点位VGH，第二传输端连接于第一时钟控制反相器111和第二时钟控制反相器112的输出端。
参阅图3，为本发明栅极驱动电路第二实施例的电路结构示意图，该栅极驱动电路包括：输入与锁存电路31、电性连接输入与锁存电路31的信号处理电路32、电性连接信号处理电路32的输出缓冲电路33。
输入与锁存电路31根据上级扫描驱动信号G(N-1)、第一时钟信号CK1以及与第一时钟信号CK1反相的第二时钟信号CK2输出第一控制信号Q(N)，信号处理电路32根据第一控制信号Q(N)以及第三时钟信号CK3输出第二控制信号A(N)，输出缓冲电路33根据第二控制信号A(N)输出本级扫描驱动信号G(N)；
其中，信号处理电路32为一与非门，与非门电路的第一输入端接入第一控制信号Q(N)，与非门电路的第二输入端接入第三时钟信号CK3，与非门电路的输出端输出第二控制信号A(N)，与非门电路包括设置于与非门电路的输出端与参考电位之间的两个开关组件。
其中，信号处理电路32包括第一P型开关管TP1、第二P型开关管TP2、第一N型开关管TN1、第二N型开关管TN2、第三N型开关管TN3、第四N型开关管TN4；
第一P型开关管TP1的控制端接入第一控制信号Q(N)，第二P型开关管TP2的控制端接入第三时钟信号CK3，第一P型开关管TP1的第一传输端和第二P型开关管TP2的第一传输端端接入高参考电位VGH，第一P型开关管TP1的第二传输和第二P型开关管TP2的第二传输端与与非门的输出端相连接；
第一N型开关管TN1的控制端和第四N型开关管TN4的控制端相连接，并接入第一控制信号Q(N)，第二N型开关管TN2的控制端和第三N型开关管TN3的控制端相连接，并接入第三时钟信号CK3，第二N型开关管TN2的第一输入端和第四N型开关管TN4的第一输入端接入低参考电位VGL，第一N型开关管TN1的第一传输端与第二N型开关管TN2的第二传输端相连接，第三N型开关管TN3的第一传输端连接于第四N型开关管TN4的第二传输端，第一N型开关管TN1的第二输出端与第三N型开关管TN3的第二输出端连接与非门的输出端。
输入与锁存电路31包括：第一时钟控制反相器311、第二时钟控制反相器312以及第一反相器F1，第一时钟控制反相器311的正相控制端接入第一时钟信号CK1，第一时钟控制反相器311的反相控制端接入第二时钟信号CK2，第一时钟控制反相器311的输入端接入上级扫描驱动信号G(N-1)，第一时钟控制反相器311的输出端连接第二时钟控制反相器312的输出端，第二时钟控制反相器312的正相控制端接入第二时钟信号CK2，第二时钟控制反相器312的反相控制端接入第一时钟信号CK1，第一反相器F1的输入端连接第一时钟控制反相器311的输出端和第二时钟控制反相器312的输出端，第一反相器F1的输出端连接第二时钟控制反相器312的输入端，并输出第一控制信号CK1；
其中，第一时钟控制反相器311包括第三P型开关管TP3、第四P型开关管TP4、第五N型开关管TN5、第六N型开关管TN6；
第三P型开关管TP3控制端接入第二时钟信号CK2，第一传输端接入高参考电位VGH，第二传输端与第二P型开关管TP2的第一传输端相连接；第四P型开关管TP4的控制端接入上级扫描驱动信号G(N-1)，第四P型开关管的第二传输端和第五N型开关管TN5的第二传输端与第一时钟控制反相器311的输出端相连接；第五N型开关管TN5的控制端接入上级第扫描驱动信号G(N-1)，第一传输端与第六N型开关管TN6的第二传输端相连接；第六N型开关管TN6的控制端接入第一时钟信号CK1，第六N型开关管TN6的第一传输端接入低参考电位VGL；
第二时钟控制反相器312包括第五P型开关管TP5、第六P型开关管TP6、第七N型开关管TN7，第八N型开关管TN8；
第五P型开关管TP5的控制端接入第一时钟信号CK1，第一传输端接入高参考点位VGH，第二传输端与第六P型开关管TP6的第一传输端相连接；第六P型开关管TP6的控制端接入第一控制信号Q(N)，第六P型开关管TP6的第二传输端和第七N型开关管TN7的第二传输端与第二时钟控制反相器312输出端相连接；第七N型开关管TN7的控制端接入第一控制信号Q(N)，第一传输端与第八N型开关管TN8的第二传输端相连接；第八N型开关管TN8的控制端接入第二时钟信号CK2，第一传输端接入低参考电位VGL。
其中，输出缓冲电路33包括依次串联的奇数个第二反相器F2，接近信号处理电路的第二反向器F2的输入端接入第二控制信号A(N)，远离信号处理电路32的第二反相器F2输出端输出本级扫描驱动信号G(N)。
结合图2和图3，当产生高电位的第三时钟控制信号CK3时，第一控制信号Q(N)也处在高电位，信号处理电路32中第一N型开关管TN1、第四N型开关管TN4、第二N型开关管TN2、第三N型开关管TN3全部打开，则输出的第二控制信号A(N)为低电平信号。
在本发明实施例中，通过在信号处理电路32中将原先的与非门拆分成两个，并将这两个与非门交叉连接，使得接近VGL的晶体管与靠近第二控制信号A(N)输出点的晶体管(等效)所受的压力程度相同，有效提高电路设计的均匀性以及电路工作的稳定性。
参阅图4，本发明栅极驱动电路第二实施例还可以和第一实施例相结合以形成本发明栅极驱动电路第三实施例，具体结构以及电路工作原理在上述实施例中已经有了详尽的描述，在此不做赘述。
参阅图5，本发明还提供了一种液晶显示器一实施例的结构示意图，该液晶显示器包括显示面板701及背光702，显示面板701中包括多个级联设置的上述栅极驱动电路，其具体实施方式类似，这里不再赘述。
此外，本发明实施例中的栅极驱动电路不仅仅局限应用于液晶显示器，本领域技术人员可以知道，还可以应用于OLED显示面板等领域，以及应用于手机、显示器、电视的栅极驱动领域。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种栅极驱动电路，其特征在于，包括：输入与锁存电路、电性连接所述输入与锁存电路的信号处理电路以及电性连接所述信号处理电路的输出缓冲电路；
    所述输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与所述第一时钟信号反相的第二时钟信号输出第一控制信号，所述信号处理电路根据所述第一控制信号以及第三时钟信号输出第二控制信号，所述输出缓冲电路根据所述第二控制信号输出本级扫描驱动信号；
    其中，所述输入与锁存电路或所述信号处理电路包括并联设置的两个开关组件，其中每一所述开关组件分别包括串联设置的两个开关管，所述两个开关组件的一开关组件的两个开关管的控制端与所述两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
    其中，所述输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，所述第一时钟控制反相器的正相控制端接入所述第一时钟信号，所述第一时钟控制反相器的反相控制端接入所述第二时钟信号，所述第一时钟控制反相器的输入端接入所述上级扫描驱动信号，所述第一时钟控制反相器的输出端连接所述第二时钟控制反相器的输出端，所述第二时钟控制反相器的正相控制端接入所述第二时钟信号，所述第二时钟控制反相器的反相控制端接入第一时钟信号，所述第一反相器的输入端连接所述第一时钟控制反相器的输出端和所述第二时钟控制反相器的输出端，所述第一反相器的输出端连接所述第二时钟控制反相器的输入端，并输出所述第一控制信号，其中所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个内设置有连接于所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个的输出端与参考电位之间的所述两个开关组件。
    其中，所述输出缓冲电路包括依次串联的奇数个第二反相器，接近所述信号处理电路的第二反向器的输入端接入所述第二控制信号，所述远离信号处理电路的第二反相器输出端输出所述本级扫描驱动信号。
  2. 一种栅极驱动电路，其特征在于，包括：输入与锁存电路、电性连接所述输入与锁存电路的信号处理电路以及电性连接所述信号处理电路的输出缓冲电路；
    所述输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与所述第一时钟信号反相的第二时钟信号输出第一控制信号，所述信号处理电路根据所述第一控制信号以及第三时钟信号输出第二控制信号，所述输出缓冲电路根据所述第二控制信号输出本级扫描驱动信号；
    其中，所述输入与锁存电路或所述信号处理电路包括并联设置的两个开关组件，其中每一所述开关组件分别包括串联设置的两个开关管，所述两个开关组件的一开关组件的两个开关管的控制端与所述两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
  3. 根据权利要求2所述的栅极驱动电路，其特征在于，所述输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，所述第一时钟控制反相器的正相控制端接入所述第一时钟信号，所述第一时钟控制反相器的反相控制端接入所述第二时钟信号，所述第一时钟控制反相器的输入端接入所述上级扫描驱动信号，所述第一时钟控制反相器的输出端连接所述第二时钟控制反相器的输出端，所述第二时钟控制反相器的正相控制端接入所述第二时钟信号，所述第二时钟控制反相器的反相控制端接入第一时钟信号，所述第一反相器的输入端连接所述第一时钟控制反相器的输出端和所述第二时钟控制反相器的输出端，所述第一反相器的输出端连接所述第二时钟控制反相器的输入端，并输出所述第一控制信号，其中所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个内设置有连接于所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个的输出端与参考电位之间的所述两个开关组件。
  4. 根据权利要求3所述的栅极驱动电路，其特征在于，
    所述第一时钟控制反相器包括第一P型开关管、第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管、第三N型开关管以及第四N型开关管；
    所述第一P型开关管控制端与所述第四P型开关管的控制端相连接，并接入所述第二时钟信号，所述第二P型开关管的控制端和所述第四P型开关管的控制端相连接，并接入所述上级扫描驱动信号，所述第一P型开关管的第一传输端和所述第三P型开关管的第一传输端接入高参考电位，所述第二P型开关管的第一传输端与所述第一P型开关管的第二传输端相连接，所述第四P型开关管的第一传输端和所述第三P型开关管的第二传输端相连接，所述第二P型开关管的第二传输端和所述第四P型开关管的第二传输端连接所述第一时钟控制反相器的输出端；
    所述第一N型开关管的控制端与所述第四N型开关管的控制端相连接，并接入所述上级扫描驱动信号，所述第二N型开关管和所述第三N型开关管的控制端相连接，并接入所述第一时钟信号，所述第二N型开关管的第一传输端和所述第四N型开关管的第一传输端接入低参考电位，所述第一N型开关管的第一传输端与所述第二N型开关管的第二传输端相连接，所述第三N型开关管的第一传输端与所述第四N型开关管的第二传输端相连接，所述第一N型开关管的第二传输端和所述第四N型开关管的第二传输端连接所述第一时钟控制反相器的输出端。
  5. 根据权利要求3所述的栅极驱动电路，其特征在于，
    所述第二时钟控制反相器包括第五P型开关管、第六P型开关管、七P型开关管、第八P型开关管、第五N型开关管、第六N型开关管，第七N型开关管、第八N型开关管；
    所述第五P型开关管的控制端与和第八P型开关管的控制端相连接，并接入所述第一控制信号，所述第六P型开关管的控制端与第七P型开关管的控制端相连接，并接入所述第一时钟信号，其中所述第五P型开关管的第一传输端和所述第七P型开关管的第一传输端接入高参考点位，所述第五P型开关管的第二传输端与所述第六P型开关管的第一传输端相连接，所述第八P型开关管的第一传输端与所述第七P型开关管的第二传输端相连接，所述第八P型开关管的第二传输端和所述第六P型开关管的第二传输端连接所述第二时钟控制反相器的输出端；
    所述第五N型开关管的控制端与第八N型开关管的控制端相连接，并接入所述第二时钟信号，所述第六N型开关管的控制端与第七N型开关管的控制端相连接，并接入所述第一控制信号，所述第六N型开关管的第一传输端和所述第八N型开关管的第一传输端接入低参考电位，所述第五N型开关管的第一传输端与所述第六N型开关管的第二传输端相连接，所述第八N型开关管第二传输端与所述第七N型开关管的第一传输端相连接，所述第五N型开关管第二传输端和所述第七N型开关管的第二传输端连接所述第二时钟控制反相器的输出端。
  6. 根据权利要求3所述的栅极驱动电路，其特征在于，
    所述信号处理电路为一与非门，所述与非门电路的第一输入端接入所述第一控制信号，所述与非门电路的第二输入端接入所述第三时钟信号，所述与非门电路的输出端输出所述第二控制信号，所述与非门电路包括设置于所述与非门电路的输出端与参考电位之间的所述两个开关组件。
  7. 根据权利要求6所述的栅极驱动电路，其特征在于，
    所述信号处理电路包括第九P型开关管、第十P型开关管、第九N型开关管、第十N型开关管、第十一N型开关管、第十二N型开关管；
    所述第九P型开关管的控制端接入所述第一控制信号，所述第十P型开关管的控制端接入所述第三时钟信号，所述第九P型开关管的第一传输端和所述第十P型开关管的第一传输端端接入高参考电位，所述第九P型开关管的第二传输和所述第十P型开关管的第二传输端与所述与非门的输出端相连接；
    所述第九N型开关管的控制端和第十二N型开关管的控制端相连接，并接入所述第一控制信号，所述第十N型开关管的控制端和第十一N型开关管的控制端相连接，并接入所述第三时钟信号，所述第十N型开关管的第一输入端和所述第十二N型开关管的第一输入端接入低参考电位，所述第九N型开关管的第一传输端与所述第十N型开关管的第二传输端相连接，所述第十一N型开关管的第一传输端连接于所述第十二N型开关管的第二传输端，所述第九N型开关管的第二输出端与所述第十一N型开关管的第二输出端连接所述与非门的输出端。
  8. 根据权利要求2所述的栅极驱动电路，其特征在于，
    所述信号处理电路为一与非门，所述与非门电路的第一输入端接入所述第一控制信号，所述与非门电路的第二输入端接入所述第三时钟信号，所述与非门电路的输出端输出所述第二控制信号，所述与非门电路包括设置于所述与非门电路的输出端与参考电位之间的所述两个开关组件。
  9. 根据权利要求8所述的栅极驱动电路，其特征在于，
    所述信号处理电路包括第一P型开关管、第二P型开关管、第一N型开关管、第二N型开关管、第三N型开关管、第四N型开关管；
    所述第一P型开关管的控制端接入所述第一控制信号，所述第二P型开关管的控制端接入所述第三时钟信号，所述第一P型开关管的第一传输端和所述第二P型开关管的第一传输端端接入高参考电位，所述第一P型开关管的第二传输和所述第二P型开关管的第二传输端与所述与非门的输出端相连接；
    所述第一N型开关管的控制端和第四N型开关管的控制端相连接，并接入所述第一控制信号，所述第二N型开关管的控制端和第三N型开关管的控制端相连接，并接入所述第三时钟信号，所述第二N型开关管的第一输入端和所述第四N型开关管的第一输入端接入低参考电位，所述第一N型开关管的第一传输端与所述第二N型开关管的第二传输端相连接，所述第三N型开关管的第一传输端连接于所述第四N型开关管的第二传输端，所述第一N型开关管的第二输出端与所述第三N型开关管的第二输出端连接所述与非门的输出端。
  10. 根据权利要求2所述的栅极驱动电路，其特征在于，
    所述输出缓冲电路包括依次串联的奇数个第二反相器，接近所述信号处理电路的第二反向器的输入端接入所述第二控制信号，所述远离信号处理电路的第二反相器输出端输出所述本级扫描驱动信号。
  11. 一种液晶显示器，其特征在于，所述液晶显示器包括多个级联设置的栅极驱动电路，所述栅极驱动电路包括：输入与锁存电路、电性连接所述输入与锁存电路的信号处理电路以及电性连接所述信号处理电路的输出缓冲电路；
    所述输入与锁存电路根据上级扫描驱动信号、第一时钟信号以及与所述第一时钟信号反相的第二时钟信号输出第一控制信号，所述信号处理电路根据所述第一控制信号以及第三时钟信号输出第二控制信号，所述输出缓冲电路根据所述第二控制信号输出本级扫描驱动信号；
    其中，所述输入与锁存电路或所述信号处理电路包括并联设置的两个开关组件，其中每一所述开关组件分别包括串联设置的两个开关管，所述两个开关组件的一开关组件的两个开关管的控制端与所述两个开关组件的另一开关组件的两个开关管的控制端交叉连接。
  12. 根据权利要求11所述的液晶显示器，其特征在于，所述输入与锁存电路包括：第一时钟控制反相器、第二时钟控制反相器以及第一反相器，所述第一时钟控制反相器的正相控制端接入所述第一时钟信号，所述第一时钟控制反相器的反相控制端接入所述第二时钟信号，所述第一时钟控制反相器的输入端接入所述上级扫描驱动信号，所述第一时钟控制反相器的输出端连接所述第二时钟控制反相器的输出端，所述第二时钟控制反相器的正相控制端接入所述第二时钟信号，所述第二时钟控制反相器的反相控制端接入第一时钟信号，所述第一反相器的输入端连接所述第一时钟控制反相器的输出端和所述第二时钟控制反相器的输出端，所述第一反相器的输出端连接所述第二时钟控制反相器的输入端，并输出所述第一控制信号，其中所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个内设置有连接于所述第一时钟控制反相器和所述第二时钟控制反相器的至少一个的输出端与参考电位之间的所述两个开关组件。
  13. 根据权利要求12所述的液晶显示器，其特征在于，
    所述第一时钟控制反相器包括第一P型开关管、第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管、第三N型开关管以及第四N型开关管；
    所述第一P型开关管控制端与所述第四P型开关管的控制端相连接，并接入所述第二时钟信号，所述第二P型开关管的控制端和所述第四P型开关管的控制端相连接，并接入所述上级扫描驱动信号，所述第一P型开关管的第一传输端和所述第三P型开关管的第一传输端接入高参考电位，所述第二P型开关管的第一传输端与所述第一P型开关管的第二传输端相连接，所述第四P型开关管的第一传输端和所述第三P型开关管的第二传输端相连接，所述第二P型开关管的第二传输端和所述第四P型开关管的第二传输端连接所述第一时钟控制反相器的输出端；
    所述第一N型开关管的控制端与所述第四N型开关管的控制端相连接，并接入所述上级扫描驱动信号，所述第二N型开关管和所述第三N型开关管的控制端相连接，并接入所述第一时钟信号，所述第二N型开关管的第一传输端和所述第四N型开关管的第一传输端接入低参考电位，所述第一N型开关管的第一传输端与所述第二N型开关管的第二传输端相连接，所述第三N型开关管的第一传输端与所述第四N型开关管的第二传输端相连接，所述第一N型开关管的第二传输端和所述第四N型开关管的第二传输端连接所述第一时钟控制反相器的输出端。
  14. 根据权利要求12所述的液晶显示器，其特征在于，
    所述第二时钟控制反相器包括第五P型开关管、第六P型开关管、七P型开关管、第八P型开关管、第五N型开关管、第六N型开关管，第七N型开关管、第八N型开关管；
    所述第五P型开关管的控制端与和第八P型开关管的控制端相连接，并接入所述第一控制信号，所述第六P型开关管的控制端与第七P型开关管的控制端相连接，并接入所述第一时钟信号，其中所述第五P型开关管的第一传输端和所述第七P型开关管的第一传输端接入高参考点位，所述第五P型开关管的第二传输端与所述第六P型开关管的第一传输端相连接，所述第八P型开关管的第一传输端与所述第七P型开关管的第二传输端相连接，所述第八P型开关管的第二传输端和所述第六P型开关管的第二传输端连接所述第二时钟控制反相器的输出端；
    所述第五N型开关管的控制端与第八N型开关管的控制端相连接，并接入所述第二时钟信号，所述第六N型开关管的控制端与第七N型开关管的控制端相连接，并接入所述第一控制信号，所述第六N型开关管的第一传输端和所述第八N型开关管的第一传输端接入低参考电位，所述第五N型开关管的第一传输端与所述第六N型开关管的第二传输端相连接，所述第八N型开关管第二传输端与所述第七N型开关管的第一传输端相连接，所述第五N型开关管第二传输端和所述第七N型开关管的第二传输端连接所述第二时钟控制反相器的输出端。
  15. 根据权利要求14所述的液晶显示器，其特征在于，
    所述信号处理电路为一与非门，所述与非门电路的第一输入端接入所述第一控制信号，所述与非门电路的第二输入端接入所述第三时钟信号，所述与非门电路的输出端输出所述第二控制信号，所述与非门电路包括设置于所述与非门电路的输出端与参考电位之间的所述两个开关组件。
  16. 根据权利要求15所述的液晶显示器，其特征在于，
    所述信号处理电路包括第九P型开关管、第十P型开关管、第九N型开关管、第十N型开关管、第十一N型开关管、第十二N型开关管；
    所述第九P型开关管的控制端接入所述第一控制信号，所述第十P型开关管的控制端接入所述第三时钟信号，所述第九P型开关管的第一传输端和所述第十P型开关管的第一传输端端接入高参考电位，所述第九P型开关管的第二传输和所述第十P型开关管的第二传输端与所述与非门的输出端相连接；
    所述第九N型开关管的控制端和第十二N型开关管的控制端相连接，并接入所述第一控制信号，所述第十N型开关管的控制端和第十一N型开关管的控制端相连接，并接入所述第三时钟信号，所述第十N型开关管的第一输入端和所述第十二N型开关管的第一输入端接入低参考电位，所述第九N型开关管的第一传输端与所述第十N型开关管的第二传输端相连接，所述第十一N型开关管的第一传输端连接于所述第十二N型开关管的第二传输端，所述第九N型开关管的第二输出端与所述第十一N型开关管的第二输出端连接所述与非门的输出端。
  17. 根据权利要求11所述的栅极驱动电路，其特征在于，
    所述信号处理电路为一与非门，所述与非门电路的第一输入端接入所述第一控制信号，所述与非门电路的第二输入端接入所述第三时钟信号，所述与非门电路的输出端输出所述第二控制信号，所述与非门电路包括设置于所述与非门电路的输出端与参考电位之间的所述两个开关组件。
  18. 根据权利要求17所述的栅极驱动电路，其特征在于，
    所述信号处理电路包括第一P型开关管、第二P型开关管、第一N型开关管、第二N型开关管、第三N型开关管、第四N型开关管；
    所述第一P型开关管的控制端接入所述第一控制信号，所述第二P型开关管的控制端接入所述第三时钟信号，所述第一P型开关管的第一传输端和所述第二P型开关管的第一传输端端接入高参考电位，所述第一P型开关管的第二传输和所述第二P型开关管的第二传输端与所述与非门的输出端相连接；
    所述第一N型开关管的控制端和第四N型开关管的控制端相连接，并接入所述第一控制信号，所述第二N型开关管的控制端和第三N型开关管的控制端相连接，并接入所述第三时钟信号，所述第二N型开关管的第一输入端和所述第四N型开关管的第一输入端接入低参考电位，所述第一N型开关管的第一传输端与所述第二N型开关管的第二传输端相连接，所述第三N型开关管的第一传输端连接于所述第四N型开关管的第二传输端，所述第一N型开关管的第二输出端与所述第三N型开关管的第二输出端连接所述与非门的输出端。
  19. 根据权利要求11所述的栅极驱动电路，其特征在于，
    所述输出缓冲电路包括依次串联的奇数个第二反相器，接近所述信号处理电路的第二反向器的输入端接入所述第二控制信号，所述远离信号处理电路的第二反相器输出端输出所述本级扫描驱动信号。
PCT/CN2016/074558 2016-01-28 2016-02-25 一种基于栅极驱动电路及其液晶显示器 Ceased WO2017128470A1 (zh)

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