WO2017071023A1 - 一种薄膜晶体管、阵列基板及其制成方法 - Google Patents

一种薄膜晶体管、阵列基板及其制成方法 Download PDF

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Publication number
WO2017071023A1
WO2017071023A1 PCT/CN2015/097899 CN2015097899W WO2017071023A1 WO 2017071023 A1 WO2017071023 A1 WO 2017071023A1 CN 2015097899 W CN2015097899 W CN 2015097899W WO 2017071023 A1 WO2017071023 A1 WO 2017071023A1
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layer
buffer layer
copper layer
power
gate
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French (fr)
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周志超
武岳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present application relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, and a method of fabricating the same.
  • TFT thin film transistor
  • the array substrate of the transistor (abbreviation: TFT) is used as a switch of the liquid crystal display panel, and its structure and process are crucial to the display effect of the liquid crystal display panel.
  • TFT the transistor
  • the gate, the source, and the drain of the TFT are often laminated with a layer of molybdenum and copper or a layer of titanium and copper, wherein the molybdenum layer and the titanium layer serve as a buffer layer.
  • a buffer layer and a copper layer are separately deposited, and then a pattern corresponding to the gate, source, or drain is obtained by etching. During the etching process, it is easy to cause the photoresist to fall off, which leads to over-etching.
  • the present application provides a thin film transistor, an array substrate, and a method of fabricating the same, which can prevent photo-resistance from falling off during etching.
  • a first aspect of the present application provides a thin film transistor including a gate, a source, and a drain, wherein the source and the drain are both disposed on a same side of the gate, wherein the gate includes a sequential a stacked first buffer layer, a first copper layer, a second copper layer, and a second buffer layer, and the second buffer layer is disposed adjacent to the source and drain sides; and/or the source
  • the drain and the drain each include a first buffer layer, a first copper layer, a second copper layer and a second buffer layer which are sequentially stacked, and the first buffer layer is disposed on a side close to the gate; A first copper layer is deposited at a first power, the second copper layer is deposited at a second power, and the first power is higher than the second power.
  • the first power is between 50 KW and 70 KW
  • the second power is between 20 KW and 40 KW.
  • the first buffer layer has a thickness between 100 ⁇ and 200 ⁇
  • the first copper layer has a thickness between 3000 ⁇ and 5000 ⁇
  • the second copper layer has a thickness between 1000 ⁇ and 2000 ⁇ .
  • the thickness of the two buffer layers is between 100 ⁇ and 200 ⁇ .
  • the first buffer layer and the second buffer layer are a molybdenum film, a titanium film, or a stacked molybdenum film and a titanium film.
  • At least one of the first buffer layer, the first copper layer, the second copper layer and the second buffer layer is made by physical vapor deposition.
  • a gate insulating layer and a channel layer disposed between the gate and the source and the drain are further included.
  • a second aspect of the present application provides an array substrate including a substrate and a plurality of thin film transistors disposed on the substrate, wherein the thin film transistor is the thin film transistor described above.
  • a third aspect of the present invention provides a method of fabricating an array substrate, comprising: forming a gate of a thin film transistor on a substrate; forming a source and a drain of the thin film transistor on the gate; wherein the forming a gate, and/or forming a source and a drain, comprising: sequentially forming a first buffer layer, a first copper layer, a second copper layer, and a second buffer layer, wherein the second power is made, the second The copper layer is made at a second power, and the first power is higher than the second power; a photoresist is coated on the second buffer layer and etched.
  • At least one of the first buffer layer, the first copper layer, the second copper layer and the second buffer layer is made by physical vapor deposition.
  • the first power is between 50 KW and 70 KW
  • the second power is between 20 KW and 40 KW
  • the thickness of the first buffer layer is between 100 ⁇ and 200 ⁇
  • the thickness of the first copper layer is Between 3000 ⁇ and 5,000 ⁇
  • the thickness of the second copper layer is between 1000 ⁇ and 2000 ⁇
  • the thickness of the second buffer layer is between 100 ⁇ and 200 ⁇ .
  • At least one of the gate, the source and the drain of the TFT is formed by using a first buffer layer, a first copper layer, a second copper layer and a second buffer layer structure, wherein the first copper layer is made into a power It is higher in power than the second copper layer.
  • the second buffer layer protects the second copper layer, thereby avoiding the problem of directly etching the copper layer and causing the photoresist to fall off.
  • the second copper layer is made to have a lower power, the surface flatness of the second copper layer is ensured, thereby ensuring the uniformity and flatness of the second buffer layer to the second copper layer, further preventing the photoresist from falling off.
  • the problem, and the high fabrication power of the first copper layer also ensures the efficiency of TFT generation.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present application.
  • FIG. 2 is a schematic structural view of an embodiment of a thin film transistor of the present application.
  • FIG. 3 is a schematic structural view of another embodiment of a thin film transistor of the present application.
  • FIG. 4 is a flow chart of an embodiment of a method for fabricating an array substrate of the present application.
  • Figure 5 is a flow diagram of the sub-steps of steps 410 and/or 420 shown in Figure 4.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate of the present application.
  • the array substrate 100 includes a substrate 110 and a plurality of TFTs. 120 (FIG. 1 exemplarily shows one TFT 120 on the substrate 110 for explanation).
  • the substrate 110 may be a transparent substrate made of a glass substrate or other insulating material.
  • TFT 120 includes a gate 121, a source 122, and a drain 123 disposed on the substrate 110.
  • the source 122 and the drain 123 are both disposed on the same side of the gate 121 away from the substrate 110.
  • the TFT 120 may further include a gate insulating layer disposed between the gate 121 and the source 122 and the drain 1225 (English: gate Insulator, abbreviated as: GI) 124, channel layer 125.
  • the gate insulating layer 124 is stacked between the gate electrode 121 and the channel layer 125 to insulate the gate electrode 121 and the channel layer 125.
  • the source 122 and the drain 123 are located on the same layer on the channel layer 125.
  • the gate 121 obtains a voltage greater than or equal to the turn-on voltage
  • the channel layer 125 induces electrons, and the source 122 and the drain 123 are guided. through.
  • the gate insulating layer 124 may be an aluminum nitride (chemical formula: AlN) film, and the channel layer 125 may be composed of a metal oxide, such as indium gallium zinc oxide (English: indium) Gallium zinc oxide, referred to as: IGZO).
  • AlN aluminum nitride
  • IGZO indium gallium zinc oxide
  • TFT 120 further includes an etch stop layer 126 disposed on the channel layer 125 and a passivation layer 127 overlying the source and drain electrodes 122 and 123, and the etch stop layer 126 is disposed at the source Between the pole 122 and the drain 123.
  • the source, the drain, and the pixel electrode may be an integral structure composed of a transparent conductive film.
  • the patterns of the gate electrode 121, the source electrode 122 and the drain electrode 123 are all obtained by etching, such as wet etching, dry etching, or the like.
  • etching such as wet etching, dry etching, or the like.
  • FIG. 2 is a schematic structural diagram of any one of the gate, the source and the drain in an embodiment of the thin film transistor of the present application.
  • the gate electrode 121, the source electrode 122, and the drain electrode 123 of the present embodiment each include a first buffer layer a1, a first copper layer a2, a second copper layer a3, and a second buffer layer a4 which are sequentially stacked.
  • the second buffer layer a4 of the gate electrode 121 is disposed on a side close to the source electrode 122 and the drain electrode 123, and the first buffer layer a1 of the source electrode 122 and the drain electrode 123 is disposed on a side close to the gate electrode 121.
  • the first copper layer a2 is deposited at a first power, that is, the first copper layer a2 is deposited by the deposition apparatus operating at a first power.
  • the second copper layer is deposited at a second power, that is, the second copper layer a3 is deposited by the deposition apparatus operating at a second power.
  • the first power is higher than the second power.
  • the first buffer layer a1, the first copper layer a2, the second copper layer a3, and the second buffer layer a4 is used, for example, physical vapor deposition (English: Physical Vapor) Deposition, abbreviated as: PVD) is generated by deposition methods.
  • PVD Physical vapor deposition
  • the first buffer layer a1 and the second buffer layer a4 are both metal layers, which can be used to protect the copper layer and prevent copper ion diffusion of the copper layer.
  • the first buffer layer a1 and the second buffer layer a4 may be a molybdenum film, a titanium film, or a stacked molybdenum film and a titanium film.
  • the first buffer layer a1 includes a stacked molybdenum film a11 and a titanium film a12
  • the second buffer layer a4 includes a stacked molybdenum film a41 and a titanium film a42.
  • the first power is preferably, but not limited to, between 50 KW and 70 KW
  • the second power is preferably, but not limited to, between 20 KW and 40 KW.
  • the thickness of the first buffer layer is preferably, but not limited to, between 100 ⁇ and 200 ⁇
  • the thickness of the first copper layer is preferably, but not limited to, between 300 ⁇ and 500 ⁇
  • the thickness of the second copper layer is preferably but not limited.
  • the thickness of the second buffer layer is preferably, but not limited to, between 100 ⁇ and 200 ⁇ .
  • the first power is 52.5 KW and the second power is 32.5 KW.
  • the first buffer layer has a thickness of 140 ⁇
  • the first copper layer has a thickness of 3750 ⁇
  • the second copper layer has a thickness of 1250 ⁇
  • the second buffer layer has a thickness of 140 ⁇ .
  • the gate, the source, and the drain of the TFT are not necessarily all set to the above structure.
  • the gate of the TFT may be provided with the above structure only according to the actual application, or only the source and the drain of the TFT may be provided as described above.
  • the structure in which the gate layer, the source and the drain of the TFT are sandwiched by the first buffer layer and the second buffer layer can achieve the following effects:
  • the first buffer layer and the second buffer layer can improve the adhesion of the corresponding copper layer to the substrate or other structures, and prevent the copper ions at the poles from diffusing, thereby preventing the I-V characteristics from deteriorating;
  • the second buffer layer protects the copper layer.
  • the metal etching angle (English: Taper), and the GI wire is also prevented from being bad, thereby reducing static electricity. Protection (English abbreviation: ESD) risk to ensure yield;
  • the first copper layer and the second copper layer having different powers are used as the conductive layer for the gate, the source and the drain of the TFT, and the following analysis is performed:
  • the high-power deposited first copper layer can increase the fabrication rate of the copper layer, thereby increasing the production efficiency of the TFT.
  • the local undulation of the surface of the copper layer is large as shown in Figs. 2 and 3.
  • the uniformity of the thickness of the first copper layer is generally 15%, which is difficult to form a theoretical absolute flatness. surface.
  • the buffer layer acts as an auxiliary layer, its thickness is relatively small relative to the copper layer. Taking the thickness of the first copper layer as 5000 ⁇ , the difference between the first copper film thickness region and the thin region is often more than 750 ⁇ , and the second buffer layer generally does not exceed 300 ⁇ . ⁇ (copper acid etch buffer layer is slower, so the buffer layer tends to be thinner).
  • the second buffer layer often cannot effectively cover the surface of the first copper layer, and the first copper layer is partially not covered with the second buffer layer. Therefore, during the etching process, the portion of the first copper layer not covered with the second buffer layer tends to be preferentially attacked by the acid solution, so that the photoresist is still easily detached from the underlying metal. Therefore, a second copper layer of lower power is continuously deposited over the first copper layer. The low power deposition can effectively improve the surface flatness of the second copper layer, thereby making the second buffer layer on the second copper layer more uniform and complete.
  • the copper layer of the present application is first made of high power and then made of the remaining part by low power, which ensures the production efficiency of the copper layer and the production tact (Tact Time) also ensures the flatness of the copper layer surface and further prevents the photoresist from falling off.
  • FIGS. 2 and 3 only schematically represent the actual normal state of the surface of the high-power copper layer, and does not mean that the surface of the first copper layer of each TFT of the present application forms the undulations shown in FIGS. 2 and 3. Moreover, it is worth noting that the undulation is not a defining feature of the first copper layer of the present application.
  • the first copper layer of the present application is theoretically made flat, and the undulation is only due to the high power of the first copper layer. .
  • the present application also provides an embodiment of a TFT, specifically, the structure of the TFT and the structure of the TFT in the above embodiment, and thus will not be described herein.
  • FIG. 4 is a flow chart of an embodiment of a method for fabricating an array substrate of the present application
  • FIG. 5 is a flow chart of sub-steps of steps 410 and/or 420 shown in FIG. The method includes:
  • the forming the gate in the above 410, and/or the forming the source and the drain in the above 420 may include the following sub-steps:
  • At least one of the first buffer layer, the first copper layer, the second copper layer, and the second buffer layer is formed by deposition such as PVD.
  • the first buffer layer and the second buffer layer are both metal layers, such as a molybdenum film, a titanium film, or a stacked molybdenum film and a titanium film.
  • the first power is preferably, but not limited to, between 50 KW and 70 KW
  • the second power is preferably, but not limited to, between 20 KW and 40 KW.
  • the thickness of the first buffer layer is preferably, but not limited to, between 100 ⁇ and 200 ⁇
  • the thickness of the first copper layer is preferably, but not limited to, between 300 ⁇ and 500 ⁇
  • the thickness of the second copper layer is preferably but not limited.
  • the thickness of the second buffer layer is preferably, but not limited to, between 100 ⁇ and 200 ⁇ .
  • the etching method includes wet etching and dry etching.
  • the manufacturing method may further include: forming a gate insulating layer and a channel layer on the gate, wherein the gate insulating layer is stacked on the gate and the channel Between the layers, the gate insulating layer may be an AlN film; the above 420 specifically forms a source and a drain on the channel layer.
  • the forming method may further include: forming an etch stop layer on the source and the drain on the channel layer, and the etch stop layer is provided with the source and the drain A passivation layer is formed on the source and drain.
  • At least one of the gate, the source and the drain of the TFT is formed by using a first buffer layer, a first copper layer, a second copper layer and a second buffer layer structure, wherein the first copper layer is made into a power It is higher in power than the second copper layer.
  • the second buffer layer protects the second copper layer, thereby avoiding the problem of directly etching the copper layer and causing the photoresist to fall off.
  • the second copper layer is made to have a lower power, the surface flatness of the second copper layer is ensured, thereby ensuring the uniformity and flatness of the second buffer layer to the second copper layer, further preventing the photoresist from falling off.
  • the problem, and the high fabrication power of the first copper layer also ensures the efficiency of TFT generation.

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Abstract

一种薄膜晶体管（120）、阵列基板（100）及其制成方法，其中，该薄膜晶体管（120）包括栅极（121）、源极（122）和漏极（123），该源极（122）和漏极（123）均设置在该栅极（121）的同一侧，其中，该栅极（121）包括依序叠置的第一缓冲层（a1）、第一铜层（a2）、第二铜层（a3）及第二缓冲层（a4），且该第二缓冲层（a4）设置在靠近该源极（122）和漏极（123）一侧；和/或，该源极（122）和漏极（123）均包括依序叠置的第一缓冲层（a1）、第一铜层（a2）、第二铜层（a3）及第二缓冲层（a4），且该第一缓冲层（a1）设置在靠近该栅极（121）一侧；该第一铜层（a2）以第一功率沉积得到，该第二铜层（a3）以第二功率沉积得到，且该第一功率高于该第二功率。通过该方式，能够防止蚀刻时光阻脱落。

Description

一种薄膜晶体管、阵列基板及其制成方法
【技术领域】
本申请涉及显示技术领域，特别是涉及一种薄膜晶体管、阵列基板及其制成方法。
【背景技术】
在液晶显示领域中，设有薄膜晶体管（英文：thin film transistor，简称：TFT）的阵列基板作为液晶显示面板的开关，其结构与工艺对该液晶显示面板的显示效果影响至关重要。而为响应目前大尺寸化需求，且降低信号传输过程中的RC延迟等问题，低成本，低阻抗铜显然制成TFT的栅极、源极、漏极的不二选择。
在目前的TFT制程工艺中，TFT的栅极、源极、漏极常采用钼层与铜层叠置或钛层与铜层叠置的结构，其中，钼层和钛层作为缓冲层。在TFT制作过程中，先分别沉积缓冲层和铜层，再经蚀刻得到对应栅极、源极、或漏极的图案。在蚀刻过程中，易产生光阻脱落，进而导致过刻。
【发明内容】
本申请提供一种薄膜晶体管、阵列基板及其制成方法，能够防止蚀刻时光阻脱落。
本申请第一方面提供一种薄膜晶体管，其中，包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。
其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间。
其中，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
其中，所述第一缓冲层和所述第二缓冲层为钼膜、钛膜、或叠置的钼膜和钛膜。
其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
其中，还包括设置在所述栅极与所述源极和漏极之间的栅极绝缘层和沟道层。
本申请第二方面提供一种阵列基板，包括基板和设置于基板上的多个薄膜晶体管，其中，所述薄膜晶体管为上述的薄膜晶体管。
本申请第三方面提供一种阵列基板的制成方法，包括：在基板上形成薄膜晶体管的栅极；在所述栅极上形成所述薄膜晶体管的源极和漏极；其中，所述形成栅极，和/或形成源极和漏极包括：依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率；在所述第二缓冲层上涂覆光阻，并进行蚀刻。
其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
上述方案中，TFT的栅极、源极、漏极的至少一极采用第一缓冲层、第一铜层、第二铜层及第二缓冲层结构构成，其中第一铜层的制成功率比第二铜层的制成功率高。第二缓冲层对第二铜层起到保护作用，避免了直接蚀刻铜层而导致光阻脱落问题。而且，由于第二铜层的制成功率较低，保证了第二铜层的表面平整性，进而保证第二缓冲层对第二铜层覆盖的均匀性和平整性，进一步防止了光阻脱落问题，并且第一铜层的高制成功率也保证了TFT的生成效率。
【附图说明】
图1是本申请阵列基板一实施方式的结构示意图；
图2是本申请薄膜晶体管一实施方式的结构示意图；
图3是本申请薄膜晶体管另一实施方式的结构示意图；
图4是本申请阵列基板的制成方法一实施方式的流程图；
图5是图4所示的步骤410和/或420的子步骤流程图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请阵列基板一实施方式的结构示意图。本实施方式中，阵列基板100包括基板110和多个TFT 120（图1仅示范性示出基板110上的一个TFT 120进行说明）。其中，所述基板110可以为玻璃基板或其他绝缘材料构成的透明基板。TFT 120包括设置在所述基板110上的栅极121、源极122、漏极123。该源极122和漏极123均设置在该栅极121远离基板110的同一侧。
本实施方式中，TFT 120还可包括设置在栅极121与源极122、漏极1225之间的栅绝缘层（英文：gate insulator，简称：GI）124、沟道层125。所述栅绝缘层124叠置在所述栅极121和沟道层125之间，以将所述栅极121和沟道层125绝缘。所述源极122和漏极123位于沟道层125上的同一层，当栅极121获得大于或等于开启电压的电压时，沟道层125感应出电子，使源极122和漏极123导通。其中，该栅绝缘层124可为氮化铝（化学式：AlN）薄膜，该沟道层125可由金属氧化物构成，例如为铟镓锌氧化物（英文：indium gallium zinc oxide，简称：IGZO）。
可选地，TFT 120还包括设置在所述沟道层125上的刻蚀阻挡层126和覆盖在所述源极122和漏极123上的钝化层127，且所述刻蚀阻挡层126设置在所述源极122和漏极123之间。
可选地，为增加像素电极的开口率，源极、漏极和像素电极可是一体结构，由透明导电薄膜构成。
上述栅极121、源极122和漏极123的图案均由蚀刻如湿刻、干刻等工艺而得到。具体地，请结合参阅图2，图2是本申请薄膜晶体管一实施方式中栅极、源极、漏极的任意一极的结构示意图。本实施方式的栅极121、源极122及漏极123均包括以下结构：依序叠置的第一缓冲层a1、第一铜层a2、第二铜层a3及第二缓冲层a4。其中，栅极121的第二缓冲层a4设置在靠近所述源极122和漏极123一侧，源极122和漏极123的第一缓冲层a1设置在靠近所述栅极121一侧。该第一铜层a2以第一功率沉积得到，即由沉积设备以第一功率运作时沉积该第一铜层a2。所述第二铜层以第二功率沉积得到，即由沉积设备以第二功率运作时沉积该第二铜层a3。且所述第一功率高于所述第二功率。
具体地，第一缓冲层a1、第一铜层a2、第二铜层a3及第二缓冲层a4中的至少一层采用如物理气相沉积（英文：Physical Vapor Deposition，简称：PVD）等沉积方式生成。
其中，第一缓冲层a1和所述第二缓冲层a4均为金属层，可用于保护铜层并阻止铜层的铜离子扩散。具体，第一缓冲层a1和所述第二缓冲层a4可为钼膜、钛膜、或叠置的钼膜和钛膜。如在图3所示的另一实施方式中，该第一缓冲层a1包括叠置的钼膜a11和钛膜a12，第二缓冲层a4包括叠置的钼膜a41和钛膜a42。
本实施方式中，该第一功率优选但不限定位于50KW至70KW之间，所述第二功率优选但不限定位于20KW至40KW之间。所述第一缓冲层的厚度优选但不限定位于100Å至200Å之间，所述第一铜层的厚度优选但不限定位于300Å至500Å之间，所述第二铜层的厚度优选但不限定位于100Å至200Å之间，所述第二缓冲层的厚度优选但不限定位于100Å至200Å之间。在一应用实施例中，第一功率为52.5KW，所述第二功率为32.5KW。所述第一缓冲层的厚度为140Å，所述第一铜层的厚度为3750Å，所述第二铜层的厚度为1250Å，所述第二缓冲层的厚度为140Å。
可以理解的是，在其他实施方式中，TFT的栅极、源极、漏极未必均设置为上述结构。在其他实施方式中，还可根据实际应用情况，仅对TFT的栅极设置为上述结构，或者仅对TFT的源极和漏极设置为上述结构。
针对上述TFT的栅极、源极和漏极采用第一缓冲层和第二缓冲层将铜层夹置其中的结构，可达如下效果：
1）上述第一缓冲层、第二缓冲层可改善了对应铜层与基板或其他结构的附着性，且阻止其所在极的铜离子扩散，进而防止了I-V 特性下降；
2）第二缓冲层对铜层起到保护作用，在蚀刻时，利用铜层与第二缓冲层的蚀刻选择比降低金属蚀刻下角（英文：Taper），也避免GI搭线不良，进而减少静电防护（英文简称：ESD）风险，以保证良率；
3）对于边缘场开关(英文：Fringe Field Switching，简称：FFS)或平面转换（英文：In-Plane Switching，简称：IPS）等液晶显示技术需要使用到的有机平坦层（英文简称：PFA）材料时，源极和漏极的第二缓冲层可防止其铜层与PFA搭配不良的问题。
针对上述TFT的栅极、源极和漏极采用制成功率不同的第一铜层和第二铜层作为导电层，进行如下分析：
高功率沉积的第一铜层可提高了铜层的制成速率，进而提高了TFT的生产效率。但第一铜层在成膜时会引起铜层表面局部的起伏度较大如图2、3所示，经试验其厚度的均匀性即U%一般为15%，难以形成理论上的绝对平整表面。由于缓冲层作为辅助层，其厚度相对铜层较小。以第一铜层厚度为5000Å为例，其第一铜膜厚区与薄区的差异往往超过750Å，而第二缓冲层一般不超过300 Å(铜酸蚀刻缓冲层速率较慢，因此缓冲层往往较薄)。显然，第二缓冲层往往不能有效地覆盖第一铜层表面，而导致第一铜层局部未覆盖有第二缓冲层。故在蚀刻过程中，未覆盖有第二缓冲层的第一铜层部分往往会受到酸液的择优攻击，使得光阻仍易与底层金属发生脱离。故在第一铜层之上继续沉积制成功率较低的第二铜层。低功率沉积可有效改善第二铜层的表面平整性，进而使得第二铜层上的第二缓冲层覆盖的更加均匀和完整。故本申请铜层先采用高功率制成一部分再由低功率制成剩余部分，即保证了铜层的制成效率及生产节拍（Tact time），也保证了铜层表面平整性，进一步防止光阻脱落问题。
可以理解的是，图2、3仅示意性表示出高功率铜层表面的实际常态，并不代表本申请每个TFT的第一铜层的表面均形成图2、3所示的起伏。而且值得注意的是该起伏非为本申请第一铜层的限定特征，本申请第一铜层理论上是要制成平整的，该起伏仅是由于第一铜层的高功率而产生的效果。
本申请还提供一种TFT的实施例，具体，该TFT的结构与上面实施方式中TFT的结构，故在此不作赘述。
请参阅图4和5，图4是本申请阵列基板的制成方法一实施方式的流程图，图5是图4所示的步骤410和/或420的子步骤流程图。所述方法包括：
410：在基板上形成薄膜晶体管的栅极。
420：在所述栅极上形成所述薄膜晶体管的源极和漏极。
其中，所述上述410中的所述形成栅极，和/或上述420中的所述形成源极和漏极可包括以下子步骤：
411：依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率。
该第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层采用如PVD等沉积方式生成。该第一缓冲层和所述第二缓冲层均为金属层，如为钼膜、钛膜、或叠置的钼膜和钛膜。
本实施方式中，该第一功率优选但不限定位于50KW至70KW之间，所述第二功率优选但不限定位于20KW至40KW之间。所述第一缓冲层的厚度优选但不限定位于100Å至200Å之间，所述第一铜层的厚度优选但不限定位于300Å至500Å之间，所述第二铜层的厚度优选但不限定位于100Å至200Å之间，所述第二缓冲层的厚度优选但不限定位于100Å至200Å之间。
412：在所述第二缓冲层上涂覆光阻，并进行蚀刻。其中，该蚀刻方式包括湿刻和干刻等方式。
在另一实施方式中，在上述410之后，所述制成方法还可包括：在栅极上形成栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间，且所述栅绝缘层可为AlN薄膜；上述420具体为在所述沟道层上形成源极和漏极。
在再一实施方式中，在上述420之后，所述制成方法还可包括：在沟道层上的源极和漏极形成刻蚀阻挡层，且刻蚀阻挡层设置源极和漏极之间；在源极和漏极上形成钝化层。
上述方案中，TFT的栅极、源极、漏极的至少一极采用第一缓冲层、第一铜层、第二铜层及第二缓冲层结构构成，其中第一铜层的制成功率比第二铜层的制成功率高。第二缓冲层对第二铜层起到保护作用，避免了直接蚀刻铜层而导致光阻脱落问题。而且，由于第二铜层的制成功率较低，保证了第二铜层的表面平整性，进而保证第二缓冲层对第二铜层覆盖的均匀性和平整性，进一步防止了光阻脱落问题，并且第一铜层的高制成功率也保证了TFT的生成效率。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种阵列基板，其中，包括基板和设置于基板上的多个薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，
    所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；
    和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；
    所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。
  2. 根据权利要求1所述的阵列基板，其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间。
  3. 根据权利要求1所述的阵列基板，其中，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
  4. 根据权利要求1所述的阵列基板，其中，所述第一缓冲层和所述第二缓冲层为钼膜、钛膜、或叠置的钼膜和钛膜。
  5. 根据权利要求1所述的阵列基板，其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
  6. 根据权利要求1所述的阵列基板，其中，还包括设置在所述栅极与所述源极和漏极之间的栅极绝缘层和沟道层。
  7. 一种薄膜晶体管，其中，包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，
    所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；
    和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；
    所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间。
  9. 根据权利要求7所述的薄膜晶体管，其中，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
  10. 根据权利要求7所述的薄膜晶体管，其中，所述第一缓冲层和所述第二缓冲层为钼膜、钛膜、或叠置的钼膜和钛膜。
  11. 根据权利要求7所述的薄膜晶体管，其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
  12. 根据权利要求7所述的薄膜晶体管，其中，还包括设置在所述栅极与所述源极和漏极之间的栅极绝缘层和沟道层。
  13. 一种阵列基板的制作方法，其中，包括：
    在基板上形成薄膜晶体管的栅极；
    在所述栅极上形成所述薄膜晶体管的源极和漏极；
    其中，所述形成栅极，和/或形成源极和漏极包括：
    依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率；
    在所述第二缓冲层上涂覆光阻，并进行蚀刻。
  14. 根据权利要求13所述的方法，其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
  15. 根据权利要求13所述的方法，其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
  16. 根据权利要求14所述的方法，其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间，所述第一缓冲层的厚度位于100Å至200Å之间，所述第一铜层的厚度位于3000Å至5000Å之间，所述第二铜层的厚度位于1000Å至2000Å之间，所述第二缓冲层的厚度位于100Å至200Å之间。
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