WO2017063347A1 - 鳍式场效应晶体管的制作方法 - Google Patents

鳍式场效应晶体管的制作方法 Download PDF

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WO2017063347A1
WO2017063347A1 PCT/CN2016/078741 CN2016078741W WO2017063347A1 WO 2017063347 A1 WO2017063347 A1 WO 2017063347A1 CN 2016078741 W CN2016078741 W CN 2016078741W WO 2017063347 A1 WO2017063347 A1 WO 2017063347A1
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gate
fin
fin structure
layer
effect transistor
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PCT/CN2016/078741
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English (en)
French (fr)
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李�杰
赵立新
王永刚
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格科微电子（上海）有限公司
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Publication of WO2017063347A1 publication Critical patent/WO2017063347A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

Definitions

  • the present invention relates to the field of semiconductors, and in particular, to a method of fabricating a fin field effect transistor.
  • FIG. 1 to FIG. 4 are schematic diagrams showing the steps of each step of fabricating a fin field effect transistor in the prior art.
  • a substrate 100 is provided, a fin structure 110 is formed on the substrate 100, and the fin structure 110 is covered with a first dielectric layer 200, an upper surface of the first dielectric layer 200 and an upper surface of the fin structure 110. The surface is flush.
  • FIGS. 1 to FIG. 4 are schematic diagrams showing the steps of each step of fabricating a fin field effect transistor in the prior art.
  • a substrate 100 is provided, a fin structure 110 is formed on the substrate 100, and the fin structure 110 is covered with a first dielectric layer 200, an upper surface of the first dielectric layer 200 and an upper surface of the fin structure 110. The surface is flush.
  • the first dielectric layer 200 on both sides of the etched fin structure 110 forms a recess 300 extending in the Y direction, and then the gate layer 400 is laid, and the gate layer 400 covers the first
  • the dielectric layer 200 and the recess 300 are further etched to form the gate structure 410 of the FinFET; in the prior art, the recess 200 extends over the Fin structure and has a large shape and a range.
  • the gate layer 400 needs to etch the gate layer to the bottom of the recess 300 in the process of etching the gate structure 410, that is, the continuous gate layer 400 is cut off, and the required process is difficult, and it is difficult to control the etching.
  • the accuracy is difficult to clean the area where the groove does not need the gate layer, and it is difficult to form a well-controlled gate structure. Therefore, how to form a fin field effect In the transistor, a gate region with a good interface shape can be formed, the etching difficulty of the gate layer is reduced, and the performance of the transistor is improved, which is an urgent problem to be solved in the industry.
  • the present invention provides a method for fabricating a FinFET, characterized in that the method includes:
  • the semiconductor substrate forming at least one fin structure and a dielectric layer located around the fin structure; etching a portion of the dielectric layer on both sides of the fin structure to form grooves on both sides of the fin structure Filling the gate layer; etching the gate layer to form a gate structure covering the surface of the fin structure between the bottom of the groove and the groove, the gate structure being inverted U-shaped; the gate of the FinFET
  • the upper length of the pole structure in the channel direction is defined by the gate etch; the lower length of the gate structure of the fin field effect transistor in the channel direction is defined by the groove.
  • the bottom width of the gate structure is greater than the top width.
  • the bottom of the groove is from 200 angstroms to 2000 angstroms from the bottom of the fin structure.
  • a portion of the gate layer corresponding to the region around the recess is etched to expose the dielectric layer, and the dielectric layer functions to reduce the etching difficulty of the gate layer.
  • a nitride layer or an oxynitride layer is formed on the upper surface of the fin structure, and the nitride layer or the oxynitride layer functions as a hard mask in the step of etching to form the recess.
  • the formed fin field effect transistor structure there is a nitride layer or an oxynitride layer between the gate structure and the upper surface of the fin structure.
  • At least three adjacent fin structures and a dielectric layer located around the fin structure are formed; wherein the middle fin structure is defined as a channel region, the peripheral fin structure is an auxiliary fin structure, and the middle fin shape
  • the side slope of the structure is: greater than or equal to 82 degrees.
  • a part of the medium between the intermediate fin structure and the auxiliary fin structure is etched a layer, forming a recess; filling the gate layer, etching the gate layer, forming a gate structure covering a surface of the fin structure between the bottom of the groove and the groove, the gate structure being inverted U-shaped.
  • the peripheral fin structure is symmetrical based on an intermediate fin structure
  • the invention has better shape and interface of the gate structure, greatly reduces the process difficulty, can be realized on the existing equipment, and can be compatible with the planar process.
  • FIG. 4 are schematic structural diagrams of steps of fabricating a fin field effect transistor in the prior art
  • FIG. 5 to FIG. 7 are schematic structural diagrams of steps of fabricating a fin field effect transistor according to an embodiment of the present invention.
  • FIG. 8 to FIG. 10 are schematic diagrams showing the steps of fabricating a FinFET in another embodiment of the present invention.
  • the present invention provides a method for fabricating a FinFET, the method comprising: Providing a semiconductor substrate, the semiconductor substrate forming at least one fin structure and a dielectric layer located around the fin structure; etching the fin structure a portion of the dielectric layer on both sides forming a groove on both sides of the fin structure; filling the gate layer; etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin structure between the grooves,
  • the gate structure is inverted U-shaped; the upper length of the gate structure of the fin field effect transistor along the channel direction is defined by gate etching; the gate structure of the fin field effect transistor is lower along the channel direction The length is defined by the groove.
  • FIG. 5 to FIG. 7 are schematic diagrams showing the steps of fabricating the FinFET in an embodiment of the present invention.
  • a fin structure 110' is formed on the semiconductor substrate 100' in the prior art, and a dielectric layer 200' is laid around the fin structure 110', wherein the upper surface of the dielectric layer 200' is flush with the upper surface of the fin structure 110'.
  • a portion of the dielectric layer 200' is etched in a partial region on both sides of the fin structure 110' to form a recess 300' on both sides of the surface of the fin structure 110', using photoresist, exposure, development, etching
  • the method performs the above steps, wherein the size of the groove 300' corresponds to the size of the gate structure.
  • the width of the groove is 100 nm
  • the width of the groove ranges from 30 nm to 100 um
  • the depth of the groove is: 1500A
  • the range of groove depth is: 500A ⁇ 2000A.
  • the surface of the dielectric layer 200' and the surface of the recess 300' cover the gate layer 400'.
  • the material of the gate layer 400' may be polysilicon, metal, or High-K. In the embodiment, polysilicon material is used.
  • the gate layer 400' is etched in FIG. 7 to form a gate structure 410' covering the surface of the fin structure 110' between the bottom of the recess 300' and the recess 300'.
  • the gate structure 410' is inverted U-shaped;
  • the upper length of the gate structure 410' of the field effect transistor along the channel direction Y is defined by the gate etch; the lower length of the gate structure of the fin field effect transistor along the channel direction Y is defined by the recess.
  • the gate layer 400' not etched to the region of the recess 300' is etched by etching the gate, and the dielectric layer 200' can serve as an auxiliary etch gate layer 400';
  • the etching of the gate layer 400' is defined by the recess 300'.
  • the recess 300' functions as an auxiliary etching gate layer 400', and a portion of the gate layer corresponding to the region around the recess. 400' is etched to expose the dielectric layer 200'.
  • a region around the recess 300' is etched to the surface of the dielectric layer 200', and an inner region of the recess 300' can control the gate layer 400'.
  • the formed gate structure 410' completely covers the bottom and sidewalls of the recess 300'; in the second embodiment, the formed gate structure 410 covers the bottom of the recess 300' and partially covers the recess a sidewall of the trench 300'; in the third embodiment, the formed gate structure 410 covers the bottom of the recess 300' without covering the sidewall of the recess 300'; in the second embodiment, the third embodiment, the gate The pole structure 410' covers the position of the groove 300' at a boundary corresponding to the upper and lower portions of the channel direction Y.
  • the sidewall of the gate structure 410' has an arc, and the bottom width of the gate structure 410' is greater than the top width, controlling the shape and extent of the etched gate layer to form a symmetrical gate structure 410'.
  • the distance from the bottom of the recess 300' to the bottom of the fin structure 110' is: 200A to 2000A, which in this embodiment is greater than 500A.
  • At least three adjacent fin structures and a dielectric layer located around the fin structure are formed; wherein the middle fin structure is defined as a channel region, and the peripheral fin structure is an auxiliary fin structure, the middle The side slope of the fin structure is: greater than or equal to 82 degrees.
  • Other steps and implementation methods are the same as in the first embodiment.
  • a third embodiment at least three adjacent fin structures and a dielectric layer located around the fin structure are formed; wherein the middle fin structure is defined as a channel region, and the peripheral fin structure is an auxiliary fin structure, the middle The side slope of the fin structure is: greater than or equal to 82 degrees.
  • the peripheral fin structure is symmetrical based on the middle fin structure; a part of the dielectric layer between the middle fin structure and the auxiliary fin structure is etched to form a groove having a symmetric shape structure; filling the gate layer, etching the gate
  • the layer forms a gate structure that covers the surface of the fin and is symmetric between the groove and the groove, and the gate structure is inverted U-shaped.
  • Other steps and implementation methods are the same as in the first embodiment.
  • FIG. 8 to FIG. 10 are schematic diagrams showing the steps of fabricating a FinFET in another embodiment of the present invention
  • FIG. 8 is a semiconductor substrate in the prior art.
  • a fin structure 110' is formed on 100', a top portion of the fin structure 110' is formed with a hard mask layer 120', and a dielectric layer 200' is disposed around the fin structure 110', wherein the upper surface of the dielectric layer 200' is hard
  • the upper surface of the mask layer 120' is flush, and a portion of the dielectric layer 200' is etched in a partial region on both sides of the fin structure 110' to form a recess 300' on both sides of the surface of the fin structure 110', wherein the hard
  • the mask layer 120' functions as an auxiliary etching recess 300'
  • the hard mask layer 120' is a nitride layer or an oxynitride layer; wherein the size of the recess 300' corresponds to the size of the gate
  • the hard mask layer 120 ′ is removed, and the surface of the dielectric layer 200 ′ and the surface of the recess 300 ′ are covered with the gate layer 400 ′.
  • the material of the gate layer 400 ′ may be polysilicon, metal, or high. -K material; in this embodiment, polysilicon material is used.
  • the gate layer 400' is etched in FIG.
  • gate structure 410' covering the surface of the fin structure 110' between the bottom of the recess 300' and the recess 300', the gate structure 410' being inverted U-shaped;
  • the upper length of the gate structure 410' of the fin field effect transistor along the channel direction Y is defined by gate etching; the gate structure of the fin field effect transistor is recessed along the lower length of the channel direction Y by the groove definition. That is, the gate layer 400' not etched to the region of the recess 300' is etched by etching the gate, and a portion of the gate layer 400' corresponding to the region around the recess is etched to expose the dielectric layer 200.
  • the dielectric layer 200' can function to assist in etching the gate layer 400'; in the region etched to the recess 300', the etching of the gate layer 400' is defined by the recess 300', the recess 300' At this time, it functions as an auxiliary etching gate layer 400'.
  • the region around the recess 300' is etched to the surface of the dielectric layer 200', and the inner region of the recess 300' can control the progress and etching of the gate layer 400'.
  • the shape of the gate structure 410' is etched to the surface of the dielectric layer 200'.
  • the formed gate structure 410' completely covers the bottom and sidewalls of the recess 300'; in the fifth embodiment, the formed gate structure 410' covers the bottom of the recess 300' and partially covers a sidewall of the recess 300'; in the sixth embodiment, the formed gate structure 410' covers the bottom of the recess 300' and does not cover the recess 300' In the fifth embodiment and the sixth embodiment, the gate structure 410' covers the portion of the groove 300' at a position corresponding to the upper and lower portions of the channel direction Y.
  • the sidewalls of the gate structure 410' have a curvature, and the bottom width of the gate structure 410' is greater than the top width, controlling the shape and extent of the etched gate layer 400' to form a symmetrical gate structure 410'.
  • the bottom of the recess 300' is at a distance from the bottom of the fin structure 110': 200A to 2000A, and in this embodiment is greater than 500A.
  • the hard mask layer 120 ′ is not removed after the recess 300 ′ is formed, and the gate layer 400 ′ is directly formed on the surface of the hard mask layer 120 ′, and the finally formed gate structure 410 ′ A hard mask layer 120' remains between the upper surfaces of the fin structures 110'.
  • the process difficulty of forming the gate structure 410' can be reduced, the etching is assisted by the surface of the groove and the dielectric layer, the difficulty of etching the gate layer is reduced, and the process difficulty is greatly reduced, and the existing equipment can be used. Implemented and compatible with planar processes.
  • At least three adjacent fin structures and a dielectric layer located around the fin structure are formed; wherein the middle fin structure is defined as a channel region, and the peripheral fin structure is an auxiliary fin structure, the middle The side slope of the fin structure is: greater than or equal to 82 degrees.
  • Other steps and implementation methods are the same as in the fourth embodiment.
  • At least three adjacent fin structures and a dielectric layer located around the fin structure are formed; wherein the middle fin structure is defined as a channel region, and the peripheral fin structure is an auxiliary fin structure, the middle The side slope of the fin structure is: greater than or equal to 82 degrees.
  • the peripheral fin structure is symmetrical based on the middle fin structure; a part of the dielectric layer between the middle fin structure and the auxiliary fin structure is etched to form a groove having a symmetric shape structure; filling the gate layer, etching the gate
  • the layer forms a gate structure that covers the surface of the fin and is symmetric between the groove and the groove, and the gate structure is inverted U-shaped.
  • Other steps and implementation methods are the same as in the fourth embodiment.

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Abstract

本发明提供一种鳍式场效应晶体管的制作方法，方法包括：提供半导体衬底，所述半导体衬底形成至少一个鳍形结构及位于所述鳍形结构周围的介质层；刻蚀鳍形结构两侧的部分介质层，形成位于鳍形结构两侧的凹槽；填充栅极层；刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型；所述鳍式场效应晶体管的栅极结构沿沟道方向的上部长度由栅极刻蚀定义；所述鳍式场效应晶体管的栅极结构沿沟道方向的下部长度由凹槽定义。

Description

鳍式场效应晶体管的制作方法
本申请要求2015年10月15日提交中国专利局、申请号为201510662851.7、发明名称为“鳍式场效应晶体管的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种鳍式场效应晶体管的制作方法。
背景技术
进入21世纪以来，半导体工艺技术飞速发展，工艺制程已向40nm节点以下发展，在应用于核心中央处理器、图像处理器领域中28nm节点制程量产已成熟化。在向20nm节点以下工艺发展过程中，传统的2D平面晶体管结构已出现性能及工艺制程的弊端，因此，Intel、TSMC、Samsung先后提出了16nm、14nm制程节点采用3D结构的鳍式场效应晶体管(FinFet)，在相同的物理长度实现更长的有效沟道长度，从而大幅度提高芯片的性能。
请参考图1至图4，图1至图4为现有技术中制作鳍式场效应晶体管的各步骤结构示意图。现有技术中，提供衬底100，在衬底100上形成鳍形结构110，并且鳍形结构110周围覆盖有第一介质层200，第一介质层200的上表面与鳍形结构110的上表面齐平，图2至图4中，刻蚀鳍形结构110两侧的第一介质层200形成延伸于Y方向上的凹槽300，再铺设栅极层400，栅极层400覆盖第一介质层200及凹槽300，再对栅极层400进行刻蚀形成鳍式场效应晶体管的栅极结构410；现有技术中，凹槽200为延伸于鳍形结构，形状、范围较大，并且栅极层400在刻蚀形成栅极结构410的过程中需要刻蚀栅极层至凹槽300的底部，即刻断连续的栅极层400，所需的工艺难度较高，难以控制刻蚀的精准度，难以将凹槽不需要栅极层的区域刻蚀清除干净，难以形成形状良好可控的栅极结构。因此，如何在形成鳍式场效 应晶体管中，形成界面良好形状可控的栅极区域，降低栅极层刻蚀难度，提高晶体管的性能为业内亟待解决的问题。
发明内容
为了提高鳍式场效应晶体管的性能，特别解决形成栅极结构工艺难度较高的问题，本发明提供一种：一种鳍式场效应晶体管的制作方法，其特征在于，所述方法包括：
提供半导体衬底，所述半导体衬底形成至少一个鳍形结构及位于所述鳍形结构周围的介质层；刻蚀鳍形结构两侧的部分介质层，形成位于鳍形结构两侧的凹槽；填充栅极层；刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型；所述鳍式场效应晶体管的栅极结构沿沟道方向的上部长度由栅极刻蚀定义；所述鳍式场效应晶体管的栅极结构沿沟道方向的下部长度由凹槽定义。
优选的，所述栅极结构的底部宽度大于顶部宽度。
优选的，所述凹槽底部距离鳍形结构底部为：200埃至2000埃。
优选的，刻蚀栅极层的步骤中，位于凹槽周围区域对应的部分栅极层被刻蚀至暴露出介质层，所述介质层起到降低栅极层刻蚀难度的作用。
优选的，于鳍形结构上表面形成氮化物层或氮氧化物层，所述氮化物层或氮氧化物层于刻蚀形成凹槽的步骤中起到硬掩膜的作用。
优选的，形成的鳍式场效应晶体管结构中，栅极结构与鳍形结构上表面之间有氮化物层或氮氧化物层。
优选的,形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。
优选的，刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质 层，形成凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型。
优选的，所述周边鳍形结构基于中间鳍形结构对称；
刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成形状结构对称的凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面并对称的栅极结构，所述栅极结构为倒U型。
本发明形成栅极结构形状、界面更好,大大降低了工艺难度,在现有设备上就可以实现,并且可以和平面工艺兼容。
附图说明
通过说明书附图以及随后与说明书附图一起用于说明本发明某些原理的具体实施方式，本发明所具有的其它特征和优点将变得清楚或得以更为具体地阐明。其中：
图1至图4为现有技术中制作鳍式场效应晶体管的各步骤结构示意图；
图5至图7为本发明一实施例中制作鳍式场效应晶体管的各步骤结构示意图；
图8至图10为本发明另一实施例中制作鳍式场效应晶体管的各步骤结构示意图。
具体实施方式
为解决现有技术中鳍式场效应晶体管(FinFET)栅极结构工艺难度较大，栅极层难以刻蚀的问题，本发明提供一种鳍式场效应晶体管的制作方法，所述方法包括：提供半导体衬底，所述半导体衬底形成至少一个鳍形结构及位于所述鳍形结构周围的介质层；刻蚀鳍形结构 两侧的部分介质层，形成位于鳍形结构两侧的凹槽；填充栅极层；刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型；所述鳍式场效应晶体管的栅极结构沿沟道方向的上部长度由栅极刻蚀定义；所述鳍式场效应晶体管的栅极结构沿沟道方向的下部长度由凹槽定义。
第一实施例:
下面结合具体实施方式对发明的内容进行详细说明，请参考图5至图7，图5至图7为本发明一实施例中制作鳍式场效应晶体管的各步骤结构示意图；图5中在现有技术中的半导体衬底100’上形成鳍形结构110’，鳍形结构110’的周围铺设有介质层200’，其中介质层200’的上表面与鳍形结构110’的上表面齐平，在鳍形结构110’两侧的部分区域对部分介质层200’进行刻蚀，形成位于鳍形结构110’表面两侧的凹槽300’，采用光刻胶、曝光、显影、刻蚀的方式完成上述步骤，其中凹槽300’的大小对应于形成栅极结构的大小，在本实施例中凹槽的宽度为100nm，凹槽的宽度范围为：30nm～100um，凹槽的深度为：1500A,凹槽深度的范围为：500A～2000A。请继续参考图6，图6中于介质层200’的表面以及凹槽300’的表面覆盖栅极层400’，栅极层400’的材质可为多晶硅、金属、High-K材质；在本实施例中采用多晶硅材质。图7中刻蚀栅极层400’，形成覆盖凹槽300’底部和凹槽300’之间鳍形结构110’表面的栅极结构410’，栅极结构410’为倒U型；鳍式场效应晶体管的栅极结构410’沿沟道方向Y的上部长度由栅极刻蚀定义；鳍式场效应晶体管的栅极结构沿沟道方向Y的下部长度由凹槽定义。即在未刻蚀至凹槽300’区域的栅极层400’刻蚀通过对栅极刻蚀即可，介质层200’可起到辅助刻蚀栅极层400’；在刻蚀至凹槽300’的区域，栅极层400’的刻蚀由凹槽300’定义，此时凹槽300’起到辅助刻蚀栅极层400’的作用，位于凹槽周围区域对应的部分栅极层400’被刻蚀至暴露出介质层200’。在对栅极层400’刻蚀过程中，凹槽300’周围的区域刻蚀至介质层200’的表面，凹槽300’内部区域可控制栅极层400’ 刻蚀的进度及刻蚀栅极结构410’的形状。在第一实施例中，形成的栅极结构410’完全覆盖凹槽300’的底部和侧壁；在第二实施例中，形成的栅极结构410覆盖凹槽300’的底部并部分覆盖凹槽300’的侧壁；在第三实施例中，形成的栅极结构410覆盖凹槽300’的底部不覆盖凹槽300’的侧壁；在第二实施例、第三实施例中，栅极结构410’覆盖至凹槽300’位置处为对应于沟道方向Y的上部和下部的分界处。栅极结构410’的侧壁具有弧度，栅极结构410’的底部宽度大于顶部宽度，控制刻蚀栅极层的形状、范围，使形成对称的栅极结构410’。凹槽300’底部距离鳍形结构110’底部的距离为：200A至2000A,在本实施例中为大于500A。通过此方案可降低形成栅极结构410’的工艺难度，通过凹槽和介质层表面对刻蚀栅极层进行辅助，降低栅极层刻蚀的难度，大大降低了工艺难度,在现有设备上就可以实现,并且可以和平面工艺兼容。
第二实施例,形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型。其他的步骤及实现方法与第一实施例相同。
第三实施例,形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。所述周边鳍形结构基于中间鳍形结构对称；刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成形状结构对称的凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面并对称的栅极结构，所述栅极结构为倒U型。其他步骤及实现方法与第一实施例相同。
第四实施例，请参考图8至图10，图8至图10为本发明另一实施例中制作鳍式场效应晶体管的各步骤结构示意图；图8中在现有技术中的半导体衬底100’上形成鳍形结构110’，鳍形结构110’的顶部形成有硬掩膜层120’，鳍形结构110’的周围铺设有介质层200’，其中介质层200’的上表面与硬掩膜层120’的上表面齐平，在鳍形结构110’两侧的部分区域对部分介质层200’进行刻蚀，形成位于鳍形结构110’表面两侧的凹槽300’，其中硬掩膜层120’起到辅助刻蚀凹槽300’的作用，硬掩膜层120’为氮化物层或氮氧化物层；其中凹槽300’的大小对应于形成栅极结构的大小，在本实施例中凹槽300’的宽度为100nm，凹槽300’宽度的范围在30nm～100nm：，凹槽300’的深度为：1500A,凹槽300’深度的范围为：500A～2000A。请继续参考图9，去除硬掩膜层120’，并于介质层200’的表面以及凹槽300’的表面覆盖栅极层400’，栅极层400’的材质可为多晶硅、金属、High-K材质；在本实施例中采用多晶硅材质。图10中刻蚀栅极层400’，形成覆盖凹槽300’底部和凹槽300’之间鳍形结构110’表面的栅极结构410’，所述栅极结构410’为倒U型；所述鳍式场效应晶体管的栅极结构410’沿沟道方向Y的上部长度由栅极刻蚀定义；所述鳍式场效应晶体管的栅极结构沿沟道方向Y的下部长度由凹槽定义。即在未刻蚀至凹槽300’区域的栅极层400’刻蚀通过对栅极刻蚀即可，位于凹槽周围区域对应的部分栅极层400’被刻蚀至暴露出介质层200’,介质层200’可起到辅助刻蚀栅极层400’的作用；在刻蚀至凹槽300’的区域，栅极层400’的刻蚀由凹槽300’定义，凹槽300’此时起到辅助刻蚀栅极层400’的作用。通在对栅极层400’刻蚀过程中，凹槽300’周围的区域刻蚀至介质层200’的表面，凹槽300’内部区域可控制栅极层400’刻蚀的进度及刻蚀栅极结构410’的形状。在第四实施例中，形成的栅极结构410’完全覆盖凹槽300’的底部和侧壁；在第五实施例中，形成的栅极结构410’覆盖凹槽300’的底部并部分覆盖凹槽300’的侧壁；在第六实施例中，形成的栅极结构410’覆盖凹槽300’的底部不覆盖凹槽300’ 的侧壁；在第五实施例、第六实施例中，栅极结构410’覆盖至凹槽300’位置处为对应于沟道方向Y的上部和下部的分解处。栅极结构410’的侧壁具有弧度，所述栅极结构410’的底部宽度大于顶部宽度，控制刻蚀栅极层400’的形状、范围，使形成对称的栅极结构410’。凹槽300’底部距离鳍形结构110’底部为：200A至2000A，在本实施例中为大于500A。在又一实施例中，在形成凹槽300’后不去除硬掩膜层120’，而在硬掩膜层120’的表面直接形成栅极层400’，最终形成的栅极结构410’与鳍形结构110’上表面之间仍保留有硬掩膜层120’。通过此方案可降低形成栅极结构410’的工艺难度，通过凹槽和介质层表面对刻蚀进行辅助，降低栅极层刻蚀的难度，大大降低了工艺难度,在现有设备上就可以实现,并且可以和平面工艺兼容。
第五实施例,形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型。其他的步骤及实现方法与第四实施例相同。
第六实施例,形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。所述周边鳍形结构基于中间鳍形结构对称；刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成形状结构对称的凹槽；填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面并对称的栅极结构，所述栅极结构为倒U型。其他步骤及实现方法与第四实施例相同。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术 人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (9)

  1. 一种鳍式场效应晶体管的制作方法，其特征在于，所述方法包括：
    提供半导体衬底，所述半导体衬底形成至少一个鳍形结构及位于所述鳍形结构周围的介质层；
    刻蚀鳍形结构两侧的部分介质层，形成位于鳍形结构两侧的凹槽；
    填充栅极层；
    刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型；
    所述鳍式场效应晶体管的栅极结构沿沟道方向的上部长度由栅极刻蚀定义；所述鳍式场效应晶体管的栅极结构沿沟道方向的下部长度由凹槽定义。
  2. 根据权利要求1所述的鳍式场效应晶体管的制作方法，其特征在于，所述栅极结构的底部宽度大于顶部宽度。
  3. 根据权利要求1所述的鳍式场效应晶体管的制作方法，其特征在于，所述凹槽底部距离鳍形结构底部为：200埃至2000埃。
  4. 根据权利要求1所述的鳍式场效应晶体管的制作方法，其特征在于，刻蚀栅极层的步骤中，位于凹槽周围区域对应的部分 栅极层被刻蚀至暴露出介质层，所述介质层起到降低栅极层刻蚀难度的作用。
  5. 根据权利要求1所述的鳍式场效应晶体管的制作方法，其特征在于，所述方法还包括：于鳍形结构上表面形成氮化物层或氮氧化物层，所述氮化物层或氮氧化物层于刻蚀形成凹槽的步骤中起到硬掩膜的作用。
  6. 根据权利要求5所述的鳍式场效应晶体管的制作方法，其特征在于，形成的鳍式场效应晶体管结构中，栅极结构与鳍形结构上表面之间保留有氮化物层或氮氧化物层。
  7. 根据权利要求1所述的鳍式场效应晶体管的制作方法，其特征在于，所述方法还包括：形成至少三个相邻的鳍形结构及位于所述鳍形结构周围的介质层；其中，中间鳍形结构定义为沟道区域，周边鳍形结构为辅助鳍形结构，中间鳍形结构的侧面坡度为：大于等于82度。
  8. 根据权利要求7所述的鳍式场效应晶体管的制作方法，其特征在于，
    刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成凹槽；
    填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面的栅极结构，所述栅极结构为倒U型。
  9. 根据权利要求7所述的鳍式场效应晶体管的制作方法，其特征在于，所述周边鳍形结构基于中间鳍形结构对称；
    刻蚀所述中间鳍形结构与辅助鳍形结构之间的部分介质层，形成形状结构对称的凹槽；
    填充栅极层，刻蚀栅极层，形成覆盖凹槽底部和凹槽之间鳍形结构表面并对称的栅极结构，所述栅极结构为倒U型。
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