WO2017057358A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2017057358A1 WO2017057358A1 PCT/JP2016/078446 JP2016078446W WO2017057358A1 WO 2017057358 A1 WO2017057358 A1 WO 2017057358A1 JP 2016078446 W JP2016078446 W JP 2016078446W WO 2017057358 A1 WO2017057358 A1 WO 2017057358A1
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- electrode
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- semiconductor device
- transistor
- power transistor
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Definitions
- the present invention relates to a semiconductor device.
- many semiconductor devices having a power transistor include a temperature detection element that detects abnormal heat generation of the power transistor.
- Patent Document 1 and Patent Document 2 can be cited as examples of conventional techniques related to the above.
- the conventional semiconductor device has room for further improvement in the detection accuracy of abnormal heat generation (and hence the reliability of the temperature protection circuit).
- an object of the invention disclosed in this specification is to provide a semiconductor device capable of correctly detecting abnormal heat generation of a power transistor.
- a semiconductor device disclosed in the present specification has a power transistor having a vertical structure and a temperature detection element for detecting abnormal heat generation of the power transistor, and the power transistor is a first main transistor of a semiconductor substrate.
- a first electrode formed on a surface side; a second electrode formed on a second main surface side of the semiconductor substrate; and at least one pad arranged unevenly on the first electrode;
- the detection element has a configuration (first configuration) formed at the maximum heat generation location of the power transistor specified by the uneven arrangement of the pads.
- the semiconductor device having the first configuration there are a plurality of pads, and a configuration in which the pads that are most likely to concentrate current are arranged unevenly on the first electrode so as to be uniquely identified (second configuration) Configuration).
- the pad is single, and the pad is unevenly arranged on the first electrode so that the current density distribution around the pad is biased in a specific direction (third Configuration).
- the second electrode may have a configuration (fourth configuration) that is a substrate electrode for applying a power supply voltage to the semiconductor substrate.
- a semiconductor device having a fourth configuration includes a power supply line formed on the first main surface side of the semiconductor substrate, and a via connecting the substrate electrode and the power supply line ( The fifth configuration is preferable.
- the power transistor functions as a high-side switch in which the first electrode is connected to a load and the second electrode is connected to a power supply terminal. (Sixth configuration) is preferable.
- the power transistor functions as a low-side switch in which the first electrode is connected to a ground terminal and the second electrode is connected to a load ( A seventh configuration is preferable.
- the first electrode is formed with a slit for drawing out the wiring of the temperature detection element to the end side (eighth configuration). It is good to.
- the temperature detection element is provided in the vicinity of the pad, and the slit is directed in a direction opposite to the pad as viewed from the temperature detection element. It is good to use the structure (9th structure) currently formed.
- the plurality of pads are unevenly arranged on the first electrode so that the current is most concentrated at the corner of the pad closest to the temperature protection circuit. (10th configuration).
- the temperature detecting element may be provided in the vicinity of the corner portion (an eleventh configuration).
- the temperature detection element is a distance from the corner to each end of the plurality of directions from the corner to the end of the first electrode.
- the plurality of pads may be configured to include a main pad and a subpad smaller than the main pad (a thirteenth configuration).
- the semiconductor device disclosed in this specification includes a power transistor having a lateral structure and a temperature detection element that detects abnormal heat generation of the power transistor, and the power transistor is formed on a semiconductor substrate.
- the temperature detection element is configured in the vicinity of the current concentration pad (fourteenth configuration).
- the semiconductor device having any one of the first to fourteenth configurations further includes a temperature protection circuit that forcibly turns off the power transistor when the temperature detection element detects abnormal heat generation of the power transistor. (Fifteenth configuration) is preferable.
- the electronic device disclosed in the present specification has a configuration (sixteenth configuration) having a semiconductor device having the fifteenth configuration.
- the vehicle disclosed in the present specification has a configuration (a seventeenth configuration) including a battery and an electronic device having a sixteenth configuration that operates by receiving supply of a power supply voltage from the battery. ing.
- the semiconductor device disclosed in the present specification it is possible to correctly detect abnormal heat generation of the power transistor and improve the reliability of the temperature protection circuit.
- Block diagram showing the overall configuration of a semiconductor device Schematic diagram showing the first embodiment of the transistor N1 The schematic diagram which shows 2nd Embodiment of transistor N1. Schematic diagram illustrating a third embodiment of the transistor N1. The schematic diagram which shows 4th Embodiment of transistor N1. Schematic diagram showing an example of power line installation The schematic diagram which shows 5th Embodiment of transistor N1. Circuit diagram showing application example to low-side switch Schematic diagram showing an application example to the low-side switch Schematic diagram illustrating a sixth embodiment of the transistor N1. Schematic diagram showing a specific example of IC layout Enlarged view of broken line area A in FIG. External view showing a configuration example of a vehicle
- FIG. 1 is a block diagram showing the overall configuration of the semiconductor device.
- the semiconductor device 100 of this configuration example is an in-vehicle high-side switch IC, and has a plurality of external terminals (IN pin, GND pin, OUT pin, ST pin, VBB) as means for establishing electrical connection with the outside of the device. Pin).
- the IN pin is an input terminal for receiving an external input of a control signal from a CMOS logic IC or the like.
- the GND pin is a ground terminal.
- the OUT pin is an output terminal to which a load (an engine control ECU [electronic control unit], an air conditioner, a body device, etc.) is externally connected.
- a load an engine control ECU [electronic control unit], an air conditioner, a body device, etc.
- the ST pin is an output terminal for outputting a self-diagnosis signal to a CMOS logic IC or the like.
- the VBB pin is a power supply terminal for receiving supply of a power supply voltage Vbb (for example, 4.5V to 18V) from the battery. Note that a plurality of VBB pins may be provided in parallel (for example, 4-pin parallel) in order to flow a large current.
- the semiconductor device 100 of this configuration example includes an internal power supply circuit 1, a constant voltage generation circuit 2, an oscillation circuit 3, a charge pump circuit 4, a logic circuit 5, a gate control circuit 6, and a clamp circuit 7. , Input circuit 8, reference generation circuit 9, temperature protection circuit 10, voltage drop protection circuit 11, open protection circuit 12, overcurrent protection circuit 13, N-channel MOS field effect transistors N1 to N3, Resistors R1 and R2, a sense resistor Rs, and Zener diodes Z1 and Z2 are integrated.
- the internal power supply circuit 1 is connected between the VBB pin and the GND pin, generates a predetermined internal power supply voltage VREG from the power supply voltage Vbb, and supplies it to each part of the semiconductor device 100.
- the internal power supply circuit 1 is controlled to be operable according to the logic level of the enable signal EN. More specifically, the internal power supply circuit 1 is in an operating state when the enable signal EN is at a logic level (eg, high level) when enabled, and is at a logic level (eg, low level) when the enable signal EN is disabled. It becomes a stop state when it is.
- the constant voltage generation circuit 2 has a logic level (for example, a high level) when the enable signal EN is at a logic level (for example, high level) when enabled or when the abnormality protection signal S5a has not detected an abnormality. )
- the enable signal EN is at a logic level (for example, low level) when disabled, or when the abnormality protection signal S5a is at a logic level (for example, low level) when detecting an abnormality. Stopped.
- the oscillation circuit 3 operates in response to the supply of the high voltage VH and the low voltage VL, generates a clock signal CLK having a predetermined frequency, and outputs it to the charge pump circuit 4.
- the clock signal CLK is a rectangular wave signal that is pulse-driven between the high voltage VH and the low voltage VL.
- the charge pump circuit 4 operates by receiving the high voltage VH and the low voltage VL, and drives the flying capacitor using the clock signal CLK, thereby generating a boosted voltage VCP higher than the power supply voltage Vbb and performing gate control. This is supplied to the circuit 6 and the overcurrent protection circuit 13.
- the logic circuit 5 operates in response to the supply of the internal power supply voltage VREG, generates a gate control signal S5b, and outputs it to the gate control circuit 6.
- the logic circuit 5 has a function of monitoring the temperature protection signal S10, the voltage drop protection signal S11, the open protection signal S12, and the overcurrent protection signal S13, respectively, and performing an abnormality protection operation as necessary.
- the logic circuit 5 stops the constant voltage generation circuit 2 with the abnormality protection signal S5a as the logic level at the time of detecting the abnormality, and the gate control signal.
- S5b is set to the low level to forcibly turn off both the transistors N1 and N2.
- the logic circuit 5 also has a function of generating the gate signal S5c of the transistor N3 according to the abnormality detection result.
- the gate control circuit 6 enters an operating state when the overcurrent protection signal S13 is at a logic level (eg, low level) when no abnormality is detected, and the logic when the overcurrent protection signal S13 detects an abnormality. When it is at a level (for example, high level), it is in a stopped state.
- a logic level eg, low level
- the clamp circuit 7 is connected between the VBB pin and the gates of the transistors N1 and N2.
- a clamp circuit 7 (so-called active clamp circuit) is provided for energy absorption.
- the active clamp voltage represented by Vbb ⁇ (Vclp + Vgs) is preferably set to 48 V, for example (where Vbb is the power supply voltage, Vclp is the negative clamp voltage at the OUT pin, and Vgs is the gate-source voltage of the transistor N1). ).
- the input circuit 8 is a Schmitt trigger that receives an input of a control signal from the IN pin and generates an enable signal EN.
- the reference generation circuit 9 operates in response to the supply of the internal power supply voltage VREG, generates a predetermined reference voltage Vref and a reference current Iref, and supplies them to each part of the semiconductor device 100.
- the reference voltage Vref and the reference current Iref are used to set a target value of the internal power supply voltage VREG in the internal power supply circuit 1 and to set an abnormality detection threshold value in the various protection circuits 9 to 13. It is done.
- the transistor N1 is a power transistor having a drain connected to the VBB pin and a source connected to the OUT pin, and is a switch element (high side) for conducting / cutting off a current path through which an output current I1 flows from the battery to the load. Function as a switch).
- the transistor N1 is turned on when the gate voltage VG is at a high level and turned off when the gate voltage VG is at a low level.
- the transistor N2 is a mirror transistor connected in parallel to the transistor N1, and generates a mirror current I2 corresponding to the output current I1.
- the transistor N3 is an open drain type transistor having a drain connected to the ST pin and a source connected to the GND pin.
- the resistor R1 is connected between the IN pin and the input terminal of the input circuit 8, and functions as a current limiting resistor for suppressing an excessive surge current.
- the zener diode Z1 is connected between the gates of the transistors N1 and N2 and the OUT pin so that the cathode is on the gate side of the transistors N1 and N2 and the anode is on the OUT pin side.
- the Zener diode Z1 connected in this way limits the gate-source voltage of the transistors N1 and N2 to a predetermined upper limit value or less in a normal connection state in which a battery is connected to the VBB pin and a load is connected to the OUT pin. Functions as a clamp element (surge voltage absorption element).
- the zener diode Z2 is connected between the gates of the transistors N1 and N2 and the OUT pin so that the anode is on the gate side of the transistors N1 and N2 and the cathode is on the OUT pin side.
- the Zener diode Z2 connected in this way is a reverse circuit for blocking the current path from the OUT pin to the gates of the transistors N1 and N2 in a reverse connection state where a load is connected to the VBB pin and a battery is connected to the OUT pin. Functions as a connection protection element.
- the semiconductor device 100 is configured as a monolithic power IC in which CMOS logic (logic circuit 5 or the like) and a power MOS device (transistor N1 or the like) are incorporated on one chip.
- CMOS logic logic circuit 5 or the like
- MOS device transistor N1 or the like
- FIG. 2 is a schematic diagram showing the first embodiment of the transistor N1.
- a top view of the transistor N1 is depicted, and the layout of the pads and the current density distribution (and thus the temperature distribution) around the pads are depicted.
- the hatched area in the top view indicates that the current density is higher as the hatched density (concentration) is higher.
- a vertical cross-sectional view when the transistor N1 is cut along the one-dot chain line ⁇ 1- ⁇ 2 in the top view is depicted.
- the layer thickness, the size and number of trench gates, the size and number of pads, the size of the temperature detection element 10a, and the like may be different from actual ones.
- a vertical structure trench gate type
- the semiconductor substrate 200 includes an n-type semiconductor substrate layer 201 as a base.
- a low concentration n-type semiconductor layer 202 is formed on the surface of the n-type semiconductor substrate layer 201. Further, a high concentration p-type semiconductor layer 203 is formed on the surface of the low concentration n-type semiconductor layer 202.
- a plurality of trench gates extending from the surface of the high concentration p-type semiconductor layer 203 to the low concentration n-type semiconductor layer 202 are formed in the semiconductor substrate 200.
- the inner wall surface of the trench gate is covered with a gate oxide film 204, and the inside thereof is filled with gate polysilicon 205.
- a high-concentration n-type semiconductor region 206 is formed around the trench gate. Note that the surface of the trench gate is covered with an interlayer insulating film 207.
- a source electrode 208 is formed on the surface of the semiconductor substrate 200 so as to cover the entire power transistor formation region.
- a drain electrode 209 is formed on the back surface of the semiconductor substrate 200 so as to cover the entire power transistor formation region.
- a unit cell is formed for each of a plurality of trench gates, and a single power transistor is formed by connecting a large number of unit cells in parallel.
- the unit cell can be miniaturized in the case of the trench gate type transistor N1, it is possible to reduce the on-resistance (tens of m ⁇ ) of the transistor N1.
- the transistor N1 of this embodiment six pads 210a to 210f are arranged on the source electrode 208 in a lattice shape (3 vertical ⁇ 2 horizontal) at equal intervals in the vertical and horizontal directions.
- the current from the drain electrode 209 to the source electrode 208 flows uniformly in the power transistor formation region, so that the current density distribution around each of the pads 210a to 210f is biased in all directions. There will be no. Accordingly, the heat generation points of the transistor N1 can be dispersed, so that the safety of the semiconductor device 100 can be improved and the product life can be extended.
- the transistor N1 is likely to generate heat normally in the vicinity of the pads 210a to 210f.
- the temperature detecting element 10a for detecting abnormal heat generation of the transistor N1 (for example, a bipolar transistor having a base-emitter voltage Vbe having temperature dependence) generates the most heat among the plurality of pads 210a to 210f. It is desirable to provide in the vicinity of a large thing.
- the transistor N1 of the present embodiment there are a plurality of equivalent heat generation points as the pads 210a to 210f are arranged uniformly on the source electrode 208. Therefore, in the example of this figure, on the assumption that there is no difference in the current density distribution (and hence the temperature distribution) around each of the pads 210a to 210f, the temperature is detected in the power transistor formation region near the left side of the pad 210b. Element 10a is formed.
- FIG. 3 is a schematic diagram showing a second embodiment of the transistor N1.
- the transistor N1 of the present embodiment is characterized in that the arrangement layout of the pads 210a to 210f is devised while being based on the first embodiment (FIG. 2). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 2, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.
- the pads 210a to 210f are not evenly arranged on the entire surface of the source electrode 208, but are unevenly distributed so as to approach only the right half surface of the source electrode 208. With such uneven distribution, the current flowing from the drain electrode 209 to the left side of the source electrode 208 is concentrated from the left side of the pads 210a to 210c arranged in the left column among the pads 210a to 210f. Flows in.
- the vicinity of the left side of the pads 210a to 210c is the region with the highest current density, and further becomes the maximum heat generation portion of the transistor N1.
- the temperature detection element 10a is formed in the power transistor formation region in the vicinity of the left side of the pad 210b.
- the pads 210a to 210f in the present embodiment are intentionally limited, and the maximum heat generating portion where the temperature detection element 10a is to be formed is narrowed down. Therefore, the detection accuracy of abnormal heat generation by the temperature detection element 10a (and thus the reliability of the temperature protection circuit 10) can be improved.
- FIG. 4 is a schematic diagram showing a third embodiment of the transistor N1.
- the transistor N1 of the present embodiment is characterized in that it is based on the second embodiment (FIG. 3) and further devised in the layout of the pads 210a to 210f. Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 3, and redundant descriptions are omitted. In the following, the characteristic portions of the third embodiment are mainly described.
- the three pads 210a to 210c where current is likely to concentrate can be narrowed down, but current flows through these pads 210a to 210c under the same conditions. For this reason, it cannot be completely denied that a large current flows through the pads 210a and 210c instead of the pads 210b close to the temperature detection element 10a due to manufacturing variations of the transistor N1.
- the pad 210b is disposed so as to protrude toward the center (close to the left end) of the source electrode 208. With such uneven distribution, the current flowing from the drain electrode 209 to the left opposite surface of the source electrode 208 is concentrated from the left side of the pads 210a to 210f closest to the left end of the source electrode 208. Flow into.
- the vicinity of the left side of the pad 210b is the region with the highest current density, and further, the maximum heat generation portion of the transistor N1.
- the temperature detection element 10a is formed in the power transistor formation region in the vicinity of the left side of the pad 210b.
- the pad 210b where the current is most likely to be concentrated can be uniquely identified. Therefore, the maximum heat generation location where the temperature detection element 10a is to be formed is determined. It can only be identified. Therefore, it is possible to improve the detection accuracy of abnormal heat generation by the temperature detection element 10a (and hence the reliability of the temperature protection circuit 10).
- the current concentration pad and other pads are depicted as if there is a significant difference in current density in the surroundings. Excessive current concentration on the pad leads to local deterioration of the metal layer and bonding wire and should be avoided as much as possible.
- the layout of the pads 210a to 210f is such that the difference in current density around each of the pads 210a to 210f is minimized, that is, when manufacturing variations of the transistor N1 occur.
- the pads 210a to 210f are appropriately unevenly arranged on the source electrode 208 so as to give a difference that does not reverse the magnitude relation of the current density between the current concentration pad and the other pads. .
- FIG. 5 is a schematic diagram showing the fourth embodiment of the transistor N1.
- the transistor N1 of this embodiment is based on the first embodiment (FIG. 2), and the pads 210a to 210f are integrated into a single pad 210g, and the layout of the pads 210g is further devised. Characterized by points. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 2, and redundant descriptions are omitted. In the following, the characteristic portions of the fourth embodiment are mainly described.
- the pad 210g is a large current pad to which a bonding wire having a large diameter (for example, several hundred ⁇ m) can be connected, and only one pad 210g is provided on the source electrode 208.
- the pads 210g are unevenly arranged at positions shifted from the center of gravity of the source electrode 208 in the right direction on the paper surface. With such uneven distribution, the current density distribution around the pad 210g is not uniform in all directions, and the region with high current density is biased in a specific direction (left side of the pad 210g in the example of this figure). As a result, this region becomes the maximum heat generation portion of the transistor N1.
- the temperature detection element 10a is formed in the power transistor formation region in the vicinity of the left side of the pad 210g.
- the region where the current is most likely to be concentrated around the pad 210g is made unique. Since it can be specified, it is possible to uniquely specify the maximum heat generation point where the temperature detection element 10a is to be formed. Therefore, it is possible to improve the detection accuracy of abnormal heat generation by the temperature detection element 10a (and hence the reliability of the temperature protection circuit 10).
- FIG. 6 is a schematic diagram illustrating an example of laying power supply lines in the semiconductor device 100.
- the semiconductor device 100 in this figure has a semiconductor substrate 300 (corresponding to the semiconductor substrate 200 in FIGS. 2 to 5) based on an n-type semiconductor substrate layer.
- a power transistor formation region 301 (see the lower stages of FIGS. 2 to 5) in which the vertical transistor N1 is formed is formed.
- a source electrode 302 is formed on the surface side (corresponding to the first main surface side) of the power transistor formation region 301.
- the source electrode 302 is connected to the OUT pin through a pad.
- a drain electrode 303 is formed on the back side (corresponding to the second main surface side) of the power transistor formation region 301.
- the drain electrode 303 is connected to the VBB pin.
- a substrate electrode (back surface electrode) for applying the power supply voltage Vbb (the highest voltage in the system) to the n-type semiconductor substrate layer is formed on the back surface of the semiconductor substrate 300. Therefore, the substrate electrode of the semiconductor substrate 300 can be used as it is as the drain electrode 303.
- circuit formation regions 304a and 304b are formed in the semiconductor substrate 300.
- circuit blocks (such as the internal power supply circuit 1 and the constant voltage generation circuit 2) that operate upon receiving the supply of the power supply voltage Vbb are formed.
- the power supply lines 305a and 305b separately provided for the circuit formation regions 304a and 304b are laid, and
- the interlayer vias 306a and 306b are desirably provided in the vicinity of the circuit formation regions 304a and 304b, respectively.
- Such a configuration eliminates the need to route the power supply lines 305a and 305b from the power supply pad. Therefore, it is possible to minimize the laying distance of the power supply lines 305a and 305b without depending on the layout of the circuit formation regions 304a and 304b.
- the planar structure of the transistor N1 is a planar gate type. Also good.
- the position where the temperature detecting element 10a is formed can be appropriately determined by arranging the pads unevenly on the electrodes.
- FIG. 7 is a schematic diagram (top view) showing the fifth embodiment of the transistor N1.
- the transistor N1 of the present embodiment is a lateral power transistor, and is laid from the semiconductor substrate 400, the channel region 401 formed on the semiconductor substrate 400, and the channel region 401 toward the edge of the semiconductor substrate 400.
- the source electrode 402 is further unevenly distributed closer to the channel region 401 than the pad row 404 A disposed current concentration pad 406 is included.
- the current flowing from the drain electrode 403 to the source electrode 402 flows intensively into the current concentration pad 406 closest to the channel region 401.
- the white arrow in this figure has shown the electric current which flows into the source electrode 402 via the channel region 401 from the drain electrode 403, and the thickness of the arrow has shown the magnitude
- the vicinity of the current concentration pad 406 is a region with the highest current density, and further becomes the maximum heat generation portion of the transistor N1.
- the temperature detection element 10 a is formed in the vicinity of the current concentration pad 406.
- FIG. 9 is a schematic diagram showing an application example to the low-side switch.
- the low-side switch LSW to which the same pad layout layout as that in the fourth embodiment (FIG. 5) is applied is illustrated.
- FIG. 10 is a schematic diagram illustrating a sixth embodiment of the transistor N1.
- a more specific structure is depicted based on the actual machine, based on the third embodiment (FIG. 4).
- the source electrode 208 is formed with a slit 208a for drawing out the metal wiring 10b of the temperature detection element 10a provided in the vicinity of the pad 210b to its own edge.
- the slit 208a is formed in a straight line in the direction opposite to the pad 210b when viewed from the temperature detecting element 10a. With such a configuration, the metal wiring 10b can be drawn to the end of the source electrode 208 without interrupting the current path to the pads 210a to 210f as much as possible.
- a diode is used as the temperature detection element 10a. More specifically, a high concentration p-type semiconductor region 10a1 corresponding to the anode of the diode is formed in the low concentration n-type semiconductor layer 202, and inside the high concentration p-type semiconductor region 10a1, a cathode of the diode is formed. A high-concentration n-type semiconductor region 10a2 corresponding to is formed. A diode formed by such a pn junction is suitable as the temperature detecting element 10a because its forward drop voltage Vf changes depending on the junction temperature Tj.
- the components of the transistor N1 will be supplementarily described.
- a unit cell is formed for each of a plurality of trench gates, and a single power transistor is formed by connecting a large number of unit cells in parallel.
- the size of the pad 210b is 70 ⁇ m or more on one side, and the width and interval of the trench gate are several ⁇ m. Therefore, as shown in this figure, there are a plurality of trench gates immediately below the pad 210b.
- FIG. 11 is a schematic diagram showing a specific example of the IC layout.
- N-channel MOS field effect transistors 510 and 520 each corresponding to the above-mentioned transistor N1 for two channels are integrated.
- the transistors 510 and 520 are arranged close to the side portion of the semiconductor device 500 instead of the central portion.
- a driver DRV (which corresponds to the gate control circuit 6 in FIG. 1 or the like) for turning on / off the transistors 510 and 520 in accordance with a control signal input to the semiconductor device 500 is provided at the center of the semiconductor device 500.
- a temperature protection circuit TSD (corresponding to the temperature protection circuit 10 in FIG. 1) for forcibly turning off both the transistors 510 and 520 when a temperature abnormality is detected is formed.
- other circuit elements others are formed in the remaining area of the semiconductor device 500.
- the transistors 510 and 520 are formed in an L shape in a plan view of the semiconductor device 500. By adopting such a layout, it is possible to increase the resistance to inductive loads such as inductors.
- the transistors 510 and 520 are laid out symmetrically in the plan view of the semiconductor device 500. By adopting such a layout, it is possible to improve the uniformity of characteristics and the ease of laying wiring.
- transistor elements unit cells
- currents flowing from the respective transistor elements are supplied to the pads (512 a) arranged on the source electrode 511.
- 512b, 513 When attention is paid to one transistor element, the conduction path of the current flowing through the transistor element is fixed by the arrangement position of the pad. This is because the current flows through the shortest path (the path with the smallest resistance value).
- innumerable current paths from the innumerable transistor elements forming the transistor 510 to the pads are determined by the positions of the pads.
- the place where the current is most concentrated in the formation region of the transistor 510 is where the current path from the transistor element is most concentrated.
- the most concentrated area of the current on the source electrode 511 is the lower right corner P1 of the main pad 512a.
- any current flowing from the transistor elements in the area zone1 flows into the corner portion P1.
- the area zone2 is specified by points x1 and x2 at which the distance from the right side of the main pad 512a and the distance from the corner P2 of the sub pad 513 are equal to each other.
- the current density of the corner portion P1 is larger than the current density of the corner portion P2.
- each pad (512a, 512b, 513) has the most current in the corner of the pad closest to the temperature protection circuit TSD (the corner P1 on the lower right of the main pad 512a in the example of this figure). Are concentrated on the source electrode 511 so as to concentrate.
- the temperature detection element D10 (corresponding to the above-described temperature detection element 10a) for detecting the temperature of the transistor 510 be disposed in a region where the heat concentration is most likely to occur in the region where the transistor 510 is formed.
- the temperature detection element D10 since the current is concentrated most at the lower right corner P1 of the main pad 512a, it can be said that it is desirable to provide the temperature detection element D10 in the vicinity of the part.
- the distance from the corner P1 to each end may be long.
- the source electrode 511 is formed with a linear slit from the position where the temperature detection element D10 is disposed to the right end side of the source electrode 511, as in FIG. It shall be.
- the transistor 520 adopts the same IC layout as described above except that the left and right sides of the transistor 510 are inverted.
- the tenth digit of the reference numeral referred to in explaining the uneven distribution of pads in the transistor 510 can be understood as an explanation of the transistor 520 by replacing “1” with “2”.
- FIG. 13 is an external view showing a configuration example of a vehicle.
- the vehicle X of this configuration example includes a battery (not shown in the figure) and various electronic devices X11 to X18 that operate by receiving supply of the power supply voltage Vbb from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from actual ones for convenience of illustration.
- the electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).
- the electronic device X12 is a lamp control unit that controls turning on and off such as HID [high intensity discharged lamp] and DRL [daytime running lamp].
- the electronic device X13 is a transmission control unit that performs control related to the transmission.
- the electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the movement of the vehicle X.
- control ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.
- the electronic device X15 is a security control unit that performs drive control such as door locks and security alarms.
- the electronic device X16 is an electronic device that is built into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.
- the electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].
- a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].
- the electronic device X18 is an electronic device equipped with a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.
- a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.
- semiconductor device 100 described above can be incorporated in any of the electronic devices X11 to X18.
- the on-vehicle high-side switch IC has been described as an example.
- the application target of the invention disclosed in this specification is not limited to this, and other It can be widely applied to all semiconductor devices having a power transistor including an in-vehicle IPD [intelligent power device] (in-vehicle low-side switch IC, in-vehicle power supply IC, etc.) used for the above-described applications.
- the invention disclosed in this specification can be used for in-vehicle IPD.
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Abstract
Description
図1は、半導体装置の全体構成を示すブロック図である。本構成例の半導体装置100は、車載用ハイサイドスイッチICであり、装置外部との電気的な接続を確立する手段として、複数の外部端子(INピン、GNDピン、OUTピン、STピン、VBBピン)を備えている。INピンは、CMOSロジックICなどから制御信号の外部入力を受け付けるための入力端子である。GNDピンは、接地端子である。OUTピンは、負荷(エンジン制御用ECU[electronic control unit]、エアコン、ボディ機器など)が外部接続される出力端子である。STピンは、CMOSロジックICなどに自己診断信号を外部出力するための出力端子である。VBBピンは、バッテリから電源電圧Vbb(例えば4.5V~18V)の供給を受け付けるための電源端子である。なお、VBBピンは、大電流を流すために複数並列(例えば4ピン並列)に設けてもよい。
図2は、トランジスタN1の第1実施形態を示す模式図である。本図の上段には、トランジスタN1の上面図が描写されており、パッドの配置レイアウトやパッド周辺の電流密度分布(延いては温度分布)が描写されている。なお、上面図のハッチング領域は、斜線密度(濃度)が高い領域ほど電流密度が高いことを示している。一方、本図の下段には、トランジスタN1を上面図の一点鎖線α1-α2で切断したときの縦断面図が描写されている。なお、図示の便宜上、層の厚さ、トレンチゲートのサイズや数、パッドのサイズや数、温度検出素子10aのサイズなどについては、実際と異なっている場合がある。
図3は、トランジスタN1の第2実施形態を示す模式図である。本実施形態のトランジスタN1は、先の第1実施形態(図2)をベースとしつつ、パッド210a~210fの配置レイアウトに工夫を凝らした点に特徴を有する。そこで、第1実施形態と同様の構成要素については、図2と同一の符号を付すことで重複した説明を割愛し、以下では、第2実施形態の特徴部分について重点的な説明を行う。
図4は、トランジスタN1の第3実施形態を示す模式図である。本実施形態のトランジスタN1は、先の第2実施形態(図3)をベースとしつつ、パッド210a~210fの配置レイアウトにさらなる工夫を凝らした点に特徴を有する。そこで、第2実施形態と同様の構成要素については、図3と同一の符号を付すことで重複した説明を割愛し、以下では、第3実施形態の特徴部分について重点的な説明を行う。
図5は、トランジスタN1の第4実施形態を示す模式図である。本実施形態のトランジスタN1は、先の第1実施形態(図2)をベースとしつつ、パッド210a~210fを単一のパッド210gに集約し、さらに、そのパッド210gの配置レイアウトに工夫を凝らした点に特徴を有する。そこで、第1実施形態と同様の構成要素については、図2と同一の符号を付すことで重複した説明を割愛し、以下では、第4実施形態の特徴部分について重点的な説明を行う。
図6は、半導体装置100における電源ラインの敷設例を示す模式図である。本図の半導体装置100は、n型半導体基板層を土台とする半導体基板300(図2~図5の半導体基板200に相当)を有する。
図7は、トランジスタN1の第5実施形態を示す模式図(上面図)である。本実施形態のトランジスタN1は、横型構造のパワートランジスタであり、半導体基板400と、半導体基板400上に形成されたチャネル領域401と、チャネル領域401から半導体基板400の端辺に向けて敷設されたソース電極402及びドレイン電極403と、各電極上にそれぞれ形成されたワイヤボンディング用のパッド列404及び405と、を含むほか、さらに、ソース電極402上でパッド列404よりもチャネル領域401寄りに偏在配置された電流集中パッド406を含む。
上記では、いずれもハイサイドスイッチを適用対象としてパッドの配置レイアウトに関する説明を行ったが、これまでに説明してきたパッドの配置レイアウトについては、ローサイドスイッチ(図8を参照)にも適用することが可能である。
図10は、トランジスタN1の第6実施形態を示す模式図である。本実施形態では、先出の第3実施形態(図4)をベースとしつつ、実機に即してより具体的な構造が描写されている。なお、本図下段には、本図上段の破線領域(=温度検出素子10aの周辺領域)における縦断面図が描写されている。
図11は、ICレイアウトの一具体例を示す模式図である。本図の半導体装置500には、2チャンネル分のNチャネル型MOS電界効果トランジスタ510及び520(それぞれ先出のトランジスタN1に相当)が集積化されている。
図13は、車両の一構成例を示す外観図である。本構成例の車両Xは、バッテリ(本図では不図示)と、バッテリから電源電圧Vbbの供給を受けて動作する種々の電子機器X11~X18と、を搭載している。なお、本図における電子機器X11~X18の搭載位置については、図示の便宜上、実際とは異なる場合がある。
なお、上記の実施形態では、車載用ハイサイドスイッチICを例に挙げて説明を行ったが、本明細書中に開示されている発明の適用対象は、これに限定されるものではなく、その他の用途に供される車載用IPD[intelligent power device](車載用ローサイドスイッチICや車載用電源ICなど)を始めとして、パワートランジスタを有する半導体装置全般に広く適用することが可能である。
2 定電圧生成回路
3 発振回路
4 チャージポンプ回路
5 ロジック回路
6 ゲート制御回路
7 クランプ回路
8 入力回路
9 基準生成回路
10 温度保護回路
10a 温度検出素子
10a1 高濃度p型半導体領域
10a2 高濃度n型半導体領域
10b メタル配線
11 減電圧保護回路
12 オープン保護回路
13 過電流保護回路
100 半導体装置
200 半導体基板
201 n型半導体基板層
202 低濃度n型半導体層
203 高濃度p型半導体層
204 ゲート酸化膜
205 ゲートポリシリコン
206 高濃度n型半導体領域
207 層間絶縁膜
208 ソース電極(第1電極)
208a スリット
209 ドレイン電極(第2電極)
210a~210g パッド
300 半導体基板
301 パワートランジスタ形成領域
302 ソース電極
303 ドレイン電極(基板電極)
304a、304b 回路形成領域
305a、305b 電源ライン
306a、306b 層間ビア
400 半導体基板
401 チャネル領域
402 ソース電極
403 ドレイン電極
404、405 パッド列
406 電流集中パッド
500 半導体装置
510、520 Nチャネル型MOS電界効果トランジスタ
511、521 ソース電極
512a、512b、522a、522b 主パッド
513、523 副パッド
D10、D20 温度検出素子(ダイオード)
N1 Nチャネル型MOS電界効果トランジスタ(パワートランジスタ)
N2 Nチャネル型MOS電界効果トランジスタ(電流検出トランジスタ)
N3 Nチャネル型MOS電界効果トランジスタ(信号出力トランジスタ)
R1、R2 抵抗
Rs センス抵抗
Z1、Z2 ツェナダイオード
LSW ローサイドスイッチ
X 車両
X11~X18 電子機器
Claims (17)
- 縦型構造のパワートランジスタと、
前記パワートランジスタの異常発熱を検出する温度検出素子と、
を有し、
前記パワートランジスタは、
半導体基板の第1主面側に形成された第1電極と、
前記半導体基板の第2主面側に形成された第2電極と、
前記第1電極上で偏在配置された少なくとも一つのパッドと、
を含み、
前記温度検出素子は、前記パッドの偏在配置により特定される前記パワートランジスタの最大発熱箇所に形成されていることを特徴とする半導体装置。 - 前記パッドは複数であり、最も電流の集中しやすいパッドが唯一に特定されるように前記第1電極上で偏在配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記パッドは単一であり、その周囲における電流密度分布が特定の方向へ偏るように前記第1電極上で偏在配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記第2電極は、前記半導体基板に電源電圧を印加するための基板電極であることを特徴とする請求項1~請求項3のいずれか一項に記載の半導体装置。
- 前記半導体基板の前記第1主面側に形成された電源ラインと、
前記基板電極と前記電源ラインとの間を接続するビアと、
を有することを特徴とする請求項4に記載の半導体装置。 - 前記パワートランジスタは、前記第1電極が負荷に接続されて前記第2電極が電源端に接続されたハイサイドスイッチとして機能することを特徴とする請求項1~請求項5のいずれか一項に記載の半導体装置。
- 前記パワートランジスタは、前記第1電極が接地端に接続されて前記第2電極が負荷に接続されたローサイドスイッチとして機能することを特徴とする請求項1~請求項5のいずれか一項に記載の半導体装置。
- 前記第1電極には、前記温度検出素子の配線を端辺まで引き出すためのスリットが形成されていることを特徴とする請求項1~請求項7のいずれか一項に記載の半導体装置。
- 前記温度検出素子は、前記パッドの近傍に設けられており、
前記スリットは、前記温度検出素子から見て、前記パッドとは反対の方向に向けて形成されていることを特徴とする請求項8に記載の半導体装置。 - 前記複数のパッドは、それらのうちで最も温度保護回路に近いパッドの角部に最も電流が集中するように、前記第1電極上で偏在配置されていることを特徴とする請求項2に記載の半導体装置。
- 前記温度検出素子は、前記角部の近傍に設けられていることを特徴とする請求項10に記載の半導体装置。
- 前記温度検出素子は、前記角部から前記第1電極の端辺に至る複数の方向のうち、前記角部から各端辺までの距離が長い方向に配置されていることを特徴とする請求項10または請求項11に記載の半導体装置。
- 前記複数のパッドは、主パッドと、前記主パッドよりも小さい副パッドと、を含むことを特徴とする請求項10~請求項12のいずれか一項に記載の半導体装置。
- 横型構造のパワートランジスタと、
前記パワートランジスタの異常発熱を検出する温度検出素子と、
を有し、
前記パワートランジスタは、
半導体基板上に形成されたチャネル領域と、
前記チャネル領域から前記半導体基板の端辺に向けて敷設された電極と、
前記電極上に配列されたパッド列と、
前記パッド列よりも前記チャネル領域寄りに配置された電流集中パッドと、
を含み、
前記温度検出素子は、前記電流集中パッドの近傍に形成されていることを特徴とする半導体装置。 - 前記温度検出素子で前記パワートランジスタの異常発熱が検出されたときに前記パワートランジスタを強制的にオフさせる温度保護回路をさらに有することを特徴とする請求項1~請求項14のいずれか一項に記載の半導体装置。
- 請求項15に記載の半導体装置を有することを特徴とする電子機器。
- バッテリと、
前記バッテリから電源電圧の供給を受けて動作する請求項16に記載の電子機器と、
を有することを特徴とする車両。
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CN108807368A (zh) * | 2017-04-28 | 2018-11-13 | 英飞凌科技股份有限公司 | 功率半导体器件和用于形成功率半导体器件的方法 |
CN108807368B (zh) * | 2017-04-28 | 2024-02-02 | 英飞凌科技股份有限公司 | 功率半导体器件和用于形成功率半导体器件的方法 |
JP6573189B1 (ja) * | 2018-06-19 | 2019-09-11 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP2020136288A (ja) * | 2019-02-12 | 2020-08-31 | ローム株式会社 | 半導体装置 |
JP7291495B2 (ja) | 2019-02-12 | 2023-06-15 | ローム株式会社 | 半導体装置 |
Also Published As
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US20220406770A1 (en) | 2022-12-22 |
KR20180042410A (ko) | 2018-04-25 |
US11699698B2 (en) | 2023-07-11 |
CN108140610A (zh) | 2018-06-08 |
KR102089881B1 (ko) | 2020-03-16 |
EP3343598B1 (en) | 2022-03-02 |
EP3343598A4 (en) | 2019-04-10 |
US20180269200A1 (en) | 2018-09-20 |
JP6755375B2 (ja) | 2020-09-16 |
EP3343598A1 (en) | 2018-07-04 |
US20230317713A1 (en) | 2023-10-05 |
JP2019212930A (ja) | 2019-12-12 |
US11469224B2 (en) | 2022-10-11 |
US10964688B2 (en) | 2021-03-30 |
CN108140610B (zh) | 2022-04-01 |
JP6592099B2 (ja) | 2019-10-16 |
JPWO2017057358A1 (ja) | 2018-07-26 |
US20210175229A1 (en) | 2021-06-10 |
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