WO2017049704A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2017049704A1
WO2017049704A1 PCT/CN2015/092809 CN2015092809W WO2017049704A1 WO 2017049704 A1 WO2017049704 A1 WO 2017049704A1 CN 2015092809 W CN2015092809 W CN 2015092809W WO 2017049704 A1 WO2017049704 A1 WO 2017049704A1
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WIPO (PCT)
Prior art keywords
gate
signal
circuit
inverter
transmission
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Ceased
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PCT/CN2015/092809
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English (en)
French (fr)
Inventor
曹尚操
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/893,525 priority Critical patent/US9824658B2/en
Publication of WO2017049704A1 publication Critical patent/WO2017049704A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit and a liquid crystal display.
  • Array substrate row driver (GOA, Gate Driver On Array or Gate On The Array) circuit is formed by using a conventional thin film transistor display device (TFT-LCD) array (Array) process to form a gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • TFT-LCD thin film transistor display device
  • Array gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • COF flexible circuit board
  • COG glass circuit board
  • GOA circuit The main structure of GOA circuit includes forward and reverse scanning circuit, output circuit, signal transmission circuit and latch circuit; currently narrow border and no border are the goals pursued by mobile phone screen; and the width of GOA circuit is the main factor affecting border; GOA CMOS circuits consume a lot of power and are unstable.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can jointly drive a GOA circuit by using two sets of clock signals to improve the stability of the circuit.
  • a technical solution adopted by the present invention is to provide a GOA circuit, wherein the GOA circuit includes a plurality of cascaded GOA units, and each level of the GOA unit includes a transmission circuit, a latch circuit, and a sequentially connected circuit.
  • the transmission circuit is configured to receive the N-1th stage level signal of the N-1th GOA unit during forward scanning, and send it to the latch a circuit; or receiving an N+1th stage signal of the N+1th GOA unit during reverse scanning, and transmitting the signal to the latch circuit;
  • the latch circuit is configured to simultaneously receive the first clock signal and the first period during the scanning a clock signal, and outputting an Nth stage level signal having the same level as the first clock signal and opposite to the second clock signal level;
  • the output circuit is configured to receive the Nth stage level signal and output the level N stage Transmitting an Nth-level scan signal having the same signal level;
  • the transmission circuit includes a first transmission gate and a second transmission gate, and the input end of the first transmission gate is connected to the N-1th-level transmission signal for forward scanning Turn on, send the signal of the N-1th level to the latch circuit;
  • the input end of the second transmission gate is connected to the N+1th level transmission signal for opening in the reverse scanning, and
  • GOA circuit including a plurality of cascaded GOA units, each of which includes a transmission circuit, a latch circuit, and an output circuit; Let N be a positive integer.
  • the transmission circuit is configured to receive the N-1th stage signal of the N-1th GOA unit during forward scanning and send it to the latch circuit; or Receiving an N+1th stage pass signal of the N+1th stage GOA unit in the reverse scan, and transmitting the signal to the latch circuit;
  • the latch circuit is configured to simultaneously receive the first clock signal and the second clock signal during the scan And outputting an Nth-level transmission signal having the same level as the first clock signal and opposite to the second clock signal level;
  • the output circuit is configured to receive the Nth-level transmission signal, and output the signal to the N-th stage The same Nth level scan signal is flat.
  • the latch circuit comprises a first NOR gate and a first transistor, the first transistor is P-type; the first input end of the first NOR gate receives the level transmission signal sent by the transmission circuit, and the output end is connected to the gate of the first transistor a first transistor having a source connected to the first clock signal and a drain connected to the second input terminal of the first NOR gate for outputting the same Nth stage as the first clock signal when the first transistor is turned on Signal.
  • the latch circuit further includes a second transistor and a first inverter, the second transistor is P-type; the source of the second transistor is connected to the second clock signal, and the gate is connected to the output end of the first NOR gate, and the drain The drain of the first transistor is forwardly coupled through the first inverter; wherein the second clock signal is inverted from the first clock signal.
  • the transmission circuit includes a first transmission gate and a second transmission gate, and the input end of the first transmission gate is connected to the N-1th level transmission signal for opening in the forward scanning, and transmitting the N-1th level
  • the signal is sent to the latch circuit; the input end of the second transmission gate is connected to the N+1th stage transmission signal for opening in the reverse scan, and transmitting the N+1th stage transmission signal to the latch circuit.
  • the output circuit includes a second NOR gate, a second inverter, a third inverter, and a fourth inverter connected in sequence; the first input terminal of the second NOR gate receives the Nth sent by the latch circuit The level signal is transmitted, and the second input terminal receives the reset signal.
  • the output of the second NOR gate outputs a low level signal and passes through the second After the inverter, the third inverter, and the fourth inverter, a high-level Nth-level scan signal is output.
  • the output circuit is connected to the transmission circuit for receiving the N-1th level transmission signal during forward scanning and outputting the same Nth level scanning signal as the N-1th stage transmission signal; or during reverse scanning The N+1th stage transmission signal is received, and the same Nth stage scanning signal as the N+1th stage transmission signal is output.
  • the latch circuit includes a third NOR gate, a third transfer gate, a fourth transfer gate, a fifth inverter, and a sixth inverter;
  • the first input terminal of the third NOR gate receives the stage sent by the transmission circuit Transmitting a signal, the output end is respectively connected to a control end of the third transmission gate and the fourth transmission gate, and the output end of the third NOR gate is further connected to the third transmission gate and the fourth transmission gate respectively through the fifth inverter a control terminal;
  • an input end of the third transmission gate is connected to the first clock signal, and an output end is connected to the second input end of the third NOR gate;
  • the input end of the fourth transmission gate is connected to the second clock signal, and the output end is connected through the sixth inversion
  • the device is forwardly connected to the second input of the third NOR gate.
  • the latch circuit includes a fourth NOR gate, a seventh inverter, a first NAND gate, and an eighth inverter; the first input terminal of the fourth NOR gate receives the level transmission signal sent by the transmission circuit, and the output The terminal is connected to the first input end of the first NAND gate through the seventh inverter; the second input end of the first NAND gate is connected to the first clock signal, and the output end is connected to the fourth NOR gate through the eighth inverter The second input end; the output end of the eighth inverter is connected to the output circuit to send the Nth stage level transmission signal to the output circuit.
  • the GOA unit of two adjacent stages includes a set of transmission circuit, a latch circuit and an output circuit; and the transmission circuit is configured to receive the signal of the N-2th stage of the N-2th GOA unit during forward scanning, And sending to the latch circuit; or receiving the N+3 level signal of the N+3 stage GOA unit during reverse scanning, and transmitting the signal to the latch circuit;
  • the latch circuit includes the fifth NOR gate, the second AND Gate, third NAND gate, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, fourth transistor, and fifth transistor; first of fifth or non-gate The input end receives the level transmission signal sent by the transmission circuit, and the output end is connected to the first input end of the second NAND gate and the first input end of the third NAND gate through the ninth inverter and the eleventh inverter respectively.
  • the output end of the second NAND gate is connected to the output circuit through the tenth inverter, the output end of the third NAND gate is connected to the output circuit through the twelfth inverter, and the second input end of the second NAND gate is connected to the third a clock signal, a second input terminal of the third NAND gate is connected to the fourth clock signal; the fourth transistor and the fifth crystal
  • the drains of the tubes are respectively connected to the output ends of the tenth inverter and the twelfth inverter, the source is connected to the second input end of the fifth NOR gate, and the gates are respectively connected to the fourth clock signal and the third clock signal;
  • the output circuit is connected to the output ends of the tenth inverter and the twelfth inverter, respectively, to output the Nth scan signal and the N+1th scan signal, respectively.
  • a liquid crystal display including a GOA circuit, the GOA circuit including a plurality of cascaded GOA units, each of which includes a transmission circuit, a latch circuit and an output circuit; let N be a positive integer, in the Nth stage GOA unit: the transmission circuit is configured to receive the N-1th level signal of the N-1th GOA unit during forward scanning, and Sending to the latch circuit; or receiving the N+1th stage pass signal of the N+1th GOA unit in the reverse scan, and transmitting the signal to the latch circuit; the latch circuit is configured to receive the first time during the scan a clock signal and a second clock signal, and output an Nth stage level signal having the same level as the first clock signal and opposite to the second clock signal level; the output circuit is configured to receive the Nth stage level signal, and output the The Nth stage transmits an Nth-level scan signal having the same signal level.
  • the latch circuit comprises a first NOR gate and a first transistor, the first transistor is P-type; the first input end of the first NOR gate receives the level transmission signal sent by the transmission circuit, and the output end is connected to the gate of the first transistor a first transistor having a source connected to the first clock signal and a drain connected to the second input terminal of the first NOR gate for outputting the same Nth stage as the first clock signal when the first transistor is turned on Signal.
  • the latch circuit further includes a second transistor and a first inverter, the second transistor is P-type; the source of the second transistor is connected to the second clock signal, and the gate is connected to the output end of the first NOR gate, and the drain The drain of the first transistor is forwardly coupled through the first inverter; wherein the second clock signal is inverted from the first clock signal.
  • the transmission circuit includes a first transmission gate and a second transmission gate, and the input end of the first transmission gate is connected to the N-1th level transmission signal for opening in the forward scanning, and transmitting the N-1th level
  • the signal is sent to the latch circuit; the input end of the second transmission gate is connected to the N+1th stage transmission signal for opening in the reverse scan, and transmitting the N+1th stage transmission signal to the latch circuit.
  • the output circuit includes a second NOR gate, a second inverter, a third inverter, and a fourth inverter connected in sequence; the first input terminal of the second NOR gate receives the Nth sent by the latch circuit The level signal is transmitted, and the second input terminal receives the reset signal.
  • the output of the second NOR gate outputs a low level signal and passes through the second After the inverter, the third inverter, and the fourth inverter, a high-level Nth-level scan signal is output.
  • the output circuit is connected to the transmission circuit for receiving the N-1th level transmission signal during forward scanning and outputting the same Nth level scanning signal as the N-1th stage transmission signal; or during reverse scanning The N+1th stage transmission signal is received, and the same Nth stage scanning signal as the N+1th stage transmission signal is output.
  • the latch circuit includes a third NOR gate, a third transfer gate, a fourth transfer gate, a fifth inverter, and a sixth inverter;
  • the first input terminal of the third NOR gate receives the stage sent by the transmission circuit Transmitting a signal, the output end is respectively connected to a control end of the third transmission gate and the fourth transmission gate, and the output end of the third NOR gate is further connected to the third transmission gate and the fourth transmission gate respectively through the fifth inverter a control terminal;
  • an input end of the third transmission gate is connected to the first clock signal, and an output end is connected to the second input end of the third NOR gate;
  • the input end of the fourth transmission gate is connected to the second clock signal, and the output end is connected through the sixth inversion
  • the device is forwardly connected to the second input of the third NOR gate.
  • the latch circuit includes a fourth NOR gate, a seventh inverter, a first NAND gate, and an eighth inverter; the first input terminal of the fourth NOR gate receives the level transmission signal sent by the transmission circuit, and the output The terminal is connected to the first input end of the first NAND gate through the seventh inverter; the second input end of the first NAND gate is connected to the first clock signal, and the output end is connected to the fourth NOR gate through the eighth inverter The second input end; the output end of the eighth inverter is connected to the output circuit to send the Nth stage level transmission signal to the output circuit.
  • the GOA unit of two adjacent stages includes a set of transmission circuit, a latch circuit and an output circuit; and the transmission circuit is configured to receive the signal of the N-2th stage of the N-2th GOA unit during forward scanning, And sending to the latch circuit; or receiving the N+3 level signal of the N+3 stage GOA unit during reverse scanning, and transmitting the signal to the latch circuit;
  • the latch circuit includes the fifth NOR gate, the second AND Gate, third NAND gate, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, fourth transistor, and fifth transistor; first of fifth or non-gate The input end receives the level transmission signal sent by the transmission circuit, and the output end is connected to the first input end of the second NAND gate and the first input end of the third NAND gate through the ninth inverter and the eleventh inverter respectively.
  • the output end of the second NAND gate is connected to the output circuit through the tenth inverter, the output end of the third NAND gate is connected to the output circuit through the twelfth inverter, and the second input end of the second NAND gate is connected to the third a clock signal, a second input terminal of the third NAND gate is connected to the fourth clock signal; the fourth transistor and the fifth crystal
  • the drains of the tubes are respectively connected to the output ends of the tenth inverter and the twelfth inverter, the source is connected to the second input end of the fifth NOR gate, and the gates are respectively connected to the fourth clock signal and the third clock signal;
  • the output circuit is connected to the output ends of the tenth inverter and the twelfth inverter, respectively, to output the Nth scan signal and the N+1th scan signal, respectively.
  • the present invention has the beneficial effects that, different from the prior art, the present invention provides a GOA circuit comprising a plurality of cascaded GOA units, each stage of which includes a transmission circuit, a latch circuit and an output.
  • a circuit in the Nth stage GOA unit, the transmission circuit is configured to receive the N-1th stage signal of the N-1th GOA unit during forward scanning, and send the signal to the latch circuit; or in the reverse scan Receiving an N+1th stage signal of the N+1th GOA unit and transmitting the signal to the latch circuit; the latch circuit is configured to simultaneously receive the first clock signal and the second clock signal during the scanning, and output the The first clock signal has the same level, and the Nth stage signal is opposite to the second clock signal level; the output circuit is configured to receive the Nth stage level signal and output the same level as the Nth stage level signal N-level scan signal.
  • the present embodiment uses two clock signals to simultaneously drive to prevent failure of the clock signal when switching between high and low levels, thereby improving the stability of the circuit.
  • FIG. 1 is a schematic diagram showing the circuit structure of an embodiment of a GOA circuit of the present invention
  • FIG. 2 is a schematic diagram showing the circuit structure of an Nth stage GOA unit in an embodiment of the GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of an Nth stage GOA unit in the first embodiment of the GOA circuit of the present invention
  • FIG. 4 is a circuit timing diagram of an Nth stage GOA unit in the first embodiment of the GOA circuit of the present invention
  • Figure 5 is a circuit diagram of an Nth stage GOA unit in a second embodiment of the GOA circuit of the present invention.
  • FIG. 6 is a circuit diagram of an Nth stage GOA unit in a third embodiment of the GOA circuit of the present invention.
  • FIG. 7 is a circuit diagram of an Nth stage GOA unit in a fourth embodiment of the GOA circuit of the present invention.
  • Figure 8 is a circuit diagram of an Nth stage GOA unit in a fifth embodiment of the GOA circuit of the present invention.
  • FIG. 9 is a schematic structural view of an embodiment of a liquid crystal display of the present invention.
  • a schematic diagram of a circuit structure of an embodiment of a GOA circuit of the present invention includes a plurality of cascaded GOA units, wherein during a forward scan, a first stage GOA unit receives an STV level transmission signal, and each subsequent Each of the primary GOA units receives the level-transmitted signal from the upper-level GOA unit, for example, the N-th stage GOA circuit receives the N-1th-level transmitted signal Q(N-1) of the N-1th-level GOA output; or During the reverse scan, the last stage GOA unit receives the STV level transmission signal, and each subsequent GOA unit receives the level transmission signal sent by the next stage GOA unit. For example, the Nth stage GOA circuit receives the N+1th stage. The N+1th stage of the GOA output transmits a signal Q(N+1).
  • Each stage of the GOA unit includes a transmission circuit 101, a latch circuit 102, and an output circuit 103.
  • N be a positive integer, in the Nth level GOA unit:
  • the transmission circuit 101 is configured to receive the N-1th stage-level signal Q(N-1) of the N-1th stage GOA unit during forward scanning, and send it to the latch circuit 102; or receive in reverse scan
  • the N+1th stage of the N+1th GOA unit transmits the signal Q(N+1) and sends it to the latch circuit 102.
  • the latch circuit 102 is configured to start to operate according to the level transmission signal sent by the transmission circuit 101, that is, when receiving the N-1th stage transmission signal Q(N-1) transmitted by the transmission circuit 101 is high, the reception clock signal is turned on.
  • the channel starts scanning. During the scanning, the first clock signal XCK(N) and the second clock signal CK(N) are simultaneously received, and the output is the same level as the first clock signal XCK(N), and the second clock signal CK(N) level
  • the opposite Nth stage passes the signal Q(N).
  • the output circuit 103 is for receiving the Nth stage level transmission signal Q(N) and outputting the Nth stage scanning signal G(N) of the same level as the Nth stage level transmission signal Q(N).
  • the present embodiment provides a GOA circuit including a plurality of cascaded GOA units, each of which includes a transmission circuit, a latch circuit, and an output circuit; in the Nth stage GOA unit
  • the transmission circuit is configured to receive the N-1th stage signal Q(N-1) of the N-1th stage GOA unit during forward scanning, and send it to the latch circuit; or receive during reverse scanning
  • the N+1th stage of the N+1th GOA unit transmits a signal Q(N+1) and sends it to the latch circuit
  • the latch circuit is configured to simultaneously receive the first clock signal XCK(N) during the scan and a second clock signal CK(N), and outputting an Nth stage-level signal Q(N) having the same level as the first clock signal XCK(N) and opposite to the second clock signal CK(N);
  • the output circuit It is configured to receive the Nth stage level transmission signal Q(N), and output an Nth stage scanning signal G(N) of the same level as the Nth stage level transmission signal Q(N).
  • FIG. 3 there is shown a circuit diagram of an Nth stage GOA unit in the first embodiment of the GOA circuit of the present invention.
  • the transmission circuit 301 includes a first transmission gate G1 and a second transmission gate G2.
  • the input end of the first transmission gate G1 is connected to the N-1th level transmission signal Q(N-1) for forward scanning. Turning on, transmitting the N-1th level transmission signal Q(N-1) to the latch circuit 302; the input end of the second transmission gate G2 is connected to the N+1th level transmission signal Q(N+1), When turned on in the reverse scan, the N+1th stage pass signal Q(N+1) is sent to the latch circuit 302.
  • the latch circuit 302 includes a first NOR gate H1 and a first transistor T1, and the first transistor T1 is P-type; the first input end of the first NOR gate H1 receives the level transmission signal sent by the transmission circuit 301, and the output end The gate of the first transistor T1 is connected; the source of the first transistor T1 is connected to the first clock signal XCK(N), and the drain is connected to the second input terminal of the first NOR gate H1.
  • the latch circuit 302 further includes a second transistor T2 and a first inverter F1, the second transistor T2 is P-type; the source of the second transistor T2 is connected to the second clock signal CK(N), and the gate is connected to the first At the output of the NOR gate H1, the drain is forwardly connected to the drain of the first transistor T1 through the first inverter F1.
  • the latch circuit 302 further includes a third transistor T3, which is N-type, whose gate is connected to the output end of the first inverter F1, and the drain is connected to the input end of the first inverter F1, the source.
  • the pole is connected to a low level signal for stabilizing the voltage at the output of the first inverter F1.
  • the output circuit 303 includes a second NOR gate H2, a second inverter F2, a third inverter F3, and a fourth inverter F4 connected in sequence; the first input terminal of the second NOR gate H2 receives the lock.
  • the Nth stage transmits the signal Q(N) sent by the memory circuit, and the second input receives the reset signal Reset.
  • the second inverter F2 is for inverting the output signal
  • the third inverter F3 and the fourth inverter F4 function as a buffer.
  • the following example is only the timing of each node of the circuit in the Nth stage GOA unit in the forward scan, wherein during the forward scan, the D2U in the circuit of each level of the GOA unit is low, and the U2D is high.
  • the level is such that the first transmission gate G1 is always open to receive the level transmission signal of the upper level GOA unit.
  • the second clock signal CK(N) is at a high level, and the second transistor T2 is turned on, so that the input terminal of the first inverter F1 generates a high level, and thus outputs a low level.
  • the gate of the third transistor T3 is at a low level and is not turned on.
  • the output end of the second NOR gate H2 is a high level signal, and after passing through the second inverter F2, the third inverter F3, and the fourth inverter F4, outputs an Nth-level scan signal of a low level.
  • G(N) The second clock signal CK(N) is at a high level, and the second transistor T2 is turned on, so that the input terminal of the first inverter F1 generates a high level, and thus outputs a low level.
  • the gate of the third transistor T3 is at a low level and is not turned on.
  • the output end of the second NOR gate H2 is a high level signal, and after passing through the second inverter F2, the third
  • the third transistor T3 Since Q(N) is a high level, the third transistor T3 is turned on, so that the input end of the first inverter F1 is connected to a low level, and then a high level signal is output to ensure that the high level of Q(N) is stable. .
  • the output end of the second NOR gate H2 is a low level signal, and after passing through the second inverter F2, the third inverter F3, and the fourth inverter F4, outputs an Nth-level scan signal of a high level. G(N).
  • the third transistor T3 Since Q(N) is a high level, the third transistor T3 is turned on, so that the input end of the first inverter F1 is connected to a low level, and then a high level signal is output to ensure that the high level of Q(N) is stable. .
  • the output end of the second NOR gate H2 is a low level signal, and after passing through the second inverter F2, the third inverter F3, and the fourth inverter F4, outputs an Nth-level scan signal of a high level. G(N).
  • Q(N-1) is high level
  • XCK(N) is low level
  • CK(N) is high level
  • X(N) is low level
  • Q(N) Instantly becomes low level
  • point a is low level, that is, the first input end and the second input end of the first NOR gate H1 are input with low level
  • the first NOR gate H1 is caused to output a high level, that is, the b point is at a high level, and therefore, the first transistor T1 and the second transistor T2 are both turned off.
  • the gate of the third transistor T3 is at a low level and is not turned on.
  • the output end of the second NOR gate H2 is a high level signal, and after passing through the second inverter F2, the third inverter F3, and the fourth inverter F4, outputs an Nth-level scan signal of a low level.
  • the first clock signal and the second clock signal of each stage are different.
  • the clock signal of each stage is more than the corresponding front.
  • the clock signal of one stage is delayed by half cycle, that is, two action sections in FIG. 4; in addition, in this embodiment, the clock signal of each stage can be delayed by 1/4 of the clock signal of the corresponding previous stage.
  • the second clock signal CK(N) of the Nth stage GOA unit is smaller than the second clock signal CK(N-1) of the N-1th stage GOA unit
  • the scanning signals of the adjacent two stages are also delayed by 1/4 period, that is, the high levels overlap each other.
  • this embodiment discloses a specific circuit of a GOA unit, which passes the first clock signal XCK(N).
  • the two clock signals are driven together with the second clock signal CK(N) to improve the stability of the circuit.
  • the corresponding clock signals of the adjacent two stages adopt overlapping timing settings, which can reduce the latch circuit when the level is high and low.
  • the risk of failure; in addition, the implementation of logic functions using devices such as NOR gates can reduce the power consumption of the circuit and reduce leakage.
  • a circuit diagram of an Nth stage GOA unit in a second embodiment of the GOA circuit of the present invention includes a transmission circuit 501, a latch circuit 502, and an output circuit 503.
  • the output circuit 503 is connected to the transmission circuit 501 for receiving the N-1th stage transmission signal Q(N-1) during the forward scanning, and outputting the signal N(N-1) with the N-1th stage.
  • the same Nth-level scanning signal G(N); or receiving the N+1th-level transmission signal Q(N+1) in the reverse scanning, and outputting the signal with the N+1th order signal Q(N+1) The same Nth-level scan signal G(N).
  • the transmission circuit 501, the latch circuit 502, and the output circuit 503 of the present embodiment are identical to the circuit of the second embodiment of the GOA circuit of the present invention, except that the output circuit 503 no longer receives the Q issued by the latch circuit 502.
  • the (N) signal receives the Q(N-1) signal from the transmission circuit 501, and the latch module 502 provides only the level-transmitted signal, thereby improving the stability of the circuit.
  • a circuit diagram of an Nth stage GOA unit in a third embodiment of the GOA circuit of the present invention includes a transmission circuit 601, a latch circuit 602, and an output circuit 603.
  • the transmission circuit 601 and the output circuit 603 are the same as the corresponding circuits in the above embodiments, except that the latch circuit of the present embodiment includes a third NOR gate H3, a third transmission gate G3, and a fourth transmission gate. G4, a fifth inverter F5, and a sixth inverter F6.
  • the first input end of the third NOR gate H3 receives the level transmission signal sent by the transmission circuit, and the output end is respectively connected to a control end of the third transmission gate G3 and the fourth transmission gate G4, and the output of the third NOR gate H3.
  • the terminal further connects the third transmission gate G3 and the other control terminal of the fourth transmission gate G4 through the fifth inverter F5; the input end of the third transmission gate G3 is connected to the first clock signal XCK(N), and the output terminal is connected.
  • the latch circuit of the present embodiment uses a NAND gate transfer gate to constitute a latch module, and can stabilize the potential of the Q(N) point.
  • a circuit diagram of an Nth stage GOA unit in a fourth embodiment of the GOA circuit of the present invention includes a transmission circuit 701, a latch circuit 702, and an output circuit 703.
  • the transmission circuit 701 and the output circuit 703 are the same as the corresponding circuits in the above embodiments, except that the latch circuit of the present embodiment includes a fourth NOR gate H4, a seventh inverter F7, and the first The NOT gate Y1 and the eighth inverter F8.
  • the first input end of the fourth NOR gate H4 receives the level transmission signal sent by the transmission circuit, and the output end is connected to the first input end of the first NAND gate Y1 through the seventh inverter F7; the first NAND gate Y1
  • the second input terminal is connected to the first clock signal XCK(N), the output terminal is connected to the second input terminal of the fourth NOR gate H4 through the eighth inverter F8; the output end of the eighth inverter F8 is connected to the output circuit to
  • the output circuit transmits an Nth stage pass signal Q(N).
  • the latch circuit of the present embodiment uses a NAND gate plus NAND gate to form a latch module, which can reduce the power consumption of the circuit.
  • a reset circuit as shown in FIGS. 3, 5, 6, and 7 may be added to the node where Q(N) is located for resetting the circuit before or after scanning.
  • FIG. 8 a circuit diagram of an Nth stage GOA unit in a fifth embodiment of the GOA circuit of the present invention, wherein two adjacent stages of GOA units include a set of transmission circuits 801, a latch circuit 802, and an output circuit 803.
  • the latch circuit 802 of the present embodiment combines the latch circuits 702 of the fifth embodiment of the GOA circuit of the present invention into a new latch circuit 802; in the fifth embodiment of the GOA circuit of the present invention The output circuits 703 are combined to form a new output circuit 803.
  • the transmission circuit 801 is configured to receive the N-2th stage-level signal Q(N-2) of the N-2th stage GOA unit during forward scanning, and send it to the latch circuit 802; or in the reverse direction
  • the N+3 level pass signal Q(N+3) of the N+3 stage GOA unit is received during scanning and sent to the latch circuit 802.
  • the latch circuit 802 includes a fifth NOR gate H5, a second NAND gate Y2, a third NAND gate Y3, a ninth inverter F9, a tenth inverter F10, an eleventh inverter F11, and a tenth.
  • the inverter F11 is connected to the first input end of the second NAND gate Y2 and the first input end of the third NAND gate Y3, and the output end of the second NAND gate Y2 is connected to the output circuit through the tenth inverter F10,
  • the output end of the third NAND gate Y3 is connected to the output circuit through the twelfth inverter F12, the second input end of the second NAND gate Y2 is connected to the third clock signal, and the second input end of the third NAND gate Y3 is connected.
  • the drains of the fourth transistor T4 and the fifth transistor T5 are respectively connected to the output ends of the tenth inverter F10 and the twelfth inverter F12, and the source is connected to the second input terminal of the fifth NOR gate H5
  • the gate is respectively connected to the fourth clock signal and the third clock signal
  • the output circuit is respectively connected to the tenth inverter F10 and the twelfth reverse
  • the output of the phaser F12 outputs an Nth-th scan signal G(N) and an N+1-th scan signal G(N+1), respectively.
  • the third clock signal and the fourth clock signal may also be two signals whose timing overlaps, wherein the fourth clock signal is delayed by 1/4 cycle of the third clock signal.
  • the present embodiment combines two levels of GOA units into the same unit and shares one transmission circuit, which reduces the number of electronic devices and reduces power consumption.
  • the liquid crystal display includes a display panel 901 and a backlight 902.
  • the display panel 901 includes a GOA circuit, wherein the GOA circuit is a GOA circuit according to various embodiments described above. The specific implementation is similar, and details are not described herein again.

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Abstract

一种GOA电路及液晶显示器，该GOA电路包括多个级联的GOA单元，每一级的GOA单元均包括传输电路（101、201、301、401、501、601、701、801）、锁存电路（102、202、302、402、502、602、702、802）以及输出电路（103、203、303、403、503、603、703、803）；传输电路（101、201、301、401、501、601、701、801）用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号（Q(N-1)），并发送给锁存电路（102、202、302、402、502、602、702、802）；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号（Q(N+1)），并发送给锁存电路（102、202、302、402、502、602、702、802）；锁存电路（102、202、302、402、502、602、702、802）用于在扫描期间，同时接收第一时钟信号（XCK(N)）以及第二时钟信号（CK (N)），并输出与第一时钟信号（XCK (N)）电平相同，与第二时钟信号（CK (N)）电平相反的第N级级传信号（Q(N)）；输出电路（103、203、303、403、503、603、703、803）用于接收第N级级传信号（Q(N)），并输出与第N级级传信号电平相同的第N级扫描信号（G(N)）。通过上述方式，能够通过两组时钟信号共同驱动GOA电路，提高电路的稳定性。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及显示技术领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
阵列基板行驱动（GOA，Gate Driver On Array 或Gate On Array）电路，是利用现有薄膜晶体管显示装置（TFT-LCD）阵列（Array）制程将栅线（Gate）行扫描驱动信号电路制作在阵列基板上，以实现对栅线逐行扫描的驱动方式的一项技术。其与传统的柔性电路板（COF）和玻璃电路板（COG）工艺相比，不仅节省了制作成本，而且还可以省去栅极方向邦定（Bonding）的工艺，对提升产能极为有利，并提高了显示装置的集成度。
CMOS GOA电路的主要架构有正反向扫描电路、输出电路、讯号传递电路和锁存电路；目前窄边框和无边框是手机屏追求的目标；而GOA电路的宽度是影响border的主要因素；另外目前的GOA CMOS电路功耗较大，而且不稳定。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够采用两组时钟信号共同驱动GOA电路，提高电路的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，其中，GOA电路包括多个级联的GOA单元，每级GOA单元均包括依次连接的传输电路、锁存电路以及输出电路；设N为正整数，在第N级GOA单元中：传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给锁存电路；锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与第一时钟信号电平相同，与第二时钟信号电平相反的第N级级传信号；输出电路用于接收第N级级传信号，并输出与第N级级传信号电平相同的第N级扫描信号；传输电路包括第一传输门以及第二传输门，第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将第N-1级级传信号发送给锁存电路；第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将第N+1级级传信号发送给锁存电路；输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；第二或非门的第一输入端接收锁存电路发送的第N级级传信号，第二输入端接收复位信号，当第N级级传信号和复位信号中至少一个为高电平时，第二或非门的输出端输出低电平信号，并在通过第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，该GOA电路包括多个级联的GOA单元，每级GOA单元均包括传输电路、锁存电路以及输出电路；设N为正整数，在第N级GOA单元中：传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给锁存电路；锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与第一时钟信号电平相同，与第二时钟信号电平相反的第N级级传信号；输出电路用于接收第N级级传信号，并输出与第N级级传信号电平相同的第N级扫描信号。
其中，锁存电路包括第一或非门和第一晶体管，第一晶体管为P型；第一或非门的第一输入端接收传输电路发送的级传信号，输出端连接第一晶体管的栅极；第一晶体管的源极连接第一时钟信号，漏极连接第一或非门的第二输入端，用于在第一晶体管导通时，输出与第一时钟信号相同的第N级级传信号。
其中，锁存电路还包括第二晶体管以及第一反相器，第二晶体管为P型；第二晶体管的源极连接第二时钟信号，栅极连接第一或非门的输出端，漏极通过第一反相器正向连接第一晶体管的漏极；其中，第二时钟信号与第一时钟信号反向。
其中，传输电路包括第一传输门以及第二传输门，第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将第N-1级级传信号发送给锁存电路；第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将第N+1级级传信号发送给锁存电路。
其中，输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；第二或非门的第一输入端接收锁存电路发送的第N级级传信号，第二输入端接收复位信号，当第N级级传信号和复位信号中至少一个为高电平时，第二或非门的输出端输出低电平信号，并在通过第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
其中，输出电路连接传输电路，用于在正向扫描时接收第N-1级级传信号，并输出与第N-1级级传信号相同的第N级扫描信号；或在反向扫描时接收第N+1级级传信号，并输出与第N+1级级传信号相同的第N级扫描信号。
其中，锁存电路包括第三或非门、第三传输门、第四传输门、第五反相器以及第六反相器；第三或非门的第一输入端接收传输电路发送的级传信号，输出端分别连接第三传输门与第四传输门的一控制端，第三或非门的输出端还通过第五反相器分别连接第三传输门与第四传输门的另一控制端；第三传输门的输入端连接第一时钟信号，输出端连接第三或非门的第二输入端；第四传输门的输入端连接第二时钟信号，输出端通过第六反相器正向连接第三或非门的第二输入端。
其中，锁存电路包括第四或非门、第七反相器、第一与非门以及第八反相器；第四或非门的第一输入端接收传输电路发送的级传信号，输出端通过第七反相器连接第一与非门的第一输入端；第一与非门的第二输入端连接第一时钟信号，输出端通过第八反相器连接第四或非门的第二输入端；第八反相器的输出端连接输出电路，以向输出电路发送第N级级传信号。
其中，相邻两级的GOA单元包括一组传输电路、锁存电路以及输出电路；传输电路用于在正向扫描时，接收第N-2级GOA单元的第N-2级级传信号，并发送给锁存电路；或在反向扫描时接收N+3级GOA单元的N+3级级传信号，并发送给锁存电路；锁存电路包括第五或非门、第二与非门、第三与非门、第九反相器、第十反相器、第十一反相器、第十二反相器、第四晶体管以及第五晶体管；第五或非门的第一输入端接收传输电路发送的级传信号，输出端分别通过第九反相器以及第十一反相器连接第二与非门的第一输入端以及第三与非门的第一输入端，第二与非门的输出端通过第十反相器连接输出电路，第三与非门的输出端通过第十二反相器连接输出电路，第二与非门的第二输入端连接第三时钟信号，第三与非门的第二输入端连接第四时钟信号；第四晶体管以及第五晶体管的漏极分别连接第十反相器和第十二反相器的输出端，源极连接第五或非门的第二输入端，栅极分别连接第四时钟信号和第三时钟信号；输出电路分别连接第十反相器和第十二反相器的输出端以分别输出第N级扫描信号和第N+1级扫描信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，该液晶显示器包括GOA电路，该GOA电路包括多个级联的GOA单元，每级GOA单元均包括传输电路、锁存电路以及输出电路；设N为正整数，在第N级GOA单元中：传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给锁存电路；锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与第一时钟信号电平相同，与第二时钟信号电平相反的第N级级传信号；输出电路用于接收第N级级传信号，并输出与第N级级传信号电平相同的第N级扫描信号。
其中，锁存电路包括第一或非门和第一晶体管，第一晶体管为P型；第一或非门的第一输入端接收传输电路发送的级传信号，输出端连接第一晶体管的栅极；第一晶体管的源极连接第一时钟信号，漏极连接第一或非门的第二输入端，用于在第一晶体管导通时，输出与第一时钟信号相同的第N级级传信号。
其中，锁存电路还包括第二晶体管以及第一反相器，第二晶体管为P型；第二晶体管的源极连接第二时钟信号，栅极连接第一或非门的输出端，漏极通过第一反相器正向连接第一晶体管的漏极；其中，第二时钟信号与第一时钟信号反向。
其中，传输电路包括第一传输门以及第二传输门，第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将第N-1级级传信号发送给锁存电路；第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将第N+1级级传信号发送给锁存电路。
其中，输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；第二或非门的第一输入端接收锁存电路发送的第N级级传信号，第二输入端接收复位信号，当第N级级传信号和复位信号中至少一个为高电平时，第二或非门的输出端输出低电平信号，并在通过第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
其中，输出电路连接传输电路，用于在正向扫描时接收第N-1级级传信号，并输出与第N-1级级传信号相同的第N级扫描信号；或在反向扫描时接收第N+1级级传信号，并输出与第N+1级级传信号相同的第N级扫描信号。
其中，锁存电路包括第三或非门、第三传输门、第四传输门、第五反相器以及第六反相器；第三或非门的第一输入端接收传输电路发送的级传信号，输出端分别连接第三传输门与第四传输门的一控制端，第三或非门的输出端还通过第五反相器分别连接第三传输门与第四传输门的另一控制端；第三传输门的输入端连接第一时钟信号，输出端连接第三或非门的第二输入端；第四传输门的输入端连接第二时钟信号，输出端通过第六反相器正向连接第三或非门的第二输入端。
其中，锁存电路包括第四或非门、第七反相器、第一与非门以及第八反相器；第四或非门的第一输入端接收传输电路发送的级传信号，输出端通过第七反相器连接第一与非门的第一输入端；第一与非门的第二输入端连接第一时钟信号，输出端通过第八反相器连接第四或非门的第二输入端；第八反相器的输出端连接输出电路，以向输出电路发送第N级级传信号。
其中，相邻两级的GOA单元包括一组传输电路、锁存电路以及输出电路；传输电路用于在正向扫描时，接收第N-2级GOA单元的第N-2级级传信号，并发送给锁存电路；或在反向扫描时接收N+3级GOA单元的N+3级级传信号，并发送给锁存电路；锁存电路包括第五或非门、第二与非门、第三与非门、第九反相器、第十反相器、第十一反相器、第十二反相器、第四晶体管以及第五晶体管；第五或非门的第一输入端接收传输电路发送的级传信号，输出端分别通过第九反相器以及第十一反相器连接第二与非门的第一输入端以及第三与非门的第一输入端，第二与非门的输出端通过第十反相器连接输出电路，第三与非门的输出端通过第十二反相器连接输出电路，第二与非门的第二输入端连接第三时钟信号，第三与非门的第二输入端连接第四时钟信号；第四晶体管以及第五晶体管的漏极分别连接第十反相器和第十二反相器的输出端，源极连接第五或非门的第二输入端，栅极分别连接第四时钟信号和第三时钟信号；输出电路分别连接第十反相器和第十二反相器的输出端以分别输出第N级扫描信号和第N+1级扫描信号。
本发明的有益效果是：区别于现有技术的情况，本发明提供了一种GOA电路，该GOA电路包括多个级联的GOA单元，每级GOA单元均包括传输电路、锁存电路以及输出电路；在第N级GOA单元中，传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给锁存电路；锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与第一时钟信号电平相同，与第二时钟信号电平相反的第N级级传信号；输出电路用于接收第N级级传信号，并输出与第N级级传信号电平相同的第N级扫描信号。通过上述方式，本实施方式采用两个时钟信号同时进行驱动，防止时钟信号高低电平转换时失效，提高电路的稳定性。
【附图说明】
图1是本发明GOA电路一实施方式的电路结构示意图；
图2是本发明GOA电路一实施方式中第N级GOA单元的电路结构示意图；
图3是本发明GOA电路第一实施方式中第N级GOA单元的电路图；
图4是本发明GOA电路第一实施方式中第N级GOA单元的电路时序图；
图5是本发明GOA电路第二实施方式中第N级GOA单元的电路图；
图6是本发明GOA电路第三实施方式中第N级GOA单元的电路图；
图7是本发明GOA电路第四实施方式中第N级GOA单元的电路图；
图8是本发明GOA电路第五实施方式中第N级GOA单元的电路图；
图9是本发明液晶显示器一实施方式的结构示意图。
【具体实施方式】
参阅图1，本发明GOA电路一实施方式的电路结构示意图，该GOA电路包括多个级联的GOA单元，其中，在正向扫描期间，第一级GOA单元接收STV级传信号，以后的每一级GOA单元均接收上一级GOA单元发出的级传信号，例如，第N级GOA电路均接收第N-1级GOA输出的第N-1级级传信号Q(N-1)；或在反向扫描期间，最后一级GOA单元接收STV级传信号，以后的每一级GOA单元均接收下一级GOA单元发出的级传信号，例如，第N级GOA电路接收第N+1级GOA输出的第N+1级级传信号Q(N+1)。
同时参阅图2，本发明GOA电路一实施方式中第N级GOA单元的电路结构示意图，每级GOA单元均包括传输电路101、锁存电路102以及输出电路103。
设N为正整数，在第N级GOA单元中：
传输电路101用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号Q(N-1)，并发送给锁存电路102；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号Q(N+1)，并发送给锁存电路102。
锁存电路102用于根据传输电路101发送的级传信号开始工作，即当接收到传输电路101发送的第N-1级级传信号Q(N-1)为高电平时，开启接收时钟信号的通道，即开始扫描。在扫描期间，同时接收第一时钟信号XCK(N)以及第二时钟信号CK(N)，并输出与第一时钟信号XCK(N)电平相同，与第二时钟信号CK(N)电平相反的第N级级传信号Q(N)。
输出电路103用于接收第N级级传信号Q(N)，并输出与第N级级传信号Q(N)电平相同的第N级扫描信号G(N)。
区别于现有技术，本实施方式提供了一种GOA电路，该GOA电路包括多个级联的GOA单元，每级GOA单元均包括传输电路、锁存电路以及输出电路；在第N级GOA单元中，传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号Q(N-1)，并发送给锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号Q(N+1)，并发送给锁存电路；锁存电路用于在扫描期间，同时接收第一时钟信号XCK(N)以及第二时钟信号CK(N)，并输出与第一时钟信号XCK(N)电平相同，与第二时钟信号CK(N)电平相反的第N级级传信号Q(N)；输出电路用于接收第N级级传信号Q(N)，并输出与第N级级传信号Q(N)电平相同的第N级扫描信号G(N)。通过上述方式，本实施方式采用两个时钟信号同时进行驱动，防止时钟信号高低电平转换时失效，提高电路的稳定性。
参阅图3，本发明GOA电路第一实施方式中第N级GOA单元的电路图。
其中，传输电路301包括第一传输门G1以及第二传输门G2，第一传输门G1的输入端接入第N-1级级传信号Q(N-1)，用于在正向扫描时打开，将第N-1级级传信号Q(N-1)发送给锁存电路302；第二传输门G2的输入端接入第N+1级级传信号Q(N+1)，用于在反向扫描时打开，将第N+1级级传信号Q(N+1)发送给锁存电路302。
其中，锁存电路302包括第一或非门H1和第一晶体管T1，第一晶体管T1为P型；第一或非门H1的第一输入端接收传输电路301发送的级传信号，输出端连接第一晶体管T1的栅极；第一晶体管T1的源极连接第一时钟信号XCK(N)，漏极连接第一或非门H1的第二输入端。
其中，锁存电路302还包括第二晶体管T2以及第一反相器F1，第二晶体管T2为P型；第二晶体管T2的源极连接第二时钟信号CK(N)，栅极连接第一或非门H1的输出端，漏极通过第一反相器F1正向连接第一晶体管T1的漏极。
另外，锁存电路302还包括第三晶体管T3，该第三晶体管T3为N型，其栅极连接第一反相器F1的输出端，漏极连接第一反相器F1的输入端，源极接入一低电平信号，用于稳定第一反相器F1输出端的电压。
其中，输出电路303包括依次连接的第二或非门H2、第二反相器F2、第三反相器F3以及第四反相器F4；第二或非门H2的第一输入端接收锁存电路发送的第N级级传信号Q(N)，第二输入端接收复位信号Reset。
具体地，第二反相器F2用于使输出信号反相，而第三反相器F3和第四反相器F4起到缓冲的作用。
结合以上电路，并参阅图4，本发明GOA电路第一实施方式中第N级GOA单元的电路时序图，对本实施方式进行详细阐述。
具体地，以下例子仅为正向扫描中第N级GOA单元中电路各个节点的时序，其中，在正向扫描期间，每级GOA单元的电路中的D2U均为低电平，U2D均为高电平，以使第一传输门G1一直打开从而接收上一级GOA单元的级传信号。
在第一作用区间，Q(N-1)为高电平、XCK(N)为低电平、CK(N)为高电平，由于Q(N-1)为高电平，因此a点为高电平，即，第一或非门H1的第一输入端输入高电平，使得第一或非门H1输出低电平，即，b点为低电平，因此，第一晶体管T1和第二晶体管T2均导通。由于第一时钟信号XCK(N)为低电平，因此Q(N)为低电平。第二时钟信号CK(N)为高电平，且第二晶体管T2导通，因此第一反相器F1的输入端产生高电平，进而输出低电平。第三晶体管T3的栅极为低电平，不导通。第二或非门H2的输出端为高电平信号，并在通过第二反相器F2、第三反相器F3以及第四反相器F4后，输出低电平的第N级扫描信号G(N)。
在第二作用区间，Q(N-1)为高电平、XCK(N)为高电平、CK(N)为低电平，由于Q(N-1)为高电平，因此a点为高电平，即，第一或非门H1的第一输入端输入高电平，使得第一或非门H1输出低电平，b点为低电平，因此，第一晶体管T1和第二晶体管T2均导通。由于第一时钟信号XCK(N)为高电平，因此Q(N)为高电平。由于Q(N)为高电平，第三晶体管T3导通，使第一反相器F1的输入端连接低电平，进而输出高电平信号，以保证Q(N)的高电平稳定。第二或非门H2的输出端为低电平信号，并在通过第二反相器F2、第三反相器F3以及第四反相器F4后，输出高电平的第N级扫描信号G(N)。
在第三作用区间，Q(N-1)为低电平、XCK(N)为高电平、CK(N)为低电平，由于Q(N-1)为低电平，因此a点为低电平，但由于Q(N)为高电平，即，第一或非门H1的第二输入端输入高电平，使得第一或非门H1输出低电平，b点继续保持为低电平，因此，第一晶体管T1和第二晶体管T2继续导通。由于第一时钟信号XCK(N)为高电平，因此Q(N)为高电平。由于Q(N)为高电平，第三晶体管T3导通，使第一反相器F1的输入端连接低电平，进而输出高电平信号，以保证Q(N)的高电平稳定。第二或非门H2的输出端为低电平信号，并在通过第二反相器F2、第三反相器F3以及第四反相器F4后，输出高电平的第N级扫描信号G(N)。
在第四作用区间，Q(N-1)为高电平、XCK(N)为低电平、CK(N)为高电平，由于XCK(N)为低电平，使得Q(N)瞬间变为低电平，同时由于Q(N)为低电平，因此a点为低电平，即，第一或非门H1的第一输入端和第二输入端均输入低电平，使得第一或非门H1输出高电平，即，b点为高电平，因此，第一晶体管T1和第二晶体管T2均截止。第三晶体管T3的栅极为低电平，不导通。第二或非门H2的输出端为高电平信号，并在通过第二反相器F2、第三反相器F3以及第四反相器F4后，输出低电平的第N级扫描信号G(N)。
值得注意的是，以正向扫描为例，在扫描期间，每一级的第一时钟信号和第二时钟信号均是不同的，一般情况下，每一级的时钟信号要比相对应的前一级的时钟信号延迟半个周期，即图4中的两个作用区间；另外，在本实施方式中，每一级的时钟信号可以比相对应的前一级的时钟信号延迟1/4个周期，即相邻两级对应的时钟信号的高电平互相重叠，例如，第N级GOA单元的第一时钟信号XCK(N)比第N-1级GOA单元的第一时钟信号XCK(N-1) 延迟1/4个周期，第N级GOA单元的第二时钟信号CK(N)比第N-1级GOA单元的第二时钟信号CK(N-1) 延迟1/4个周期，通过上述方式，如图4中，相邻两级的扫描信号也相应的延迟1/4个周期，即高电平互相重叠。
区别于现有技术，本实施方式公开了一GOA单元的具体电路，通过第一时钟信号XCK(N) 和第二时钟信号CK(N)两个时钟信号共同驱动，提高了电路的稳定性；同时，相邻两级的相应时钟信号采用重叠的时序设置，能够降低锁存电路在电平高低转换时失效的风险；另外，采用或非门等器件实现逻辑功能，能够降低电路的功耗，减小漏电。
参阅图5，本发明GOA电路第二实施方式中第N级GOA单元的电路图，该电路包括传输电路501、锁存电路502以及输出电路503。
其中，输出电路503连接传输电路501，用于在正向扫描时接收第N-1级级传信号Q(N-1)，并输出与第N-1级级传信号Q(N-1)相同的第N级扫描信号G(N)；或在反向扫描时接收第N+1级级传信号Q(N+1)，并输出与第N+1级级传信号Q(N+1)相同的第N级扫描信号G(N)。
具体地，本实施方式的传输电路501、锁存电路502以及输出电路503与本发明GOA电路第二实施方式的电路完全相同，不同之处在于输出电路503不再接收锁存电路502发出的Q(N)信号，而是接收传输电路501发出的Q(N-1)信号，而锁存模块502只提供级传信号，因此提高了电路的稳定性。
本实施方式与上述实施方式类似，这里不再赘述。
参阅图6，本发明GOA电路第三实施方式中第N级GOA单元的电路图，该电路包括传输电路601、锁存电路602以及输出电路603。
其中，传输电路601和输出电路603与上述各个实施方式中的相应电路相同，不同之处在于，本实施方式的锁存电路包括第三或非门H3、第三传输门G3、第四传输门G4、第五反相器F5以及第六反相器F6。
其中，第三或非门H3的第一输入端接收传输电路发送的级传信号，输出端分别连接第三传输门G3与第四传输门G4的一控制端，第三或非门H3的输出端还通过第五反相器F5分别连接第三传输门G3与第四传输门G4的另一控制端；第三传输门G3的输入端连接第一时钟信号XCK(N)，输出端连接第三或非门H3的第二输入端；第四传输门G4的输入端连接第二时钟信号CK(N)，输出端通过第六反相器F6正向连接第三或非门H3的第二输入端。
区别于上述各实施方式，本实施方式的锁存电路采用或非门加传输门组成锁存模块，能够稳定Q(N)点的电位。
参阅图7，本发明GOA电路第四实施方式中第N级GOA单元的电路图，该电路包括传输电路701、锁存电路702以及输出电路703。
其中，传输电路701和输出电路703与上述各个实施方式中的相应电路相同，不同之处在于，本实施方式的锁存电路包括第四或非门H4、第七反相器F7、第一与非门Y1以及第八反相器F8。
第四或非门H4的第一输入端接收传输电路发送的级传信号，输出端通过第七反相器F7连接第一与非门Y1的第一输入端；第一与非门Y1的第二输入端连接第一时钟信号XCK(N)，输出端通过第八反相器F8连接第四或非门H4的第二输入端；第八反相器F8的输出端连接输出电路，以向输出电路发送第N级级传信号Q(N)。
区别于上述各实施方式，本实施方式的锁存电路采用或非门加与非门组成锁存模块，能够降低电路的功耗。
另外，上述各个实施方式中均可以在Q(N)所在的节点增加如图3、5、6、7中的复位电路，用于在扫描前或扫描后对电路进行复位。
参阅图8，本发明GOA电路第五实施方式中第N级GOA单元的电路图，其中，相邻两级的GOA单元包括一组传输电路801、锁存电路802以及输出电路803。
具体地，本实施方式的锁存电路802是将两个本发明GOA电路第五实施方式中的锁存电路702组合形成新的锁存电路802；将两个本发明GOA电路第五实施方式中的输出电路703组合形成新的输出电路803。
具体地，传输电路801用于在正向扫描时，接收第N-2级GOA单元的第N-2级级传信号Q(N-2)，并发送给锁存电路802；或在反向扫描时接收N+3级GOA单元的N+3级级传信号Q(N+3)，并发送给锁存电路802。
锁存电路802包括第五或非门H5、第二与非门Y2、第三与非门Y3、第九反相器F9、第十反相器F10、第十一反相器F11、第十二反相器F12、第四晶体管T4以及第五晶体管T5；第五或非门H5的第一输入端接收传输电路发送的级传信号，输出端分别通过第九反相器F9以及第十一反相器F11连接第二与非门Y2的第一输入端以及第三与非门Y3的第一输入端，第二与非门Y2的输出端通过第十反相器F10连接输出电路，第三与非门Y3的输出端通过第十二反相器F12连接输出电路，第二与非门Y2的第二输入端连接第三时钟信号，第三与非门Y3的第二输入端连接第四时钟信号；第四晶体管T4以及第五晶体管T5的漏极分别连接第十反相器F10和第十二反相器F12的输出端，源极连接第五或非门H5的第二输入端，栅极分别连接第四时钟信号和第三时钟信号；输出电路分别连接第十反相器F10和第十二反相器F12的输出端以分别输出第N级扫描信号G(N)和第N+1级扫描信号G(N+1)。
具体地，第三时钟信号和第四时钟信号也可以是时序重叠的两个信号，其中第四时钟信号延迟于第三时钟信号1/4周期。
区别与上述实施方式，本实施方式将两级GOA单元合并为同一单元并共用一个传输电路，减少了电子器件的数量，减小了功耗。
参阅图9，本发明液晶显示器一实施方式的结构示意图，该液晶显示器包括显示面板901及背光902，显示面板901中包括GOA电路，其中，该GOA电路是如上述各个实施方式的GOA电路，其具体实施方式类似，这里不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种GOA电路，其中，所述GOA电路包括多个级联的GOA单元，每级GOA单元均包括依次连接的传输电路、锁存电路以及输出电路；
    设N为正整数，在第N级GOA单元中：
    所述传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给所述锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给所述锁存电路；
    所述锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与所述第一时钟信号电平相同，与所述第二时钟信号电平相反的第N级级传信号；
    所述输出电路用于接收所述第N级级传信号，并输出与所述第N级级传信号电平相同的第N级扫描信号；
    所述传输电路包括第一传输门以及第二传输门，所述第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将所述第N-1级级传信号发送给所述锁存电路；所述第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将所述第N+1级级传信号发送给所述锁存电路；
    所述输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；所述第二或非门的第一输入端接收所述锁存电路发送的所述第N级级传信号，第二输入端接收复位信号，当所述第N级级传信号和所述复位信号中至少一个为高电平时，所述第二或非门的输出端输出低电平信号，并在通过所述第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
  2. 一种GOA电路，其中，所述GOA电路包括多个级联的GOA单元，每级GOA单元均包括依次连接的传输电路、锁存电路以及输出电路；
    设N为正整数，在第N级GOA单元中：
    所述传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给所述锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给所述锁存电路；
    所述锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与所述第一时钟信号电平相同，与所述第二时钟信号电平相反的第N级级传信号；
    所述输出电路用于接收所述第N级级传信号，并输出与所述第N级级传信号电平相同的第N级扫描信号。
  3. 根据权利要求2所述的电路，其中，所述锁存电路包括第一或非门和第一晶体管，所述第一晶体管为P型；
    所述第一或非门的第一输入端接收所述传输电路发送的级传信号，输出端连接所述第一晶体管的栅极；
    所述第一晶体管的源极连接所述第一时钟信号，漏极连接所述第一或非门的第二输入端，用于在所述第一晶体管导通时，输出与所述第一时钟信号相同的第N级级传信号。
  4. 根据权利要求3所述的电路，其中，所述锁存电路还包括第二晶体管以及第一反相器，所述第二晶体管为P型；
    所述第二晶体管的源极连接所述第二时钟信号，栅极连接所述第一或非门的输出端，漏极通过所述第一反相器正向连接所述第一晶体管的漏极；其中，所述第二时钟信号与所述第一时钟信号反向。
  5. 根据权利要求2所述的电路，其中，所述传输电路包括第一传输门以及第二传输门，
    所述第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将所述第N-1级级传信号发送给所述锁存电路；
    所述第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将所述第N+1级级传信号发送给所述锁存电路。
  6. 根据权利要求2所述的电路，其中，所述输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；
    所述第二或非门的第一输入端接收所述锁存电路发送的所述第N级级传信号，第二输入端接收复位信号，当所述第N级级传信号和所述复位信号中至少一个为高电平时，所述第二或非门的输出端输出低电平信号，并在通过所述第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
  7. 根据权利要求2所述的电路，其中，所述输出电路连接所述传输电路，用于在正向扫描时接收所述第N-1级级传信号，并输出与所述第N-1级级传信号相同的第N级扫描信号；或
    在反向扫描时接收所述第N+1级级传信号，并输出与所述第N+1级级传信号相同的第N级扫描信号。
  8. 根据权利要求2所述的电路，其中，所述锁存电路包括第三或非门、第三传输门、第四传输门、第五反相器以及第六反相器；
    所述第三或非门的第一输入端接收所述传输电路发送的级传信号，输出端分别连接所述第三传输门与所述第四传输门的一控制端，所述第三或非门的输出端还通过所述第五反相器分别连接所述第三传输门与所述第四传输门的另一控制端；
    所述第三传输门的输入端连接第一时钟信号，输出端连接所述第三或非门的第二输入端；
    所述第四传输门的输入端连接第二时钟信号，输出端通过所述第六反相器正向连接所述第三或非门的第二输入端。
  9. 根据权利要求2所述的电路，其中，所述锁存电路包括第四或非门、第七反相器、第一与非门以及第八反相器；
    所述第四或非门的第一输入端接收所述传输电路发送的级传信号，输出端通过所述第七反相器连接所述第一与非门的第一输入端；
    所述第一与非门的第二输入端连接第一时钟信号，输出端通过所述第八反相器连接所述第四或非门的第二输入端；
    所述第八反相器的输出端连接所述输出电路，以向所述输出电路发送所述第N级级传信号。
  10. 根据权利要求2所述的电路，其中，相邻两级的GOA单元包括一组传输电路、锁存电路以及输出电路；
    所述传输电路用于在正向扫描时，接收第N-2级GOA单元的第N-2级级传信号，并发送给所述锁存电路；或在反向扫描时接收N+3级GOA单元的N+3级级传信号，并发送给所述锁存电路；
    所述锁存电路包括第五或非门、第二与非门、第三与非门、第九反相器、第十反相器、第十一反相器、第十二反相器、第四晶体管以及第五晶体管；
    所述第五或非门的第一输入端接收所述传输电路发送的级传信号，输出端分别通过所述第九反相器以及第十一反相器连接第二与非门的第一输入端以及第三与非门的第一输入端，第二与非门的输出端通过第十反相器连接所述输出电路，第三与非门的输出端通过第十二反相器连接所述输出电路，第二与非门的第二输入端连接第三时钟信号，第三与非门的第二输入端连接第四时钟信号；
    所述第四晶体管以及第五晶体管的漏极分别连接第十反相器和第十二反相器的输出端，源极连接第五或非门的第二输入端，栅极分别连接第四时钟信号和第三时钟信号；
    所述输出电路分别连接所述第十反相器和第十二反相器的输出端以分别输出第N级扫描信号和第N+1级扫描信号。
  11. 一种液晶显示器，其中，所述液晶显示器包括GOA电路，所述GOA电路包括多个级联的GOA单元，每级GOA单元均包括依次连接的传输电路、锁存电路以及输出电路；
    设N为正整数，在第N级GOA单元中：
    所述传输电路用于在正向扫描时，接收第N-1级GOA单元的第N-1级级传信号，并发送给所述锁存电路；或在反向扫描时接收第N+1级GOA单元的第N+1级级传信号，并发送给所述锁存电路；
    所述锁存电路用于在扫描期间，同时接收第一时钟信号以及第二时钟信号，并输出与所述第一时钟信号电平相同，与所述第二时钟信号电平相反的第N级级传信号；
    所述输出电路用于接收所述第N级级传信号，并输出与所述第N级级传信号电平相同的第N级扫描信号。
  12. 根据权利要求11所述的液晶显示器，其中，所述锁存电路包括第一或非门和第一晶体管，所述第一晶体管为P型；
    所述第一或非门的第一输入端接收所述传输电路发送的级传信号，输出端连接所述第一晶体管的栅极；
    所述第一晶体管的源极连接所述第一时钟信号，漏极连接所述第一或非门的第二输入端，用于在所述第一晶体管导通时，输出与所述第一时钟信号相同的第N级级传信号。
  13. 根据权利要求12所述的液晶显示器，其中，所述锁存电路还包括第二晶体管以及第一反相器，所述第二晶体管为P型；
    所述第二晶体管的源极连接所述第二时钟信号，栅极连接所述第一或非门的输出端，漏极通过所述第一反相器正向连接所述第一晶体管的漏极；其中，所述第二时钟信号与所述第一时钟信号反向。
  14. 根据权利要求11所述的液晶显示器，其中，所述传输电路包括第一传输门以及第二传输门，
    所述第一传输门的输入端接入第N-1级级传信号，用于在正向扫描时打开，将所述第N-1级级传信号发送给所述锁存电路；
    所述第二传输门的输入端接入第N+1级级传信号，用于在反向扫描时打开，将所述第N+1级级传信号发送给所述锁存电路。
  15. 根据权利要求11所述的液晶显示器，其中，所述输出电路包括依次连接的第二或非门、第二反相器、第三反相器以及第四反相器；
    所述第二或非门的第一输入端接收所述锁存电路发送的所述第N级级传信号，第二输入端接收复位信号，当所述第N级级传信号和所述复位信号中至少一个为高电平时，所述第二或非门的输出端输出低电平信号，并在通过所述第二反相器、第三反相器以及第四反相器后，输出高电平的第N级扫描信号。
  16. 根据权利要求11所述的液晶显示器，其中，所述输出电路连接所述传输电路，用于在正向扫描时接收所述第N-1级级传信号，并输出与所述第N-1级级传信号相同的第N级扫描信号；或
    在反向扫描时接收所述第N+1级级传信号，并输出与所述第N+1级级传信号相同的第N级扫描信号。
  17. 根据权利要求11所述的液晶显示器，其中，所述锁存电路包括第三或非门、第三传输门、第四传输门、第五反相器以及第六反相器；
    所述第三或非门的第一输入端接收所述传输电路发送的级传信号，输出端分别连接所述第三传输门与所述第四传输门的一控制端，所述第三或非门的输出端还通过所述第五反相器分别连接所述第三传输门与所述第四传输门的另一控制端；
    所述第三传输门的输入端连接第一时钟信号，输出端连接所述第三或非门的第二输入端；
    所述第四传输门的输入端连接第二时钟信号，输出端通过所述第六反相器正向连接所述第三或非门的第二输入端。
  18. 根据权利要求11所述的液晶显示器，其中，所述锁存电路包括第四或非门、第七反相器、第一与非门以及第八反相器；
    所述第四或非门的第一输入端接收所述传输电路发送的级传信号，输出端通过所述第七反相器连接所述第一与非门的第一输入端；
    所述第一与非门的第二输入端连接第一时钟信号，输出端通过所述第八反相器连接所述第四或非门的第二输入端；
    所述第八反相器的输出端连接所述输出电路，以向所述输出电路发送所述第N级级传信号。
  19. 根据权利要求11所述的液晶显示器，其中，相邻两级的GOA单元包括一组传输电路、锁存电路以及输出电路；
    所述传输电路用于在正向扫描时，接收第N-2级GOA单元的第N-2级级传信号，并发送给所述锁存电路；或在反向扫描时接收N+3级GOA单元的N+3级级传信号，并发送给所述锁存电路；
    所述锁存电路包括第五或非门、第二与非门、第三与非门、第九反相器、第十反相器、第十一反相器、第十二反相器、第四晶体管以及第五晶体管；
    所述第五或非门的第一输入端接收所述传输电路发送的级传信号，输出端分别通过所述第九反相器以及第十一反相器连接第二与非门的第一输入端以及第三与非门的第一输入端，第二与非门的输出端通过第十反相器连接所述输出电路，第三与非门的输出端通过第十二反相器连接所述输出电路，第二与非门的第二输入端连接第三时钟信号，第三与非门的第二输入端连接第四时钟信号；
    所述第四晶体管以及第五晶体管的漏极分别连接第十反相器和第十二反相器的输出端，源极连接第五或非门的第二输入端，栅极分别连接第四时钟信号和第三时钟信号；
    所述输出电路分别连接所述第十反相器和第十二反相器的输出端以分别输出第N级扫描信号和第N+1级扫描信号。
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CN104537995A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存器
CN104732940A (zh) * 2015-03-30 2015-06-24 深圳市华星光电技术有限公司 Cmos栅极驱动电路

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