WO2017049569A1 - 扫描驱动电路及具有该电路的液晶显示装置 - Google Patents

扫描驱动电路及具有该电路的液晶显示装置 Download PDF

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Publication number
WO2017049569A1
WO2017049569A1 PCT/CN2015/090672 CN2015090672W WO2017049569A1 WO 2017049569 A1 WO2017049569 A1 WO 2017049569A1 CN 2015090672 W CN2015090672 W CN 2015090672W WO 2017049569 A1 WO2017049569 A1 WO 2017049569A1
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WO
WIPO (PCT)
Prior art keywords
controllable switch
module
control
scan
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/090672
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English (en)
French (fr)
Inventor
肖军城
赵莽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/889,272 priority Critical patent/US9818359B2/en
Publication of WO2017049569A1 publication Critical patent/WO2017049569A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a liquid crystal display device having the same.
  • GOA Gate Driver On
  • Array scan drive circuit that is, the existing thin film transistor liquid crystal display array process is used to fabricate the scan drive circuit on the array substrate to realize the drive mode of gate progressive scan.
  • the existing scan driving circuit often has a failure problem in the case of poor device characteristics, and the anti-sweep control is not well performed, which will affect the stability of the scan driving circuit.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a liquid crystal display device having the same to ensure the stability of the operation of the scan driving circuit.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, including: a forward-reverse scan module for outputting a forward scan drive signal and a reverse scan drive signal to drive the scan drive a pull-up maintaining module, configured to receive the selection signal output by the forward-reverse scanning module, and pull-up the pull-down control signal point according to the received selection signal; the input module And connecting the forward/reverse scan module and the pull-up maintaining module, configured to receive an upper clock signal and charge the pull-up control signal point according to the received upper-level clock signal; and the control module is connected to the upper a pull-maintaining module, configured to receive a clock signal of the current stage and control the pull-up maintaining module according to the received clock signal of the current level; and an output module, connected to the pull-up maintaining module and the control module, for output scanning Driving a signal to the scan line; and scanning the line for transmitting the scan drive signal to the pixel unit.
  • the forward and reverse scan module includes a first controllable switch, a second controllable switch, a third controllable switch, and a fourth controllable switch, and the control end of the first controllable switch is connected to the first scan control voltage
  • the input end of the first controllable switch is connected to a lower-level scan signal, and the output end of the first controllable switch is connected to the input module and the pull-up maintaining module; and the control end of the second controllable switch Connecting a second scan control voltage, the input end of the second controllable switch is connected to an upper scan signal, and the output end of the second controllable switch is connected to the output end of the first controllable switch;
  • the control end of the control switch is connected to the first scan control voltage, the input end of the third controllable switch is connected to a third lower stage clock signal, and the output end of the third controllable switch is connected to the pull-up maintenance module;
  • the control end of the fourth controllable switch is connected to the second scan control voltage, the input end
  • the input unit includes a fifth controllable switch, and the control end of the fifth controllable switch is connected to a second lower-level clock signal, and the input end of the fifth controllable switch is connected to the first controllable switch.
  • the output end of the fifth controllable switch is connected to the pull-up maintaining module and the control module.
  • the pull-up maintaining module includes a sixth controllable switch, a seventh controllable switch, an eighth controllable switch, a ninth controllable switch, and a first capacitor, and an output end of the sixth controllable switch is connected to the An output end of the fifth controllable switch, a control end of the sixth controllable switch is connected to a control end of the ninth controllable switch, the sixth controllable switch, the seventh controllable switch, and the The input end of the nine controllable switch is connected to the open voltage end, the control end of the seventh controllable switch is connected to the control module, and the output end of the seventh controllable switch is connected to the control end of the sixth controllable switch And the control end of the ninth controllable switch, the output end of the ninth controllable switch is connected to a scan line and the output module, and one end of the first capacitor is connected to the input end of the ninth controllable switch The other end of the first capacitor is connected to the control end of the ninth controllable switch, and the control end of the eighth control
  • the scan driving circuit further includes a voltage stabilizing module for stabilizing the voltage and preventing leakage of the pull-up maintaining module, the voltage stabilizing module includes a tenth controllable switch, and the control end of the tenth controllable switch is connected An input end of the eighth controllable switch and the turn-off voltage, an input end of the tenth controllable switch is connected to an output end of the fifth controllable switch, and the control module, the tenth controllable switch The output is connected to the output module.
  • the voltage stabilizing module includes a tenth controllable switch, and the control end of the tenth controllable switch is connected An input end of the eighth controllable switch and the turn-off voltage, an input end of the tenth controllable switch is connected to an output end of the fifth controllable switch, and the control module, the tenth controllable switch The output is connected to the output module.
  • the output module includes an eleventh controllable switch and a second capacitor, and a control end of the eleventh controllable switch is connected to an output end of the tenth controllable switch, and the eleventh controllable switch is The input end is connected to the clock signal of the first stage, the output end of the eleventh controllable switch is connected to the output end of the ninth controllable switch and the scan line, and one end of the second capacitor is connected to the eleventh The control end of the control switch, the other end of the second capacitor is connected to the output end of the eleventh controllable switch.
  • the scan driving circuit further includes a pull-up auxiliary module, configured to prevent the input unit from leaking during charging of a pull-up control signal point in the output module, where the pull-up auxiliary module includes a twelfth Controlling a switch, a control end of the twelfth controllable switch is connected to an output end of the first controllable switch, and an input end of the twelfth controllable switch is connected to the open voltage end, the twelfth An output end of the control switch is connected to a control end of the sixth controllable switch .
  • the pull-up auxiliary module includes a twelfth Controlling a switch, a control end of the twelfth controllable switch is connected to an output end of the first controllable switch, and an input end of the twelfth controllable switch is connected to the open voltage end, the twelfth An output end of the control switch is connected to a control end of the sixth controllable switch .
  • the control module includes a thirteenth controllable switch, and the control end of the thirteenth controllable switch is connected to the input clock of the current level and the input end of the eleventh controllable switch, the thirteenth An input end of the controllable switch is connected to a control end of the seventh controllable switch, and an output end of the thirteenth controllable switch is connected to an input end of the tenth controllable switch and an output of the fifth controllable switch end.
  • the first to thirteenth controllable switches are PMOS type thin film transistors or NMOS type thin film transistors.
  • another technical solution adopted by the present invention is to provide a liquid crystal display device comprising the scan driving circuit as described above.
  • the liquid crystal display device of the present invention controls the pull-up maintaining module through the control module, thereby avoiding the scan driving circuit failure due to the competition balance phenomenon of the controllable switch during control. And the liquid crystal display device pulls up the pull-up control signal point by the signal selected by the forward-reverse scan module, thereby preventing the scan drive circuit from working normally during the anti-sweep period, thereby ensuring the stability of the scan drive circuit. .
  • FIG. 1 is a schematic structural view of a scan driving circuit in the prior art
  • FIG. 3 is a schematic structural view of a scan driving circuit of a first embodiment of the present invention.
  • Figure 4 is a waveform diagram of a scan driving circuit of a first embodiment of the present invention.
  • Figure 5 is a block diagram showing the structure of a scan driving circuit of a second embodiment of the present invention.
  • Figure 6 is a waveform diagram of a scan driving circuit of a second embodiment of the present invention.
  • Fig. 7 is a schematic view of a liquid crystal display device of the present invention.
  • the conventional scan driving circuit can work normally under a good environment, but when the scan driving circuit works in an extremely harsh environment, that is, when the device characteristics are poor,
  • the gate voltage of the thin film transistor PT8 is smaller than the gate voltage of the thin film transistor PT6, which causes the source-drain current formed by the gate-source voltage of the thin film transistor PT8 and the source-drain current formed by the gate-source voltage of the thin film transistor PT6 to reach a dynamic state due to the competition relationship.
  • the balance is such that the pull-down control signal point P cannot maintain a constant low potential during non-working hours, thereby causing the scan drive circuit to fail.
  • FIG. 2 a waveform diagram of the scan driving circuit operating under the condition that the device characteristics are deteriorated. It can be seen from FIG. 2 that due to the competition relationship between the thin film transistors PT6 and PT8, a dynamic balance occurs between the pull-down of the pull-down control signal point P and the pull-up of the pull-up control signal point Q, and thus the phenomenon is the pull-up control signal.
  • the point Q is maintained at a low potential, and the pull-down control signal point P is maintained at a high potential, thereby causing the scan driving circuit to fail.
  • the scan driving circuit 1 of the first embodiment of the present invention includes a forward-reverse scan module 100 for outputting a forward scan drive signal and a reverse scan drive signal to drive the scan drive circuit 1;
  • the pull-and-hold module 300 is connected to the forward-reverse scan module 100 for receiving the selection signal output by the forward-reverse scan module 100 and pulling up the pull-down control signal point P according to the received selection signal;
  • the module 200 is connected to the forward-reverse scan module 100 and the pull-up maintaining module 300 for receiving an upper-level clock signal CK_N+2 and pairing the pull-up control signal point Q according to the received upper-level clock signal CK_N+2 Charging is performed;
  • the control module 700 is connected to the pull-up maintaining module 300 for receiving the local clock signal CK_N and controlling the pull-up maintaining module 300 according to the received local clock signal CK_N;
  • the output module 500 is connected The pull-up maintaining module 100 for receiving the local clock signal CK_N and controlling the pull-up maintaining module 300 according to the received
  • the forward and reverse scan module 100 includes a first controllable switch PT0, a second controllable switch PT1, a third controllable switch PT2, and a fourth controllable switch PT3, and the control end of the first controllable switch PT0 is connected.
  • a scan control voltage U2D an input end of the first controllable switch PT0 is connected to a lower-level scan signal G_N+1, and an output end of the first controllable switch PT0 is connected to the input module 200 and the pull-up maintenance module
  • the control end of the second controllable switch PT1 is connected to the second scan control voltage D2U, the input end of the second controllable switch PT1 is connected to an upper scan signal G_N-1, and the second controllable switch PT1 is The output end is connected to the output end of the first controllable switch PT0; the control end of the third controllable switch PT2 is connected to the first scan control voltage U2D, and the input end of the third controllable switch PT2 is connected to the third end a lower-level clock signal CK_N+3, an output end of the third controllable switch PT2 is connected to the pull-up maintaining module 300; a control end of the fourth controllable switch PT3 is connected to the second scan control voltage D2U
  • the scan driving circuit 1 when the first scan control voltage U2D is at a high level and the second scan control voltage D2U is at a low level, the scan driving circuit 1 is in a forward scan state; when the first scan control voltage U2D When the level is low and the second scan control voltage D2U is at a high level, the scan driving circuit 1 is in a reverse scan state.
  • the input unit 200 includes a fifth controllable switch PT4, the control end of the fifth controllable switch PT4 is connected to the second lower-level clock signal CK_N+2, and the input end of the fifth controllable switch PT4 is connected to the first
  • the output end of the controllable switch PT0 is connected to the pull-up maintaining module 300 and the control module 700.
  • the pull-up maintaining module 300 includes a sixth controllable switch PT5, a seventh controllable switch PT6, an eighth controllable switch PT8, a ninth controllable switch PT9, and a first capacitor C1, and the sixth controllable switch PT5
  • the output end is connected to the output end of the fifth controllable switch PT4, the control end of the sixth controllable switch PT5 is connected to the control end of the ninth controllable switch PT9, the sixth controllable switch PT5, the The input ends of the seventh controllable switch PT6 and the ninth controllable switch PT9 are connected to the open voltage terminal VGH, and the control end of the seventh controllable switch PT6 is connected to the control module 700, the seventh controllable switch An output end of the PT6 is connected to a control end of the sixth controllable switch PT5 and a control end of the ninth controllable switch PT9, and an output end of the ninth controllable switch PT9 is connected to a scan line G_N and the
  • the scan driving circuit further includes a voltage stabilizing module 400 for stabilizing the voltage and preventing leakage of the pull-up maintaining module 300.
  • the voltage stabilizing module 400 includes a tenth controllable switch PT7, and the tenth controllable switch PT7 The control terminal is connected to the input end of the eighth controllable switch PT8 and the closed voltage terminal VGL, and the input end of the tenth controllable switch PT7 is connected to the output end of the fifth controllable switch PT4 and the control module 700. The output end of the tenth controllable switch PT7 is connected to the output module 500.
  • the output module 500 includes an eleventh controllable switch PT10 and a second capacitor C2.
  • the control end of the eleventh controllable switch PT10 is connected to the output end of the tenth controllable switch PT7.
  • the input end of the control switch PT10 is connected to the clock signal CK_N of the current stage, and the output end of the eleventh controllable switch PT10 is connected to the output end of the ninth controllable switch PT9 and the scan line G_N, and the second capacitor C2
  • One end is connected to the control end of the eleventh controllable switch PT10, and the other end of the second capacitor C2 is connected to the output end of the eleventh controllable switch PT10.
  • the scan driving circuit 1 further includes a pull-up assisting module 600 for preventing the input unit 200 from leaking during charging of the pull-up control signal point Q in the output module 500, and the pull-up assisting module 600 includes a twelfth controllable switch PT11, a control end of the twelfth controllable switch PT11 is connected to an output end of the first controllable switch PT0, and an input end of the twelfth controllable switch PT11 is connected to the turn-on voltage The output end of the twelfth controllable switch PT11 is connected to the control end of the sixth controllable switch PT5 .
  • the control module 700 includes a thirteenth controllable switch PT12, and a control end of the thirteenth controllable switch PT12 is connected to the input end of the local clock signal CK_N and the eleventh controllable switch PT10, The input end of the thirteenth controllable switch PT12 is connected to the control end of the seventh controllable switch PT6, and the output end of the thirteenth controllable switch PT12 is connected to the input end of the tenth controllable switch PT7 and the The output of the fifth controllable switch PT4.
  • the scan driving circuit 1 controls the pull-up maintaining module 300 through the control module 700 and the local clock signal CK_N, and the thirteenth controllable switch during the output of the clock signal by the local clock signal CK_N PT12 is turned on, at this time, the pull-up control signal point Q controls the seventh controllable switch PT6 to stabilize the high level of the pull-down control signal point P, to prevent the pull-down control signal point P from leaking to the output scan signal G_N Impact.
  • the local clock signal CK_N becomes a high level
  • the thirteenth controllable switch PT12 is turned off, and then the pull-down control of the pull-down control signal point P is performed,
  • the cut-off of the thirteenth controllable switch PT12 causes the control end of the seventh controllable switch PT6 to be in a high impedance state, thereby effectively avoiding the seventh controllable switch PT6 and the eighth controllable switch PT8 The balance of competition between the two.
  • the source-drain current of the eighth controllable switch PT8 is greater than the source-drain current of the seventh controllable switch PT6, thereby implementing a normal pull-down of the pull-down control signal point P.
  • the first controllable switch to the thirteenth controllable switch PT0-PT12 are all PMOS type thin film transistors.
  • the scan driving circuit 1 does not directly pull up the pull-down control signal point P by using the upper-level scan signal G_N-1, but is selected by the forward-reverse scan module 100.
  • the upper scanning signal G_N-1 and the lower scanning signal G_N+1 pull up the pull-down control signal point P, thereby preventing the scan driving circuit 1 from malfunctioning during the reverse scanning.
  • the scan driving circuit 1 can provide a good pull-up and pull-down control of the pull-down control signal point P, and there is no competition balance between the controllable switches.
  • FIG. 4 it is assumed that there is a leakage phenomenon in the pull-down control signal point P.
  • the thirteenth controllable switch PT12 is turned off during the action of the pull-up control signal point Q, the pull-down control signal point P cannot be Pulling to a stable high level, the charge on the capacitor C1 is continuously leaked, but since the pull-up control signal point Q is constantly maintained at a low level, the circuit of the scan driving circuit 1 works normally.
  • the thirteenth controllable switch PT12 is turned on, and the pull-down control signal point P is pulled to the stable high level by the pull-up control signal point Q, and the output scan signal is stabilized. It is maintained. After the output of the scan signal is completed, the thirteenth controllable switch PT12 is turned off to cause the control end of the seventh controllable switch PT6 to be in a high impedance state, and does not affect the normal pull-down of the pull-down control signal point P.
  • FIG. 5 it is a schematic structural view of a scan driving circuit 2 according to a second embodiment of the present invention.
  • the scan driving circuit 2 of the second embodiment is different from the scan driving circuit 1 of the first embodiment in that the first controllable switch to the thirteenth controllable switch PT0-PT12 are NMOS. Thin film transistor.
  • FIG. 6 is a waveform diagram of the scan driving circuit 2 of the second embodiment of the present invention.
  • the scan driving circuit of the second embodiment has the same good performance as the scan driving circuit of the first embodiment, thereby realizing stable pull-up control and pull-down control of the pull-down control signal point P. .
  • FIG. 7 is a schematic diagram of a liquid crystal display device of the present invention.
  • the liquid crystal display device includes the aforementioned scan driving circuit 1 or scan driving circuit 2, and the scan driving circuit 1 or 2 is disposed at both ends of the liquid crystal display device, and the scan driving circuit 1 or 2 is any one of the inventions Scan drive circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

一种扫描驱动电路(1,2)及液晶显示装置，所述扫描驱动电路(1,2)包括正反向扫描模块(100)，输出正向及反向扫描驱动信号；上拉维持模块(300)连接正反向扫描模块(100)，接收正反向扫描模块(100)输出的选择信号以对下拉控制信号点(P)进行上拉；输入模块(200)连接正反向扫描模块(100)与上拉维持模块(300)，接收上级时钟信号(CK_N+2)以对上拉控制信号点(Q)充电；控制模块(700)连接上拉维持模块(300)，接收本级时钟信号(CK_N)以控制上拉维持模块(300)；输出模块(500)连接上拉维持模块(300)及控制模块(700)，输出扫描信号(G_N)给扫描线，以将扫描信号(G_N)传输至像素单元，来保证扫描驱动电路(1,2)的稳定性。

Description

扫描驱动电路及具有该电路的液晶显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及具有该电路的液晶显示装置。
【背景技术】
目前的液晶显示装置中采用GOA（Gate Driver On Array）扫描驱动电路，也就是利用现有薄膜晶体管液晶显示器阵列制程将扫描驱动电路制作在阵列基板上，实现对gate逐行扫描的驱动方式。现有的扫描驱动电路在器件特性较差的情况下常常出现失效的问题，并且不能很好的进行反扫的控制，这些都将影响扫描驱动电路的稳定性。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及具有该电路的液晶显示装置，以保证扫描驱动电路工作的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括：正反向扫描模块，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；上拉维持模块，连接所述正反向扫描模块，用于接收所述正反向扫描模块输出的选择信号并根据接收到的所述选择信号对下拉控制信号点进行上拉；输入模块，连接所述正反向扫描模块与所述上拉维持模块，用于接收一上级时钟信号并根据接收到的所述上级时钟信号对上拉控制信号点进行充电；控制模块，连接所述上拉维持模块，用于接收本级时钟信号并根据接收到的所述本级时钟信号控制所述上拉维持模块；输出模块，连接所述上拉维持模块及所述控制模块，用于输出扫描驱动信号给扫描线;扫描线，用于将所述扫描驱动信号传输至像素单元。
其中，所述正反向扫描模块包括第一可控开关、第二可控开关、第三可控开关及第四可控开关，所述第一可控开关的控制端连接第一扫描控制电压，所述第一可控开关的输入端连接一下级扫描信号，所述第一可控开关的输出端连接所述输入模块及所述上拉维持模块；所述第二可控开关的控制端连接第二扫描控制电压，所述第二可控开关的输入端连接一上级扫描信号，所述第二可控开关的输出端连接所述第一可控开关的输出端；所述第三可控开关的控制端连接所述第一扫描控制电压，所述第三可控开关的输入端连接一第三下级时钟信号，所述第三可控开关的输出端连接所述上拉维持模块；所述第四可控开关的控制端连接所述第二扫描控制电压，所述第四可控开关的输入端连接一第一下级时钟信号，所述第四可控开关的输出端连接所述第三可控开关的输出端。
其中，所述输入单元包括第五可控开关，所述第五可控开关的控制端连接一第二下级时钟信号，所述第五可控开关的输入端连接所述第一可控开关的输出端，所述第五可控开关的输出端连接所述上拉维持模块及所述控制模块。
其中，所述上拉维持模块包括第六可控开关、第七可控开关、第八可控开关、第九可控开关及第一电容，所述第六可控开关的输出端连接所述第五可控开关的输出端，所述第六可控开关的控制端连接所述第九可控开关的控制端，所述第六可控开关、所述第七可控开关及所述第九可控开关的输入端均连接开启电压端，所述第七可控开关的控制端连接所述控制模块，所述第七可控开关的输出端连接所述第六可控开关的控制端及所述第九可控开关的控制端，所述第九可控开关的输出端连接一扫描线及所述输出模块，所述第一电容的一端连接所述第九可控开关的输入端，所述第一电容的另一端连接所述第九可控开关的控制端，所述第八可控开关的控制端连接所述第三可控开关的输出端，所述第八可控开关的输入端连接关闭电压端，所述第八可控开关的输出端连接所述第七可控开关的输出端。
其中，所述扫描驱动电路还包括稳压模块，用于稳定电压及防止所述上拉维持模块漏电，所述稳压模块包括第十可控开关，所述第十可控开关的控制端连接所述第八可控开关的输入端及所述关闭电压，所述第十可控开关的输入端连接所述第五可控开关的输出端及所述控制模块，所述第十可控开关的输出端连接所述输出模块。
其中，所述输出模块包括第十一可控开关及第二电容，所述第十一可控开关的控制端连接所述第十可控开关的输出端，所述第十一可控开关的输入端连接本级时钟信号，所述第十一可控开关的输出端连接所述第九可控开关的输出端及所述扫描线，所述第二电容的一端连接所述第十一可控开关的控制端，所述第二电容的另一端连接所述第十一可控开关的输出端。
其中，所述扫描驱动电路还包括上拉辅助模块，用于防止所述输入单元在对所述输出模块中的上拉控制信号点充电过程中漏电，所述上拉辅助模块包括第十二可控开关，所述第十二可控开关的控制端连接所述第一可控开关的输出端，所述第十二可控开关的输入端连接所述开启电压端，所述第十二可控开关的输出端连接所述第六可控开关的控制端 。
其中，所述控制模块包括第十三可控开关，所述第十三可控开关的控制端连接所述本级时钟信号及所述第十一可控开关的输入端，所述第十三可控开关的输入端连接所述第七可控开关的控制端，所述第十三可控开关的输出端连接所述第十可控开关的输入端及所述第五可控开关的输出端。
其中，所述第一至所述第十三可控开关是PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，包括如上所述任一所述的扫描驱动电路。
本发明的有益效果是：区别于现有技术的情况，本发明的液晶显示装置通过控制模块对上拉维持模块进行控制，避免在控制时由于可控开关的竞争平衡现象造成扫描驱动电路失效，并且所述液晶显示装置通过正反向扫描模块选择后的信号对上拉控制信号点进行上拉，从而避免所述扫描驱动电路在反扫期间不能正常工作，以此保证扫描驱动电路的稳定性。
【附图说明】
图1是现有技术中扫描驱动电路的结构示意图；
图2是现有技术中扫描驱动电路的波形图；
图3是本发明的第一实施例的扫描驱动电路的结构示意图；
图4是本发明的第一实施例的扫描驱动电路的波形图；
图5是本发明的第二实施例的扫描驱动电路的结构示意图；
图6是本发明的第二实施例的扫描驱动电路的波形图；
图7是本发明的液晶显示装置的示意图。
【具体实施方式】
请参阅图1及图2，现有的扫描驱动电路在较好的环境下可以正常的工作，但是当所述扫描驱动电路工作在极其恶劣的环境下时，也就是当器件特性较差时，薄膜晶体管PT8的栅极电压小于薄膜晶体管PT6栅极电压，这将造成薄膜晶体管PT8的栅源电压形成的源漏电流与薄膜晶体管PT6的栅源电压形成的源漏电流由于竞争关系而达到一个动态的平衡，使得下拉控制信号点P在非工作时间内不能保持恒低的电位，从而造成所述扫描驱动电路可能失效。同时，图1所示扫描驱动电路仅利用上级扫描信号G_N-1对下拉控制信号点P进行控制可能会造成反扫电路不能正常工作。请一并参阅图2是所述扫描驱动电路工作在器件特性变差情况下的波形图。由图2可知，由于薄膜晶体管PT6和PT8的竞争关系，使得下拉控制信号点P的下拉和上拉控制信号点Q的上拉之间出现了一个动态平衡，因此造成的现象是上拉控制信号点Q维持低电位，下拉控制信号点P维持高电位，以此造成所述扫描驱动电路失效。
请参阅图3，是本发明的第一实施例的扫描驱动电路的结构示意图。如图3所示，本发明的第一实施例的扫描驱动电路1包括正反向扫描模块100，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路1；上拉维持模块300，连接所述正反向扫描模块100，用于接收所述正反向扫描模块100输出的选择信号并根据接收到的所述选择信号对下拉控制信号点P进行上拉；输入模块200连接所述正反向扫描模块100与所述上拉维持模块300，用于接收一上级时钟信号CK_N+2并根据接收到的所述上级时钟信号CK_N+2对上拉控制信号点Q进行充电；控制模块700，连接所述上拉维持模块300，用于接收本级时钟信号CK_N并根据接收到的所述本级时钟信号CK_N控制所述上拉维持模块300；输出模块500，连接所述上拉维持模块300及所述控制模块700，用于输出扫描驱动信号G_N给扫描线;扫描线，用于将所述扫描驱动信号传输至像素单元。
所述正反向扫描模块100包括第一可控开关PT0、第二可控开关PT1、第三可控开关PT2及第四可控开关PT3，所述第一可控开关PT0的控制端连接第一扫描控制电压U2D，所述第一可控开关PT0的输入端连接一下级扫描信号G_N+1，所述第一可控开关PT0的输出端连接所述输入模块200及所述上拉维持模块300；所述第二可控开关PT1的控制端连接第二扫描控制电压D2U，所述第二可控开关PT1的输入端连接一上级扫描信号G_N-1，所述第二可控开关PT1的输出端连接所述第一可控开关PT0的输出端；所述第三可控开关PT2的控制端连接所述第一扫描控制电压U2D，所述第三可控开关PT2的输入端连接第三下级时钟信号CK_N+3，所述第三可控开关PT2的输出端连接所述上拉维持模块300；所述第四可控开关PT3的控制端连接所述第二扫描控制电压D2U，所述第四可控开关PT3的输入端连接第一下级时钟信号CK_N+1，所述第四可控开关PT3的输出端连接所述第三可控开关PT2的输出端。其中，当所述第一扫描控制电压U2D为高电平且所述第二扫描控制电压D2U为低电平时，所述扫描驱动电路1处于正向扫描状态；当所述第一扫描控制电压U2D为低电平且所述第二扫描控制电压D2U为高电平时，所述扫描驱动电路1处于反向扫描状态。
所述输入单元200包括第五可控开关PT4，所述第五可控开关PT4的控制端连接第二下级时钟信号CK_N+2，所述第五可控开关PT4的输入端连接所述第一可控开关PT0的输出端，所述第五可控开关PT4的输出端连接所述上拉维持模块300及所述控制模块700。
所述上拉维持模块300包括第六可控开关PT5、第七可控开关PT6、第八可控开关PT8、第九可控开关PT9及第一电容C1，所述第六可控开关PT5的输出端连接所述第五可控开关PT4的输出端，所述第六可控开关PT5的控制端连接所述第九可控开关PT9的控制端，所述第六可控开关PT5、所述第七可控开关PT6及所述第九可控开关PT9的输入端均连接开启电压端VGH，所述第七可控开关PT6的控制端连接所述控制模块700，所述第七可控开关PT6的输出端连接所述第六可控开关PT5的控制端及所述第九可控开关PT9的控制端，所述第九可控开关PT9的输出端连接一扫描线G_N及所述输出模块500，所述第一电容C1的一端连接所述第九可控开关PT9的输入端，所述第一电容C1的另一端连接所述第九可控开关PT9的控制端，所述第八可控开关PT8的控制端连接所述第三可控开关PT2的输出端，所述第八可控开关PT8的输入端连接关闭电压端VGL，所述第八可控开关PT8的输出端连接所述第七可控开关PT6的输出端。
所述扫描驱动电路还包括稳压模块400，用于稳定电压及防止所述上拉维持模块300漏电，所述稳压模块400包括第十可控开关PT7，所述第十可控开关PT7的控制端连接所述第八可控开关PT8的输入端及所述关闭电压端VGL，所述第十可控开关PT7的输入端连接所述第五可控开关PT4的输出端及所述控制模块700，所述第十可控开关PT7的输出端连接所述输出模块500。
所述输出模块500包括第十一可控开关PT10及第二电容C2，所述第十一可控开关PT10的控制端连接所述第十可控开关PT7的输出端，所述第十一可控开关PT10的输入端连接本级时钟信号CK_N，所述第十一可控开关PT10的输出端连接所述第九可控开关PT9的输出端及所述扫描线G_N，所述第二电容C2的一端连接所述第十一可控开关PT10的控制端，所述第二电容C2的另一端连接所述第十一可控开关PT10的输出端。
所述扫描驱动电路1还包括上拉辅助模块600，用于防止所述输入单元200在对所述输出模块500中的上拉控制信号点Q充电过程中漏电，所述上拉辅助模块600包括第十二可控开关PT11，所述第十二可控开关PT11的控制端连接所述第一可控开关PT0的输出端，所述第十二可控开关PT11的输入端连接所述开启电压端VGH，所述第十二可控开关PT11的输出端连接所述第六可控开关PT5的控制端 。
所述控制模块700包括第十三可控开关PT12，所述第十三可控开关PT12的控制端连接所述本级时钟信号CK_N及所述第十一可控开关PT10的输入端，所述第十三可控开关PT12的输入端连接所述第七可控开关PT6的控制端，所述第十三可控开关PT12的输出端连接所述第十可控开关PT7的输入端及所述第五可控开关PT4的输出端。
所述扫描驱动电路1通过控制模块700及所述本级时钟信号CK_N对所述上拉维持模块300进行控制，在所述本级时钟信号CK_N输出时钟信号期间，所述第十三可控开关PT12导通，此时所述上拉控制信号点Q控制所述第七可控开关PT6稳定所述下拉控制信号点P的高电平，避免所述下拉控制信号点P漏电对输出扫描信号G_N的影响。当本级扫描信号G_N输出完成之后，所述本级时钟信号CK_N变成高电平，所述第十三可控开关PT12截止，之后进行所述下拉控制信号点P的下拉控制，由于所述第十三可控开关PT12的截止，致使所述第七可控开关PT6的控制端处于高阻态，从而有效地避免了所述第七可控开关PT6和所述第八可控开关PT8之间的竞争平衡。当下级时钟信号CK_N+1为低电平时，所述第八可控开关PT8的源漏电流大于所述第七可控开关PT6的源漏电流，从而实现所述下拉控制信号点P的正常下拉，以此实现所述扫描驱动电路1的正常工作。在所述第一实施例中，所述第一可控开关至所述第十三可控开关PT0-PT12均为PMOS型薄膜晶体管。
在所述第一实施例中，所述扫描驱动电路1没有直接利用上级扫描信号G_N-1对所述下拉控制信号点P进行上拉控制，而是通过所述正反向扫描模块100选择后的上级扫描信号G_N-1和下级扫描信号G_N+1拉对所述下拉控制信号点P进行上拉，以此避免反扫期间所述扫描驱动电路1不能正常工作。
请一并参阅图4，是本发明第一实施例的所述扫描驱动电路1的波形图。在本实施例中，所述扫描驱动电路1能够提供很好的下拉控制信号点P的上拉和下拉控制，不会出现可控开关之间的竞争平衡现象。如图4所示，假设所述下拉控制信号点P存在漏电现象，在所述上拉控制信号点Q作用期间由于所述第十三可控开关PT12截止，所述下拉控制信号点P不能被拉至稳定的高电平，电容C1上的电荷会不断泄露，但是，由于所述上拉控制信号点Q一直被稳定的维持在低电平，从而所述扫描驱动电路1电路工作正常。在扫描信号G_N输出期间，所述第十三可控开关PT12导通，所述下拉控制信号点P又会被所述上拉控制信号点Q拉至稳定的高电平，输出扫描信号的稳定得以维持。扫描信号输出完毕之后，所述第十三可控开关PT12截止致使所述第七可控开关PT6的控制端处于高阻态，不影响所述下拉控制信号点P的正常下拉。
请参见图5，是本发明的第二实施例的扫描驱动电路2的结构示意图。所述第二实施例的扫描驱动电路2与上述第一实施例的扫描驱动电路1的不同之处在于：所述第一可控开关至所述第十三可控开关PT0-PT12均为NMOS型薄膜晶体管。
请一并参阅图6，是本发明第二实施例的扫描驱动电路2的波形图。由图6可知，所述第二实施例的扫描驱动电路具有与所述第一实施例的扫描驱动电路同样好的工作性能，以此实现下拉控制信号点P的稳定的上拉控制和下拉控制。
请参阅图7，为本发明一种液晶显示装置的示意图。所述液晶显示装置包括前述的扫描驱动电路1或扫描驱动电路2，所述扫描驱动电路1或2设置在所述液晶显示装置的两端，所述扫描驱动电路1或2为本发明任一种扫描驱动电路。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    正反向扫描模块(100)，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；
    上拉维持模块(300)，连接所述正反向扫描模块(100)，用于接收所述正反向扫描模块(100)输出的选择信号并根据接收到的所述选择信号对下拉控制信号点(P)进行上拉；
    输入模块(200)，连接所述正反向扫描模块(100)与所述上拉维持模块(300)，用于接收一上级时钟信号并根据接收到的所述上级时钟信号对上拉控制信号点(Q)进行充电；
    控制模块(700)，连接所述上拉维持模块(300)，用于接收本级时钟信号并根据接收到的所述本级时钟信号控制所述上拉维持模块(300)；
    输出模块(500)，连接所述上拉维持模块(300)及所述控制模块(700)，用于输出扫描驱动信号给扫描线;
    扫描线，用于将所述扫描驱动信号传输至像素单元。
  2. 根据权利要求1所述的扫描驱动电路，其中， 所述正反向扫描模块(100)包括第一可控开关(PT0)、第二可控开关(PT1)、第三可控开关(PT2)及第四可控开关(PT3)，所述第一可控开关(PT0)的控制端连接第一扫描控制电压(U2D)，所述第一可控开关(PT0)的输入端连接一下级扫描信号，所述第一可控开关(PT0)的输出端连接所述输入模块(200)及所述上拉维持模块(300)；所述第二可控开关(PT1)的控制端连接第二扫描控制电压(D2U)，所述第二可控开关(PT1)的输入端连接一上级扫描信号，所述第二可控开关(PT1)的输出端连接所述第一可控开关(PT0)的输出端；所述第三可控开关(PT2)的控制端连接所述第一扫描控制电压(U2D)，所述第三可控开关(PT2)的输入端连接一第三下级时钟信号，所述第三可控开关(PT2)的输出端连接所述上拉维持模块(300)；所述第四可控开关(PT3)的控制端连接所述第二扫描控制电压(D2U)，所述第四可控开关(PT3)的输入端连接一第一下级时钟信号，所述第四可控开关(PT3)的输出端连接所述第三可控开关(PT2)的输出端。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述输入单元(200)包括第五可控开关(PT4)，所述第五可控开关(PT4)的控制端连接一第二下级时钟信号，所述第五可控开关(PT4)的输入端连接所述第一可控开关(PT0)的输出端，所述第五可控开关(PT4)的输出端连接所述上拉维持模块(300)及所述控制模块(700)。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述上拉维持模块(300)包括第六可控开关(PT5)、第七可控开关(PT6)、第八可控开关(PT8)、第九可控开关(PT9)及第一电容（C1），所述第六可控开关（PT5）的输出端连接所述第五可控开关（PT4）的输出端，所述第六可控开关(PT5)的控制端连接所述第九可控开关（PT9）的控制端，所述第六可控开关(PT5)、所述第七可控开关(PT6)及所述第九可控开关(PT9)的输入端均连接开启电压端(VGH)，所述第七可控开关(PT6)的控制端连接所述控制模块(700)，所述第七可控开关(PT6)的输出端连接所述第六可控开关(PT5)的控制端及所述第九可控开关(PT9)的控制端，所述第九可控开关(PT9)的输出端连接一扫描线及所述输出模块(500)，所述第一电容(C1)的一端连接所述第九可控开关(PT9)的输入端，所述第一电容(C1)的另一端连接所述第九可控开关(PT9)的控制端，所述第八可控开关(PT8)的控制端连接所述第三可控开关(PT2)的输出端，所述第八可控开关(PT8)的输入端连接关闭电压端(VGL)，所述第八可控开关(PT8)的输出端连接所述第七可控开关(PT6)的输出端。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述扫描驱动电路还包括稳压模块(400)，用于稳定电压及防止所述上拉维持模块(300)漏电，所述稳压模块(400)包括第十可控开关(PT7)，所述第十可控开关(PT7)的控制端连接所述第八可控开关(PT8)的输入端及所述关闭电压(VGL)，所述第十可控开关(PT7)的输入端连接所述第五可控开关(PT4)的输出端及所述控制模块(700)，所述第十可控开关(PT7)的输出端连接所述输出模块(500)。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述输出模块(500)包括第十一可控开关(PT10)及第二电容(C2)，所述第十一可控开关(PT10)的控制端连接所述第十可控开关(PT7)的输出端，所述第十一可控开关(PT10)的输入端连接本级时钟信号，所述第十一可控开关(PT10)的输出端连接所述第九可控开关(PT9)的输出端及所述扫描线，所述第二电容(C2)的一端连接所述第十一可控开关(PT10)的控制端，所述第二电容(C2)的另一端连接所述第十一可控开关(PT10)的输出端。
  7. 根据权利要求4所述的扫描驱动电路，其中，所述扫描驱动电路还包括上拉辅助模块(600)，用于防止所述输入单元(200)在对所述输出模块(500)中的上拉控制信号点(Q)充电过程中漏电，所述上拉辅助模块(600)包括第十二可控开关(PT11)，所述第十二可控开关(PT11)的控制端连接所述第一可控开关(PT0)的输出端，所述第十二可控开关(PT11)的输入端连接所述开启电压端(VGH)，所述第十二可控开关(PT11)的输出端连接所述第六可控开关(PT5)的控制端 。
  8. 根据权利要求6所述的扫描驱动电路，其中，所述控制模块(700)包括第十三可控开关(PT12)，所述第十三可控开关(PT12)的控制端连接所述本级时钟信号及所述第十一可控开关(PT10)的输入端，所述第十三可控开关(PT12)的输入端连接所述第七可控开关(PT6)的控制端，所述第十三可控开关(PT12)的输出端连接所述第十可控开关(PT7)的输入端及所述第五可控开关(PT4)的输出端。
  9. 根据权利要求8所述的扫描驱动电路，其中， 所述第一至所述第十三可控开关(PT0-PT12)是PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括扫描驱动电路，所述扫描驱动电路包括：
    正反向扫描模块(100)，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；
    上拉维持模块(300)，连接所述正反向扫描模块(100)，用于接收所述正反向扫描模块(100)输出的选择信号并根据接收到的所述选择信号对下拉控制信号点(P)进行上拉；
    输入模块(200)，连接所述正反向扫描模块(100)与所述上拉维持模块(300)，用于接收一上级时钟信号并根据接收到的所述上级时钟信号对上拉控制信号点(Q)进行充电；
    控制模块(700)，连接所述上拉维持模块(300)，用于接收本级时钟信号并根据接收到的所述本级时钟信号控制所述上拉维持模块(300)；
    输出模块(500)，连接所述上拉维持模块(300)及所述控制模块(700)，用于输出扫描驱动信号给扫描线;
    扫描线，用于将所述扫描驱动信号传输至像素单元。
  11. 根据权利要求10所述的扫描驱动电路，其中， 所述正反向扫描模块(100)包括第一可控开关(PT0)、第二可控开关(PT1)、第三可控开关(PT2)及第四可控开关(PT3)，所述第一可控开关(PT0)的控制端连接第一扫描控制电压(U2D)，所述第一可控开关(PT0)的输入端连接一下级扫描信号，所述第一可控开关(PT0)的输出端连接所述输入模块(200)及所述上拉维持模块(300)；所述第二可控开关(PT1)的控制端连接第二扫描控制电压(D2U)，所述第二可控开关(PT1)的输入端连接一上级扫描信号，所述第二可控开关(PT1)的输出端连接所述第一可控开关(PT0)的输出端；所述第三可控开关(PT2)的控制端连接所述第一扫描控制电压(U2D)，所述第三可控开关(PT2)的输入端连接一第三下级时钟信号，所述第三可控开关(PT2)的输出端连接所述上拉维持模块(300)；所述第四可控开关(PT3)的控制端连接所述第二扫描控制电压(D2U)，所述第四可控开关(PT3)的输入端连接一第一下级时钟信号，所述第四可控开关(PT3)的输出端连接所述第三可控开关(PT2)的输出端。
  12. 根据权利要求11所述的扫描驱动电路，其中，所述输入单元(200)包括第五可控开关(PT4)，所述第五可控开关(PT4)的控制端连接一第二下级时钟信号，所述第五可控开关(PT4)的输入端连接所述第一可控开关(PT0)的输出端，所述第五可控开关(PT4)的输出端连接所述上拉维持模块(300)及所述控制模块(700)。
  13. 根据权利要求12所述的扫描驱动电路，其中，所述上拉维持模块(300)包括第六可控开关(PT5)、第七可控开关(PT6)、第八可控开关(PT8)、第九可控开关(PT9)及第一电容（C1），所述第六可控开关（PT5）的输出端连接所述第五可控开关（PT4）的输出端，所述第六可控开关(PT5)的控制端连接所述第九可控开关（PT9）的控制端，所述第六可控开关(PT5)、所述第七可控开关(PT6)及所述第九可控开关(PT9)的输入端均连接开启电压端(VGH)，所述第七可控开关(PT6)的控制端连接所述控制模块(700)，所述第七可控开关(PT6)的输出端连接所述第六可控开关(PT5)的控制端及所述第九可控开关(PT9)的控制端，所述第九可控开关(PT9)的输出端连接一扫描线及所述输出模块(500)，所述第一电容(C1)的一端连接所述第九可控开关(PT9)的输入端，所述第一电容(C1)的另一端连接所述第九可控开关(PT9)的控制端，所述第八可控开关(PT8)的控制端连接所述第三可控开关(PT2)的输出端，所述第八可控开关(PT8)的输入端连接关闭电压端(VGL)，所述第八可控开关(PT8)的输出端连接所述第七可控开关(PT6)的输出端。
  14. 根据权利要求13所述的扫描驱动电路，其中，所述扫描驱动电路还包括稳压模块(400)，用于稳定电压及防止所述上拉维持模块(300)漏电，所述稳压模块(400)包括第十可控开关(PT7)，所述第十可控开关(PT7)的控制端连接所述第八可控开关(PT8)的输入端及所述关闭电压(VGL)，所述第十可控开关(PT7)的输入端连接所述第五可控开关(PT4)的输出端及所述控制模块(700)，所述第十可控开关(PT7)的输出端连接所述输出模块(500)。
  15. 根据权利要求14所述的扫描驱动电路，其中，所述输出模块(500)包括第十一可控开关(PT10)及第二电容(C2)，所述第十一可控开关(PT10)的控制端连接所述第十可控开关(PT7)的输出端，所述第十一可控开关(PT10)的输入端连接本级时钟信号，所述第十一可控开关(PT10)的输出端连接所述第九可控开关(PT9)的输出端及所述扫描线，所述第二电容(C2)的一端连接所述第十一可控开关(PT10)的控制端，所述第二电容(C2)的另一端连接所述第十一可控开关(PT10)的输出端。
  16. 根据权利要求13所述的扫描驱动电路，其中，所述扫描驱动电路还包括上拉辅助模块(600)，用于防止所述输入单元(200)在对所述输出模块(500)中的上拉控制信号点(Q)充电过程中漏电，所述上拉辅助模块(600)包括第十二可控开关(PT11)，所述第十二可控开关(PT11)的控制端连接所述第一可控开关(PT0)的输出端，所述第十二可控开关(PT11)的输入端连接所述开启电压端(VGH)，所述第十二可控开关(PT11)的输出端连接所述第六可控开关(PT5)的控制端 。
  17. 根据权利要求15所述的扫描驱动电路，其中，所述控制模块(700)包括第十三可控开关(PT12)，所述第十三可控开关(PT12)的控制端连接所述本级时钟信号及所述第十一可控开关(PT10)的输入端，所述第十三可控开关(PT12)的输入端连接所述第七可控开关(PT6)的控制端，所述第十三可控开关(PT12)的输出端连接所述第十可控开关(PT7)的输入端及所述第五可控开关(PT4)的输出端。
  18. 根据权利要求17所述的扫描驱动电路，其中， 所述第一至所述第十三可控开关(PT0-PT12)是PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
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