WO2016019651A1 - 可控电压源、移位寄存器及其单元和一种显示器 - Google Patents

可控电压源、移位寄存器及其单元和一种显示器 Download PDF

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Publication number
WO2016019651A1
WO2016019651A1 PCT/CN2014/091062 CN2014091062W WO2016019651A1 WO 2016019651 A1 WO2016019651 A1 WO 2016019651A1 CN 2014091062 W CN2014091062 W CN 2014091062W WO 2016019651 A1 WO2016019651 A1 WO 2016019651A1
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Prior art keywords
terminal
transistor
module
coupled
low level
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PCT/CN2014/091062
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English (en)
French (fr)
Inventor
张盛东
廖聪维
胡治晋
李文杰
李君梅
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北京大学深圳研究生院
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Priority to US15/329,143 priority Critical patent/US10192474B2/en
Publication of WO2016019651A1 publication Critical patent/WO2016019651A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of electronic circuits, and in particular to a controllable voltage source, a shift register and a unit thereof, and a display.
  • Narrow bezel display technology is increasingly becoming the mainstream of flat panel display technology. Its core technology is the thin film transistor (TFT) integrated gate-driver on Array (GOA). This is mainly to reduce the number of TFT flat-panel driver chips and the corresponding number of wires, thereby significantly reducing the frame size of the display, making the entire TFT display panel more compact and beautiful, and in order to reduce the rear package of the display module. The number of processes. Therefore, the integrated line scan driving circuit can reduce the manufacturing cost of the display and improve the yield of the display module, thereby improving the resolution and overall reliability of the TFT screen.
  • TFT thin film transistor
  • GOA gate-driver on Array
  • TFT integrated line scan driver circuits The key issue in the design of TFT integrated line scan driver circuits is how to improve their reliability.
  • the TFT which functions as a low level sustaining is biased at the positive gate voltage for a long time, and therefore the threshold voltage of these low level sustaining TFTs increases as the operating time elapses.
  • the threshold voltage of the low level sustain TFT drifts by a certain amount, the line scan driving circuit will fail.
  • the reliability of TFT integrated line scan drive circuits is particularly acute due to the long time of use.
  • the TFT-integrated row driver circuit design that has appeared internationally is only starting from the TFT device, mainly suppressing the drift of the electrical characteristics of the device to improve the reliability of the GOA circuit.
  • the low-level sustain TFTs almost all adopt the constant gate bias mode.
  • a bias causes the associated TFT to remain in an excessively high gate bias state for a long time, so that the threshold voltage of the TFT drifts too fast, and the life of the circuit is difficult to prolong.
  • almost all GOA circuits include the following three basic modules: input, output, and low-level maintenance modules. T100 is the input device; T200 is the output device, and the scan pulse signal of the output line is; T300 and T400 are the low level sustain devices.
  • the high level voltage of the gate inputs of T300 and T400 is a constant value.
  • C GD the source and drain electrodes
  • the T200 gate potential which was originally at the low level will also rise due to the coupling of C GD , if this rises Failure to get effective control will cause T200 to enter the sub-threshold zone or even turn on, which will cause a considerable current to charge the output, and the low level of the output will not be maintained.
  • T300 and T400 are in an on state, respectively suppressing the rise of the gate potential of T200 and discharging the output terminal, maintaining the low level of the output terminal.
  • a major problem with TFTs is that their threshold voltage increases with time under electrical stress, resulting in a decrease in conduction capability, such that when its threshold voltage increases from an initial value (such as V TH0 ) to a certain threshold (eg, After V THC ), T300 and T400 will no longer effectively suppress the gate potential rise of T200 and discharge the output, and the circuit will fail.
  • the T300 and T400 gate overdrive voltage (the difference between the gate source voltage and the threshold voltage) is slightly larger than the difference (V GH -V THC -V GL ) to ensure the normal operation of the circuit, wherein V GH and V GL is the high and low level of the clock signals driving T300 and T400 respectively.
  • V GH and V GL is the high and low level of the clock signals driving T300 and T400 respectively.
  • the level of the drive clock signal of the low level sustain device is constant, so the gate overdrive voltage of T300 and T400 is much longer than the difference (V GH). -V THC -V GL ).
  • V GH , V THC , V TH0 and V GL are 25V, 20V, 3V and 0V respectively.
  • the gate overdrive voltage of T300 and T400 is slightly greater than 5V, but the actual overdrive voltage is The value (V GH -V TH0 -V GL ) reaches 22V.
  • the driving method of the high level of the clock signal is constant, causing the threshold voltage of the associated TFT to drift too fast, and the circuit life is difficult to prolong.
  • the application provides a controllable voltage source, a shift register and a unit thereof, and a display to adjust the voltage supplied to the external circuit.
  • the present application provides a controllable voltage source, including: a control module, a storage module, and an output module. among them,
  • the control module is coupled between the high side and the low side;
  • the storage module includes a storage capacitor; two ends of the storage capacitor are respectively coupled to the control module to form the first terminal and the second terminal.
  • the output module is coupled to the second terminal, the signal output of which is used to output a voltage signal of the controllable voltage source to an external circuit.
  • the control module couples the first terminal to the high level end in response to the active level of the first clock signal, and charges the first terminal from the high level end.
  • the control module couples the second terminal to the high level end in response to the active level of the second clock signal, and charges the second terminal from the high level terminal; the first terminal is coupled to the low level terminal, and the first terminal is discharged through the low level terminal.
  • the active level of the first clock signal does not overlap the active level of the second clock signal.
  • the present application provides a shift register comprising: at least one shift register unit, an isolation module, and the above controllable voltage source. among them,
  • the shift register unit includes:
  • a driving module configured to transmit a first signal to a signal output end of the shift register unit by switching state switching, thereby outputting a scan signal
  • the low level maintenance module is configured to maintain the signal output end of the driving module at a low level after the shift register unit outputs the scan signal by switching state switching.
  • the signal output end of the controllable voltage source is coupled to the low level maintenance enable terminal of the low level maintenance module;
  • the controllable voltage source adjusts the output to the low level to maintain the supply voltage of the enable terminal.
  • the present application provides a display, including:
  • a two-dimensional pixel array composed of a plurality of pixels, and a plurality of data lines in a first direction and a plurality of gate scan lines in a second direction connected to each pixel in the array;
  • a data driving circuit that provides a data signal for the data line
  • the gate driving circuit is configured by using the above shift register to provide a gate driving signal for the gate scanning line.
  • the beneficial effects of the present application are: according to the controllable voltage source provided by the present application, the duty ratio, the amplitude of the first clock signal and/or the second clock signal, and the clock of the first clock signal and the second clock signal can be adjusted
  • the timing is used to adjust the supply voltage to the external circuit, thereby compensating for circuit performance degradation caused by long-term operation or environmental temperature changes.
  • the supply voltage of the low-level sustain enable terminal is adjusted by the controllable voltage source, and the threshold voltage drift of the low-level sustain transistor can be compensated as much as possible, thereby prolonging the life of the circuit.
  • 1 is a circuit diagram of a conventional shift register unit
  • FIG. 2 is a structural diagram of a controllable voltage source circuit disclosed in Embodiment 1 of the present application;
  • FIG. 3 is a SPICE simulation result of a working timing of a controllable voltage source according to an embodiment of the present application
  • FIG. 4 is a structural diagram of a controllable voltage source circuit disclosed in Embodiment 2 of the present application.
  • FIG. 6 is a circuit structural diagram of a shift register unit disclosed in Embodiment 3 of the present application.
  • FIG. 8 is another circuit configuration diagram of a conventional shift register unit disclosed in Embodiment 4 of the present application.
  • Embodiment 9 is a structural diagram of a controllable voltage source circuit disclosed in Embodiment 4 of the present application.
  • FIG. 11 is a structural diagram of a shift register circuit disclosed in Embodiment 4 of the present application.
  • FIG. 12 is a schematic diagram of a simulation result of a shift register compensation in the fourth embodiment of the present application.
  • FIG. 13 is a structural diagram of a display according to Embodiment 4 of the present application.
  • Figure 14 is a schematic diagram showing the basic structure of a shift register unit in the case of a conventional driving.
  • the switch tube in this application is a transistor.
  • the transistor in the present application may be a bipolar transistor or a field effect transistor.
  • the gate of the transistor is the base of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be a bipolar transistor.
  • Emitter or collector when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor
  • the first pole can be the drain or source of the field effect transistor
  • the corresponding second pole can be the field effect The source or drain of the transistor.
  • the transistor in the display is typically a field effect transistor: a thin film transistor (TFT).
  • TFT thin film transistor
  • the present application will be described in detail by taking a transistor as a field effect transistor.
  • the transistor may also be a bipolar transistor.
  • Overlap means that the two signals are in an active level state at least at the same time, and therefore do not overlap at the moment when the two signals are not in the active level state.
  • the active level may be a high level or a low level. In this embodiment, the active level is a high level.
  • T1 ⁇ T7 are the logic function implementation devices of the conventional shift register unit.
  • T5 and T7 will shift the register unit signal after the low level sustain enable terminal P obtains the enable signal.
  • the output terminal and the drive control terminal Q are coupled to the low level terminal to maintain their low level V L .
  • the enable signal of the low level sustain enable terminal P is high (provided by V DD ). Therefore, the threshold voltage drift may occur due to the high level of T5 and T7 for a long time.
  • the enable signal obtained by the low level sustain enable terminal P should also be adjusted accordingly so that the signal output terminal of the shift register unit and the drive control terminal Q are reliably coupled to low. Level end.
  • the present embodiment discloses a controllable voltage source for adjusting the voltage enable signal for the output low level maintenance enable terminal P, which will be described below in conjunction with the specific embodiments.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 2 is a structural diagram of a controllable voltage source circuit according to the embodiment.
  • the controllable voltage source includes: a control module 1 , a storage module 2 , and an output module 3 . among them,
  • Control module 1 is for coupling between a high level terminal and a low level terminal.
  • the memory module 2 includes a storage capacitor C1 coupled to the control module 1 to form a first terminal A and a second terminal B, respectively.
  • the output module 3 is coupled to the second terminal B, the signal output of which is used to output a voltage signal V DD of the controllable voltage source to an external circuit.
  • Control module 1 responds to the first clock signal
  • the active level couples the first terminal A to the high level terminal and the high terminal to the first terminal A.
  • Control module 1 responds to the second clock signal
  • the active level couples the second terminal B to the high level terminal, and charges the second terminal B from the high level terminal; the first terminal A is coupled to the low level terminal, and the first terminal A is discharged through the low level terminal.
  • first clock signal Active level and second clock signal The effective levels do not overlap.
  • the control module 1 includes a first transistor M1, a second transistor M2, and a third transistor M3.
  • a first pole (eg, a drain) of the first transistor M1 and a first pole (eg, a drain) of the second transistor M2 are coupled and coupled to a high level terminal;
  • a second pole (eg, a source) of the first transistor M1 and a first A second pole (eg, a source) of the second transistor M2 is coupled to both ends of the storage capacitor C1 to form a first terminal A and a second terminal B, respectively;
  • a control electrode (eg, a source gate) of the first transistor M1 is used for inputting One clock signal
  • a control electrode (eg, a source gate) of the second transistor M2 is used to input a second clock signal
  • the output module 3 includes a sixth transistor M6, a first pole (eg, a drain) of the sixth transistor M6 is coupled to a control pole (eg, a gate) and coupled to a second terminal B; a second pole of the sixth transistor M6 (eg, a source) The pole is the signal output of the output module 3.
  • the output module 3 may further comprise a filter capacitor C2, one end of the filter capacitor C2 is coupled to the second pole of the sixth transistor M6, and the other of the filter capacitor C2 One end is used to couple to the low side.
  • the output module 3 may further comprise a seventh transistor M7.
  • a first pole (eg, a drain) of the seventh transistor M7 is coupled to a signal output terminal of the output module 3, and a second pole (eg, a source) of the seventh transistor M7 is coupled to a low-level terminal, and the control of the seventh transistor M7 A pole (eg, a gate) is used to input a pull down control signal.
  • the seventh transistor M7 is coupled to the active terminal of the pull-down control signal to couple the signal output of the output module 3 to the low-level terminal, thereby maintaining the signal output of the output module 3 when the controllable voltage source is strobed.
  • the potential of the terminal is low V SS .
  • the potential at the high level terminal is the high level voltage V H
  • the potential at the low level terminal is the low level voltage V SS .
  • V CK is the first clock signal
  • second clock signal Timing where the solid line is the first clock signal Timing, the dotted line is the second clock signal
  • the timing of the output signal based on the capacitor bootstrap is controlled as follows:
  • the sixth transistor M6 is also in an on state.
  • the stored power on the storage capacitor C1 is then charged to the load capacitance on the output terminal V DD through the sixth transistor M6.
  • This charging process can only occur when the second terminal B of the storage capacitor C1 is bootstrapped to a higher potential and the sixth transistor M6 is in an on state. Therefore, as shown in FIG. 3, in the voltage bootstrap phase, the voltage difference across the storage capacitor C1 is reduced. Therefore, in the voltage bootstrap phase, the output potential V DD of the controllable voltage source rises close to a linear relationship.
  • Storage capacitor C1 is at the first clock signal The amount of voltage increase during the high level and its second clock signal The amount of voltage loss during the high period gradually reaches equilibrium.
  • the terminals A and B of the storage capacitor C1 are still switched between different level states due to the charge and discharge relationship, the voltage value on the storage capacitor C1 is relatively stable, and the output value tends to be stable.
  • the controllable voltage source disclosed in this embodiment adjusts the first clock signal And/or second clock signal Duty cycle, amplitude, first clock signal And second clock signal
  • the clock timing can adjust the amplitude of the output voltage signal V DD .
  • reducing the first clock signal And second clock signal The duty cycle, the amplitude of the output voltage signal V DD decreases.
  • Decrease the first clock signal Or second clock signal The magnitude of the voltage, the amplitude of the output voltage signal V DD decreases.
  • the voltage source circuit is composed of a TFT and can be integrated on the same substrate as a circuit such as a row scanning circuit or a TFT array.
  • this voltage source circuit includes the ability to save the pulse width control integration (power IC) on the periphery of the voltage source, and reduce the excessive supply voltage at the interface, thus suppressing the influence of electromagnetic interference on the interface.
  • this method is used to adjust the power supply voltage output to the external circuit, thereby compensating for circuit performance degradation caused by long-term operation or environmental temperature changes. Taking the change in the ambient temperature as an example, in a severe low-temperature environment, the on-current of a transistor such as a-Si TFT is reduced due to a decrease in effective mobility, an increase in threshold voltage, and the like, and thus the driving ability is degraded.
  • such a circuit can increase the first clock signal And/or second clock signal
  • the duty cycle and frequency which in turn output a higher drive voltage to the external TFT circuit, maintains its relatively constant circuit performance, allowing the circuit to operate normally even in harsh low temperature environments.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the controllable voltage source circuit disclosed in Embodiment 1 can also sense a change in characteristics of the TFT, such as its threshold voltage drift, or a change in its current-voltage characteristics due to a change in temperature. According to the characteristics of the TFT, the output voltage signal V DD of the voltage source is adjusted accordingly, so that the response of the system can be adjusted following the change of the TFT characteristics, and the adaptive bias of the controllable voltage source is realized.
  • the controllable voltage source further includes: a threshold modulation module 4.
  • the threshold modulation module 4 is coupled to the first terminal A and the second terminal B, respectively; the threshold modulation module 4 is further configured to be coupled to the low level end; the sensing end of the threshold modulation module 4 is configured to be coupled to the external circuit to be sensed for The threshold voltage of the element to be sensed is sensed and fed back to the first terminal A and/or the second terminal B.
  • the threshold modulation module 4 includes a fourth transistor M4 and a fifth transistor M5.
  • a first pole (eg, a drain) of the fourth transistor M4 is coupled to the first terminal A, a second pole (eg, a source) is coupled to the low-level terminal; and a first pole (eg, a drain) of the fifth transistor M5 is coupled To the second terminal B, the second pole (eg, the source) is coupled to the low-level terminal; the control electrode (eg, the gate) of the fourth transistor M4 is coupled to the control electrode (eg, the gate) of the fifth transistor M5 to form an induction end.
  • the threshold modulation module 4 can also be implemented by other means, such as an optocoupler or the like.
  • the value of the voltage V C1 stored on the storage capacitor C1 in the charge storage phase and the voltage bootstrap phase is also modulated by the fourth transistor M4 and the fifth transistor M5. Since the sensing terminals formed by the gates (eg, gates) of M4 and M5 are coupled to the components to be sensed (eg, the gates of the transistors to be sensed), M4 and M5 sense the threshold voltage drift of the components to be sensed. As the circuit operation time elapses, the threshold voltages ⁇ V TH of M4 and M5 increase, and thus their conduction capabilities deteriorate.
  • the storage capacitor C1 can store more voltages on the first terminal A and the second terminal B, while the amount of loss of V C1 is also less in the voltage bootstrap phase.
  • the value of the voltage signal V DD output by the controllable voltage source increases accordingly.
  • FIG. 5 is a SPICE simulation result of adaptive biasing of a controllable voltage source according to the embodiment. It is shown in Fig. 5 that when the value of the threshold voltage ⁇ V TH is increased from 0 V to 25 V, the value of V DD is correspondingly increased from 0 V to 22 V. This proves that the mechanism of this voltage source is correct and the linearity of the threshold voltage response is good. It is worth noting that the value of V DD does not reach 100% for ⁇ V TH . According to SPICE simulation, the compensation rate is approximately equal to 88%. This means that in a TFT-integrated circuit (such as a shift register), the driving capability of the element to be sensed (for example, a pull-down transistor) still has some degradation. However, compared to the constant voltage driving mode, the controllable voltage source disclosed in this embodiment can sense the threshold voltage drift of the component to be sensed, and adaptively adjust the output voltage signal. The life of such a self-compensating circuit will be greatly extended.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the controllable voltage source disclosed in the above embodiments is suitable for providing a supply voltage to any device circuit, and the shift register unit is taken as an example for description.
  • FIG. 6 is a circuit diagram of a shift register unit disclosed in this embodiment.
  • the shift register unit includes a driving module 20, an input module 10, a low level maintaining module 30, and the above controllable voltage source 40. among them,
  • the driving module 20 is configured to transmit the first signal V A to the signal output end of the shift register unit by switching state switching, thereby outputting the scan signal. After the drive control terminal Q is charged to obtain the drive voltage, the first signal V A is transmitted to the signal output terminal of the shift register unit.
  • the drive module 20 can include a transistor T2 for coupling to a signal output of the shift register unit and a capacitor Cs for storing charge of the drive control terminal Q. In other embodiments, other Existing drive methods.
  • the input module 10 is configured to control the driving module 20 to switch the switch state.
  • the first pulse signal V I1 is input from the first pulse signal input terminal
  • the driving control terminal Q of the driving module 20 is charged to provide a driving voltage
  • the second pulse signal V I2 is also input from the second pulse signal input terminal.
  • the signal output terminal of the shift register unit and the drive control terminal Q are coupled to the low level terminal.
  • the input module 10 may include a transistor T1 for inputting the first pulse signal V I1 and a transistor T3 for inputting the second pulse signal V I2 , and in other embodiments, may be other Some input methods.
  • the low level maintenance module 30 is configured to maintain the signal output end of the driving module 20 at a low level after the shift register unit outputs a scan signal by switching state switching. After the low level sustain enable terminal P obtains the enable signal V P , the signal output terminal of the shift register unit and the drive control terminal Q are coupled to the low level terminal. In the present embodiment, the so-called enable signal V P is a high level signal.
  • the low level maintenance module 30 includes a transistor T5 and a transistor T7, and a control electrode (eg, a gate) of the transistor T5 and a control electrode (eg, a gate) of the transistor T7 are coupled to a low level sustain enable.
  • Terminal P the control pole (eg, the gate) of transistor T5 and the second pole (eg, the source) of transistor T7 are coupled to the low level terminal; the first pole (eg, the drain) of transistor T5 is coupled to the drive control terminal Q The first pole (eg, the drain) of transistor T7 is coupled to the signal output of the shift register unit.
  • the transistor T6 can be further coupled between the low-level sustain enable terminal P and the low-level terminal, and the control electrode (eg, the gate) of the transistor T6 is coupled to the drive control terminal Q for Turn off T5 and T7 during the bootstrap phase.
  • other existing low level maintenance modes are also possible.
  • each of the above modules only schematically illustrates the shift register unit by way of example, and each module can adopt the existing technical solutions. Therefore, some details are not described in detail in the above modules, which are common in the art.
  • the technician can implement the connection between the modules of the shift register unit according to the existing technical solutions.
  • the capacitor C L and the resistor R for filtering may be further coupled to the signal output end of the shift register unit. L.
  • the controllable voltage source 40 has a signal output coupled to the low level maintenance enable terminal P of the low level maintenance module 30 for adjusting the supply voltage output to the low level sustain enable terminal P.
  • the threshold voltage of the low-level maintenance module 30 (such as transistors T5 and T7) will increase after a long period of operation, so the overdrive voltages of T5 and T7 are reduced, or their overdrive capability is reduced, and therefore, in order to sense low level
  • the threshold voltage of the module 30 is maintained to dynamically adjust the supply voltage to the low level maintenance module 30.
  • the controllable voltage source 40 preferably further includes a threshold voltage modulation module 4. The sensing end of the threshold modulation module 4 is coupled to the low level maintenance enable terminal P of the low level maintenance module 30.
  • the controllable voltage source senses the threshold voltage of the low level maintenance module 30, and adjusts the output to a low level according to the threshold voltage. Enable the supply voltage of terminal P.
  • the isolation module should be connected in series between the signal output end of the controllable voltage source and the low level maintenance enable terminal P.
  • the isolation module can be implemented by dragging capacitors, inductors, mutual inductance or other means.
  • the isolation module includes a transistor T4 coupled to the signal output terminal of the controllable voltage source and the low level sustain enable terminal P. between.
  • the second pole (eg, the source) of the transistor T4 is coupled to the low level sustain enable terminal P, and the first pole (eg, the drain) and the control pole (eg, the gate) are coupled to the signal output of the controllable voltage source. end.
  • the transistor T4 is for transmitting the adaptive voltage V DD to the low level sustain enable terminal P.
  • the clock signals required for the operation of the shift register unit described above preferably have the same clock period.
  • First clock signal in the controllable voltage source And second clock signal It can also be provided by any two non-overlapping signals in the shift register unit.
  • the high level end of the voltage source in the low level sustaining phase, should maintain a high level V H , and the potential of the high level end can be provided by an external power source, or can be a clock signal in the shift register unit. Provided, or other means capable of maintaining the high level of the voltage source at a high level V H .
  • FIG. 7 is a SPICE simulation result of the shift register unit of the embodiment, and FIG. 7 respectively shows the driving control terminal Q, the low level maintenance enable terminal P and the output signal V O in the row shift register unit circuit.
  • the waveforms, in Fig. 7, correspond to V Q , V DD and V O , respectively .
  • the simulation results verify that the designed TFT integrated shift register unit circuit and controllable voltage source work correctly. It is worth noting that during the bootstrap or voltage coupling of the drive control terminal Q, the controllable voltage source may be affected and a voltage feedthrough effect occurs.
  • the V DD ports of the shift register unit circuits of each stage can be connected in parallel, so there is a large storage capacitor on the V DD port, which can function as a filter regulator and suppress the voltage feedthrough effect. Impact.
  • the above-mentioned controllable voltage source can effectively adjust the potential V P of the low-level sustain enable terminal P of the shift register unit, and can effectively compensate the threshold voltage drift of the transistor performing the low-level sustain operation, thereby making the transistor Get a long working life.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the shift register unit is preferably provided with two sets of low level sustain modules that alternate to operate to maintain the low level of the signal output of the shift register unit.
  • FIG. 8 is a circuit diagram of the shift register unit of the embodiment.
  • the shift register unit circuit of the embodiment has two low-level sustain modules connected in parallel.
  • the first low level sustaining module comprises transistors T5, T6 and T7, the control poles (such as the gate) of T5, the control poles (such as the gate) of T7 and the first poles (such as the drains) of T6 are coupled with each other.
  • the second low level maintenance module includes T9, T10, and T11, a control pole (eg, a gate) of T9, a control pole (eg, a gate) of T11, and a first pole (eg, a drain) of T10 coupled to each other to form a second
  • the low level sustain enable terminal P2 the first pole (eg, the drain) of T9 is coupled to the drive control terminal Q, and the second poles (eg, the source) of T9, T10, and T11 are coupled to the low level terminal.
  • two controllable voltage sources having the same circuit structure are used, and the signal output ends of the two controllable voltage sources are respectively coupled to P1 and P2 to supply a supply voltage to each low level maintenance module.
  • controllable voltage source can also sense the threshold voltages of the two low level sustain modules, respectively.
  • isolation module should be connected in series between the signal output end of the controllable voltage source and the low level maintenance enable end.
  • the first low level maintenance module further includes a transistor T4, the control electrode (eg, the gate) of T4 being shorted to the first pole (eg, the drain) and coupled to the first controllable voltage source a signal output terminal for inputting an output voltage signal V DD1 of the first controllable voltage source, a second pole (eg, a source) of T4 coupled to the first low level sustain enable terminal P1;
  • the module further includes a transistor T8, a control electrode (eg, a gate) of T8 being shorted to the first pole (eg, the drain) and coupled to a signal output of the second controllable voltage source for inputting the second controllable voltage source
  • the second pole (e.g., source) of the output voltage signal V DD2 , T8 is coupled to the second low level sustain enable terminal P2.
  • the period of the output voltage signal V DD1 of the first controllable voltage source and the output voltage signal V DD2 of the second controllable voltage source is much longer than the period of the shift register unit circuit operating clock signal.
  • FIG. 9 is a circuit adaptive self-adjusting pair of controllable voltage source circuit structures based on capacitor bootstrap.
  • the controllable voltage source is comprised of two controllable voltage sources of the above-described embodiments that produce V DD1 and V DD2 , respectively.
  • the generation principle of V DD1 or V DD2 is similar to the above-mentioned controllable voltage source, and the same portions will not be described herein.
  • the difference between the pair generated V DD1 and V DD2 shown in Figure 9 is:
  • the input signals V1 and V2 of the high-level terminals of the two controllable voltage sources are complementary two low-frequency pulse signals instead of the DC voltage signals.
  • V1 when V1 is high, V2 is low, the output voltage V DD1 is high, and the output voltage V DD2 is low.
  • the first low level maintaining module of the shift register unit circuit is in an active state, and the second low level maintaining module is in a resting state.
  • V1 is low
  • V2 is high
  • output voltage V DD1 is low
  • output voltage V DD2 is high.
  • the first low level maintaining module corresponding to the shift register unit circuit is in a rest state
  • the second low level maintaining module is in an active state.
  • the output modules of the two controllable voltage sources should respectively include a reset transistor, such as a seventh transistor M7 and a fourteenth transistor M14 as shown in FIG. 9, wherein the coupling of the fourteenth transistor M14
  • a reset transistor such as a seventh transistor M7 and a fourteenth transistor M14 as shown in FIG. 9, wherein the coupling of the fourteenth transistor M14
  • the role of M7 is that its gate (such as the gate) is pulled down to the low level voltage V SS in response to the active level of the pull-down control signal; similarly, the role of M14 is its gate (eg gate) The active level conduction in response to the pull-down control signal pulls V DD2 down to the low level voltage V SS .
  • the pull-down control signal of the second transistor M7 of V2 that is, the control electrode of the seventh transistor M7 (for example, the gate) may be preferably used.
  • the input signal is V2; and the pull-down control signal of M14 is preferably V1, ie the control electrode (eg, gate) of M14 preferably has an input signal of V1.
  • Figure 10 is a SPICE simulation result of the shift register unit of the present embodiment.
  • the periods of V1 and V2 are 20 ms, so correspondingly, after a working time of 10 ms, the voltage states of V DD1 and V DD2 are inverted, and the two low-level sustaining modules switch their operating states. It is worth noting that in practical applications, the periods of V1 and V2 can be further lengthened, so that the switching frequency of V DD1 and V DD2 is lower.
  • the low level sustaining portion better suppresses the clock feedthrough effect, so the noise voltage at the output portion is smaller. This is mainly because the drive control terminal Q of the shift register is stabilized at a low level V SS by the low level sustaining portion, and even if the clock signal V A periodically jumps, the potential of the drive control terminal Q is not disturbed. The transistor T2 is then kept in the off state, thereby reducing the amount of noise in the output portion.
  • the first low level sustain enable terminal P1 and the second low level sustain enable terminal P2 are in a pulse voltage mode.
  • the two low level maintenance modules can be alternately turned on. Therefore, the low-level sustain TFT can not only reduce its threshold voltage drift due to low-frequency alternate pulse biasing. Shift, and compensate for the effect of threshold voltage drift on the reduction in overdrive voltage due to the action of a controllable voltage source. For these two reasons, the life of the row driver circuit will be further extended.
  • the low-level maintenance part is in the low-frequency pulse mode, and its dynamic power consumption is reduced due to the decrease in the number of signal transitions. Therefore, the power consumption of the shift register unit can be reduced.
  • the embodiment further discloses a shift register.
  • the method includes:
  • a plurality of cascaded shift register units SSC is a plurality of cascaded shift register units SSC.
  • a plurality of clock lines (CLK1, CLK2, CLK3, and CLK4) for transmitting desired clock signals to the shift register units SSC of each stage.
  • the enable signal line STV is coupled to the first pulse signal input terminal of the first stage shift register unit SSC for transmitting a start signal to the first stage shift register unit SSC to start the shift register to start operation.
  • the clock signal required by the controllable voltage source can be selectively coupled to the clock lines CLK1, CLK2, CLK3 and/or CLK4 through the clock signal input; the sensing of the controllable voltage source The terminal is coupled to the low level sustaining enable terminal P of each stage of the shift register unit SSC through the sensing line; the low level end of the controllable voltage source is coupled to the low level end of each stage of the shift register unit SSC; the controllable voltage source The signal output is coupled to a low level sustain enable P of each stage of shift register unit SSC, and the output voltage signal V DD (or V DD1 and V DD2 ) is used to provide an enable signal to each stage of shift register unit SSC. V P .
  • the controllable voltage source is shared by the shift register units SSC of each stage.
  • the rationality of the design is: on the one hand, the uniformity of the amorphous thin film transistor is good; on the other hand, the levels of the shift register array are The low-level sustain transistor of the shift register unit SSC undergoes the same electrical stress condition, so the threshold voltage drift values of the shift register unit SSC low-level sustain transistors of the stages are also highly uniform. Therefore, only the threshold voltage V TH of the first stage shift register unit SSC needs to be extracted, and the remaining stages of the shift register unit SSC circuits share the V TH extracted by the first stage shift register unit SSC circuit, thereby simplifying the circuit.
  • the structure reduces the complexity of the circuit and the layout area.
  • Figure 12 shows the simulation results of the adaptive compensation effect of the shift register.
  • V G n represents an output signal of the output terminal of the SSC signal of the nth stage shift register unit, n is a positive integer;
  • V Q n is a potential of the nth stage shift register unit SSC driving the control terminal Q.
  • This embodiment also discloses a display. As shown in Figure 13, it includes:
  • the display panel 100 includes a two-dimensional pixel array composed of a plurality of two-dimensional pixels, and a plurality of gate scan lines and a second direction (for example, a vertical direction) in a first direction (for example, a lateral direction) connected to each pixel. Multiple data lines. The same row of pixels in the pixel array are connected to the same gate scan line, and the same column of pixels in the pixel array are connected to the same data line.
  • the display panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, or the like, and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like.
  • the gate driving circuit 200, the gate scanning signal output terminal of the gate driving unit circuit in the gate driving circuit 200 is coupled to the corresponding gate scanning line in the display panel 100 for progressive scanning of the pixel array, the gate The driving circuit 200 may be connected to the display panel 100 by soldering or integrated in the display panel 100.
  • the gate driving circuit 200 employs the shift register provided in the above embodiment.
  • the gate driving circuit 200 may be disposed on one side of the display panel 100; in a preferred embodiment, a pair of gate driving circuits 200 are disposed on both sides of the display panel 100.
  • the data driving circuit 400 is configured to generate an image data signal and output it to a data line corresponding thereto in the display panel 100, and transmit the data to the corresponding pixel unit through the data line to realize image grayscale.
  • the timing generation circuit 300 is configured to generate various control signals required by the gate driving circuit 200.
  • the gate bias of the conventional shift register circuit is constant, and the threshold voltage drift speed of the low-level sustain transistor is fast, which easily leads to circuit failure and short life.
  • a controllable voltage source it is capable of adaptively biasing the low level to maintain the threshold voltage drift of the TFT, maintaining a low level to maintain the TFT always maintaining a high driving capability, thereby extending the life of the shift register.
  • the low level in the shift register unit circuit of each stage maintains the same electrical stress state of the transistor.
  • the shift register units of each stage share a controllable voltage source, which not only simplifies the shift register circuit architecture, but also consumes less power.

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Abstract

一种可控电压源，包括控制模块（1）、存储模块（2）和输出模块（3）。控制模块（1）用于耦合至高电平端和低电平端之间；存储模块（2）包括存储电容；存储电容的两端分别耦合至控制模块（1）形成第一端子和第二端子。输出模块（3）耦合至第二端子，其信号输出端用于向外部电路输出可控电压源的电压信号。控制模块（1）响应第一时钟信号的有效电平将第一端子耦合至高电平端，由高电平端向第一端子充电。控制模块（1）响应第二时钟信号的有效电平将第二端子耦合至高电平端，由高电平端向第二端子充电；将第一端子耦合至低电平端，第一端子通过低电平端放电。第一时钟信号的有效电平与第二时钟信号的有效电平不交叠。基于该可控电压源，还公开了一种移位寄存器及其单元以及显示器。

Description

可控电压源、移位寄存器及其单元和一种显示器 技术领域
本申请涉及电子电路领域，具体涉及到一种可控电压源、移位寄存器及其单元和一种显示器。
背景技术
窄边框显示技术日益成为平板显示技术的主流，其技术核心是薄膜晶体管(thin film transistor，TFT)集成的行列驱动电路(Gate-driver on Array，简称GOA)。这主要为了减少TFT平板上行列驱动芯片的数量，以及相应的连接线数量，从而显著地缩小显示器的边框尺寸，使得整个TFT显示面板更加紧凑、美观，而且是为了减少显示模组的后道封装工艺数量。因此，集成行扫描驱动电路可以降低显示器的制造成本、提高显示模组的良率，从而提高TFT屏幕的分辨率和整体的可靠性。
TFT集成化的行扫描驱动电路设计的关键问题在于如何提高其可靠性。在行扫描驱动电路中，起到低电平维持作用的TFT长时间处于正极性栅极电压偏置，因此这些低电平维持TFT的阈值电压随着工作时间的推移而增加。当低电平维持TFT的阈值电压漂移达到一定的量之后，行扫描驱动电路将发生失效。对于台式机显示器或者电视面板而言，由于使用时间长，TFT集成化的行扫描驱动电路的可靠性问题尤其突出。然而，国际上出现的TFT集成的行驱动电路设计都还只是从TFT器件着手，主要抑制器件的电学特性漂移，以提高GOA电路的可靠性。从电路结构来看，迄今为止所报道的各种GOA电路中，低电平维持TFT几乎均采用了恒定栅偏压模式。然而，从GOA电路的工作原理分析，这样的偏置导致相关TFT在很长时间一直处于无必要的过高的栅偏压状态下，使得TFT的阈值电压漂移过快，电路的寿命难以延长。以图14所示的GOA基本电路结构为例，几乎所有的GOA电路都包含以下3个基本模块：输入、输出和低电平维持模块。其中T100是输入器件；T200是输出器件，输出行线的扫描脉冲信号；T300和T400是低电平维持器件，一般而言T300和T400的栅极输入的高电平电压为恒定值。通常在TFT栅电极和源漏电极之间存在着相当大的交叠电容，如图14中所示的T200的CGD。在低电平维持期间，当T200漏端的时钟信号每次从低电平跳变为高电平时，原本处在低电平的T200栅电位由于CGD的耦合也将随之上升，如果这个上升不能得到有效控制，将使得T200进入亚阈区甚至导通，这将导致相当大的电流给输出端充电，输出端的低电平将不能维持。不过，此时，T300和T400处于导通态，分别抑制T200的栅电位上升和给输出端放电，维持了输出端的低电平。但是，TFT的 一个主要问题是其阈值电压在电应力下随时间不断增加，从而导致导通能力不断减弱，这样，当其阈值电压从初始值(如VTH0)增加到某一临界值(如VTHC)后，T300和T400将不再能有效压制T200的栅电位上升和给输出端放电，电路因而失效。
由上述GOA电路工作原理可知，需要T300和T400栅过驱动电压(栅源电压与阈值电压之差)略大于差值(VGH-VTHC-VGL)才能确保电路正常工作，其中VGH和VGL分别为驱动T300和T400的时钟信号的高、低电平。但迄今所有的GOA电路中，低电平维持器件的驱动时钟信号的电平为恒定的，因此T300和T400的栅过驱动电压大部分时间内，特别是早期，远远大于差值(VGH-VTHC-VGL)。比如，VGH、VTHC、VTH0和VGL分别为25V、20V、3V和0V，则电路工作的早期，T300和T400的栅过驱动电压略大于5V即可，但过驱动电压的实际的值(VGH-VTH0-VGL)达到了22V。理论和实验研究均已经表明，TFT的阈值电压的漂移速度随过驱动电压的增加而显著增加。因此，在现行的GOA电路中，时钟信号的高电平为恒定的驱动方法造成了相关TFT阈值电压漂移过快，电路寿命难以延长。
发明内容
本申请提供一种可控电压源、移位寄存器及其单元和一种显示器，以实现供给外部电路的电压可调。
根据本申请的第一方面，本申请提供一种可控电压源，包括：控制模块、存储模块和输出模块。其中，
控制模块用于耦合至高电平端和低电平端之间；
存储模块包括存储电容；存储电容的两端分别耦合至控制模块形成第一端子和第二端子。
输出模块耦合至第二端子，其信号输出端用于向外部电路输出可控电压源的电压信号。
控制模块响应第一时钟信号的有效电平将第一端子耦合至高电平端，由高电平端向第一端子充电。
控制模块响应第二时钟信号的有效电平将第二端子耦合至高电平端，由高电平端向第二端子充电；将第一端子耦合至低电平端，第一端子通过低电平端放电。
第一时钟信号的有效电平与第二时钟信号的有效电平不交叠。
根据本申请的第二方面，本申请提供一种移位寄存器，包括：至少一个移位寄存器单元、隔离模块和上述可控电压源。其中，
移位寄存器单元包括：
驱动模块，用于通过开关状态切换，将第一信号传送到移位寄存器单元的信号输出端，从而输出扫描信号；
输入模块，用于控制驱动模块切换开关状态；
低电平维持模块，用于通过开关状态切换，在该移位寄存器单元输出扫描信号后将驱动模块的信号输出端维持在低电平。
可控电压源的信号输出端耦合至低电平维持模块的低电平维持使能端；
可控电压源调整输出给低电平维持使能端的供电电压。
根据本申请的第三方面，本申请提供一种显示器，包括：
由多个像素构成的二维像素阵列，以及与阵列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；
数据驱动电路，为数据线提供数据信号；
栅极驱动电路，采用上述移位寄存器构成，为栅极扫描线提供栅极驱动信号。
本申请的有益效果是：根据本申请提供的可控电压源，可以通过调整第一时钟信号和/或第二时钟信号的占空比、幅度，以及第一时钟信号和第二时钟信号的时钟时序，来调整输出给外部电路的供电电压，从而能够补偿长时间工作后、或者环境温度变化造成的电路性能劣化。
根据本申请提供的移位寄存器，通过可控电压源调整输出给低电平维持使能端的供电电压，能够尽可能地补偿低电平维持晶体管的阈值电压漂移，从而延长电路的寿命。
附图说明
图1是现有移位寄存器单元电路结构图；
图2是本申请实施例一公开的一种可控电压源电路结构图；
图3是本申请实施例一可控电压源工作时序的SPICE模拟结果；
图4是本申请实施例二公开的一种可控电压源电路结构图；
图5是本申请实施例二可控电压源自适应偏置的SPICE模拟结果；
图6是本申请实施例三公开的移位寄存器单元电路结构图；
图7是本申请实施例三的移位寄存器单元的SPICE模拟结果；
图8是本申请实施例四公开的现有移位寄存器单元另一种电路结构图；
图9是本申请实施例四公开的可控电压源电路结构图；
图10是本申请实施例四的移位寄存器单元的SPICE模拟结果；
图11是本申请实施例四公开的移位寄存器电路结构图；
图12是本申请实施例四移位寄存器补偿模拟结果示意图；
图13是本申请实施例四还公开的一种显示器结构图；
图14是常规驱动情况下移位寄存器单元基本结构示意图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。
首先对一些术语进行说明：
本申请中的开关管为晶体管。
本申请中的晶体管可以为双极型晶体管或场效应晶体管。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极。显示器中的晶体管通常为一种场效应晶体管：薄膜晶体管(TFT)。下面以晶体管为场效应晶体管为例对本申请做详细的说明，在其它实施例中晶体管也可以是双极型晶体管。
交叠是指两路信号至少在某一相同时刻都处于有效电平状态，因此，不交叠为两路信号没有共同处于有效电平状态的时刻。
有效电平可以是高电平，也可以是低电平，在本实施例中，有效电平为高电平。
请参考图1，以移位寄存器单元为例对本实施例所依据的发明构思进行说明。图中，T1～T7为常规移位寄存器单元的逻辑功能实现器件，在低电平维持阶段，T5和T7在低电平维持使能端P获得使能信号后，将移位寄存器单元的信号输出端和驱动控制端Q耦合到低电平端，以保持其低电平VL。通常低电平维持使能端P的使能信号为高电平(由VDD提供)，因此，T5和T7长期在高电平的作用下，可能会发生阈值电压漂移。当T5和T7发生阈值电压漂移时，低电平维持使能端P获得的使能信号也应当作相应的调整，以使得移位寄存器单元的信号输出端和驱动控制端Q可靠地耦合到低电平端。
基于此，本实施例公开了一种可控电压源，以调整给输出低电平维持使能端P的电压使能信号，下面结合具体实施例进行说明。
实施例一：
请参考图2，为本实施例公开的一种可控电压源电路结构图，该可控电压源包括：控制模块1、存储模块2和输出模块3。其中，
控制模块1用于耦合至高电平端和低电平端之间。
存储模块2包括存储电容C1，其两端分别耦合至控制模块1形成第一端子A和第二端子B。
输出模块3耦合至第二端子B，其信号输出端用于向外部电路输出可控电压源的电压信号VDD。
控制模块1响应第一时钟信号
Figure PCTCN2014091062-appb-000001
的有效电平将第一端子A耦合至高电平端，由高电平端向第一端子A充电。
控制模块1响应第二时钟信号
Figure PCTCN2014091062-appb-000002
的有效电平将第二端子B耦合至高电平端，由高电平端向第二端子B充电；将第一端子A耦合至低电平 端，第一端子A通过低电平端放电。
其中，第一时钟信号
Figure PCTCN2014091062-appb-000003
的有效电平与第二时钟信号
Figure PCTCN2014091062-appb-000004
的有效电平不交叠。
在一种具体实施例中，控制模块1包括：第一晶体管M1、第二晶体管M2和第三晶体管M3。第一晶体管M1的第一极(例如漏极)和第二晶体管M2的第一极(例如漏极)耦合并用于耦合至高电平端；第一晶体管M1的第二极(例如源极)和第二晶体管M2的第二极(例如源极)分别耦合至存储电容C1的两端分别形成第一端子A和第二端子B；第一晶体管M1的控制极(例如源栅极)用于输入第一时钟信号
Figure PCTCN2014091062-appb-000005
第二晶体管M2的控制极(例如源栅极)用于输入第二时钟信号
Figure PCTCN2014091062-appb-000006
输出模块3包括第六晶体管M6，第六晶体管M6的第一极(例如漏极)与控制极(例如栅极)耦合并耦合至第二端子B；第六晶体管M6的第二极(例如源极)为输出模块3的信号输出端。
为了实现对输出模块3信号输出端的滤波，在优选的实施例中，输出模块3还可以进一步包括滤波电容C2，滤波电容C2的一端耦合至第六晶体管M6的第二极，滤波电容C2的另一端用于耦合至低电平端。
在优选的实施例中，输出模块3还可以进一步包括第七晶体管M7。第七晶体管M7的第一极(例如漏极)耦合至输出模块3的信号输出端，第七晶体管M7的第二极(例如源极)用于耦合至低电平端，第七晶体管M7的控制极(例如栅极)用于输入下拉控制信号。第七晶体管M7响应下拉控制信号的有效电平导通将输出模块3的信号输出端耦合至低电平端，从而使得当该可控电压源为被选通状态时，保持输出模块3的信号输出端的电位为低电平VSS。
在本实施例中，高电平端的电位为高电平电压VH，低电平端的电位为低电平电压VSS。
图3是本实施例可控电压源工作时序的SPICE模拟结果(图3中，VCK为第一时钟信号
Figure PCTCN2014091062-appb-000007
和第二时钟信号
Figure PCTCN2014091062-appb-000008
的时序，其中，实线为第一时钟信号
Figure PCTCN2014091062-appb-000009
的时序，虚线为第二时钟信号
Figure PCTCN2014091062-appb-000010
的时序)，其基于电容自举的输出信号幅度可控工作过程如下：
(1)电荷存储阶段
在可控电压源工作的前期，当第二时钟信号
Figure PCTCN2014091062-appb-000011
为高电平，第一时钟信号
Figure PCTCN2014091062-appb-000012
为低电平时，第一晶体管M1为关断，第二晶体管M2和第三晶体管M3为开启。于是，存储电容C1的第一端子A被下拉到低电平电压VSS，存储电容C1的第二端子B被上拉到高电平电压VH。因此，存储电容C1在B-A方向存储着电压差VH-VSS。但是因为时钟信号(如
Figure PCTCN2014091062-appb-000013
)的高电平持续时间有限，而且TFT的导通能力受限，因此实际的存储电容C1上存储着的电压值VC1＝ΔV，其中，ΔV小于VH-VSS。
(2)电压自举阶段
在可控电压源工作的前期，当第二时钟信号
Figure PCTCN2014091062-appb-000014
为低电平，第一时钟信号
Figure PCTCN2014091062-appb-000015
为高电平时，第一晶体管M1为开启，第二晶体管M2和第三晶体管M3为关断。于是，存储电容C1的第一端子A被上拉到高电平电压VH。由于存储电容C1在前一个阶段已经在B-A方向被充电到较高电压，因此C1的第二端子B被自举到较高电位ΔV+VH。
值得注意的是，在电压自举阶段，第六晶体管M6也是处于开启状态。于是存储电容C1上的存储电量通过第六晶体管M6给输出端子VDD上的负载电容充电。该充电过程只有在存储电容C1的第二端子B被自举到较高电位、第六晶体管M6处于开启状态时才能发生。因此，如图3所示，在电压自举阶段，存储电容C1上的电压差减少。因此，在电压自举阶段，可控电压源的输出电位VDD发生接近线性关系的抬升。
(3)电压稳定输出阶段
以上所述的两个过程，(1)电荷存储阶段，和(2)电压自举阶段，需要进行了若干个周期之后，可控电压源的输出电压信号VDD才逐步地达到了稳态值。存储电容C1在第一时钟信号
Figure PCTCN2014091062-appb-000016
的高电平期间的电压值增加量和其在第二时钟信号
Figure PCTCN2014091062-appb-000017
的高电平期间的电压值损失量逐步达到平衡。于是，虽然存储电容C1的端子A和B仍然由于充放电的关系在不同的电平状态之间切换，但是存储电容C1上的电压值相对稳定，输出值也趋于稳定。
本实施例公开的可控电压源，通过调整第一时钟信号
Figure PCTCN2014091062-appb-000018
和/或第二时钟信号
Figure PCTCN2014091062-appb-000019
的占空比、幅度，第一时钟信号
Figure PCTCN2014091062-appb-000020
和第二时钟信号
Figure PCTCN2014091062-appb-000021
的时钟时序，能够调整输出电压信号VDD的幅值。例如减小第一时钟信号
Figure PCTCN2014091062-appb-000022
和第二时钟信号
Figure PCTCN2014091062-appb-000023
的占空比，输出电压信号VDD的幅值降低。减小第一时钟信号
Figure PCTCN2014091062-appb-000024
或者第二时钟信号
Figure PCTCN2014091062-appb-000025
的电压幅度，输出电压信号VDD的幅值降低。该电压源电路的由TFT构成，可以与例如行扫描电路、TFT阵列等电路集成在同一块基板上。这种电压源电路具有的优势包括：能够节省电压源外围的脉宽控制集成(电源IC)，而且减少界面处过高的电源电压，于是抑制了电磁干扰对界面处的影响。同时采用这种方式来调整输出给外部电路的供电电压，从而补偿长时间工作后、或者环境温度变化造成的电路性能劣化。以环境温度变化为例，在恶劣低温环境下，a-Si TFT等晶体管的导通电流由于有效迁移率降低、阈值电压增加等原因而减少，于是其驱动能力退化。为了补偿这种由于温度变化而造成的电路性能劣化，这种电路可以通过调高第一时钟信号
Figure PCTCN2014091062-appb-000026
和/或第二时钟信号
Figure PCTCN2014091062-appb-000027
的占空比和频率，从而输出更高的驱动电压给外部TFT电路，从而维持其相对恒定的电路性能，使得电路系统即使在恶劣低温环境下也能正常地工作。
实施例二：
实施例一公开的可控电压源电路还能感应TFT的特性改变，例如它的阈值电压漂移，或者因为温度的改变其电流-电压特性发生改变。根据TFT的特性改变，该电压源的输出电压信号VDD会相应地调整，从而使得系统的响应能够跟随TFT特性的改变而调整，实现可控电压源的自适应偏置。
下面以感应外部电路的待感应元件的阈值电压为例进行说明，请参考图4，为本实施例公开的可控电压源电路结构原理图，与实施例一不同之处在于，本实施例公开的可控电压源还包括：阈值调制模块4。阈值调制模块4分别与第一端子A和第二端子B耦合；阈值调制模块4还用于耦合至低电平端；阈值调制模块4的感应端用于耦合至外部电路的待感应元件，用于感应待感应元件的阈值电压并反馈至第一端子A和/或第二端子B。
在一种具体实施例中，阈值调制模块4包括：第四晶体管M4和第五晶体管M5。第四晶体管M4的第一极(例如漏极)耦合至第一端子A，第二极(例如源极)用于耦合至低电平端；第五晶体管M5的第一极(例如漏极)耦合至第二端子B，第二极(例如源极)用于耦合至低电平端；第四晶体管M4的控制极(例如栅极)与第五晶体管M5的控制极(例如栅极)耦合形成感应端。
在其它实施例中，阈值调制模块4也可以通过其它方式实现，例如光耦等。
本实施例公开的可控电压源工作过程可参见实施例一，在此不再赘述。
需要说明的是，在以上工作过程中，存储电容C1上存储着的电压VC1在电荷存储阶段以及电压自举阶段的值还受到第四晶体管M4和第五晶体管M5的调制。由于M4和M5的控制极(例如栅极)形成的感应端耦合到待感应元件(例如待感应晶体管的控制极)，因此M4和M5会感应到待感应元件的阈值电压漂移。随着电路工作时间的推移，M4和M5的阈值电压ΔVTH增加，于是它们的导通能力变差。所以，在发生阈值电压漂移之后，存储电容C1在第一端子A和第二端子B上能够存储更多的电压，同时在电压自举阶段，VC1的损失量也更少。综合以上这两方面的原因，随着阈值电压的漂移，可控电压源输出的电压信号VDD的值会相应地增加。
图5为本实施例可控电压源自适应偏置的SPICE模拟结果。图5中表示了在阈值电压ΔVTH的值从0V增加到25V时，VDD的值相应地从0V增加到22V。这证明了这种电压源的机理正确，而且阈值电压响应的线性度较好。值得指出的是，VDD的值对于ΔVTH的补偿并没有达到 100％，根据SPICE仿真，其补偿率约等于88％。这意味着TFT集成的电路(例如移位寄存器)中，其待感应元件(例如下拉晶体管)的驱动能力仍然会存在一定的退化。但是，相比于恒定电压驱动模式情况下，本实施例公开的可控电压源能够感应待感应元件的阈值电压漂移，自适应地调整输出电压信号。这种自补偿电路的寿命将极大地延长。
实施例三：
上述实施例公开的可控电压源适用于向任何设备电路提供供电电压，以移位寄存器单元为例进行说明。请参考图6，为本实施例公开的移位寄存器单元电路结构图。该移位寄存器单元包括：驱动模块20、输入模块10、低电平维持模块30和上述可控电压源40。其中，
驱动模块20，用于通过开关状态切换，将第一信号VA传送到移位寄存器单元的信号输出端，从而输出扫描信号。在其驱动控制端Q充电获得驱动电压后，将第一信号VA传送到移位寄存器单元的信号输出端。在一种具体实施例中，驱动模块20可以包括用于耦合到移位寄存器单元的信号输出端的晶体管T2和用于存储驱动控制端Q电荷的电容Cs，在其它实施例中，也可以是其它现有的驱动方式。
输入模块10，用于控制驱动模块20切换开关状态。例如用于从第一脉冲信号输入端输入第一脉冲信号VI1，给驱动模块20的驱动控制端Q充电提供驱动电压；还用于从第二脉冲信号输入端输入第二脉冲信号VI2，将移位寄存器单元的信号输出端和驱动控制端Q耦合至低电平端。在一种具体实施例中，输入模块10可以包括用于输入第一脉冲信号VI1的晶体管T1和用于输入第二脉冲信号VI2的晶体管T3，在其它实施例中，也可以是其它现有的输入方式。
低电平维持模块30，用于通过开关状态切换，在该移位寄存器单元输出扫描信号后将驱动模块20的信号输出端维持在低电平。在其低电平维持使能端P获得使能信号VP后，将移位寄存器单元的信号输出端和驱动控制端Q耦合到低电平端。在本实施例中，所称使能信号VP为高电平信号。在一种具体实施例中，低电平维持模块30包括晶体管T5和晶体管T7，晶体管T5的控制极(例如栅极)和晶体管T7的控制极(例如栅极)耦合到低电平维持使能端P，晶体管T5的控制极(例如栅极)和晶体管T7的第二极(例如源极)用于耦合到低电平端；晶体管T5的第一极(例如漏极)耦合到驱动控制端Q；晶体管T7的第一极(例如漏极)耦合到移位寄存器单元的信号输出端。当然，在另一种实施例中，低电平维持使能端P和低电平端之间还可以进一步耦合晶体管T6，晶体管T6的控制极(例如栅极)耦合到驱动控制端Q，用于在自举阶段将T5和T7关断。在其它实施例中，也可以是其它现有的低电平维持方式。
需要说明的是，上述各个模块只是以示例的方式原理性地阐述移位 寄存器单元，各模块均可采用现有的技术方案，因此，上述各模块中，有些细节并未详细描述，本领域普通技术人员依据现有的技术方案能够实现移位寄存器单元各模块之间的连接。当然，在现有技术中，为了实现对移位寄存器单元的信号输出端的输出信号VO进行滤波等，在移位寄存器单元的信号输出端还可以进一步耦合用于滤波的电容CL和电阻RL。
可控电压源40，其信号输出端耦合至低电平维持模块30的低电平维持使能端P，用于调整输出给低电平维持使能端P的供电电压。
低电平维持模块30(如晶体管T5和T7)的阈值电压会在长时间工作之后增加，于是T5和T7的过驱动电压减少，或者说它们的过驱动能力降低，因此，为了感应低电平维持模块30的阈值电压，以动态调节输出给低电平维持模块30的供电电压，可控电压源40优选还包括阈值电压调制模块4。阈值调制模块4的感应端耦合至低电平维持模块30的低电平维持使能端P，可控电压源感应低电平维持模块30的阈值电压，根据阈值电压调整输出给低电平维持使能端P的供电电压。
需要说明的是，由于可控电压源40的信号输出端及其感应端耦合在移位寄存器单元的同一端口，即低电平维持使能端P。为了防止移位寄存器单元中不稳定的信号对可控电压源造成影响，应当在可控电压源的信号输出端和低电平维持使能端P之间串联隔离模块。隔离模块可以拖过电容、电感、互感或其它方式实现，在优选的实施例中，隔离模块包括晶体管T4，晶体管T4耦合在可控电压源的信号输出端和低电平维持使能端P之间。具体为：晶体管T4的第二极(例如源极)耦合到低电平维持使能端P，第一极(例如漏极)与控制极(例如栅极)耦合到可控电压源的信号输出端。晶体管T4用于向低电平维持使能端P传输自适应电压VDD。
上述移位寄存器单元工作所需的时钟信号优选具有相同的时钟周期。可控电压源中的第一时钟信号
Figure PCTCN2014091062-appb-000028
和第二时钟信号
Figure PCTCN2014091062-appb-000029
也可以由移位寄存器单元中任意两路不交叠的信号提供。在本实施例中，在低电平维持阶段，电压源的高电平端应保持高电平VH，高电平端的电位可以由外界的电源提供，也可以由移位寄存器单元中的时钟信号提供，或者其它能够保持电压源的高电平端为高电平VH的方式实现。
请参考图7，为本实施例的移位寄存器单元的SPICE模拟结果，图7分别表示了行移位寄存器单元电路中驱动控制端Q、低电平维持使能端P和输出信号VO的波形，图7中分别对应为VQ、VDD和VO。该模拟结果验证了所设计的TFT集成的移位寄存器单元电路和可控电压源工作过程正确。值得注意的是，在驱动控制端Q发生自举或者电压耦合的过程中，可控电压源可能会受到影响，发生电压馈通效应。但是可以将 各级的移位寄存器单元电路的VDD端口都并联在一起，所以在VDD端口上有数值较大的存储电容，该电容能够起到滤波稳压的作用，抑制电压馈通效应的影响。
采用上述可控电压源可以有效地调节移位寄存器单元的低电平维持使能端P的电位VP，能够得到有效地补偿执行低电平维持工作的晶体管的阈值电压漂移，从而使得该晶体管获得较长的工作寿命。
实施例四：
通常，移位寄存器单元都会优选地配备两套低电平维持模块，交替工作维持移位寄存器单元的信号输出端的低电平。请参考图8，为本实施例移位寄存器单元电路结构图。相比于实施例三，本实施例移位寄存器单元电路具有两个并联的低电平维持模块。其第一低电平维持模块包括晶体管T5、T6和T7，T5的控制极(例如栅极)、T7的控制极(例如栅极)和T6的第一极(例如漏极)相互耦合形成的第一低电平维持使能端P1，T5的第一极(例如漏极)耦合至驱动控制端Q，T5、T6和T7的第二极(例如源极)用于耦合至低电平端；第二低电平维持模块包括T9、T10和T11，T9的控制极(例如栅极)、T11的控制极(例如栅极)和T10的第一极(例如漏极)相互耦合形成的第二低电平维持使能端P2，T9的第一极(例如漏极)耦合至驱动控制端Q，T9、T10和T11的第二极(例如源极)用于耦合至低电平端。本实施例中，采用两个电路结构相同的可控电压源，将该两个可控电压源的信号输出端分别耦合至P1和P2以向各低电平维持模块提供供电电压。
当然，在优选的实施例中，可控电压源还可以分别感应两个低电平维持模块的阈值电压。根据实施例三的描述，可控电压源的信号输出端和低电平维持使能端之间应串联隔离模块。因此，在优选的实施例中，第一低电平维持模块还包括晶体管T4，T4的控制极(例如栅极)和第一极(例如漏极)短接并且耦合到第一可控电压源的信号输出端，用于输入第一可控电压源的输出电压信号VDD1，T4的第二极(例如源极)耦合到第一低电平维持使能端P1；第二低电平维持模块还包括晶体管T8，T8的控制极(例如栅极)和第一极(例如漏极)短接并且耦合到第二可控电压源的信号输出端，用于输入第二可控电压源的输出电压信号VDD2，T8的第二极(例如源极)耦合到第二低电平维持使能端P2。
其中，第一可控电压源的输出电压信号VDD1和第二可控电压源的输出电压信号VDD2的周期远大于移位寄存器单元电路工作时钟信号的周期。请参考图9，为本实施例的基于电容自举的幅度自适应一对可控电压源电路结构。该可控电压源由两个上述实施例的可控电压源构成，分别产生VDD1和VDD2。VDD1或者VDD2的产生原理与上述可控电压源类似，相同之处这里不再赘述。图9所示的这种成对产生VDD1和VDD2的不同 之处在于：
该两个可控电压源的高电平端的输入信号V1和V2是互补的两个低频脉冲信号，而不是直流电压信号。于是在V1为高电平时，V2为低电平，输出电压VDD1为高电平，而输出电压VDD2为低电平。在这种情况下，对应地，移位寄存器单元电路的第一低电平维持模块处于工作状态，第二低电平维持模块为休息状态。反之，当V1为低电平时，V2为高电平，输出电压VDD1为低电平，而输出电压VDD2为高电平。于是，对应地移位寄存器单元电路的第一低电平维持模块为休息状态，而第二低电平维持模块为工作状态。
当然在优选的实施例中，该两个可控电压源的输出模块应分别包括复位晶体管，如图9所示的第七晶体管M7和第十四晶体管M14，其中，第十四晶体管M14的耦合方式可参见第七晶体管M7的方案，在此不再赘述。其中，M7的作用是其控制极(例如栅极)响应下拉控制信号的有效电平导通将VDD1下拉到低电平电压VSS；类似的，M14的作用是其控制极(例如栅极)响应下拉控制信号的有效电平导通将VDD2下拉到低电平电压VSS。
需要说明的是，由于有效电平优选为高电平，而V1和V2互补，因此，可以优选将V2的作为第七晶体管M7的下拉控制信号，即第七晶体管M7的控制极(例如栅极)优选输入信号为V2；而M14的下拉控制信号优选为V1，即M14的控制极(例如栅极)优选输入信号为V1。此时，可以保证当其中一个可控电压源工作输出VDD1(或者VDD2)时，另一个可控电压源休眠将VDD2(或者VDD1)下拉至低电平电压。
图10为本实施例的移位寄存器单元的SPICE模拟结果。如图10所示，V1和V2的周期为20ms，于是对应地，在10ms的工作时间之后，VDD1和VDD2的电压状态发生翻转，两个低电平维持模块切换它们的工作状态。值得指出的是，在实际的应用中，V1和V2的周期可以被进一步地拉长，于是VDD1和VDD2的切换频率更低。
在VDD1和VDD2的工作频率更低的情况下，具有的有益效果为如下三点：
1、低电平维持部分更好地抑制时钟馈通效应，于是输出部分的噪声电压更小。这主要是因为移位寄存器的驱动控制端Q被低电平维持部分稳定在低电平VSS，即使时钟信号VA发生周期性地跳变，驱动控制端Q的电位也不会受到扰动，于是晶体管T2保持为关闭的状态，从而减少了输出部分的噪声量。
2、第一低电平维持使能端P1和第二低电平维持使能端P2处于脉冲电压模式，换言之，两个低电平维持模块可以交替地被开启。因此，低电平维持TFT不仅可以由于低频交替脉冲偏置而减少其阈值电压漂 移，而且因为可控电压源的作用而补偿阈值电压漂移对过驱动电压减少带来的影响。正是因为这两方面的原因，行驱动电路的寿命将进一步地被延长。
3、低电平维持部分处于低频脉冲模式下，其动态功耗因为信号跳变次数的减少而减少，因此，可以减少移位寄存器单元的功耗。
基于上述各实施例公开的移位寄存器单元，本实施例还公开了一种移位寄存器，请参考图11，包括：
多个级联的移位寄存器单元SSC。
多条时钟线(CLK1、CLK2、CLK3和CLK4)，用于向各级移位寄存器单元SSC传输所需时钟信号。
启动信号线STV，耦合至首级移位寄存器单元SSC的第一脉冲信号输入端，用于向首级移位寄存器单元SSC发送启动信号以启动移位寄存器开始工作。
可控电压源，在优选的实施例中，可控电压源所需的时钟信号可以通过时钟信号输入端选择性地耦合至时钟线CLK1、CLK2、CLK3和/或CLK4；可控电压源的感应端通过感应线耦合至各级移位寄存器单元SSC的低电平维持使能端P；可控电压源的低电平端耦合至各级移位寄存器单元SSC的低电平端；可控电压源的信号输出端耦合至各级移位寄存器单元SSC的低电平维持使能端P，输出的电压信号VDD(或者VDD1和VDD2)用于向各级移位寄存器单元SSC提供使能信号VP。
本实施例中，可控电压源为各级移位寄存器单元SSC所共有，这种设计的合理性在于：一方面，非晶薄膜晶体管的均匀性好；另一方面移位寄存器阵列的各级移位寄存器单元SSC的低电平维持晶体管经历着相同的电学应力条件，所以各级移位寄存器单元SSC低电平维持晶体管的阈值电压漂移值也高度地一致。于是，只需要抽取例如第一级移位寄存器单元SSC的阈值电压VTH，其余各级移位寄存器单元SSC电路都公用第一级移位寄存器单元SSC电路提取出来的VTH，从而精简了电路结构，减少了电路的复杂度和版图面积。图12示意了该移位寄存器自适应补偿效果的模拟结果。其中，VG n表示第n级移位寄存器单元SSC信号输出端的输出信号，n为正整数；VQ n为第n级移位寄存器单元SSC驱动控制端Q的电位。
本实施例还公开了一种显示器。如图13所示，包括：
显示面板100，显示面板100包括由多个二维像素构成的二维像素阵列，以及与每个像素相连的第一方向(例如横向)的多条栅极扫描线和第二方向(例如纵向)的多条数据线。像素阵列中的同一行像素均连接到同一条栅极扫描线，而像素阵列中的同一列像素则连接到同一条数据线。 显示面板100可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。
栅极驱动电路200，栅极驱动电路200中栅极驱动单元电路的栅极扫描信号输出端耦合到显示面板100中与其对应的栅极扫描线，用于对像素阵列的逐行扫描，栅极驱动电路200可以通过焊接与显示面板100相连或者集成于显示面板100内。该栅极驱动电路200采用上述实施例提供的移位寄存器。在一种具体实施例中，栅极驱动电路200可以布置在显示面板100的一侧；在优选的实施例中，采用成对的栅极驱动电路200，布置在显示面板100的两侧。
数据驱动电路400，用于产生图像数据信号，并将其输出到显示面板100中与其对应的数据线上，通过数据线传输到对应的像素单元内以实现图像灰度。
时序产生电路300，用于产生栅极驱动电路200所需的各种控制信号。
本实施例公开的移位寄存器，通过增加自适应电压源，从而具有如下特点：
(1)传统移位寄存器电路的栅偏置恒定，由于低电平维持晶体管的阈值电压漂移速度快，容易导致电路失效、寿命短。通过增加的可控电压源，其能够自适应偏置补偿低电平维持TFT的阈值电压漂移，保持低电平维持TFT始终保持较高的驱动能力，从而延长移位寄存器的寿命。
(2)根据非晶薄膜晶体管的电学特性均匀，同时各级移位寄存器单元电路中的低电平维持晶体管的电学应力状态相同的特点。各级移位寄存器单元共享可控电压源，不仅精简了移位寄存器电路架构，而且功耗较低。
(3)通过本实施例公开的移位寄存器电路中，极大地降低了显示模组外接引线的数量，而且不需要增加额外的电平线和控制线。相比于常规的移位寄存器电路，本实施例公开的移位寄存器的电路成本增加较小，且有效地增加了电路的可靠性。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (10)

  1. 一种可控电压源，其特征在于，包括：控制模块(1)、存储模块(2)和输出模块(3)；
    所述控制模块(1)用于耦合至高电平端和低电平端之间；
    所述存储模块(2)包括存储电容(C1)；所述存储电容(C1)的两端分别耦合至所述控制模块(1)形成第一端子(A)和第二端子(B)；
    所述输出模块(3)耦合至所述第二端子(B)，其信号输出端用于向外部电路输出可控电压源的电压信号(VDD)；
    所述控制模块(1)响应第一时钟信号
    Figure PCTCN2014091062-appb-100001
    的有效电平将所述第一端子(A)耦合至所述高电平端，由所述高电平端向所述第一端子(A)充电；
    所述控制模块(1)响应第二时钟信号
    Figure PCTCN2014091062-appb-100002
    的有效电平将所述第二端子(B)耦合至所述高电平端，由所述高电平端向所述第二端子(B)充电；将所述第一端子(A)耦合至所述低电平端，所述第一端子(A)通过低电平端放电；
    所述第一时钟信号
    Figure PCTCN2014091062-appb-100003
    的有效电平与所述第二时钟信号
    Figure PCTCN2014091062-appb-100004
    的有效电平不交叠。
  2. 如权利要求1所述的可控电压源，其特征在于，所述控制模块(1)包括：第一晶体管(M1)、第二晶体管(M2)和第三晶体管(M3)；
    所述第一晶体管(M1)的第一极和所述第二晶体管(M2)的第一极耦合并用于耦合至所述高电平端；
    所述第一晶体管(M1)的第二极和所述第二晶体管(M2)的第二极分别耦合至所述存储电容(C1)的两端分别形成第一端子(A)和第二端子(B)；
    所述第一晶体管(M1)的控制极用于输入第一时钟信号
    Figure PCTCN2014091062-appb-100005
    所述第二晶体管(M2)的控制极用于输入第二时钟信号
    Figure PCTCN2014091062-appb-100006
  3. 如权利要求1所述的可控电压源，其特征在于，所述输出模块(3)包括：第六晶体管(M6)；
    所述第六晶体管(M6)的第一极与控制极耦合并耦合至所述第二端子(B)；
    所述第六晶体管(M6)的第二极为所述输出模块(3)的信号输出端。
  4. 如权利要求3所述的可控电压源，其特征在于，所述输出模块还包括：滤波电容(C2)；
    所述滤波电容(C2)的一端耦合至第六晶体管(M6)的第二极，所述滤波电容(C2)的另一端用于耦合至所述低电平端。
  5. 如权利要求1所述的可控电压源，其特征在于，所述输出模块 包括：第七晶体管(M7)；
    所述第七晶体管(M7)的第一极耦合至所述输出模块(3)的信号输出端；第七晶体管(M7)的第二极用于耦合至所述低电平端；第七晶体管(M7)的控制极用于输入下拉控制信号；
    所述第七晶体管(M7)响应下拉控制信号的有效电平导通将所述输出模块(3)的信号输出端耦合至所述低电平端。
  6. 如权利要求1-5任意一项所述的可控电压源，其特征在于，还包括：阈值调制模块(4)；
    所述阈值调制模块(4)分别与第一端子(A)和第二端子(B)耦合；阈值调制模块(4)还用于耦合至所述低电平端；
    所述阈值调制模块(4)的感应端用于耦合至所述外部电路的待感应元件，用于感应所述待感应元件的阈值电压并反馈至第一端子(A)和/或第二端子(B)。
  7. 如权利要求6所述的可控电压源，其特征在于，所述阈值调制模块(4)包括：第四晶体管(M4)和第五晶体管(M5)；
    所述第四晶体管(M4)的第一极耦合至所述第一端子(A)，第二极用于耦合至所述低电平端；
    所述第五晶体管(M5)的第一极耦合至所述第二端子(B)，第二极用于耦合至所述低电平端；
    所述第四晶体管(M4)的控制极与所述第五晶体管(M5)的控制极耦合形成所述感应端。
  8. 一种移位寄存器，包括至少一个移位寄存器单元，所述移位寄存器单元包括：
    驱动模块(20)，用于通过开关状态切换，将第一信号(VA)传送到移位寄存器单元的信号输出端，从而输出扫描信号；
    输入模块(10)，用于控制驱动模块(20)切换开关状态；
    低电平维持模块(30)，用于通过开关状态切换，在该移位寄存器单元输出扫描信号后将驱动模块(20)的信号输出端维持在低电平；
    其特征在于，移位寄存器还包括：
    如权利要求1-5任意一项所述的可控电压源；所述可控电压源的信号输出端耦合至低电平维持模块(30)的低电平维持使能端(P)；
    所述可控电压源调整输出给低电平维持使能端(P)的供电电压。
  9. 如权利要求8所述的移位寄存器，其特征在于，所述可控电压源还包括阈值电压调制模块(4)；
    所述阈值调制模块(4)的感应端耦合至低电平维持模块(30)的低电平维持使能端(P)；
    所述可控电压源感应低电平维持模块(30)的阈值电压，根据阈值 电压调整输出给低电平维持使能端(P)的供电电压。
  10. 一种显示器，包括由多个像素构成的二维像素阵列，以及与阵列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；
    数据驱动电路，为数据线提供数据信号；
    栅极驱动电路，为所述栅极扫描线提供栅极驱动信号；
    其特征在于，所述栅极驱动电路采用如权利要求8或9所述的移位寄存器构成。
PCT/CN2014/091062 2014-08-04 2014-11-14 可控电压源、移位寄存器及其单元和一种显示器 WO2016019651A1 (zh)

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