WO2017045228A1 - 一种液晶显示装置及其显示面板 - Google Patents

一种液晶显示装置及其显示面板 Download PDF

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WO2017045228A1
WO2017045228A1 PCT/CN2015/091045 CN2015091045W WO2017045228A1 WO 2017045228 A1 WO2017045228 A1 WO 2017045228A1 CN 2015091045 W CN2015091045 W CN 2015091045W WO 2017045228 A1 WO2017045228 A1 WO 2017045228A1
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Prior art keywords
traces
trace
fan
display panel
metal
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English (en)
French (fr)
Inventor
王聪
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/893,489 priority Critical patent/US9857646B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display device and a display panel thereof.
  • the impedance difference between the edge region and the middle region of a group of fan-out regions is relatively large.
  • the RC delay of the data line or the scan line of the display panel is uneven, which causes the display panel to display, and the middle portion and the two sides of the display panel are different, and a color shift occurs. Or bright spots.
  • the embodiment of the invention provides a liquid crystal display device and a display panel thereof, which can reduce the RC delay between all the traces of each group of fan-out traces and improve the display quality.
  • the invention provides a display panel comprising:
  • a fan-out area connected to at least one side of the display area
  • the fan-out area includes at least one set of fan-out traces, and each set of fan-out traces includes a plurality of traces, and the plurality of traces include alternately disposed first metal traces and second metal traces, adjacent to each other. The first metal trace and the second metal trace partially overlap;
  • the plurality of traces include N traces, and the first trace of the N traces overlaps with the second trace.
  • the width of the overlap between the first trace and the second trace satisfies the following relationship:
  • the odd number of traces of the N traces are the first metal traces, and the even traces of the N traces are the second metal traces;
  • the first trace and the Nth trace of the N traces are virtual traces.
  • p 2 is the distance between the bottom ends of the adjacent two traces; h is the height of the fan-out area; ⁇ is the angle of the shaded area of the fan-out area.
  • the nth trace of the N traces partially overlaps with the n+1th trace, and the width of the nth trace overlaps with the n+1th trace satisfies the following relationship:
  • the invention also provides a display panel comprising:
  • a fan-out area connected to at least one side of the display area
  • the fan-out area includes at least one set of fan-out traces, and each set of fan-out traces includes a plurality of traces, and the plurality of traces include alternately disposed first metal traces and second metal traces, adjacent to each other. The first metal trace and the second metal trace partially overlap.
  • the plurality of traces include N traces, and the first trace of the N traces overlaps with the second trace.
  • the width of the overlap between the first trace and the second trace satisfies the following relationship:
  • p 1 is the distance between the top ends of two adjacent traces; s is the minimum distance between the metal traces of the same layer.
  • the second one of the N traces overlaps with the third trace, and the width of the second trace overlaps with the third trace satisfies the following relationship:
  • p 2 is the distance between the bottom ends of the adjacent two traces; h is the height of the fan-out area; ⁇ is the angle of the shaded area of the fan-out area.
  • the nth trace of the N traces partially overlaps with the n+1th trace, and the width of the nth trace overlaps with the n+1th trace satisfies the following relationship:
  • the top ends of the N traces are connected to the driving circuit of the display panel, and the bottom ends of the N traces are connected to the display area.
  • the odd-numbered traces of the N traces are the first-layer metal traces, and the even-numbered traces of the N traces are the second-layer metal traces.
  • the first trace and the Nth trace of the N traces are virtual traces.
  • the impedance factors of the N traces are equal.
  • the present invention also provides a liquid crystal display device including a display panel, the display panel comprising:
  • a fan-out area connected to at least one side of the display area
  • the fan-out area includes at least one set of fan-out traces, and each set of fan-out traces includes a plurality of traces, and the plurality of traces include alternately disposed first metal traces and second metal traces, adjacent to each other. The first metal trace and the second metal trace partially overlap.
  • the plurality of traces include N traces, and the first trace of the N traces overlaps with the second trace.
  • the width of the overlap between the first trace and the second trace satisfies the following relationship:
  • p 1 is the distance between the top ends of two adjacent traces; s is the minimum distance between the metal traces of the same layer.
  • the second one of the N traces overlaps with the third trace, and the width of the second trace overlaps with the third trace satisfies the following relationship:
  • p 2 is the distance between the bottom ends of the adjacent two traces; h is the height of the fan-out area; ⁇ is the angle of the shaded area of the fan-out area.
  • the nth trace of the N traces partially overlaps with the n+1th trace, and the width of the nth trace overlaps with the n+1th trace satisfies the following relationship:
  • the top ends of the N traces are connected to the driving circuit of the display panel, and the bottom ends of the N traces are connected to the display area.
  • the odd-numbered traces of the N traces are the first-layer metal traces, and the even-numbered traces of the N traces are the second-layer metal traces.
  • the first trace and the Nth trace of the N traces are virtual traces.
  • the impedance factors of the N traces are equal.
  • the fan-out area of the present invention includes at least one set of fan-out traces, each set of fan-out traces includes a plurality of traces, and the plurality of traces include alternately arranged first-layer metal traces. And the second metal trace, the adjacent first metal trace and the second metal trace partially overlap, which can reduce the RC delay between the first metal trace and the second metal trace, and improve display The display quality of the panel.
  • FIG. 1 is a schematic structural view of a display panel according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of the fanout trace shown in FIG. 1;
  • FIG 3 is a schematic structural view of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a display panel according to a first embodiment of the present invention.
  • the display panel disclosed in this embodiment includes a display area 11 and a fan-out area 12 , wherein the fan-out area 12 is connected to at least one side of the display area 11 .
  • a gate driving circuit 13 and a source driving circuit 14 are further provided on the display panel, and the gate driving circuit 13 and the source driving circuit 14 are disposed on the display panel by a COF (Chip On Film).
  • COF Chip On Film
  • the display area 11 is for displaying an image, and includes a plurality of scan lines 111 and a plurality of data lines 112.
  • the plurality of scan lines 111 and the plurality of data lines 112 are intersected in the display area 11 to form a plurality of pixel units 113.
  • Each of the pixel units 113 includes at least one pixel electrode 114 and at least one thin film transistor T1.
  • the gate of the thin film transistor T1 is connected to the corresponding scan line 111, and the source of the thin film transistor T1 is connected to the corresponding data line 112.
  • the thin film transistor T1 is connected.
  • the drain is connected to the pixel electrode 114.
  • the gate driving circuit 13 first outputs a scan signal to the scan line 111 through the fan-out region 12, so that the thin film transistor T1 of the first row of pixel units 113 is turned on, and the source driving circuit 1 outputs a data signal through the fan-out region 12 to
  • the data line 112 is such that the pixel electrodes 114 of the first row of pixel units 113 are charged according to respective desired data signals to display different gray scales; then the gate driving circuit 13 outputs the scan signals to the second row of pixel units 113.
  • the thin film transistor T1 is turned on, and then the source driving circuit 14 charges the pixel electrode 114 of the second row through the thin film transistor T1 of the second row; thus, sequentially, until all the pixel electrodes 114 of the display region 11 are charged, Rescanning begins again from the first row of pixel units 113.
  • the fan-out area 12 is connected to the two sides 115 and 116 of the display area 11.
  • the fan-out area 12 includes at least one set of fan-out traces 121, and each set of fan-out traces 121 includes a plurality of traces 122.
  • FIG. 2 is a schematic structural view of the fanout trace shown in FIG. 1.
  • the source driving circuit 14 is used as a description.
  • other chips having multiple pins disposed on the display panel, such as the gate driving circuit 13 may also be applied to the design according to the concept of the present invention. structure.
  • the plurality of traces 122 include a first layer of metal traces M1 and a second layer of metal traces M2.
  • the first layer of metal traces M1 is made by a GE process
  • the second layer of metal traces M2 is made by an SE process. Got it.
  • the first metal trace M1 and the second metal trace M2 are insulated from each other, and the adjacent first metal trace M1 and the second metal trace M2 are partially overlapped.
  • a set of fanout traces 121 includes N traces 122, where N is an integer greater than or equal to one.
  • the odd-numbered traces of the N traces 122 are the first-layer metal traces M1
  • the even-numbered traces of the N traces 122 are the second-layer metal traces M2; that is, the first of the N traces 122
  • An odd number of traces such as a trace 122, a third trace 122, and a fifth trace 122 are the first metal trace M1; the second trace 122 of the N traces 122, and the fourth
  • the even number of traces such as the trace 122 and the sixth trace 122 are the second metal trace M2.
  • one of ordinary skill in the art can completely set the odd-numbered traces of the N traces 122 to the second-layer metal traces M2, and the even-numbered traces of the N traces 122 to the first layer.
  • Metal trace M1 is an integer greater than or equal to one.
  • the two adjacent wires 122 are partially overlapped.
  • the first traces 122 of the N traces 122 overlap with the traces of the second trace 122.
  • the width of the first trace 122 overlaps with the second trace 122 is a 1 ;
  • the second trace 122 of the 122 overlaps the trace of the third trace 122, and the width of the second trace 122 overlaps with the third trace 122 is a 2 ; and so on, N traces 122
  • the traces of the n-1th trace 122 and the nth trace 122 overlap, and the width of the n- 1th trace 122 overlapping the nth trace 122 is a n-1 . Where n is less than or equal to N.
  • the top ends of the N traces 122 are connected to the driving circuit of the display panel, and the bottom ends of the N traces 122 are connected to the display area 11, that is, the top ends of the N traces 122 are connected to the pins 141 of the source driving circuit 14, N
  • the bottom end of the trace 122 is connected to the data lines D 1 , D 2 , ..., D m of the display area 11, due to the spacing between the pins 141 of the source driving circuit 14 and the data line D 1 , D 2 , ..., the spacing between D m is fixed, so the distance p 1 between the top ends of the two adjacent wires 122 and the distance p 2 between the bottom ends are
  • the fixed value that is, the distance between the top end of the n-1th trace 122 and the top end of the nth trace 122 is p 1 , the bottom end of the n-1th trace 122 and the nth trace 122 The distance between the bottom ends is p 2 .
  • the spacing between the pins 141 of the source driver circuit 14 is equal to p 1 ; the spacing between the data lines D 1 , D 2 , . . . , D m is equal to p 2 .
  • m N-2.
  • the impedance factors ⁇ of the N traces 122 are equal to reduce the RC delay of the two adjacent traces 122.
  • the impedance factor ⁇ is equal to the product of the resistance of the trace and the capacitance, namely:
  • the line width of the nth trace 122 is w n , where n is an integer greater than 2.
  • the minimum distance between the metal traces of the same layer is s, that is, the minimum between the first metal trace M1 (the first trace 122) and the first metal trace M1 (the third trace 122) The distance is s, or the minimum distance between the second metal trace M2 (the second trace 122) and the second metal trace M2 (the fourth trace 122) is s, and the N traces 122
  • the sheet resistance values are all Rs, and the height of the N traces 122 is h.
  • the line width of the first trace 122 is:
  • the width of the first trace 122 overlapping the second trace 122 is:
  • the resistance value of the first trace 122 is:
  • the capacitance value of the first trace 122 is:
  • the RC influence factor of the second trace 122 is:
  • ⁇ is the angle of the oblique line region 123 of the fan-out region 12, that is, the angle of the oblique line region of the N traces 122.
  • the line width of the second trace 122 is:
  • the capacitance value of the second trace 122 is:
  • the impedance factor ⁇ 2 of the second trace 122 is:
  • the impedance factors ⁇ of the N traces 122 are equal, namely:
  • the RC influence factor of the nth trace 122 is:
  • the line width of the nth trace 122 is:
  • the capacitance value of the nth trace 122 is:
  • the impedance factor ⁇ n of the nth trace 122 is:
  • the width of the nth trace 122 overlapping with the n+1th trace 122 is:
  • the first trace 122 and the Nth trace 122 are dummy traces, so that the m traces 122 used for transmitting signals partially overlap the adjacent two traces 122.
  • the widths of the adjacent two traces 122 are overlapped according to the above formulas (3), (15), and (20), so that the impedance factors ⁇ of the N traces 122 are equal, thereby reducing the first metal trace and
  • the RC delay between the second metal traces improves the display quality of the display panel.
  • the present invention also provides a liquid crystal display.
  • the liquid crystal display disclosed in the embodiment includes a backlight module 31 and a display panel 32 disposed in a light emitting direction of the backlight module 31.
  • the display panel 32 is as described above.
  • the display panel disclosed in the embodiments is not described herein again.
  • the fan-out area of the present invention includes at least one set of fan-out traces, each set of fan-out traces includes a plurality of traces, and the plurality of traces include alternately disposed first metal traces and second metal walks. a line, the adjacent first metal trace and the second metal trace are partially overlapped, so that the impedance factors of the plurality of traces are equal, and the first metal trace and the second metal trace can be reduced. RC delay to improve the display quality of the display panel.

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Abstract

一种液晶显示装置及其显示面板。该显示面板包括：显示区（11）；扇出区（12），与显示区（11）的至少一侧相连；其中，扇出区（12）包括至少一组扇出走线（121），每组扇出走线（121）包括多条走线（122），多条走线（122）包括交替设置的第一层金属走线（M1）和第二层金属走线（M2），相邻设置的第一层金属走线（M1）和第二层金属走线（M2）部分重叠。通过以上方式，能够减少每组扇出走线（121）的所有走线（122）之间的RC延时，提高显示质量。

Description

一种液晶显示装置及其显示面板 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示装置及其显示面板。
背景技术
在显示面板设计中，一组扇出区的边缘区域和中间区域的阻抗差异比较大。
由于扇出区的阻抗差异太大，导致显示面板的数据线或者扫描线出现RC延时不均，进而引起显示面板在显示时，显示面板的中间部分与两侧部分出现差异，出现混色色偏或者亮斑。
发明内容
本发明实施例提供了一种液晶显示装置及其显示面板，能够减少每组扇出走线的所有走线之间的RC延时，提高显示质量。
本发明提供一种显示面板，其包括：
显示区；
扇出区，与显示区的至少一侧相连；
其中，扇出区包括至少一组扇出走线，每组扇出走线包括多条走线，多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的第一层金属走线和第二层金属走线部分重叠；
其中，多条走线包括N条走线，N条走线中的第一条走线与第二条走线部分重叠，第一条走线与第二条走线重叠的宽度满足以下关系：
a1＝p1-s
其中，p1为相邻的两条走线的顶端之间的距离；s为同层的金属走线之间的最小距离；
N条走线的奇数条走线为第一层金属走线，N条走线的偶数条走线为第二层金属走线；
N条走线的第一条走线和第N条走线为虚拟走线。
其中，N条走线中的第二条走线与第三条走线部分重叠，第二条走线 与第三条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000001
其中，p2为相邻的两条走线的底端之间的距离；h为扇出区的高度；θ为扇出区的斜线区的角度。
其中，N条走线中的第n条走线与第n+1条走线部分重叠，第n条走线与第n+1条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000002
其中，n为大于2的整数；Ln满足以下关系：
Figure PCTCN2015091045-appb-000003
本发明还提供一种显示面板，其包括：
显示区；
扇出区，与显示区的至少一侧相连；
其中，扇出区包括至少一组扇出走线，每组扇出走线包括多条走线，多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的第一层金属走线和第二层金属走线部分重叠。
其中，多条走线包括N条走线，N条走线中的第一条走线与第二条走线部分重叠，第一条走线与第二条走线重叠的宽度满足以下关系：
a1＝p1-s
其中，p1为相邻的两条走线的顶端之间的距离；s为同层的金属走线之间的最小距离。
其中，N条走线中的第二条走线与第三条走线部分重叠，第二条走线与第三条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000004
其中，p2为相邻的两条走线的底端之间的距离；h为扇出区的高度；θ 为扇出区的斜线区的角度。
其中，N条走线中的第n条走线与第n+1条走线部分重叠，第n条走线与第n+1条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000005
其中，n为大于2的整数；Ln满足以下关系：
Figure PCTCN2015091045-appb-000006
其中，N条走线的顶端与显示面板的驱动电路连接，N条走线的底端与显示区连接。
其中，N条走线的奇数条走线为第一层金属走线，N条走线的偶数条走线为第二层金属走线。
其中，N条走线的第一条走线和第N条走线为虚拟走线。
其中，N条走线的阻抗因子相等。
本发明还提供一种液晶显示装置，其包括显示面板，该显示面板包括：包括：
显示区；
扇出区，与显示区的至少一侧相连；
其中，扇出区包括至少一组扇出走线，每组扇出走线包括多条走线，多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的第一层金属走线和第二层金属走线部分重叠。
其中，多条走线包括N条走线，N条走线中的第一条走线与第二条走线部分重叠，第一条走线与第二条走线重叠的宽度满足以下关系：
a1＝p1-s
其中，p1为相邻的两条走线的顶端之间的距离；s为同层的金属走线之间的最小距离。
其中，N条走线中的第二条走线与第三条走线部分重叠，第二条走线与第三条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000007
其中，p2为相邻的两条走线的底端之间的距离；h为扇出区的高度；θ为扇出区的斜线区的角度。
其中，N条走线中的第n条走线与第n+1条走线部分重叠，第n条走线与第n+1条走线重叠的宽度满足以下关系：
Figure PCTCN2015091045-appb-000008
其中，n为大于2的整数；Ln满足以下关系：
Figure PCTCN2015091045-appb-000009
其中，N条走线的顶端与显示面板的驱动电路连接，N条走线的底端与显示区连接。
其中，N条走线的奇数条走线为第一层金属走线，N条走线的偶数条走线为第二层金属走线。
其中，N条走线的第一条走线和第N条走线为虚拟走线。
其中，N条走线的阻抗因子相等。
通过上述方案，本发明的有益效果是：本发明的扇出区包括至少一组扇出走线，每组扇出走线包括多条走线，多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的第一层金属走线和第二层金属走线部分重叠，能够减少第一金属走线和第二金属走线之间的RC延时，提高显示面板的显示质量。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的显示面板的结构示意图；
图2是图1所示扇出走线的结构示意图；
图3是本发明第一实施例的液晶显示装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1，图1是本发明第一实施例的显示面板的结构示意图。如图1所述，本实施例所揭示的显示面板包括显示区11以及扇出区12，其中扇出区12与显示区11的至少一侧相连。
在显示面板上进一步设置有栅极驱动电路13以及源极驱动电路14，栅极驱动电路13和源极驱动电路14通过COF(Chip On Film，覆晶薄膜)设置在显示面板上。
显示区11用于显示影像，其包括多条扫描线111和多条数据线112，多条扫描线111和多条数据线112相交设置在显示区11内，以形成多个像素单元113。每个像素单元113包括至少一个像素电极114和至少一个薄膜晶体管T1，薄膜晶体管T1的栅极与相应的扫描线111连接，薄膜晶体管T1的源极与相应的数据线112连接，薄膜晶体管T1的漏极与像素电极114连接。当薄膜晶体管T1的栅极接收到的栅极驱动信号为高电平时，薄膜晶体管T1导通，像素电极114通过数据线112进行充电。
栅极驱动电路13会先通过扇出区12输出扫描信号至扫描线111，以使得第一行像素单元113的薄膜晶体管T1导通，同时源极驱动电路1通过扇出区12输出数据信号至数据线112，以使第一行像素单元113的像素电极114根据各自所需的数据信号进行充电，以显示不同的灰阶；接下来栅极驱动电路13输出扫描信号将第二行像素单元113的薄膜晶体管T1打开，再由源极驱动电路14经第二行的薄膜晶体管T1对第二行的像素电极114进行充电；如此依序下去，直至显示区11的所有像素电极114都充电完成，再从第一行像素单元113开始重新扫描。
优选地，扇出区12与显示区11的两侧115和116相连。其中，扇出区12包括至少一组扇出走线121，每组扇出走线121包括多条走线122。
请再参见图2，图2是图1所示扇出走线的结构示意图。本实施例是以源极驱动电路14作为说明，实际应用上，其他设置在显示面板上具有多个引脚的芯片，例如栅极驱动电路13，也可以应用在依据本发明概念做出的设计结构。
多条走线122包括交替设置的第一层金属走线M1和第二层金属走线M2，例如第一层金属走线M1采用GE制程制得，第二层金属走线M2采用SE制程制得。第一层金属走线M1和第二层金属走线M2彼此绝缘，并且相邻设置的第一层金属走线M1和第二层金属走线M2部分重叠。
如图2所示，一组扇出走线121包括N条走线122，其中N为大于或等于1的整数。优选地，N条走线122的奇数条走线为第一层金属走线M1，N条走线122的偶数条走线为第二层金属走线M2；即N条走线122中的第一条走线122、第三条走线122、第五条走线122等奇数条走线为第一层金属走线M1；N条走线122中的第二条走线122、第四条走线122、第六条走线122等偶数条走线为第二层金属走线M2。在其他实施例中，本领域的普通技术人员完全可以将N条走线122的奇数条走线设置为第二层金属走线M2，N条走线122的偶数条走线设置为第一层金属走线M1。
在本实施例中，相邻设置的两条走线122部分重叠。N条走线122中的第一条走线122和第二条走线122的走线部分重叠，第一条走线122与第二条走线122重叠的宽度为a1；N条走线122中的第二条走线122和第三条走线122的走线部分重叠，第二条走线122与第三条走线122重叠的宽度为a2；依次类推，N条走线122中的第n-1条走线122和第n条走线122的走线部分重叠，第n-1条走线122与第n条走线122重叠的宽度为an-1。其中，n小于或等于N。
N条走线122的顶端与显示面板的驱动电路连接，N条走线122的底端与显示区11连接，即N条走线122的顶端与源极驱动电路14的引脚141连接，N条走线122的底端与显示区11的数据线D1，D2，......，Dm连接，由于源极驱动电路14的引脚141之间的间距以及数据线D1，D2，......，Dm之间的间距都是固定的，因此相邻设置的两条走线122的顶端之间的距离p1 和底端之间的距离p2为定值，即第n-1条走线122的顶端和第n条走线122的顶端之间的距离为p1，第n-1条走线122的底端和第n条走线122的底端之间的距离为p2。优选地，源极驱动电路14的引脚141之间的间距等于p1；数据线D1，D2，......，Dm之间的间距等于p2。其中，m＝N-2。
在本实施例中，N条走线122的阻抗因子τ均相等，以减少相邻设置的两条走线122的RC延时。其中，阻抗因子τ等于走线的的电阻与电容的乘积，即：
τ＝RC  (1)
假设第n条走线122的线宽为wn，其中n为大于2的整数。同层的金属走线之间的最小距离为s，即第一层金属走线M1(第一条走线122)与第一层金属走线M1(第三条走线122)之间的最小距离为s，或者第二层金属走线M2(第二条走线122)与第二层金属走线M2(第四条走线122)之间的最小距离为s，N条走线122的片电阻值均为Rs，N条走线122的高度为h。
其中，第一条走线122的线宽为：
w1＝2p1-s  (2)
第一条走线122与第二条走线122重叠的宽度为：
Figure PCTCN2015091045-appb-000010
第一条走线122的电阻值为：
Figure PCTCN2015091045-appb-000011
第一条走线122的电容值为：
Figure PCTCN2015091045-appb-000012
直接令：
Figure PCTCN2015091045-appb-000013
将式(6)代入式(5)，可得：
C1＝2A(p1-s)h  (7)
根据式(1)、(4)以及(7)可得：
Figure PCTCN2015091045-appb-000014
第二条走线122的RC影响因子为：
Figure PCTCN2015091045-appb-000015
其中，θ为扇出区12的斜线区123的角度，即N条走线122的斜线区的角度。
第二条走线122的线宽为：
w2＝a1+p1  (10)
第二条走线122的电容值为：
Figure PCTCN2015091045-appb-000016
第二条走线122的阻抗因子τ2为：
Figure PCTCN2015091045-appb-000017
N条走线122的阻抗因子τ均相等，即：
τ1＝τ2  (14)
将式(8)和式(13)代入式(14)，可得第二条走线122与第三条走线122重叠的宽度为：
Figure PCTCN2015091045-appb-000018
同理可得，第n条走线122的RC影响因子为：
Figure PCTCN2015091045-appb-000019
第n条走线122的线宽为：
wn＝an-1+p1  (17)
第n条走线122的电容值为：
Cn＝A(an-1Ln-1+anLn)  (18)
第n条走线122的阻抗因子τn为：
Figure PCTCN2015091045-appb-000020
第n条走线122与第n+1条走线122重叠的宽度为：
Figure PCTCN2015091045-appb-000021
在N条走线122中，第一条走线122和第N条走线122为虚拟走线，以使用于传输信号的m条走线122都会与相邻的两条走线122部分重叠。根据上述式(3)、(15)以及(20)设置相邻的两条走线122部分重叠的宽度，以使N条走线122的阻抗因子τ均相等，进而减少第一金属走线和第二金属走线之间的RC延时，提高显示面板的显示质量。
本发明还提供一种液晶显示器，如图3所示，本实施例所揭示的液晶显示器包括背光模组31和设置在背光模组31的出光方向上的显示面板32，该显示面板32为上述实施例所揭示的显示面板，在此不再赘述。
综上所述，本发明的扇出区包括至少一组扇出走线，每组扇出走线包括多条走线，多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的第一层金属走线和第二层金属走线部分重叠，以使多条走线的阻抗因子均相等，能够减少第一金属走线和第二金属走线之间的RC延时，提高显示面板的显示质量。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种显示面板，其中，所述显示面板包括：
    显示区；
    扇出区，与所述显示区的至少一侧相连；
    其中，所述扇出区包括至少一组扇出走线，每组所述扇出走线包括多条走线，所述多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的所述第一层金属走线和所述第二层金属走线部分重叠；
    其中，所述多条走线包括N条走线，所述N条走线中的第一条走线与第二条走线部分重叠，所述第一条走线与所述第二条走线重叠的宽度满足以下关系：
    a1＝p1-s
    其中，p1为相邻的两条所述走线的顶端之间的距离；s为同层的金属走线之间的最小距离；
    所述N条走线的奇数条走线为所述第一层金属走线，所述N条走线的偶数条走线为所述第二层金属走线；
    所述N条走线的第一条走线和第N条走线为虚拟走线。
  2. 根据权利要求1所述的显示面板，其中，所述N条走线中的第二条走线与第三条走线部分重叠，所述第二条走线与所述第三条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100001
    其中，p2为相邻的两条所述走线的底端之间的距离；h为所述扇出区的高度；θ为所述扇出区的斜线区的角度。
  3. 根据权利要求2所述的显示面板，其中，所述N条走线中的第n条走线与第n+1条走线部分重叠，所述第n条走线与所述第n+1条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100002
    其中，n为大于2的整数；所述Ln满足以下关系：
    Figure PCTCN2015091045-appb-100003
  4. 一种显示面板，其中，所述显示面板包括：
    显示区；
    扇出区，与所述显示区的至少一侧相连；
    其中，所述扇出区包括至少一组扇出走线，每组所述扇出走线包括多条走线，所述多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的所述第一层金属走线和所述第二层金属走线部分重叠。
  5. 根据权利要求4所述的显示面板，其中，所述多条走线包括N条走线，所述N条走线中的第一条走线与第二条走线部分重叠，所述第一条走线与所述第二条走线重叠的宽度满足以下关系：
    a1＝p1-s
    其中，p1为相邻的两条所述走线的顶端之间的距离；s为同层的金属走线之间的最小距离。
  6. 根据权利要求5所述的显示面板，其中，所述N条走线中的第二条走线与第三条走线部分重叠，所述第二条走线与所述第三条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100004
    其中，p2为相邻的两条所述走线的底端之间的距离；h为所述扇出区的高度；θ为所述扇出区的斜线区的角度。
  7. 根据权利要求6所述的显示面板，其中，所述N条走线中的第n条走线与第n+1条走线部分重叠，所述第n条走线与所述第n+1条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100005
    其中，n为大于2的整数；所述Ln满足以下关系：
    Figure PCTCN2015091045-appb-100006
  8. 根据权利要求7所述的显示面板，其中，所述N条走线的顶端与所述显示面板的驱动电路连接，所述N条走线的底端与所述显示区连接。
  9. 根据权利要求5所述的显示面板，其中，所述N条走线的奇数条走线为所述第一层金属走线，所述N条走线的偶数条走线为所述第二层金属走线。
  10. 根据权利要求5所述的显示面板，其中，所述N条走线的第一条走线和第N条走线为虚拟走线。
  11. 根据权利要求5所述的显示面板，其中，所述N条走线的阻抗因子相等。
  12. 一种液晶显示装置，其中，所述液晶显示装置包括显示面板，所述显示面板包括：
    显示区；
    扇出区，与所述显示区的至少一侧相连；
    其中，所述扇出区包括至少一组扇出走线，每组所述扇出走线包括多条走线，所述多条走线包括交替设置的第一层金属走线和第二层金属走线，相邻设置的所述第一层金属走线和所述第二层金属走线部分重叠。
  13. 根据权利要求12所述的液晶显示装置，其中，所述多条走线包括N条走线，所述N条走线中的第一条走线与第二条走线部分重叠，所述第一条走线与所述第二条走线重叠的宽度满足以下关系：
    a1＝p1-s
    其中，p1为相邻的两条所述走线的顶端之间的距离；s为同层的金属走线之间的最小距离。
  14. 根据权利要求13所述的液晶显示装置，其中，所述N条走线中的第二条走线与第三条走线部分重叠，所述第二条走线与所述第三条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100007
    其中，p2为相邻的两条所述走线的底端之间的距离；h为所述扇出区的高度；θ为所述扇出区的斜线区的角度。
  15. 根据权利要求14所述的液晶显示装置，其中，所述N条走线中的第n条走线与第n+1条走线部分重叠，所述第n条走线与所述第n+1条走线重叠的宽度满足以下关系：
    Figure PCTCN2015091045-appb-100008
    其中，n为大于2的整数；所述Ln满足以下关系：
    Figure PCTCN2015091045-appb-100009
  16. 根据权利要求15所述的液晶显示装置，其中，所述N条走线的顶端与所述显示面板的驱动电路连接，所述N条走线的底端与所述显示区连接。
  17. 根据权利要求13所述的液晶显示装置，其中，所述N条走线的奇数条走线为所述第一层金属走线，所述N条走线的偶数条走线为所述第二层金属走线。
  18. 根据权利要求13所述的液晶显示装置，其中，所述N条走线的第一条走线和第N条走线为虚拟走线。
  19. 根据权利要求13所述的液晶显示装置，其中，所述N条走线的阻抗因子相等。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114783336A (zh) * 2022-03-28 2022-07-22 京东方科技集团股份有限公司 显示基板和显示装置
CN114822259A (zh) * 2022-05-09 2022-07-29 武汉华星光电技术有限公司 显示面板和显示装置
CN115050340A (zh) * 2022-06-30 2022-09-13 厦门天马显示科技有限公司 一种显示面板及显示装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106548757A (zh) * 2017-01-10 2017-03-29 深圳市华星光电技术有限公司 一种驱动电路及显示装置
CN106647071B (zh) * 2017-02-15 2019-11-22 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN113325642B (zh) * 2018-06-29 2022-12-30 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN108957885A (zh) * 2018-07-20 2018-12-07 深圳市华星光电技术有限公司 阵列基板
CN114299827B (zh) * 2018-10-11 2023-11-17 京东方科技集团股份有限公司 一种显示面板及显示装置
CN109300921B (zh) * 2018-11-15 2020-09-01 昆山龙腾光电股份有限公司 阵列基板及显示面板
CN109976052A (zh) * 2019-04-29 2019-07-05 深圳市华星光电技术有限公司 显示装置
CN110853511B (zh) * 2019-10-24 2021-07-06 Tcl华星光电技术有限公司 一种阵列基板
CN111625121A (zh) * 2020-05-08 2020-09-04 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111933674B (zh) 2020-08-18 2024-06-11 京东方科技集团股份有限公司 显示基板和显示装置
CN114967260B (zh) * 2022-05-30 2023-10-13 京东方科技集团股份有限公司 阵列基板、显示装置
CN120669457A (zh) * 2024-03-18 2025-09-19 合肥京东方显示技术有限公司 阵列基板、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763948A (zh) * 2004-10-22 2006-04-26 中华映管股份有限公司 薄膜晶体管阵列基板及其制造方法
CN1811540A (zh) * 2006-03-07 2006-08-02 广辉电子股份有限公司 缩小信号传递时电阻－电容效应差异的显示面板及其制法
KR20080022360A (ko) * 2006-09-06 2008-03-11 삼성전자주식회사 디스플레이장치
US20080129944A1 (en) * 2006-12-01 2008-06-05 Samsung Electronics Co., Ltd. Display panel, display apparatus having the same, and method thereof
US20110122052A1 (en) * 2009-11-23 2011-05-26 Yu-Cheng Chen Display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10339880A (ja) * 1997-06-09 1998-12-22 Hitachi Ltd 液晶表示装置
JP4132580B2 (ja) * 1999-08-06 2008-08-13 シャープ株式会社 配線構造および基板の製造方法ならびに液晶表示装置およびその製造方法
KR100923056B1 (ko) * 2002-09-16 2009-10-22 삼성전자주식회사 표시 장치 및 이의 제조방법
KR101668671B1 (ko) * 2010-05-12 2016-10-25 삼성디스플레이 주식회사 표시 장치
US9190421B2 (en) * 2011-08-18 2015-11-17 Lg Display Co., Ltd. Display device and fabrication method thereof
CN102799005A (zh) * 2012-09-07 2012-11-28 深圳市华星光电技术有限公司 Tft-lcd窄边框设计中的扇出走线的设计

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763948A (zh) * 2004-10-22 2006-04-26 中华映管股份有限公司 薄膜晶体管阵列基板及其制造方法
CN1811540A (zh) * 2006-03-07 2006-08-02 广辉电子股份有限公司 缩小信号传递时电阻－电容效应差异的显示面板及其制法
KR20080022360A (ko) * 2006-09-06 2008-03-11 삼성전자주식회사 디스플레이장치
US20080129944A1 (en) * 2006-12-01 2008-06-05 Samsung Electronics Co., Ltd. Display panel, display apparatus having the same, and method thereof
US20110122052A1 (en) * 2009-11-23 2011-05-26 Yu-Cheng Chen Display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114783336A (zh) * 2022-03-28 2022-07-22 京东方科技集团股份有限公司 显示基板和显示装置
CN114822259A (zh) * 2022-05-09 2022-07-29 武汉华星光电技术有限公司 显示面板和显示装置
CN114822259B (zh) * 2022-05-09 2023-05-30 武汉华星光电技术有限公司 显示面板和显示装置
CN115050340A (zh) * 2022-06-30 2022-09-13 厦门天马显示科技有限公司 一种显示面板及显示装置

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