WO2016095247A1 - 像素结构及具有该像素结构的液晶显示器 - Google Patents

像素结构及具有该像素结构的液晶显示器 Download PDF

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Publication number
WO2016095247A1
WO2016095247A1 PCT/CN2014/094684 CN2014094684W WO2016095247A1 WO 2016095247 A1 WO2016095247 A1 WO 2016095247A1 CN 2014094684 W CN2014094684 W CN 2014094684W WO 2016095247 A1 WO2016095247 A1 WO 2016095247A1
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WIPO (PCT)
Prior art keywords
pixel
sub
data line
electrode
line
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PCT/CN2014/094684
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English (en)
French (fr)
Inventor
陈政鸿
张天豪
郭晋波
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深圳市华星光电技术有限公司
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Priority to US14/431,047 priority Critical patent/US9935130B2/en
Publication of WO2016095247A1 publication Critical patent/WO2016095247A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a pixel structure and a liquid crystal display having the pixel structure.
  • liquid crystal display devices such as a liquid crystal display panel (Light emitting diode panel) have been widely used as display components in electronic products such as mobile phones, digital cameras, and personal digital assistants (PDAs).
  • the liquid crystal display panel has a pixel structure.
  • FIG. 1 is a schematic structural diagram of a pixel structure of the prior art.
  • the pixel structure 100 is applied to a liquid crystal display device, such as a liquid crystal display.
  • the conventional pixel structure 100 generally includes a plurality of pixel electrodes 10, a data line 20, a scan line 30, and an upper substrate.
  • the data lines 20 are distributed on adjacent pixel electrodes. Between 10 and perpendicular to the scan line 30.
  • the upper substrate has a black matrix (BM) at a position corresponding to the metal traces such as the data lines 20 and the scan lines 30, and the black matrix can shield light leakage between the data lines 20 and the shielding metal.
  • BM black matrix
  • each pixel electrode 10 is generally divided into four regions 50 by isolation electrodes 40.
  • the data line 20 is usually disposed under the isolation electrode 40 at the junction of the region 50.
  • the data line 20 of this design completely overlaps the isolation electrode 40 of the pixel electrode 100, Produces a high parasitic capacitance (Parasitic Capacitance), which will cause vertical crosstalk under the white frame of the gray background.
  • the invention provides a pixel structure and a liquid crystal display having the same, which can reduce the overlapping area of the data line and the pixel electrode above the data line, reduce the parasitic capacitance between the data line and the pixel electrode, and reduce the data.
  • the load of the line increases the charging rate of the pixel and improves the vertical crosstalk under the white frame of the gray background.
  • An aspect of the present invention provides a pixel structure including a plurality of pixel electrodes, a plurality of data lines, and a plurality of scan lines.
  • the opposite ends of each pixel electrode are respectively disposed with the scan lines, and the data lines are perpendicular to the scan lines.
  • Each pixel electrode includes at least two sub-pixel regions, the data line is located below the pixel electrode, and is located at a boundary of two adjacent sub-pixel regions, and the pixel electrode is adjacent to two sub-pixel regions
  • the junction location is provided with a plurality of slits that are aligned with the data line and above the data line.
  • the pixel electrode includes a first sub-pixel region and a second sub-pixel region, and the first sub-pixel region and the second sub-pixel region are symmetric about the data line, and the first sub-pixel region And a plurality of slits are formed on the second sub-pixel region, and the plurality of slits divide each sub-pixel region into a plurality of separators, and the plurality of slits are alternately arranged in sequence with the plurality of separators.
  • the slot on the first sub-pixel area and the corresponding slot on the second sub-pixel area are connected above the data line, and are symmetric about the data line, and the first sub-pixel area is separated.
  • a slice and a corresponding separator on the second sub-pixel region are connected above the data line, and are symmetric about the data line, and a predetermined width is formed at a boundary between the first sub-pixel region and the second sub-pixel region above the data line And equally spaced gaps.
  • the widths of the openings of the plurality of slits are all the same, and the widths of the plurality of separators are the same, and the plurality of slits are alternately arranged with the plurality of separators at equal intervals.
  • the separator on the first sub-pixel region and the corresponding separator on the second sub-pixel region are disconnected above the data line, and the pixel electrode above the data line is along the length of the data line.
  • the direction forms a strip-shaped opening to reduce the overlapping area of the data line with the pixel electrode above the data line.
  • the pixel structure further includes a plurality of pixel common electrodes, and the other opposite ends of the pixel electrode are respectively provided with a pixel common electrode, and between the opposite ends of each pixel common electrode and the scanning line A predetermined distance is apart, and an extension line of the pixel common electrode is perpendicular to the scan line.
  • the scan line is located in the same metal layer as the material constituting the common electrode of the pixel, and the pixel common electrodes located at opposite ends of the pixel electrode are parallel to the data line, and are axially symmetric about the data line, and the pixels are common.
  • the electrode is located below the pixel electrode.
  • the pixel structure further includes a plurality of pixel common electrodes, and the other opposite ends of the pixel electrode are respectively provided with a pixel common electrode, and a predetermined interval between the opposite ends of the common electrode of each pixel and the scanning line is preset.
  • the distance, and the extension line of the pixel common electrode is perpendicular to the scan line.
  • the material constituting the common electrode of the pixel is located on a different metal layer from the scan line, the common electrode of the pixel straddles the scan line, and partially overlaps with the pixel electrode, and the pixel located at opposite ends of the pixel electrode.
  • the common electrodes are all parallel to the data line and are axisymmetric with respect to the data line, and the pixel common electrode is located below the pixel electrode.
  • the pixel structure is a non-color filter array, the color resistance is formed on the color filter side of the upper substrate;
  • the pixel structure is a non-color filter array, and the color resistance is formed on the thin film transistor side of the lower substrate.
  • a liquid crystal display comprising: a scan driving circuit for generating a scan signal; a data driving circuit for generating a gray scale signal; and a pixel structure including a plurality of pixel electrodes and a plurality of data lines And a plurality of scan lines electrically connected to the scan driving circuit to transmit the scan signal, the data line being electrically connected to the data driving circuit to transmit the gray scale signal, the pixel electrode Driving the pixel according to the gradation signal; wherein the opposite ends of each pixel electrode are respectively disposed with the scan line, the data line is perpendicular to the scan line, and each pixel electrode includes at least two sub-pixel regions, The data line is located below the pixel electrode and is located at the boundary of two adjacent sub-pixel regions.
  • the pixel electrode is provided with a plurality of slits at a boundary position of two adjacent sub-pixel regions, and the plurality of slits are aligned.
  • the data line is located above the data line.
  • the pixel electrode includes a first sub-pixel region and a second sub-pixel region, and the first sub-pixel region and the second sub-pixel region are symmetric about the data line, and the first sub-pixel region And a plurality of slits are formed on the second sub-pixel region, and the plurality of slits divide each sub-pixel region into a plurality of separators, and the plurality of slits are alternately arranged in sequence with the plurality of separators.
  • the slot on the first sub-pixel area and the corresponding slot on the second sub-pixel area are connected above the data line, and are symmetric about the data line, and the first sub-pixel area is separated.
  • a slice and a corresponding separator on the second sub-pixel region are connected above the data line, and are symmetric about the data line, and a predetermined width is formed at a boundary between the first sub-pixel region and the second sub-pixel region above the data line And equally spaced gaps.
  • the widths of the openings of the plurality of slits are all the same, and the widths of the plurality of separators are the same, and the plurality of slits are alternately arranged with the plurality of separators at equal intervals.
  • the separator on the first sub-pixel region and the corresponding separator on the second sub-pixel region are disconnected above the data line, and the pixel electrode above the data line is along the length of the data line.
  • the direction forms a strip-shaped opening to reduce the overlapping area of the data line with the pixel electrode above the data line.
  • the pixel structure further includes a plurality of pixel common electrodes, and the other opposite ends of the pixel electrode are respectively provided with a pixel common electrode, and a predetermined interval between the opposite ends of the common electrode of each pixel and the scanning line is preset.
  • the distance, and the extension line of the pixel common electrode is perpendicular to the scan line.
  • the scan line is located in the same metal layer as the material constituting the common electrode of the pixel, and the pixel common electrodes located at opposite ends of the pixel electrode are parallel to the data line, and are axially symmetric about the data line, and the pixels are common.
  • the electrode is located below the pixel electrode.
  • the pixel structure further includes a plurality of pixel common electrodes, and the other opposite ends of the pixel electrode are respectively provided with a pixel common electrode, and a predetermined interval between the opposite ends of the common electrode of each pixel and the scanning line is preset.
  • the distance, and the extension line of the pixel common electrode is perpendicular to the scan line.
  • the material constituting the common electrode of the pixel is located on a different metal layer from the scan line, the common electrode of the pixel straddles the scan line, and partially overlaps with the pixel electrode, and the pixel located at opposite ends of the pixel electrode.
  • the common electrodes are all parallel to the data line and are axisymmetric with respect to the data line, and the pixel common electrode is located below the pixel electrode.
  • the pixel structure is a non-color filter array, the color resistance is formed on the color filter side of the upper substrate;
  • the pixel structure is a non-color filter array, and the color resistance is formed on the thin film transistor side of the lower substrate.
  • the pixel structure according to various embodiments of the present invention due to the number An alternately arranged slit of a predetermined width is formed at a boundary between the first sub-pixel region and the second sub-pixel region above the line, or a pixel electrode above the data line forms a strip opening along a length direction of the data line . Therefore, the overlapping area of the data line and the pixel electrode above the data line is reduced, which not only reduces the parasitic capacitance between the data line and the pixel electrode, but also improves the vertical crosstalk under the gray-white frame picture.
  • FIG. 1 is a schematic structural view of a pixel structure of the prior art.
  • FIG. 2 is a schematic structural diagram of an embodiment of a pixel structure according to a first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another embodiment of a pixel structure according to a first embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an embodiment of a pixel structure according to a second embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another embodiment of a pixel structure according to a second embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an embodiment of a pixel structure according to a third embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of another embodiment of a pixel structure according to a third embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of an embodiment of a pixel structure according to a fourth embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another embodiment of a pixel structure according to a fourth embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an embodiment of a pixel structure according to a first embodiment of the present invention.
  • the pixel structure 200 includes a plurality of pixel electrodes 210 , a plurality of data lines 220 , a plurality of scan lines 230 , and a plurality of pixel common electrodes 240 .
  • Each of the data lines 220 is located below the corresponding pixel electrode 210 and is perpendicular to the scanning line 230.
  • the pixel common electrode 240 is located on opposite sides of each pixel electrode 210 and is parallel to the data line 220.
  • the material constituting the pixel common electrode 240 is located in the same metal layer as the scan line 230.
  • the number of the pixel electrodes 210 is described by taking one example.
  • each of the pixel electrodes 210 has a substantially rectangular shape as a whole, and is located between the two pixel common electrodes 240.
  • the pixel electrode 210 is divided into upper and lower pixel domains by a pixel electrode trunk 250.
  • each pixel electrode 210 is divided by the pixel electrode trunk 250 into two pixel regions that are vertically symmetric, that is, the two pixel regions are vertically symmetric with respect to the pixel electrode trunk 250.
  • the data line 220 is disposed under the pixel electrode 210 and perpendicular to the pixel electrode trunk 250.
  • the data line 220 is used to transmit a gray signal, and the pixel electrode 210 is used to drive a pixel according to a gray signal.
  • the pixel electrode 210 is divided into two left and right pixel regions by the data line 220.
  • each pixel electrode 210 is divided by the data line 220 into two pixel regions that are bilaterally symmetric, that is, the two pixel regions.
  • the data line 220 is symmetrical.
  • each pixel electrode 210 can be divided into four sub-pixel regions by the data line 220 and the pixel electrode trunk 250 (as shown in the figure).
  • the first sub-pixel region 211, the second sub-pixel region 212, the third sub-pixel region 213, and the fourth sub-pixel region 214 are respectively indicated by a broken line in FIG.
  • the first sub-pixel region 211 and the second sub-pixel region 212 are symmetric with respect to the data line 220, and the third sub-pixel region 213 and the fourth sub-pixel region 214.
  • the data line 220 is symmetrical.
  • the first sub-pixel region 211 and the third sub-pixel region 213 are symmetric with respect to the pixel electrode trunk 250, and the second sub-pixel region 212 and the fourth sub-pixel region 214 are related to the pixel electrode trunk 250 symmetry.
  • the first sub-pixel region 211, the second sub-pixel region 212, the third sub-pixel region 213, and the fourth sub-pixel region 214 are substantially, but not limited to, rectangular sheets.
  • the first sub-pixel region 211, the second sub-pixel region 212, the third sub-pixel region 213, and the fourth sub-pixel region 214 are respectively provided with a plurality of slits 215.
  • the plurality of slits 215 divide each sub-pixel region into a plurality of strips 216 of strip shape, and the plurality of slits 215 and the plurality of separators 216 are alternately arranged in sequence.
  • the openings of the plurality of slits 215 have the same width, that is, the distance between two adjacent separators 216 is the same, and the widths of the plurality of separators 216 are the same, that is, two adjacent slits 215 The distance between them is the same.
  • the slot 215 on the first sub-pixel region 211 and the corresponding slot 215 on the second sub-pixel region 212 are connected above the data line 220, and the data is The line 220 is symmetrical; the separator 216 on the first sub-pixel region 211 and the corresponding separator 216 on the second sub-pixel region 212 are connected above the data line 220 and are symmetric about the data line 220.
  • the slit 215 on the third sub-pixel region 213 and the corresponding slit 215 on the fourth sub-pixel region 214 are connected above the data line 220 and are symmetric about the data line 220; the third sub-pixel region The separator 216 on the 213 and the corresponding separator 216 on the fourth sub-pixel region 214 are connected above the data line 220 and are symmetric about the data line 220.
  • the first sub-pixel region 211 and the third sub-pixel region 213 are symmetric with respect to the pixel electrode trunk 250, and the slit 215 and the separator 216 and the third sub-pixel region on the first sub-pixel region 211
  • the corresponding slit 215 and the spacer 216 on the 213 are respectively symmetric with respect to the pixel electrode trunk 250;
  • the second sub-pixel region 212 and the fourth sub-pixel region 214 are symmetric with respect to the pixel electrode trunk 250,
  • the second The slit 215 and the spacer 216 on the sub-pixel region 212 and the corresponding slit 215 and the spacer 216 on the fourth sub-pixel region 214 are respectively symmetrical with respect to the pixel electrode trunk 250.
  • the slit 215 on the first sub-pixel region 211 and the corresponding slit 215 on the second sub-pixel region 212 are connected at the data line 220
  • the third sub- The slit 215 on the pixel area 213 and the corresponding slit 215 on the fourth sub-pixel area 214 are connected at the data line 220, that is, the first sub-pixel area 211 and the second sub-pixel area above the data line 220.
  • alternately arranged slits of a predetermined width are formed.
  • the overlapping area of the data line 220 and the pixel electrode 210 above the data line 220 is reduced, so that the data line is not only reduced.
  • the parasitic capacitance between 220 and the pixel electrode 210, and the phenomenon of vertical crosstalk (V-Crosstalk) under the white frame of the gray background is improved.
  • the scan line 230 is used to transmit a scan signal.
  • the scan line 230 is disposed at opposite ends of the pixel electrode 210 (ie, parallel to the short side direction of the pixel electrode 210), and A predetermined distance is spaced from the pixel electrode 210.
  • the scan lines 230 located at opposite ends of the pixel electrode 210 are parallel to each other and perpendicular to the data line 220 and the pixel common electrode 240.
  • the scan line 230 is located in the same metal layer as the material constituting the pixel common electrode 240.
  • the pixel common electrode 240 is used to provide a common electrode voltage to a pixel.
  • the pixel common electrode 240 is disposed at the other opposite ends of the pixel electrode 210 (ie, parallel to the longitudinal direction of the pixel electrode 210), and is opposite to the opposite ends of the pixel electrode 210. The edges partially overlap.
  • the pixel common electrodes 240 located at opposite ends of the pixel electrode 210 are parallel to each other and located below the pixel electrode 210.
  • the opposite ends of each pixel common electrode 240 are spaced apart from the scanning line 230 by a predetermined distance, and the extension line of the pixel common electrode 240 is perpendicular to the scanning line 230.
  • the two pixel common electrodes 240 are parallel to the data line 220 and are axisymmetric with respect to the data line 220.
  • FIG. 3 is a schematic structural diagram of another embodiment of a pixel structure according to the first embodiment of the present invention.
  • the number of the pixel electrodes 210 is two as an example.
  • the two pixel electrodes 210 are arranged side by side on the same plane with a certain distance.
  • the data line 220 is disposed under the pixel electrode 210
  • the scan line 230 is located between the two pixel electrodes 210 and spaced apart from the two pixel electrodes 210 by a predetermined distance, and the data line 220 vertical.
  • Each of the pixel electrodes 210 can be divided into four sub-pixel regions by the data line 220 and the pixel electrode trunk 250, which are a first sub-pixel region 211, a second sub-pixel region 212, a third sub-pixel region 213, and a fourth sub-pixel, respectively.
  • Area 214 is a first sub-pixel region 211, a second sub-pixel region 212, a third sub-pixel region 213, and a fourth sub-pixel, respectively.
  • each pixel electrode 210 (ie, parallel to the longitudinal direction of the pixel electrode 210) are provided with a pixel common electrode 240, and the pixel common electrode 240 is located below the pixel electrode 210, and Edges of opposite ends of the pixel electrode 210 partially overlap.
  • the pixel common electrodes 240 located at opposite ends of the pixel electrode 210 are parallel to each other, and the ends of the pixel common electrode 240 are separated from the scanning line 230 by a predetermined distance from each other, and the pixel common electrode 240 is extended.
  • Line The direction is perpendicular to the scan line 230.
  • the two pixel common electrodes 240 are parallel to the data line 220 and are axisymmetric with respect to the data line 220.
  • the scan line 230 is located in the same metal layer as the material constituting the pixel common electrode 240.
  • FIG. 4 is a schematic structural diagram of an embodiment of a pixel structure according to a second embodiment of the present invention. As shown in FIG. 4, for convenience of description and description, in the present embodiment, the number of the pixel electrodes is described as an example. In the embodiment of the present invention, the structure of the pixel structure 300 constituting the embodiment is the same as that of the pixel structure 200 shown in FIG.
  • the pixel structure 300 includes a pixel electrode 210 , a data line 220 , two scan lines 230 , and Two pixel common electrodes 240, the data lines 220 are located under the pixel electrodes 210 and perpendicular to the scanning line 230, the pixel common electrodes 240 are located on opposite sides of the pixel electrodes 210, and the data The lines 220 are parallel, and the pixel common electrode 240 is located below the pixel electrode 210 and overlaps an edge portion of opposite ends of the pixel electrode 210.
  • the pixel structure 300 of the present embodiment is different from the pixel structure 200 shown in FIG. 2 in that the material constituting the pixel common electrode 240 is located in a different metal layer from the scan line 230.
  • the electrode 240 spans the scan line 230 and partially overlaps the pixel electrode 210.
  • FIG. 5 is a schematic structural diagram of another embodiment of a pixel structure according to a second embodiment of the present invention. In the present embodiment, the number of the pixel electrodes 210 will be described as two.
  • the two pixel electrodes 210 are arranged side by side on the same plane with a certain distance.
  • the data line 220 is disposed under the pixel electrode 210
  • the scan line 230 is located between the two pixel electrodes 210 and spaced apart from the two pixel electrodes 210 by a predetermined distance, and the data line 220 vertical.
  • the material constituting the pixel common electrode 240 is located at a different metal layer from the scan line 230. At this time, the pixel common electrode 240 spans the scan line 230 and partially overlaps the pixel electrode 210.
  • FIG. 6 is a schematic structural diagram of an embodiment of a pixel structure according to a third embodiment of the present invention.
  • the configuration of the pixel structure 400 constituting the embodiment is substantially the same as the configuration of the pixel structure 200 shown in FIG. 2, and the pixel structure 400 includes a pixel electrode 210, a data line 220, two scan lines 230, and two pixel common electrodes 240.
  • the data line 220 is located under the pixel electrode 210 and perpendicular to the scan line 230.
  • the pixel common electrode 240 Located on opposite sides of the pixel electrode 210 and parallel to the data line 220, the pixel common electrode 240 is located below the pixel electrode 210 and overlaps an edge portion of opposite ends of the pixel electrode 210.
  • the pixel structure 400 of the present embodiment is different from the pixel structure 200 shown in FIG. 2 in that the spacer 216 on the first sub-pixel region 211 and the corresponding spacer on the second sub-pixel region 212.
  • the 216 is not connected above the data line 220, and the separator 216 on the third sub-pixel region 213 and the corresponding separator 216 on the fourth sub-pixel region 214 are not connected above the data line 220.
  • the separator 216 on the first sub-pixel region 211 and the corresponding separator 216 on the second sub-pixel region 212 are disconnected above the data line 220, and the third sub-pixel region 213 is The separator 216 and the corresponding separator 216 on the fourth sub-pixel region 214 are disconnected above the data line 220, that is, the pixel electrode 210 above the data line 220 is formed along the length direction of the data line 220.
  • the upper and lower strip-shaped openings 218 are separated by the pixel electrode stem 250.
  • the pixel electrode 210 forms the opening 218 corresponding to the data line 220, the overlapping area of the data line 220 and the pixel electrode 210 above the data line 220 is reduced, thereby reducing the data line 220 and the pixel.
  • the parasitic capacitance between the electrodes 210, and the phenomenon of vertical crosstalk under the white frame of the gray background is improved.
  • FIG. 7 is a schematic structural diagram of another embodiment of a pixel structure according to a third embodiment of the present invention. In the present embodiment, the number of the pixel electrodes 210 will be described as two.
  • the two pixel electrodes 210 are arranged side by side on the same plane with a certain distance.
  • the data line 220 is disposed under the pixel electrode 210 , and the scan line 230 is located between the two pixel electrodes 210 and spaced apart from the two pixel electrodes 210 by a predetermined distance, and the data line 220 vertical.
  • the opposite ends of each pixel electrode 210 ie, parallel to the longitudinal direction of the pixel electrode 210) are provided with a pixel common electrode 240, and the pixel common electrode 240 is located below the pixel electrode 210, and Edges of opposite ends of the pixel electrode 210 partially overlap.
  • the pixel common electrodes 240 located at opposite ends of the pixel electrode 210 are parallel to each other, and the ends of the pixel common electrode 240 are separated from the scanning line 230 by a predetermined distance from each other.
  • the extension line direction of the pole 240 is perpendicular to the scan line 230.
  • the two pixel common electrodes 240 are parallel to the data line 220 and are axisymmetric with respect to the data line 220.
  • the scan line 230 is located in the same metal layer as the material constituting the pixel common electrode 240.
  • FIG. 8 is a schematic structural diagram of an embodiment of a pixel structure according to a fourth embodiment of the present invention. As shown in FIG. 8, for convenience of description and description, in the present embodiment, the number of the pixel electrodes is described by way of example. In the embodiment of the present invention, the structure of the pixel structure 500 constituting the embodiment is the same as that of the pixel structure 400 shown in FIG. 6 .
  • the pixel structure 500 includes a pixel electrode 210 , a data line 220 , two scan lines 230 , and Two pixel common electrodes 240, the data lines 220 are located under the pixel electrodes 210 and perpendicular to the scanning line 230, the pixel common electrodes 240 are located on opposite sides of the pixel electrodes 210, and the data The lines 220 are parallel, and the pixel common electrode 240 is located below the pixel electrode 210 and overlaps an edge portion of opposite ends of the pixel electrode 210.
  • the pixel structure 500 of the present embodiment is different from the pixel structure 400 shown in FIG. 6 in that the material constituting the pixel common electrode 240 is located on a different metal layer from the scan line 230.
  • the electrode 240 spans the scan line 230 and partially overlaps the pixel electrode 210.
  • FIG. 9 is a schematic structural diagram of another embodiment of a pixel structure according to a fourth embodiment of the present invention. In the present embodiment, the number of the pixel electrodes 210 will be described as two.
  • the two pixel electrodes 210 are arranged side by side on the same plane with a certain distance.
  • the data line 220 is disposed under the pixel electrode 210
  • the scan line 230 is located between the two pixel electrodes 210 and spaced apart from the two pixel electrodes 210 by a predetermined distance, and the data line 220 vertical.
  • the material constituting the pixel common electrode 240 is located at a different metal layer from the scan line 230. At this time, the pixel common electrode 240 spans the scan line 230 and partially overlaps the pixel electrode 210.
  • the pixel structure may be a color filter on array (CFA).
  • the color resistance is formed on the color filter (CF) side of the upper substrate, or the pixel structure may be CFA, and the color resistance is formed on the thin film transistor (TFT) side of the lower substrate.
  • each pixel electrode is not limited to four, and may be two, six, eight, or other numbers, each sub-pixel area.
  • the configuration is the same as that of the sub-pixel regions of the second to fourth embodiments described above.
  • the first sub-pixel region 211 and the second sub-pixel region 212 above the data line 220 and the third sub-pixel region Between the intersection of 213 and the fourth sub-pixel region 214, alternating slits of a predetermined width are formed, or the pixel electrode 210 above the data line 220 is formed with two strips along the length of the data line 220. Opening 218. Therefore, the overlapping area of the data line 220 and the pixel electrode 210 above the data line 220 is reduced, which not only reduces the parasitic capacitance between the data line 220 and the pixel electrode 210, but also improves the gray frame under the white frame. Vertical crosstalk.
  • the present invention further provides a liquid crystal display comprising a scan driving circuit (not shown), a data driving circuit (not shown), and the pixel structure described in the above embodiments.
  • the pixel structure includes a plurality of pixel electrodes 210, a plurality of data lines 220, a plurality of scan lines 230, and a plurality of pixel common electrodes 240.
  • the data line 220 is located under the corresponding pixel electrode 210 and perpendicular to the scanning line 230.
  • the pixel common electrode 240 is disposed on opposite sides of each pixel electrode 210, and the pixel common electrode 240 and the data line are disposed. 220 parallel.
  • the material constituting the pixel common electrode 240 is located in the same metal layer as the scanning line 230, and may be located in a different metal layer.
  • the scan driving circuit is configured to generate a scan signal, and the scan line 230 is electrically connected to the scan drive circuit for transmitting the scan signal.
  • the data driving circuit is configured to generate a gray signal, and the data line 220 is electrically connected to the data driving circuit for transmitting the gray signal.
  • the pixel electrode 210 drives a pixel according to the gradation signal.
  • liquid crystal display and the pixel structure can be applied to any product or component having a display function such as an electronic paper, a liquid crystal television, a mobile phone, a digital photo frame, a tablet computer, or the like.
  • the first sub-pixel region 211 and the second sub-pixel region 212 above the data line 220 and the third sub-pixel region 213 and the fourth sub-pixel region The junctions of 214 are formed with alternately arranged slits of a predetermined width, or the pixel electrodes 210 above the data lines 220 form two strips along the length of the data line 220. Opening 218. Therefore, the overlapping area of the data line 220 and the pixel electrode 210 above the data line 220 is reduced, which not only reduces the parasitic capacitance between the data line 220 and the pixel electrode 210, but also improves the gray frame under the white frame. Vertical crosstalk. In addition, when the liquid crystal display panel is normally displayed, the intersection of each sub-pixel region and the pixel electrode edge region may be blocked by the data line due to a dis-clination line caused by poor alignment of liquid crystal molecules. Invisible.

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Abstract

一种像素结构（200），其包括若干像素电极（210）、若干数据线（220）及若干扫描线（230），每一像素电极（210）的相对两端分别设置有扫描线（230），数据线（220）与扫描线（230）垂直，每一像素电极（210）包括至少两个子像素区域，数据线（220）位于像素电极（210）的下方，并位于相邻的两个子像素区域的交界处，像素电极（210）在相邻的两个子像素区域的交界位置开设有若干缝隙（215），若干缝隙（215）对准数据线（220）并位于数据线（220）的上方。还提供一种液晶显示器。该像素结构及具有该像素结构的液晶显示器中的数据线（220）与该数据线（220）上方的像素电极重叠面积减少，不但降低了该数据线（220）与像素电极之间的寄生电容，而且会改善在灰底白框画面下的垂直串扰的现象。

Description

像素结构及具有该像素结构的液晶显示器
本发明要求2014年12月16日递交的发明名称为“像素结构及具有该像素结构的液晶显示器”的申请号为201410783882.3的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其是涉及一种像素结构及一种具有该像素结构的液晶显示器。
背景技术
随着液晶显示技术的不断发展，液晶显示装置如液晶显示面板(Light emitting diode panel)作为显示部件已经广泛应用于移动电话、数码相机、个人数字助理(Personal Digital Assistant，PDA)等电子产品中。该液晶显示面板具有像素结构，请参阅图1，其为现有技术的像素结构的结构示意图。该像素结构100应用于液晶显示装置如液晶显示器中，现有的像素结构100一般包括若干像素电极10、数据线20、扫描线30及上基板，所述数据线20分布于相邻的像素电极10之间，并垂直于所述扫描线30。所述上基板与该数据线20及扫描线30等金属走线相对应的位置具有黑色矩阵(black matrix，BM)，该黑色矩阵可遮蔽数据线20与遮光金属(shielding metal)之间的漏光。如图1所示，每个像素电极10通常由隔离电极40划分为4个区域50。
上述像素结构100在显示黑底白框的画面时，由于面板弯曲、上下基板位移等原因，数据线20附近可能会出现漏光，进而导致垂直串扰(V-Crosstalk)的现象。此外，由于上下基板之间发生相对位移，位移较大的区域就会产生大面积暗团，则必须增大该上基板的黑色矩阵来遮蔽漏光，如此便会降低像素的开口率。为了提升像素的开口率，通常将数据线20设置于区域50交界处的隔离电极40下面，然而，由于此设计的数据线20与像素电极100的隔离电极40完全重叠，因此二者之间会产生较高的寄生电容(Parasitic Capacitance)，如此便会造成在灰底白框画面下的垂直串扰的现象。
发明内容
本发明提供一种像素结构及具有该像素结构的液晶显示器，其可减少数据线与该数据线上方的像素电极的重叠面积，降低了数据线与像素电极之间的寄生电容，而且可降低数据线的负载，提高像素的充电率，改善灰底白框画面下的垂直串扰的现象。
本发明一方面提供了一种像素结构，包括若干像素电极、若干数据线及若干扫描线，每一像素电极的相对两端分别设置有所述扫描线，所述数据线与所述扫描线垂直，每一像素电极包括至少两个子像素区域，所述数据线位于所述像素电极的下方，并位于相邻的两个子像素区域的交界处，所述像素电极在相邻的两个子像素区域的交界位置开设有若干缝隙，所述若干缝隙对准所述数据线并位于所述数据线的上方。
其中，所述像素电极包括一第一子像素区域及一第二子像素区域，所述第一子像素区域与所述第二子像素区域关于所述数据线对称，所述第一子像素区域及所述第二子像素区域上均开设有若干缝隙，该若干缝隙将每个子像素区域分隔为若干分隔片，该若干缝隙与该若干分隔片依次交替排列分布。
其中，所述第一子像素区域上的缝隙与所述第二子像素区域上对应的缝隙在所述数据线上方连通，并关于所述数据线对称，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在数据线上方连接，并关于该数据线对称，该数据线上方的第一子像素区域与第二子像素区域交界处形成了具有预定宽度且等间距交替排列的缝隙。
其中，所述若干缝隙的开口的宽度均相同，所述若干分隔片的宽度均相同，该若干缝隙与该若干分隔片依次等间距交替排列分布。
其中，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在所述数据线上方断开，所述数据线上方的像素电极沿着该数据线的长度方向形成了条状的开口，以减少所述数据线与该数据线上方的像素电极重叠面积。
其中，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间 隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
其中，所述扫描线与构成所述像素共电极的材料位于同一金属层，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
其中，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
其中，构成所述像素共电极的材料与所述扫描线位于不同的金属层，该像素共电极跨过所述扫描线，并与所述像素电极存在部分重叠，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
其中，当所述数据线上方的第一子像素区域与第二子像素区域交界处开设为所述缝隙或是设计为沿着所述数据线长度方向开设的开口时，则所述像素结构为非彩色滤光阵列，色阻制作于上基板的彩色滤光片侧；或者
像素结构为非彩色滤光阵列，色阻制作于下基板的薄膜晶体管侧。
本发明另一方面提供了一种液晶显示器，包括：一扫描驱动电路，用于产生扫描信号；一数据驱动电路，用于产生灰度信号；及一像素结构，包括若干像素电极、若干数据线及若干扫描线，所述扫描线与所述扫描驱动电路电性连接以传送所述扫描信号，所述数据线与所述数据驱动电路电性连接以传送所述灰度信号，所述像素电极根据所述灰度信号驱动像素；其中，每一像素电极的相对两端分别设置有所述扫描线，所述数据线与所述扫描线垂直，每一像素电极包括至少两个子像素区域，所述数据线位于所述像素电极的下方，并位于相邻的两个子像素区域的交界处，所述像素电极在相邻的两个子像素区域的交界位置开设有若干缝隙，所述若干缝隙对准所述数据线并位于所述数据线的上方。
其中，所述像素电极包括一第一子像素区域及一第二子像素区域，所述第一子像素区域与所述第二子像素区域关于所述数据线对称，所述第一子像素区域及所述第二子像素区域上均开设有若干缝隙，该若干缝隙将每个子像素区域分隔为若干分隔片，该若干缝隙与该若干分隔片依次交替排列分布。
其中，所述第一子像素区域上的缝隙与所述第二子像素区域上对应的缝隙在所述数据线上方连通，并关于所述数据线对称，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在数据线上方连接，并关于该数据线对称，该数据线上方的第一子像素区域与第二子像素区域交界处形成了具有预定宽度且等间距交替排列的缝隙。
其中，所述若干缝隙的开口的宽度均相同，所述若干分隔片的宽度均相同，该若干缝隙与该若干分隔片依次等间距交替排列分布。
其中，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在所述数据线上方断开，所述数据线上方的像素电极沿着该数据线的长度方向形成了条状的开口，以减少所述数据线与该数据线上方的像素电极重叠面积。
其中，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
其中，所述扫描线与构成所述像素共电极的材料位于同一金属层，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
其中，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
其中，构成所述像素共电极的材料与所述扫描线位于不同的金属层，该像素共电极跨过所述扫描线，并与所述像素电极存在部分重叠，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
其中，当所述数据线上方的第一子像素区域与第二子像素区域交界处开设为所述缝隙或是设计为沿着所述数据线长度方向开设的开口时，则所述像素结构为非彩色滤光阵列，色阻制作于上基板的彩色滤光片侧；或者
像素结构为非彩色滤光阵列，色阻制作于下基板的薄膜晶体管侧。
相较于现有技术，根据本发明的各个实施例所述的像素结构，由于所述数 据线上方的第一子像素区域与第二子像素区域交界处均形成了预定宽度的交替排列的缝隙，或者该数据线上方的像素电极沿着该数据线的长度方向形成了条状的开口。因此，所述数据线与该数据线上方的像素电极重叠面积减少，如此不但降低了该数据线与像素电极之间的寄生电容，而且会改善在灰底白框画面下的垂直串扰的现象。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的像素结构的结构示意图。
图2为本发明第一实施例的像素结构一个实施方式的结构示意图。
图3为本发明第一实施例的像素结构另一个实施方式的结构示意图。
图4为本发明第二实施例的像素结构一个实施方式的结构示意图。
图5为本发明第二实施例的像素结构另一个实施方式的结构示意图。
图6为本发明第三实施例的像素结构一个实施方式的结构示意图。
图7为本发明第三实施例的像素结构另一个实施方式的结构示意图。
图8为本发明第四实施例的像素结构一个实施方式的结构示意图。
图9为本发明第四实施例的像素结构另一个实施方式的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使 用的方向用语是为了更好、更清楚地说明及理解本发明，而非用以限定本发明。此外，在附图中，结构相似或相同的单元用相同的标号表示。
请参阅图2，图2为本发明第一实施例的像素结构一个实施方式的结构示意图。如图2所示，所述像素结构200包括若干像素电极(pixel electrode)210、若干数据线(Data)220、若干扫描线(Gate)230及若干像素共电极240。每一数据线220位于对应的像素电极210下面，并与所述扫面线230垂直，所述像素共电极240位于每一像素电极210的相对两侧，并与该数据线220平行，其中，构成所述像素共电极240的材料与所述扫描线230位于相同金属层。
为了便于说明和描述，如图2所示，在本实施例的一个实施方式中，所述像素电极210的数量以一个为例加以说明。
在本发明的实施例中，每一所述像素电极210整体大致为长方形片状，其位于两个像素共电极240之间。所述像素电极210通过一像素电极主干250被划分为上下两个像素区域(pixel domain)。较佳地，每一像素电极210由该像素电极主干250划分为上下对称的两个像素区域，即，该两个像素区域关于所述像素电极主干250上下对称。
所述数据线220设置于所述像素电极210下面，并与所述像素电极主干250垂直，该数据线220用于传送灰度信号，所述像素电极210用于根据灰度信号驱动像素。所述像素电极210通过该数据线220被划分为左右两个像素区域，较佳地，每一像素电极210由该数据线220划分为左右对称的两个像素区域，即，该两个像素区域关于所述数据线220对称。在本发明的实施例中，由于所述数据线220与所述像素电极主干250垂直，因此，每一像素电极210可被该数据线220与像素电极主干250划分为四个子像素区域(如图1中虚线所示)，分别为第一子像素区域211、第二子像素区域212、第三子像素区域213及第四子像素区域214。
在本发明的实施例中，所述第一子像素区域211与所述第二子像素区域212关于所述数据线220对称，所述第三子像素区域213与所述第四子像素区域214关于所述数据线220对称。所述第一子像素区域211与所述第三子像素区域213关于所述像素电极主干250对称，所述第二子像素区域212与所述第四子像素区域214关于所述像素电极主干250对称。
所述第一子像素区域211、所述第二子像素区域212、所述第三子像素区域213与所述第四子像素区域214整体均大致为但并不局限于长方形片状。在本发明的实施例中，所述第一子像素区域211、所述第二子像素区域212、所述第三子像素区域213与所述第四子像素区域214上均开设有若干缝隙215，该若干缝隙215将每个子像素区域分隔为条状的若干分隔片216，该若干缝隙215与该若干分隔片216依次交替排列分布。较佳地，所述若干缝隙215的开口的宽度均相同，即两个相邻的分隔片216之间的距离相同，所述若干分隔片216的宽度均相同，即两个相邻的缝隙215之间的距离相同。
较佳地，在本发明的实施方式中，所述第一子像素区域211上的缝隙215与所述第二子像素区域212上对应的缝隙215在数据线220上方连通，并关于所述数据线220对称；所述第一子像素区域211上的分隔片216与所述第二子像素区域212上对应的分隔片216在数据线220上方连接，并关于该数据线220对称。所述第三子像素区域213上的缝隙215与所述第四子像素区域214上对应的缝隙215在所述数据线220上方连通，并关于该数据线220对称；所述第三子像素区域213上的分隔片216与所述第四子像素区域214上对应的分隔片216在所述数据线220上方连接，并关于该数据线220对称。所述第一子像素区域211与所述第三子像素区域213关于所述像素电极主干250对称，所述第一子像素区域211上的缝隙215和分隔片216与所述第三子像素区域213上对应的缝隙215和分隔片216分别关于所述像素电极主干250对称；所述第二子像素区域212与所述第四子像素区域214关于所述像素电极主干250对称，所述第二子像素区域212上的缝隙215和分隔片216与所述第四子像素区域214上对应的缝隙215和分隔片216分别关于所述像素电极主干250对称。
在本发明的实施例中，由于所述第一子像素区域211上的缝隙215与所述第二子像素区域212上对应的缝隙215在所述数据线220处连通，以及所述第三子像素区域213上的缝隙215与所述第四子像素区域214上对应的缝隙215在所述数据线220处连通，即，该数据线220上方的第一子像素区域211与第二子像素区域212交界处以及所述第三子像素区域213及所述第四子像素区域214的交界处均形成了预定宽度的交替排列的缝隙。因此，所述数据线220与该数据线220上方的像素电极210重叠面积减少，如此不但降低了该数据线 220与像素电极210之间的寄生电容(Parasitic Capacitance)，而且会改善在灰底白框画面下的垂直串扰(V-Crosstalk)的现象。
所述扫描线230用于传输扫描信号，在本发明的实施例中，所述扫描线230设置于所述像素电极210的相对两端(即平行于该像素电极210的短边方向)，并与该像素电极210之间间隔有预设的距离。位于该像素电极210相对两端的扫描线230相互平行，且与所述数据线220及所述像素共电极240垂直。所述扫描线230与构成所述像素共电极240的材料位于同一金属层。
所述像素共电极240用于向像素提供共电极电压。在本发明的实施例中，所述像素共电极240设置于所述像素电极210另外的相对两端(即平行于该像素电极210的长边方向)，并与该像素电极210的相对两端的边缘部分重叠。位于该像素电极210相对两端的像素共电极240相互平行，且位于该像素电极210的下方。在本发明的实施例中，每个像素共电极240的相对两端与所述扫面线230之间间隔一预设的距离，该像素共电极240的延长线与所述扫描线230垂直。较佳地，两个所述像素共电极240与所述数据线220平行，并关于该数据线220轴对称。
可以理解，所述像素电极210的数量还可以为两个，请参阅图3，图3为本发明第一实施例的像素结构另一个实施方式的结构示意图。在本实施方式中，以该像素电极210的数量为两个为例加以说明。
在该实施方式中，两个像素电极210并排排列至同一平面上，并间隔一定的距离。所述数据线220设置于该像素电极210的下面，所述扫描线230位于两个像素电极210之间，并与该两个像素电极210互相间隔一预定的距离，并与所述数据线220垂直。每一像素电极210可被该数据线220与像素电极主干250划分为四个子像素区域，分别为第一子像素区域211、第二子像素区域212、第三子像素区域213及第四子像素区域214。
在本实施方式中，每个像素电极210的相对两端(即平行于该像素电极210的长边方向)设置有像素共电极240，该像素共电极240位于该像素电极210的下方，并与该像素电极210的相对两端的边缘部分重叠。位于该像素电极210相对两端的像素共电极240相互平行，所述像素共电极240的端部与所述扫面线230之间分离，相互间隔一预设的距离，该像素共电极240的延长线 方向与所述扫描线230垂直。较佳地，两个所述像素共电极240与所述数据线220平行，并关于该数据线220轴对称。所述扫描线230与构成所述像素共电极240的材料位于同一金属层。
请参阅图4，图4为本发明第二实施例的像素结构一个实施方式的结构示意图。如图4所示，为了便于说明和描述，在本实施方式中，所述像素电极的数量以一个为例加以说明。在本发明实施例中，组成该实施例的像素结构300的构成与上述图2所示的像素结构200的构成相同，该像素结构300包括像素电极210、数据线220、两个扫描线230及两个像素共电极240，该数据线220位于所述像素电极210下面，并与所述扫面线230垂直，所述像素共电极240位于所述像素电极210的相对两侧，并与该数据线220平行，且该像素共电极240位于该像素电极210的下方，并与该像素电极210的相对两端的边缘部分重叠。
本实施例的像素结构300与上述图2所示的像素结构200的不同之处在于：构成所述像素共电极240的材料与所述扫描线230位于不同的金属层，此时，该像素共电极240跨过所述扫描线230，并与所述像素电极210存在部分重叠。
可以理解，所述像素电极210的数量还可以为两个，请参阅图5，图5为本发明第二实施例的像素结构另一个实施方式的结构示意图。在本实施方式中，以该像素电极210的数量为两个加以说明。
在该实施方式中，两个像素电极210并排排列至同一平面上，并间隔一定的距离。所述数据线220设置于该像素电极210的下面，所述扫描线230位于两个像素电极210之间，并与该两个像素电极210互相间隔一预定的距离，并与所述数据线220垂直。构成所述像素共电极240的材料与所述扫描线230位于不同的金属层，此时，该像素共电极240跨过所述扫描线230，并与所述像素电极210存在部分重叠。
请参阅图6，图6为本发明第三实施例的像素结构一个实施方式的结构示意图。如图6所示，为了便于说明和描述，在本实施方式中，所述像素电极的数量以一个为例加以说明。在本发明实施例中，组成该实施例的像素结构400的构成与上述图2所示的像素结构200的构成基本相同，该像素结构400包括 像素电极210、数据线220、两个扫描线230及两个像素共电极240，所述数据线220位于所述像素电极210下面，并与所述扫面线230垂直，所述像素共电极240位于该像素电极210的相对两侧，并与所述数据线220平行，且该像素共电极240位于该像素电极210的下方，并与该像素电极210的相对两端的边缘部分重叠。
本实施例的像素结构400与上述图2所示的像素结构200的不同之处在于：所述第一子像素区域211上的分隔片216与所述第二子像素区域212上对应的分隔片216在所述数据线220上方不连接，所述第三子像素区域213上的分隔片216与所述第四子像素区域214上对应的分隔片216在该数据线220上方不连接。也即是说，由于该第一子像素区域211上的分隔片216与所述第二子像素区域212上对应的分隔片216在数据线220上方断开，且该第三子像素区域213上的分隔片216与所述第四子像素区域214上对应的分隔片216在所述数据线220上方断开，即，该数据线220上方的像素电极210沿着该数据线220的长度方向形成了上下两个条状的开口218，该上下两个开口218由所述像素电极主干250分隔。因此，由于该像素电极210对应所述数据线220处形成了所述开口218，所述数据线220与该数据线220上方的像素电极210重叠面积减少，如此不但降低了该数据线220与像素电极210之间的寄生电容，而且会改善在灰底白框画面下的垂直串扰的现象。
可以理解，所述像素电极210的数量还可以为两个，请参阅图7，图7为本发明第三实施例的像素结构另一个实施方式的结构示意图。在本实施方式中，以该像素电极210的数量为两个加以说明。
在该实施方式中，两个像素电极210并排排列至同一平面上，并间隔一定的距离。所述数据线220设置于该像素电极210的下面，所述扫描线230位于两个像素电极210之间，并与该两个像素电极210互相间隔一预定的距离，并与所述数据线220垂直。在本实施方式中，每个像素电极210的相对两端(即平行于该像素电极210的长边方向)设置有像素共电极240，该像素共电极240位于该像素电极210的下方，并与该像素电极210的相对两端的边缘部分重叠。位于该像素电极210相对两端的像素共电极240相互平行，所述像素共电极240的端部与所述扫面线230之间分离，相互间隔一预设的距离，该像素共电 极240的延长线方向与所述扫描线230垂直。两个所述像素共电极240与所述数据线220平行，并关于该数据线220轴对称。所述扫描线230与构成所述像素共电极240的材料位于同一金属层。
请参阅图8，图8为本发明第四实施例的像素结构一个实施方式的结构示意图。如图8所示，为了便于说明和描述，在本实施方式中，所述像素电极的数量以一个为例加以说明。在本发明实施例中，组成该实施例的像素结构500的构成与上述图6所示的像素结构400的构成相同，该像素结构500包括像素电极210、数据线220、两个扫描线230及两个像素共电极240，该数据线220位于所述像素电极210下面，并与所述扫面线230垂直，所述像素共电极240位于所述像素电极210的相对两侧，并与该数据线220平行，且该像素共电极240位于该像素电极210的下方，并与该像素电极210的相对两端的边缘部分重叠。
本实施例的像素结构500与上述图6所示的像素结构400的不同之处在于：构成所述像素共电极240的材料与所述扫描线230位于不同的金属层，此时，该像素共电极240跨过所述扫描线230，并与所述像素电极210存在部分重叠。
可以理解，所述像素电极210的数量还可以为两个，请参阅图9，图9为本发明第四实施例的像素结构另一个实施方式的结构示意图。在本实施方式中，以该像素电极210的数量为两个加以说明。
在该实施方式中，两个像素电极210并排排列至同一平面上，并间隔一定的距离。所述数据线220设置于该像素电极210的下面，所述扫描线230位于两个像素电极210之间，并与该两个像素电极210互相间隔一预定的距离，并与所述数据线220垂直。构成所述像素共电极240的材料与所述扫描线230位于不同的金属层，此时，该像素共电极240跨过所述扫描线230，并与所述像素电极210存在部分重叠。
此外当所述数据线220上方的第一子像素区域211与第二子像素区域212交界处以及所述第三子像素区域213及所述第四子像素区域214的交界处设计为预定宽度的交替排列的缝隙或是设计为沿着数据线220长度方向开设的开口218时，则像素结构可为非彩色滤光阵列(color filter on array，CFA)，则 色阻制作于上基板的彩色滤光片(color filter，CF)侧，或者，像素结构可为CFA，则色阻制作于下基板的薄膜晶体管(thin film transistor，TFT)侧。
可以理解，在本发明的其实实施例中，每个像素电极所包括的子像素区域并与不限于4个，还可以为2个、6个、8个，或其他数量个，每个子像素区域的构成与上述实施例二至实施例四的子像素区域的构成相同。
综上所述，根据本发明的上述各个实施例所述的像素结构，由于所述数据线220上方的第一子像素区域211与第二子像素区域212交界处以及所述第三子像素区域213及所述第四子像素区域214的交界处均形成了预定宽度的交替排列的缝隙，或者该数据线220上方的像素电极210沿着该数据线220的长度方向形成了上下两个条状的开口218。因此，所述数据线220与该数据线220上方的像素电极210重叠面积减少，如此不但降低了该数据线220与像素电极210之间的寄生电容，而且会改善在灰底白框画面下的垂直串扰的现象。
本发明的另一实施例的还提供一种液晶显示器，该液晶显示器包括扫描驱动电路(图未示)、数据驱动电路(图未示)及上述实施例所述的像素结构。该像素结构包括若干像素电极210、若干数据线220、若干扫描线230及若干像素共电极240。所述数据线220位于对应的像素电极210下面，并与所述扫面线230垂直，每一像素电极210的相对两侧设置有所述像素共电极240，该像素共电极240与该数据线220平行。其中，构成所述像素共电极240的材料与所述扫描线230位于相同金属层，也可以位于不同的金属层。
所述扫描驱动电路用于产生扫描信号，所述扫描线230与该扫描驱动电路电性连接，用于传送所述扫描信号。所述数据驱动电路用于产生灰度信号，所述数据线220与该数据驱动电路电性连接，用于传送所述灰度信号。所述像素电极210根据所述灰度信号驱动像素。
可以理解的是，所述液晶显示器及所述像素结构可以应用于电子纸、液晶电视、移动电话、数码相框、平板电脑等任何具有显示功能的产品或部件。
在本发明实施例的液晶显示器中，由于所述数据线220上方的第一子像素区域211与第二子像素区域212交界处以及所述第三子像素区域213及所述第四子像素区域214的交界处均形成了预定宽度的交替排列的缝隙，或者该数据线220上方的像素电极210沿着该数据线220的长度方向形成了上下两个条状 的开口218。因此，所述数据线220与该数据线220上方的像素电极210重叠面积减少，如此不但降低了该数据线220与像素电极210之间的寄生电容，而且会改善在灰底白框画面下的垂直串扰的现象。此外，当液晶显示面板正常显示时，各子像素区域的交界处和像素电极边缘区域由于受液晶分子导向不良所造成的不规则暗纹(Dis-clination line)，可通过所述数据线遮挡而不可见。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (20)

  1. 一种像素结构，包括若干像素电极、若干数据线及若干扫描线，每一像素电极的相对两端分别设置有所述扫描线，所述数据线与所述扫描线垂直，其特征在于，每一像素电极包括至少两个子像素区域，所述数据线位于所述像素电极的下方，并位于相邻的两个子像素区域的交界处，所述像素电极在相邻的两个子像素区域的交界位置开设有若干缝隙，所述若干缝隙对准所述数据线并位于所述数据线的上方。
  2. 如权利要求1所述的像素结构，其特征在于，所述像素电极包括一第一子像素区域及一第二子像素区域，所述第一子像素区域与所述第二子像素区域关于所述数据线对称，所述第一子像素区域及所述第二子像素区域上均开设有若干缝隙，该若干缝隙将每个子像素区域分隔为若干分隔片，该若干缝隙与该若干分隔片依次交替排列分布。
  3. 如权利要求2所述的像素结构，其特征在于，所述第一子像素区域上的缝隙与所述第二子像素区域上对应的缝隙在所述数据线上方连通，并关于所述数据线对称，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在数据线上方连接，并关于该数据线对称，该数据线上方的第一子像素区域与第二子像素区域交界处形成了具有预定宽度且等间距交替排列的缝隙。
  4. 如权利要求2所述的像素结构，其特征在于，所述若干缝隙的开口的宽度均相同，所述若干分隔片的宽度均相同，该若干缝隙与该若干分隔片依次等间距交替排列分布。
  5. 如权利要求2所述的像素结构，其特征在于，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在所述数据线上方断开，所述数据线上方的像素电极沿着该数据线的长度方向形成了条状的开口，以减少所 述数据线与该数据线上方的像素电极重叠面积。
  6. 如权利要求1所述的像素结构，其特征在于，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
  7. 如权利要求6所述的像素结构，其特征在于，所述扫描线与构成所述像素共电极的材料位于同一金属层，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
  8. 如权利要求1所述的像素结构，其特征在于，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
  9. 如权利要求8所述的像素结构，其特征在于，构成所述像素共电极的材料与所述扫描线位于不同的金属层，该像素共电极跨过所述扫描线，并与所述像素电极存在部分重叠，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
  10. 如权利要求5所述的像素结构，其特征在于，当所述数据线上方的第一子像素区域与第二子像素区域交界处开设为所述缝隙或是设计为沿着所述数据线长度方向开设的开口时，则所述像素结构为非彩色滤光阵列，色阻制作于上基板的彩色滤光片侧；或者
    像素结构为非彩色滤光阵列，色阻制作于下基板的薄膜晶体管侧。
  11. 一种液晶显示器，其特征在于，所述液晶显示器包括：
    一扫描驱动电路，用于产生扫描信号；
    一数据驱动电路，用于产生灰度信号；及
    一像素结构，包括若干像素电极、若干数据线及若干扫描线，所述扫描线与所述扫描驱动电路电性连接以传送所述扫描信号，所述数据线与所述数据驱动电路电性连接以传送所述灰度信号，所述像素电极根据所述灰度信号驱动像素；其中，每一像素电极的相对两端分别设置有所述扫描线，所述数据线与所述扫描线垂直，每一像素电极包括至少两个子像素区域，所述数据线位于所述像素电极的下方，并位于相邻的两个子像素区域的交界处，所述像素电极在相邻的两个子像素区域的交界位置开设有若干缝隙，所述若干缝隙对准所述数据线并位于所述数据线的上方。
  12. 如权利要求11所述的液晶显示器，其特征在于，所述像素电极包括一第一子像素区域及一第二子像素区域，所述第一子像素区域与所述第二子像素区域关于所述数据线对称，所述第一子像素区域及所述第二子像素区域上均开设有若干缝隙，该若干缝隙将每个子像素区域分隔为若干分隔片，该若干缝隙与该若干分隔片依次交替排列分布。
  13. 如权利要求12所述的液晶显示器，其特征在于，所述第一子像素区域上的缝隙与所述第二子像素区域上对应的缝隙在所述数据线上方连通，并关于所述数据线对称，所述第一子像素区域上的分隔片与所述第二子像素区域上对应的分隔片在数据线上方连接，并关于该数据线对称，该数据线上方的第一子像素区域与第二子像素区域交界处形成了具有预定宽度且等间距交替排列的缝隙。
  14. 如权利要求12所述的液晶显示器，其特征在于，所述若干缝隙的开口的宽度均相同，所述若干分隔片的宽度均相同，该若干缝隙与该若干分隔片依次等间距交替排列分布。
  15. 如权利要求12所述的液晶显示器，其特征在于，所述第一子像素区 域上的分隔片与所述第二子像素区域上对应的分隔片在所述数据线上方断开，所述数据线上方的像素电极沿着该数据线的长度方向形成了条状的开口，以减少所述数据线与该数据线上方的像素电极重叠面积。
  16. 如权利要求11所述的液晶显示器，其特征在于，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
  17. 如权利要求16所述的液晶显示器，其特征在于，所述扫描线与构成所述像素共电极的材料位于同一金属层，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
  18. 如权利要求11所述的液晶显示器，其特征在于，所述像素结构还包括若干像素共电极，所述像素电极另外的相对两端分别设置有一像素共电极，每个像素共电极的相对两端与所述扫面线之间间隔一预设的距离，且所述像素共电极的延长线与所述扫描线垂直。
  19. 如权利要求18所述的液晶显示器，其特征在于，构成所述像素共电极的材料与所述扫描线位于不同的金属层，该像素共电极跨过所述扫描线，并与所述像素电极存在部分重叠，位于该像素电极相对两端的像素共电极均与所述数据线平行，并关于该数据线轴对称，且所述像素共电极位于该像素电极的下方。
  20. 如权利要求15所述的液晶显示器，其特征在于，当所述数据线上方的第一子像素区域与第二子像素区域交界处开设为所述缝隙或是设计为沿着所述数据线长度方向开设的开口时，则所述像素结构为非彩色滤光阵列，色阻制作于上基板的彩色滤光片侧；或者
    像素结构为非彩色滤光阵列，色阻制作于下基板的薄膜晶体管侧。
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