WO2017020328A1 - Procédé de fabrication de substrat de matrice - Google Patents

Procédé de fabrication de substrat de matrice Download PDF

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Publication number
WO2017020328A1
WO2017020328A1 PCT/CN2015/086476 CN2015086476W WO2017020328A1 WO 2017020328 A1 WO2017020328 A1 WO 2017020328A1 CN 2015086476 W CN2015086476 W CN 2015086476W WO 2017020328 A1 WO2017020328 A1 WO 2017020328A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
polysilicon
array substrate
fabricating
gate
Prior art date
Application number
PCT/CN2015/086476
Other languages
English (en)
Chinese (zh)
Inventor
李金磊
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Publication of WO2017020328A1 publication Critical patent/WO2017020328A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Abstract

L'invention concerne un procédé de fabrication d'un substrat de matrice, consistant à former une couche de protection contre la lumière (112), une couche de barrière d'ions (113), une couche tampon (114) et une couche de silicium non cristallin (115) sur un substrat (111), une matière première de préparation de la couche de silicium non cristallin (115) et une matière première mélangée contenant l'élément bore étant ajoutées dans une chambre de dépôt ; la couche de silicium non cristallin (115) est convertie en une couche de silicium polycristallin (116), la couche de silicium polycristallin (116) comportant des motifs, et une couche d'isolation de grille (117), une première couche de métal (118), une couche protectrice (121) et une deuxième couche de métal étant formées sur la couche de silicium polycristallin (116) à motifs.
PCT/CN2015/086476 2015-08-06 2015-08-10 Procédé de fabrication de substrat de matrice WO2017020328A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510477766.3A CN105161456A (zh) 2015-08-06 2015-08-06 一种阵列基板的制作方法
CN201510477766.3 2015-08-06

Publications (1)

Publication Number Publication Date
WO2017020328A1 true WO2017020328A1 (fr) 2017-02-09

Family

ID=54802271

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/086476 WO2017020328A1 (fr) 2015-08-06 2015-08-10 Procédé de fabrication de substrat de matrice

Country Status (2)

Country Link
CN (1) CN105161456A (fr)
WO (1) WO2017020328A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599568A (zh) * 2020-12-03 2021-04-02 福建华佳彩有限公司 一种激光切割的面板结构及其制备方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960815B (zh) * 2017-05-05 2020-02-28 武汉华星光电技术有限公司 一种制作阵列基板的方法
CN107393827A (zh) * 2017-06-20 2017-11-24 武汉华星光电技术有限公司 薄膜晶体管基板及其制造方法
CN112289807A (zh) * 2020-10-27 2021-01-29 武汉华星光电半导体显示技术有限公司 一种oled显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142525A1 (en) * 2001-01-26 2002-10-03 Hideto Ohnuma Method of manufacturing semiconductor device
US20040063257A1 (en) * 1998-12-28 2004-04-01 Fujitsu Limited CMOS-type semiconductor device and method of fabricating the same
US20050275038A1 (en) * 2004-06-14 2005-12-15 Yi-Chi Shih Indium oxide-based thin film transistors and circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101353284B1 (ko) * 2012-04-25 2014-01-21 엘지디스플레이 주식회사 액정 디스플레이 장치와 이의 제조방법
KR102206412B1 (ko) * 2012-12-27 2021-01-22 엘지디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터 제조 방법 및 박막 트랜지스터를 포함하는 표시 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040063257A1 (en) * 1998-12-28 2004-04-01 Fujitsu Limited CMOS-type semiconductor device and method of fabricating the same
US20020142525A1 (en) * 2001-01-26 2002-10-03 Hideto Ohnuma Method of manufacturing semiconductor device
US20050275038A1 (en) * 2004-06-14 2005-12-15 Yi-Chi Shih Indium oxide-based thin film transistors and circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599568A (zh) * 2020-12-03 2021-04-02 福建华佳彩有限公司 一种激光切割的面板结构及其制备方法

Also Published As

Publication number Publication date
CN105161456A (zh) 2015-12-16

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