WO2017152451A1 - Substrat de matrice en mode ffs et procédé de fabrication associé - Google Patents

Substrat de matrice en mode ffs et procédé de fabrication associé Download PDF

Info

Publication number
WO2017152451A1
WO2017152451A1 PCT/CN2016/078755 CN2016078755W WO2017152451A1 WO 2017152451 A1 WO2017152451 A1 WO 2017152451A1 CN 2016078755 W CN2016078755 W CN 2016078755W WO 2017152451 A1 WO2017152451 A1 WO 2017152451A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
region
semiconductor layer
insulating layer
common electrode
Prior art date
Application number
PCT/CN2016/078755
Other languages
English (en)
Chinese (zh)
Inventor
葛世民
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/116,514 priority Critical patent/US20170373101A1/en
Publication of WO2017152451A1 publication Critical patent/WO2017152451A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of display, and in particular to a curved liquid crystal display panel and a curved liquid crystal display device.
  • the active matrix driven LCD display technology utilizes the bipolar polarization characteristics of the liquid crystal, and controls the arrangement direction of the liquid crystal molecules by applying an electric field, thereby realizing the switching control of the traveling direction of the backlight optical path.
  • the LCD display mode can be divided into TN series modes.
  • VA series mode refers to applying a longitudinal electric field to liquid crystal molecules
  • IPS series mode refers to applying a transverse electric field to liquid crystal molecules.
  • the IPS series mode for the application of the transverse electric field, it can be divided into the IPS mode and the FFS mode.
  • Each pixel unit of the FFS display mode includes two upper and lower electrodes, that is, a pixel electrode and a common electrode, and the common electrode of the lower layer is flattened on the entire surface of the open area.
  • the FFS display mode has a high transmittance, wide viewing angle and low color shift, and is a widely used LCD display technology.
  • etch stop layer (ESL) structure of the TFT structure is widely used, which can effectively reduce the influence of external environmental factors and etch damage of the source and drain electrodes on the back channel.
  • ESL etch stop layer
  • the conventional FFS display mode array substrate manufacturing method of the ESL structure requires more mask times, which increases the complexity of the process and the production cost.
  • An object of the present invention is to provide an FFS mode array substrate and a manufacturing method thereof.
  • the conventional FFS display mode array substrate manufacturing method for solving the ESL structure in the prior art requires more mask times, increases the complexity of the process, and Technical issues of production costs.
  • the embodiment of the invention provides a method for fabricating an array substrate of an FFS mode, which comprises the following steps:
  • the base layer is provided with a gate electrode and a channel semiconductor layer;
  • a pixel electrode layer on the second insulating layer the pixel electrode layer being provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • a third insulating layer is deposited on the source, the drain, the pixel electrode, and the second insulating layer.
  • the step of forming a base layer includes:
  • a first insulating layer and a semiconductor layer on the glass substrate and the gate, the semiconductor layer being provided with a channel region, a common electrode region, and a third spacer region between the common electrode region and the channel region;
  • the second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer.
  • the channel semiconductor layer is provided with two doped regions respectively corresponding to the first via and the second via, and the trench is removed.
  • the step of the second photoresist layer on the semiconductor layer includes:
  • the step of forming a base layer includes:
  • a common electrode layer and a second metal layer are sequentially deposited on the glass substrate, the second metal layer is provided with a gate region, the common electrode layer is provided with a common electrode region, a TFT region, and a fourth interval between the common electrode region and the TFT region region;
  • the third photoresist layer and the second metal layer on the common electrode are sequentially removed, and the third photoresist layer on the gate is removed;
  • the second insulating layer is deposited on the channel semiconductor layer and the first insulating layer.
  • the second insulating layer and the third insulating layer each comprise silicon nitride and/or silicon dioxide.
  • the channel semiconductor layer comprises indium gallium zinc oxide.
  • the invention also provides an array substrate of an FFS mode, comprising:
  • the base layer is provided with a gate electrode and a channel semiconductor layer;
  • a second insulating layer deposited on the base layer, the first insulating layer and the second via hole exposing the channel semiconductor layer are formed on the second insulating layer;
  • a pixel electrode layer deposited on the second insulating layer, wherein the pixel electrode layer is provided with a pixel electrode;
  • a source and a drain the source and the drain being disposed on the pixel electrode layer
  • a third insulating layer disposed on the source, the drain, the pixel electrode, and the second insulating layer.
  • the base layer further includes:
  • the gate is disposed on the glass substrate
  • a first insulating layer disposed on the glass substrate and the gate
  • the semiconductor layer disposed on the first insulating layer, the semiconductor layer including a channel region and a common electrode region, the channel semiconductor layer being formed in a channel region of the semiconductor layer, in the semiconductor layer Semiconductor doping of the common electrode region forms a common electrode layer;
  • the second insulating layer is disposed on the channel semiconductor layer, the common electrode layer, and the first insulating layer.
  • the base layer further includes:
  • a common electrode layer disposed on the glass substrate, the gate being disposed on the common electrode layer;
  • a first insulating layer disposed on the common electrode layer, the gate electrode, and the glass substrate;
  • the channel semiconductor layer is disposed on the first insulating layer and above the gate, and the second insulating layer is deposited on the channel semiconductor layer and the first insulating layer.
  • the channel semiconductor layer comprises indium gallium zinc oxide.
  • the source and the drain are disposed on the pixel electrode layer, so that the source, the drain, and the pixel electrode can be simultaneously formed by a photomask during the manufacturing process, thereby shortening the process flow and improving The beneficial effects of production efficiency.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of an array substrate of an FFS mode according to the present invention
  • FIG. 2 is a schematic structural view of a second preferred embodiment of an array substrate of an FFS mode according to the present invention.
  • FIG. 3 is a flow chart of a first preferred embodiment of a method for fabricating an array substrate of an FFS mode according to the present invention
  • 4A-4I are schematic diagrams showing specific fabrication in a first preferred embodiment of a method for fabricating an array substrate of an FFS mode according to the present invention
  • 5A-5J are schematic diagrams showing specific fabrication in a first preferred embodiment of a method for fabricating an array substrate of an FFS mode according to the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of an FFS mode array substrate according to the present invention.
  • An FFS mode array substrate of the preferred embodiment includes: a glass substrate 11, a gate electrode 12, a semiconductor layer (not labeled in FIG. 1), a first insulating layer 14, a second insulating layer 20, and a pixel electrode layer 30, The source 41, the drain 42 and the third insulating layer 50.
  • the glass substrate 11, the gate electrode 12, the semiconductor layer (not labeled in FIG. 1), and the first insulating layer 14 constitute a base layer.
  • the gate electrode 12 is disposed on the glass substrate 11.
  • the first insulating layer 14 is disposed on the glass substrate 11 and the gate electrode 12
  • the semiconductor layer is disposed on the first insulating layer 14 .
  • the semiconductor layer is provided with a channel region, a common electrode region, and a third spacer region (not labeled) between the channel region and the common electrode region, the channel region forming a channel of the thin film transistor
  • the semiconductor layer 13 is located above the gate electrode 12.
  • the semiconductor layer of the common electrode region is formed by doping to form a common electrode layer 15, and the semiconductor layer of the third spacer region is removed by a photolithography process.
  • the second insulating layer 20 is disposed on the first insulating layer 14 , the common electrode layer 15 , and the channel semiconductor layer 13 .
  • a first via hole and a second via hole through which the channel semiconductor layer 13 leaks are formed on the second insulating layer 20 by photolithography.
  • the pixel electrode layer 30 is disposed on the second insulating layer 20.
  • the pixel electrode layer 30 is provided with a contact portion 30a at the thin film transistor region and a plurality of pixel electrodes on a side of the thin film transistor region.
  • the contact portion 30a passes through The first via and the second via are in contact with the channel semiconductor layer 13.
  • the source 41 and the drain 42 are both disposed on the contact portion 30a of the pixel electrode layer 30, and are in contact with the channel semiconductor layer 13 through the contact portion 30a, respectively.
  • the third insulating layer 50 is disposed on the second insulating layer 20, the source 41, the drain 42 and the pixel electrode layer 30.
  • the semiconductor layer is made of indium gallium zinc oxide
  • the channel semiconductor layer 13 is made of indium gallium zinc oxide. Of course, it is not limited thereto.
  • the first insulating layer 14 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the gate electrode 12 from the common electrode layer 15.
  • the first insulating layer 14 has a thickness of 100 nm to 300 nm.
  • the second insulating layer 20 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the pixel electrode layer 30 from the common electrode layer 15.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the third insulating layer 50 is made of silicon nitride. In the present embodiment, it is a flat layer, and is mainly used to protect the pixel electrode, the source 41, and the drain 42.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • the channel semiconductor layer 13 is further provided with two doped regions corresponding to the first via holes and the second via holes, respectively, in the doped region of the channel semiconductor layer 13 The doping is performed to convert the semiconductor of the region into a conductor, thereby having the effect of lowering the impedance of the channel semiconductor layer 13.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • the channel semiconductor layer 13 and the common electrode layer 15 in the same layer, it can be formed by a photomask and formed by doping the common electrode layer 15 in the common electrode region of the semiconductor layer, thereby further shortening Process flow and improved generation efficiency.
  • FIG. 2 is a schematic structural view of a second preferred embodiment of the FFS mode array substrate of the present invention.
  • the array substrate of the FFS mode of the preferred embodiment includes: a glass substrate 11, a gate electrode 12, a channel semiconductor layer 13, a common electrode layer 15, a first insulating layer 14, a second insulating layer 20, a pixel electrode layer 30, and a source 41.
  • the glass substrate 11, the gate electrode 12, the channel semiconductor layer 13, the common electrode layer 15, and the first insulating layer 14 constitute a base layer.
  • the common electrode layer 15 is disposed on the glass base 11
  • the gate electrode 12 is disposed on the common electrode layer 15
  • the first insulating layer 14 is disposed on the glass substrate 11 , the common electrode layer 15 , and the gate electrode Above the 12, the channel semiconductor layer 13 is disposed on the first insulating layer 14 and above the gate electrode 12.
  • the second insulating layer 20 is disposed on the first insulating layer 14 and the channel semiconductor layer 13. A first via hole and a second via hole through which the channel semiconductor layer 13 leaks are formed on the second insulating layer 20 by photolithography.
  • the pixel electrode layer 30 is disposed on the second insulating layer 20.
  • the pixel electrode layer 30 is provided with a contact portion 30a at the thin film transistor region and a plurality of pixel electrodes on a side of the thin film transistor region.
  • the contact portion 30a passes through The first via and the second via are in contact with the channel semiconductor layer 13.
  • the third insulating layer 50 is disposed on the second insulating layer 20, the source 41, the drain 42 and the pixel electrode layer 30.
  • the channel semiconductor layer 13 is made of indium gallium zinc oxide, which is of course not limited thereto.
  • the first insulating layer 14 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the gate electrode 12 from the common electrode layer 15.
  • the first insulating layer 14 has a thickness of 100 nm to 300 nm.
  • the second insulating layer 20 is made of silicon nitride and/or silicon dioxide and is mainly used to insulate the pixel electrode layer 30 from the common electrode layer 15.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the third insulating layer 50 is made of silicon nitride. In the present embodiment, it is a flat layer, and is mainly used to protect the pixel electrode, the source 41, and the drain 42.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • a photomask can be formed, so that the gate electrode 12 and the pixel electrode layer 30 can be simultaneously formed by a photomask during the fabrication process. It has the beneficial effect of shortening the process flow and improving production efficiency.
  • FIG. 3 is a flowchart of an FFS mode array substrate in a first preferred embodiment of the present invention, the method comprising the following steps:
  • the base layer is provided with a gate electrode and a channel semiconductor layer;
  • the pixel electrode layer is provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • S304 depositing a first metal layer on the pixel electrode layer, the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • step S301 it specifically includes the following sub-steps:
  • the second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer.
  • the material of the gate electrode 13 is a stacked combination of one or more of molybdenum, titanium, aluminum, copper, which is formed by physical vapor deposition deposition. As shown in FIG. 4A, the process goes to step S32.
  • the first insulating layer 14 is formed by depositing silicon nitride and/or silicon dioxide by chemical vapor deposition, and is mainly used for insulating the gate electrode 12 from the common electrode layer 15.
  • the first insulating layer 14 has a thickness of 100 nm to 300 nm.
  • the semiconductor layer 1315 is formed by indium gallium zinc oxide and deposited by physical vapor deposition. It is divided into a channel region 1A, a common electrode region 1B, and a third spacer region 1C between the common electrode region 1B and the channel region 1A. As shown in FIG. 4B, the process goes to step S33.
  • step S33 the second photoresist layer 100 is processed by a halftone mask process or a gray tone mask process to make the light of the region of the second photoresist layer 100 facing the third spacer region. Block removal. As shown in FIG. 4C, the process goes to step S34.
  • the semiconductor layer 1315 may be etched by a dry method or a wet method.
  • the PLASMARATMENT process may be performed using hydrogen gas or helium gas. As shown in FIG. 4D, the process goes to step S36.
  • step S36 when the second photoresist layer 100 on the channel semiconductor layer 13 is removed, a method of oxidizing the photoresist may be employed. As shown in FIG. 4E, the process goes to step S302.
  • step S302 when a second insulating layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulating layer of the base layer, it is made of silicon nitride and/or silicon dioxide, which is mainly used for the pixel electrode. Layer 30 and common electrode layer 15 are insulated.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the first via hole 20a and the via hole 20b expose the channel semiconductor layer 13, respectively. As shown in FIG. 4F, the process goes to step S303.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • the first metal layer 40 is formed by physical vapor deposition. As shown in FIG. 4G, the process goes to step S305.
  • step S305 the second photoresist layer is processed to remove the photoresist on the second photoresist layer and the third spacer region facing the region by using a halftone mask process or a gray mask process.
  • step S306 when the first metal layer 40 and the pixel electrode layer 30 are etched, wet etching may be employed to form the source 41 and the drain respectively in the source region and the drain region of the first metal layer 40.
  • the pole 42 forms a pixel electrode in the pixel electrode region of the pixel electrode layer 30.
  • step S307 when the first photoresist layer is removed, the first metal layer 40 on the pixel electrode may be removed by oxidizing and then removing the first photoresist layer.
  • the conventional techniques in the art may be used, and details are not described herein.
  • a structure as shown in FIG. 4H is formed, and the process proceeds to step S308.
  • the third insulating layer 50 is made of silicon nitride, which is a flat layer in the embodiment, and is mainly used to protect the pixel electrode, the source 41, and the drain 42. As shown in Figure 4I.
  • the channel semiconductor layer 13 is provided with two doped regions respectively corresponding to the first via hole 20a and the second via hole 20b, and the step S36 includes:
  • the impedance of the channel semiconductor layer can be reduced by this step.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • the channel semiconductor layer 13 and the common electrode layer 15 in the same layer, it can be formed by a photomask and formed by doping the common electrode layer 15 in the common electrode region of the semiconductor layer, thereby further shortening Process flow and improved generation efficiency.
  • the base layer is provided with a gate electrode and a channel semiconductor layer;
  • the pixel electrode layer is provided with a plurality of pixel electrode regions, and a first spacing region between adjacent two pixel electrode regions;
  • S304 depositing a first metal layer on the pixel electrode layer, the first metal layer is provided with a source region, a drain region, and a second spacer region between the source region and the drain region;
  • the step S301 specifically includes the following steps:
  • S351 sequentially depositing a common electrode layer and a second metal layer on the glass substrate, the second metal layer is provided with a gate region, the common electrode layer is provided with a common electrode region, a TFT region, and a portion between the common electrode region and the TFT region Four spaced areas;
  • the glass substrate 11, the gate electrode 12, the channel semiconductor layer 13, the common electrode layer 15, and the first insulating layer 14 constitute a base layer.
  • the second insulating layer 20 is deposited over the channel semiconductor layer 13 and the first insulating layer 14.
  • the common electrode layer 15 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, which is formed by physical vapor deposition. It has a thickness of 10 nm to 100 nm.
  • the second metal layer 12 is formed by physical vapor deposition, and the material is a stack combination of one or more of molybdenum, titanium, aluminum, and copper. As shown in FIG. 5A, the process goes to step S352.
  • step S352 the third photoresist layer 300 is processed by a halftone mask process or a gray tone mask process to remove the photoresist on the third photoresist layer and the region facing the fourth spacer region. As shown in FIG. 5B, the process goes to step S353.
  • step S353 when the second metal layer 120 and the common electrode layer 15 are etched, wet etching may be employed to form a common electrode in the common electrode region of the common electrode layer 15, and in the second metal layer 120.
  • the gate region forms a gate 12.
  • the process goes to step S354.
  • step S354 the third photoresist layer on the common electrode may be removed by first oxidizing and then removed, as shown in FIG. 5D.
  • etching may be employed.
  • FIG. 5E the process goes to step S355.
  • step S355 chemical vapor deposition is performed on the common electrode, the gate electrode and the glass substrate, and the first insulating layer 14 is deposited by chemical vapor deposition using silicon nitride and/or silicon dioxide. production.
  • the channel semiconductor layer 13 is formed by indium gallium zinc oxide and deposited by physical vapor deposition. As shown in FIG. 5G, the process goes to step S302.
  • step S302 when the second insulating layer 20 is deposited on the channel semiconductor layer 13 of the base layer and the first insulating layer 14, it is made of silicon nitride and/or silicon dioxide, which is mainly used for the pixel electrode layer. 30 is insulated from the common electrode layer 15.
  • the second insulating layer 20 has a thickness of 50 nm to 150 nm.
  • the first via hole 20a and the via hole 20b expose the channel semiconductor layer 13, respectively. As shown in FIG. 5H, the process goes to step S303.
  • the pixel electrode layer 30 is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer having a thickness of 10 nm to 100 nm.
  • step S304 the first metal layer is formed by physical vapor deposition. Go to step S305.
  • step S305 the first photoresist layer is processed to remove the photoresist on the first photoresist layer and the third spacer region facing the region by using a halftone mask process or a gray mask process.
  • step S306 when the first metal layer 40 and the pixel electrode layer 30 are etched, wet etching may be employed to form the source 41 and the drain respectively in the source region and the drain region of the first metal layer 40.
  • the pole 42 forms a pixel electrode in the pixel electrode region of the pixel electrode layer 30. As shown in FIG. 5I, the process goes to step S307.
  • step S307 when the first photoresist layer is removed, the first metal layer on the pixel electrode may be removed by oxidizing and then removing the first photoresist layer. Go to step S308.
  • the third insulating layer 50 is made of silicon nitride, which is a flat layer in the embodiment, and is mainly used to protect the pixel electrode, the source 41, and the drain 42. As shown in Figure 5J.
  • the source electrode 41 and the drain electrode 42 are disposed on the pixel electrode layer 30, so that the source electrode 41, the drain electrode 42 and the pixel electrode can be simultaneously formed by a photomask during the fabrication process. Shorten the process and increase the efficiency of production efficiency.
  • a photomask can be formed, so that the gate electrode 12 and the pixel electrode layer 30 can be simultaneously formed by a photomask during the fabrication process. It has the beneficial effect of shortening the process flow and improving production efficiency.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention a trait à un substrat de matrice en mode FFS et à un procédé de fabrication associé. Le substrat de matrice en mode FFS comprend : une couche de base ; une deuxième couche isolante (20) déposée sur la couche de base, un premier trou débouchant (20a) et un second trou débouchant (20b) étant pratiqués dans la deuxième couche isolante (20) ; une couche d'électrode de pixel (30) déposée sur ladite deuxième couche isolante (20), des électrodes de pixel se trouvant sur la couche d'électrode de pixel (30) ; une source (41) et un drain (42) ; et une troisième couche isolante (50) située sur la source (41), le drain (42), les électrodes de pixel et la deuxième couche isolante (20).
PCT/CN2016/078755 2016-03-11 2016-04-08 Substrat de matrice en mode ffs et procédé de fabrication associé WO2017152451A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/116,514 US20170373101A1 (en) 2016-03-11 2016-04-08 Ffs mode array substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610141337.3 2016-03-11
CN201610141337.3A CN105629598B (zh) 2016-03-11 2016-03-11 Ffs模式的阵列基板及制作方法

Publications (1)

Publication Number Publication Date
WO2017152451A1 true WO2017152451A1 (fr) 2017-09-14

Family

ID=56044688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/078755 WO2017152451A1 (fr) 2016-03-11 2016-04-08 Substrat de matrice en mode ffs et procédé de fabrication associé

Country Status (3)

Country Link
US (1) US20170373101A1 (fr)
CN (1) CN105629598B (fr)
WO (1) WO2017152451A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229297B (zh) * 2016-09-18 2019-04-02 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法
CN108646487B (zh) * 2018-05-15 2020-12-25 Tcl华星光电技术有限公司 Ffs型阵列基板的制作方法及ffs型阵列基板
CN111063695A (zh) * 2019-12-10 2020-04-24 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法
CN113985667B (zh) * 2021-10-12 2023-08-01 Tcl华星光电技术有限公司 阵列基板及其制备方法、液晶显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078843A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
US20090101908A1 (en) * 2007-10-17 2009-04-23 Hee-Young Kwack Liquid crystal display device and method of fabricating the same
CN102938394A (zh) * 2012-11-16 2013-02-20 京东方科技集团股份有限公司 显示装置、透反式薄膜晶体管阵列基板及其制作方法
CN103456745A (zh) * 2013-09-10 2013-12-18 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105226015A (zh) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100544004C (zh) * 2006-04-21 2009-09-23 北京京东方光电科技有限公司 一种tft lcd阵列基板及其制造方法
US9366922B2 (en) * 2012-02-07 2016-06-14 Shenzhen China Star Optoelectronics Technology Co., Ltd. Thin film transistor array and method for manufacturing the same
CN104617115A (zh) * 2015-03-02 2015-05-13 深圳市华星光电技术有限公司 Ffs型薄膜晶体管阵列基板及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078843A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
US20090101908A1 (en) * 2007-10-17 2009-04-23 Hee-Young Kwack Liquid crystal display device and method of fabricating the same
CN102938394A (zh) * 2012-11-16 2013-02-20 京东方科技集团股份有限公司 显示装置、透反式薄膜晶体管阵列基板及其制作方法
CN103456745A (zh) * 2013-09-10 2013-12-18 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105226015A (zh) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Also Published As

Publication number Publication date
CN105629598B (zh) 2018-12-11
CN105629598A (zh) 2016-06-01
US20170373101A1 (en) 2017-12-28

Similar Documents

Publication Publication Date Title
WO2012097564A1 (fr) Procédé de fabrication d'un transistor à couches autoalignées
WO2014169621A1 (fr) Transistor en couches minces et son procédé de fabrication
WO2019100455A1 (fr) Écran d'affichage à commande tactile flexible et procédé de fabrication associé
WO2017054250A1 (fr) Substrat matriciel de transistor en couches minces (tft) et son procédé de fabrication
WO2016119280A1 (fr) Transistor à film mince et son procédé de fabrication
WO2017152451A1 (fr) Substrat de matrice en mode ffs et procédé de fabrication associé
WO2020082426A1 (fr) Procédé de fabrication de transistor à couches minces, transistor à couches minces et panneau d'affichage
WO2017054191A1 (fr) Substrat de matrice et procédé de fabrication correspondant
WO2019019428A1 (fr) Substrat de matrice flexible à delo et son procédé de fabrication
WO2020134965A1 (fr) Procédé et dispositif de fabrication de substrat matriciel, et substrat matriciel
WO2018107554A1 (fr) Panneau d'affichage à delo et dispositif d'affichage à delo
WO2013116995A1 (fr) Substrat de matrice de transistors en couches minces et son procédé d'obtention
WO2019041543A1 (fr) Structure de transistor à couches minces et circuit d'attaque amoled
WO2019056517A1 (fr) Structure de transistor à couches minces et son procédé de fabrication
WO2017152450A1 (fr) Substrat de matrice en mode ffs et procédé de fabrication associé
WO2017008318A1 (fr) Panneau en réseau et son procédé de fabrication
WO2019047357A1 (fr) Panneau d'affichage à diodes électroluminescentes organiques et son procédé de fabrication
WO2014121469A1 (fr) Procédé de fabrication d'un transistor à couche mince et d'une unité de pixel pour ce dernier
WO2019029008A1 (fr) Transistor à couche mince et procédé de fabrication de transistor à couche mince, et panneau d'affichage à cristaux liquides
WO2020135052A1 (fr) Procédé de préparation d'une structure de substrat de réseau, substrat de réseau et panneau d'affichage
WO2017054258A1 (fr) Procédé de fabrication de substrat de réseau de transistor à couches minces, substrat de réseau de transistor à couches minces et dispositif d'affichage
WO2018032558A1 (fr) Substrat de réseau et procédé de fabrication associé
WO2017140015A1 (fr) Substrat matriciel de tft à double électrode de grille et procédé de fabrication de celui-ci
WO2018218712A1 (fr) Substrat de transistor à couches minces (tft) en polysilicium basse température et son procédé de fabrication
WO2019232820A1 (fr) Procédé de fabrication d'un substrat de matrice et dispositif d'affichage à cristaux liquides

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15116514

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16893099

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16893099

Country of ref document: EP

Kind code of ref document: A1