WO2019019428A1 - Substrat de matrice flexible à delo et son procédé de fabrication - Google Patents

Substrat de matrice flexible à delo et son procédé de fabrication Download PDF

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Publication number
WO2019019428A1
WO2019019428A1 PCT/CN2017/106625 CN2017106625W WO2019019428A1 WO 2019019428 A1 WO2019019428 A1 WO 2019019428A1 CN 2017106625 W CN2017106625 W CN 2017106625W WO 2019019428 A1 WO2019019428 A1 WO 2019019428A1
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WO
WIPO (PCT)
Prior art keywords
layer
gate insulating
interlayer dielectric
insulating layer
dielectric layer
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Application number
PCT/CN2017/106625
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English (en)
Chinese (zh)
Inventor
白思航
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019019428A1 publication Critical patent/WO2019019428A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present invention relates to the field of flexible display panels, and in particular to a flexible OLED array substrate and a method of fabricating the same.
  • Flexible OLED The display panel has become a hot topic in the next generation of display technology due to its advantages of thinness, flexibility, flexibility, and foldability.
  • Flexible OLED for flexible OLED display panels for better flexibility The array substrate replaces the ultra-thin metal sheet with a flexible material substrate to obtain a better flexibility.
  • the existing flexible OLED array substrate has many inorganic film layers, and the difference in stress between the inorganic film layers may cause the inorganic film layer to fall off and be flexible.
  • the warpage of the OLED array substrate which in turn affects the service life and stability of the flexible OLED display panel.
  • Simultaneous flexible OLED The organic film layer in the array substrate is also susceptible to crack formation after being bent a plurality of times, thereby destroying the structure of the device in the flexible OLED display panel. Therefore existing flexible OLED The display panel has poor stability and a short service life.
  • An object of the present invention is to provide a flexible OLED capable of improving the stability and service life of a corresponding flexible OLED display panel.
  • the array substrate and the manufacturing method thereof are used to solve the technical problem that the existing flexible OLED display panel has poor use stability and short service life.
  • Embodiments of the present invention provide a flexible OLED array substrate, including:
  • a barrier layer disposed on the flexible substrate for blocking external moisture and oxygen
  • a buffer layer disposed on the barrier layer
  • An active layer disposed on the buffer layer including a channel located in a middle portion of the active layer, a source doped layer on a side of the active layer, and a drain located on the other side of the active layer Polar doped layer
  • a first gate insulating layer disposed on the buffer layer and the active layer
  • a second gate insulating layer disposed on the first gate insulating layer and the first gate, wherein the second gate insulating layer is provided with a first through to the first gate insulating layer a gate insulating layer etching hole and a second gate insulating layer etching hole penetrating to the buffer layer;
  • first interlayer dielectric layer disposed on the second gate insulating layer and the second gate;
  • the first interlayer dielectric layer is provided with a through-first gate insulating layer Etching a first interlayer dielectric layer etching hole and a second interlayer dielectric layer etching hole penetrating to the buffer layer;
  • a second interlayer dielectric layer disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer is provided with a source electrode penetrating to the source doping layer and passing through a drain electrode of the drain doped layer;
  • a passivation layer disposed on the second interlayer dielectric layer, the passivation layer being provided with a metal anode penetrating to the source electrode;
  • a pixel defining layer disposed on the passivation layer
  • a projection of the first interlayer dielectric layer etched hole on a plane of the flexible substrate covers a projection of the etched hole of the first gate insulating layer on a plane of the flexible substrate;
  • a projection of the second interlayer dielectric layer etched hole on a plane of the flexible substrate covers a projection of the etched hole of the second gate insulating layer on a plane of the flexible substrate;
  • a projection of the first gate on a plane of the flexible substrate and a projection of the second gate on a plane of the flexible substrate substantially coincide.
  • each of the pixel regions on the second gate insulating layer is provided with at least two first gate insulating layer etching holes and at least two second gate insulating layer etching holes.
  • At least two of the first gate insulating layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second gate insulating layer etch holes are symmetrically disposed on the channel On both sides.
  • each pixel region on the first interlayer dielectric layer is provided with at least two of the first interlayer dielectric layer etch holes and at least two of the second interlayer dielectric layers. Etched holes.
  • At least two of the first interlayer dielectric layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second interlayer dielectric layer etch holes are symmetrically disposed on the Both sides of the channel.
  • Embodiments of the present invention provide a flexible OLED array substrate, including:
  • a barrier layer disposed on the flexible substrate for blocking external moisture and oxygen
  • a buffer layer disposed on the barrier layer
  • An active layer disposed on the buffer layer including a channel located in a middle portion of the active layer, a source doped layer on a side of the active layer, and a drain located on the other side of the active layer Polar doped layer
  • a first gate insulating layer disposed on the buffer layer and the active layer
  • a second gate insulating layer disposed on the first gate insulating layer and the first gate, wherein the second gate insulating layer is provided with a first through to the first gate insulating layer a gate insulating layer etching hole and a second gate insulating layer etching hole penetrating to the buffer layer;
  • first interlayer dielectric layer disposed on the second gate insulating layer and the second gate;
  • the first interlayer dielectric layer is provided with a through-first gate insulating layer Etching a first interlayer dielectric layer etching hole and a second interlayer dielectric layer etching hole penetrating to the buffer layer;
  • a second interlayer dielectric layer disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer is provided with a source electrode penetrating to the source doping layer and passing through a drain electrode of the drain doped layer;
  • a passivation layer disposed on the second interlayer dielectric layer, the passivation layer being provided with a metal anode penetrating to the source electrode;
  • a pixel defining layer is disposed on the passivation layer.
  • each of the pixel regions on the second gate insulating layer is provided with at least two first gate insulating layer etching holes and at least two second gate insulating layer etching holes.
  • At least two of the first gate insulating layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second gate insulating layer etch holes are symmetrically disposed on the channel On both sides.
  • each pixel region on the first interlayer dielectric layer is provided with at least two of the first interlayer dielectric layer etch holes and at least two of the second interlayer dielectric layers. Etched holes.
  • At least two of the first interlayer dielectric layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second interlayer dielectric layer etch holes are symmetrically disposed on the Both sides of the channel.
  • a projection of the first interlayer dielectric layer etched hole on a plane of the flexible substrate covers a projection of the first gate insulating layer etched hole on a plane of the flexible substrate;
  • the projection of the interlayer dielectric etched hole on the plane of the flexible substrate covers the projection of the etched hole of the second gate insulating layer on the plane of the flexible substrate.
  • a projection of the first gate on a plane of the flexible substrate and a projection of the second gate on a plane of the flexible substrate substantially coincide.
  • the embodiment of the invention further provides a method for fabricating a flexible OLED array substrate, which includes:
  • An active layer is formed on the buffer layer, and a channel in a middle portion of the active layer, a source doped layer on one side of the active layer, and a drain doping on the other side of the active layer are formed Floor;
  • a pixel definition layer is formed on the passivation layer.
  • each of the pixel regions on the second gate insulating layer is provided with at least two first gate insulating layer etching holes and at least two second gate insulating layer etching holes.
  • At least two of the first gate insulating layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second gate insulating layer etch holes are symmetrically disposed at the Said on both sides of the channel.
  • each of the pixel regions on the first interlayer dielectric layer is provided with at least two of the first interlayer dielectric layer etching holes and at least two of the second interlayer layers.
  • the electric layer etches the holes.
  • At least two of the first interlayer dielectric layer etch holes are symmetrically disposed on both sides of the channel; at least two of the second interlayer dielectric layer etch holes are symmetrically disposed On both sides of the channel.
  • a projection of the first interlayer dielectric layer etched hole on a plane of the flexible substrate covers a projection of the etched hole of the first gate insulating layer on a plane of the flexible substrate;
  • the projection of the second interlayer dielectric layer etched hole on the plane of the flexible substrate covers the projection of the etched hole of the second gate insulating layer on the plane of the flexible substrate.
  • Flexible OLED of the present invention The array substrate and the manufacturing method thereof, the first gate insulating layer etching hole and the second gate insulating layer etching hole on the second gate insulating layer; and the first interlayer dielectric layer on the first interlayer dielectric layer Etching holes and the arrangement of the etching holes of the second interlayer dielectric layer; improving the corresponding flexibility
  • the stability and service life of the OLED display panel are solved; the technical problems of the existing flexible OLED display panel with poor stability and short service life are solved.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a flexible OLED array substrate of the present invention
  • FIG. 2 is a flow chart of a preferred embodiment of a method for fabricating a flexible OLED array substrate of the present invention
  • 3A to 3F are flexible OLEDs of the present invention
  • FIG. 1 is a flexible OLED of the present invention.
  • a schematic structural view of a preferred embodiment of the array substrate; the flexible OLED array substrate 100 of the preferred embodiment includes a flexible substrate 110, a barrier layer 120, a buffer layer 130, and an active layer 140.
  • the barrier layer 120 is disposed on the flexible substrate 110 for blocking external moisture and oxygen; the buffer layer 130 is disposed on the barrier layer 120; an active layer 140 is disposed on the buffer layer 130, including a channel 141 in the middle of the active layer 140, a source doping layer 142 on the side of the active layer 140, and an active layer a drain doping layer 143 on the other side; a first gate insulating layer 150 disposed on the buffer layer 130 and the active layer 140; and a first gate 160 disposed on the first gate insulating layer 150
  • the second gate insulating layer 170 is disposed on the first gate insulating layer 150 and the first gate 160, and the second gate insulating layer 170 is disposed on the first gate insulating layer 150.
  • the second gate electrode 180 is disposed on the second gate insulating layer 170;
  • Electric layer 190 is disposed on the second gate insulating layer 170 and the second gate 180;
  • the first interlayer dielectric layer 190 is provided with a first interlayer dielectric layer penetrating through the first gate insulating layer etching hole 171 Eclipse hole And a second interlayer dielectric layer etch hole 192 penetrating to the buffer layer 130;
  • the second interlayer dielectric layer 1A0 is disposed on the first interlayer dielectric layer 190, and the second interlayer dielectric layer 1A0
  • a source electrode 1A2 penetrating through the source doping layer 142 and a drain electrode 1A1 penetrating the drain doping layer 143 are disposed thereon; and
  • a passivation layer 1B0 is disposed on the second interlayer dielectric
  • the material of the flexible substrate 110 is PI (polyimide) or PET (polyethylene terephthalate).
  • the material of the barrier layer 120 and the buffer layer 130 is SiN x , SiO 2 or a combination of the above materials.
  • the material of the first gate 160 and the second gate 180 is metallic molybdenum (Mo).
  • the material of the first gate insulating layer 150 and the second gate insulating layer 170 is SiN x , SiO 2 or a combination of the above materials.
  • the thickness of the buffer layer 130 is about 4000 angstroms
  • the thickness of the first gate insulating layer 150 is about 1000 angstroms
  • the thickness of the second gate insulating layer 170 is about 1200 angstroms
  • the thickness of the first interlayer dielectric layer 190 is about It is 3000 angstroms.
  • each pixel region on the second gate insulating layer 170 is provided with at least two first gate insulating layer etching holes 171 And at least two second gate insulating layer etching holes 172.
  • the pixel area here refers to an independent pixel unit that can be driven separately.
  • At least two first gate insulating layer etch holes 171 are symmetrically disposed on the channel 141
  • at least two second gate insulating layer etching holes 172 are symmetrically disposed on both sides of the channel 141.
  • each pixel region of the first interlayer dielectric layer 190 is provided with at least two first interlayer dielectric layer etching holes 191. And at least two second interlayer dielectric layers etch holes 192. At least two first interlayer dielectric layer etch holes 191 are disposed on both sides of the channel 141, and at least two second interlayer dielectric layer etch holes 192 are symmetrically disposed in the channel On both sides of the 141.
  • the projection of the first interlayer dielectric layer etch hole 191 on the plane of the flexible substrate 110 covers the first gate insulating layer etched hole 171 Projection on the plane of the flexible substrate 110.
  • the second interlayer dielectric layer etching hole 192 is projected on the plane of the flexible substrate 110 to cover the second gate insulating layer etching hole 172 on the flexible substrate 110 Projection of the plane in which it is located.
  • the first gate insulating layer etching hole 171 and the second gate insulating layer etching hole 172 may be in the first gate insulating layer 150, the second gate insulating layer 170, and the buffer layer 130.
  • the metal material of the second gate 180 is introduced thereon.
  • the first interlayer dielectric layer etching hole 191 and the second interlayer dielectric layer etching hole 192 may be in the first interlayer dielectric layer 190 and the first gate insulating layer 150.
  • the second gate insulating layer 170 and the organic material of the second interlayer dielectric layer 1A0 are introduced on the buffer layer 130.
  • the stress between the inorganic film layers prevents the inorganic film layers such as the first gate insulating layer 150, the second gate insulating layer 170, and the buffer layer 130 from falling off or warping. Simultaneous flexible OLED When the display panel is bent, the radius of curvature can be reduced to obtain a better flexible display effect.
  • the first interlayer dielectric layer etching hole 191 and the first gate insulating layer etching hole 171 of the preferred embodiment Corresponding to the position of the second interlayer dielectric layer etching hole 192 and the second gate insulating layer etching hole 172, so that the first interlayer dielectric layer etching hole can be completed by using the same mask.
  • the array substrate passes through the first gate insulating layer etching hole and the second gate insulating layer etching hole on the second gate insulating layer; and the first interlayer dielectric layer etching hole on the first interlayer dielectric layer and The arrangement of the second interlayer dielectric layer etching hole; the corresponding flexibility is improved The stability and service life of OLED display panels.
  • FIG. 2 is a flexible OLED of the present invention.
  • Step S201 providing a flexible substrate
  • the material of the flexible substrate is PI (Polyimide, Polyimide) or PET ( Polyethylene terephthalate, polyterephthalic plastic).
  • Step S202 forming a barrier layer on the flexible substrate
  • the material of the barrier layer is SiN x , SiO 2 or a combination of the above.
  • Step S203 forming a buffer layer on the barrier layer
  • the material of the barrier layer is SiN x , SiO 2 or a combination of the above materials, and the buffer layer has a thickness of about 4000 angstroms.
  • Step S204 Forming an active layer on the buffer layer, and forming a channel in the middle of the active layer, a source doped layer on the active layer side, and a drain doped layer on the other side of the active layer;
  • Step S205 forming a first gate insulating layer on the buffer layer and the active layer
  • the material of the first gate insulating layer is SiN x , SiO 2 or a combination of the above materials; the thickness of the first gate insulating layer is about 1000 ⁇ .
  • Step S206 providing a first gate on the first gate insulating layer
  • the material of the first gate is metal molybdenum (Mo).
  • Step S207 forming a second gate insulating layer on the first gate insulating layer and the first gate;
  • the material of the second gate insulating layer is SiN x , SiO 2 or a combination of the above materials; the thickness of the second gate insulating layer is about 1200 ⁇ . As shown in Figure 3A.
  • Step S208 Etching the first gate insulating layer etching hole penetrating to the first gate insulating layer and the second insulating layer etching hole penetrating to the buffer layer on the second gate insulating layer;
  • Each of the pixel regions on the second gate insulating layer is provided with at least two first gate insulating layer etching holes and at least two second gate insulating layer etching holes.
  • the pixel area here refers to an independent pixel unit that can be driven separately.
  • At least two first gate insulating layer etch holes are symmetrically disposed on both sides of the channel, and at least two second gate insulating layer etch holes are symmetrically disposed on both sides of the channel. As shown 3B is shown.
  • Step S209 forming a second gate on the second gate insulating layer
  • the material of the second gate is metal molybdenum (Mo).
  • Mo metal molybdenum
  • Step S210 forming a first interlayer dielectric layer on the second gate insulating layer and the second gate;
  • the first interlayer dielectric layer has a thickness of about 3000 angstroms. As shown in Figure 3D.
  • Step S211 Etching a first interlayer dielectric layer etch hole penetrating through the first gate insulating layer etch hole and a second interlayer dielectric layer etch hole penetrating to the buffer layer on the first interlayer dielectric layer ;
  • Each pixel region of the first interlayer dielectric layer is provided with at least two first interlayer dielectric layer etch holes and at least two second interlayer dielectric layer etch holes. At least two first interlayer dielectric layer etch holes are symmetrically disposed on both sides of the channel, and at least two second interlayer dielectric layer etch holes are symmetrically disposed on both sides of the channel.
  • the projection of the first interlayer dielectric etch hole on the plane of the flexible substrate covers the projection of the etched hole of the first gate insulating layer on the plane of the flexible substrate.
  • the projection of the second interlayer dielectric layer etched hole on the plane of the flexible substrate covers the projection of the etched hole of the second gate insulating layer on the plane of the flexible substrate, as shown in the figure 3E is shown.
  • Step S212 fabricating a second interlayer dielectric layer on the first interlayer dielectric layer; as shown in FIG. 3F.
  • Step S213 Etching a source electrode that penetrates the source doping layer and a drain electrode that penetrates the drain doping layer on the second interlayer dielectric layer;
  • Step S214 forming a passivation layer on the second interlayer dielectric layer
  • Step S215 etching a metal anode penetrating to the source electrode on the passivation layer
  • Step S216 forming a pixel definition layer on the passivation layer, as shown in FIG.
  • a flexible OLED display panel structure such as a light-emitting structure, a cathode, and a protective layer to form a complete flexible OLED display panel.
  • Flexible OLED of the present invention The array substrate and the manufacturing method thereof, the first gate insulating layer etching hole and the second gate insulating layer etching hole on the second gate insulating layer; and the first interlayer dielectric layer on the first interlayer dielectric layer Etching holes and the arrangement of the etching holes of the second interlayer dielectric layer; improving the corresponding flexibility
  • the stability and service life of the OLED display panel are solved; the technical problems of the existing flexible OLED display panel with poor stability and short service life are solved.

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Abstract

L'invention concerne un substrat de matrice flexible à DELO et son procédé de fabrication. Le substrat de matrice flexible à DELO comprend un substrat flexible (110), une couche de barrière (120), une couche tampon (130), une couche active (140), une première couche d'isolation de grille (150), une première grille (160), une deuxième couche d'isolation de grille (170), une deuxième grille (180), un premier diélectrique intercouche (ILD) (190), un deuxième ILD (1A0), une couche de passivation (1B0), et une couche de définition de pixels (1C0).
PCT/CN2017/106625 2017-07-25 2017-10-18 Substrat de matrice flexible à delo et son procédé de fabrication WO2019019428A1 (fr)

Applications Claiming Priority (2)

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CN201710609768.2A CN107564941B (zh) 2017-07-25 2017-07-25 柔性oled阵列基板及其制作方法
CN201710609768.2 2017-07-25

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CN108008583B (zh) * 2017-12-04 2020-10-16 武汉华星光电半导体显示技术有限公司 柔性显示器件及其制备方法
CN109166880A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN109065616B (zh) * 2018-08-06 2022-01-04 武汉华星光电半导体显示技术有限公司 柔性显示面板及制造方法
CN109065583B (zh) * 2018-08-06 2020-10-16 武汉华星光电半导体显示技术有限公司 柔性显示面板的制造方法及柔性显示面板
CN109148481B (zh) * 2018-08-21 2020-09-01 武汉华星光电半导体显示技术有限公司 一种柔性阵列基板及其制作方法
KR102620972B1 (ko) * 2018-10-23 2024-01-05 삼성디스플레이 주식회사 디스플레이 장치
US11495620B2 (en) * 2019-11-26 2022-11-08 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel, fabrication method thereof, and display device
CN111755624A (zh) * 2020-06-24 2020-10-09 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

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