WO2017015992A1 - 显示面板及薄膜晶体管阵列基板 - Google Patents

显示面板及薄膜晶体管阵列基板 Download PDF

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Publication number
WO2017015992A1
WO2017015992A1 PCT/CN2015/086814 CN2015086814W WO2017015992A1 WO 2017015992 A1 WO2017015992 A1 WO 2017015992A1 CN 2015086814 W CN2015086814 W CN 2015086814W WO 2017015992 A1 WO2017015992 A1 WO 2017015992A1
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Prior art keywords
layer
disposed
sub
signal line
insulating layer
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Ceased
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PCT/CN2015/086814
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English (en)
French (fr)
Inventor
陈归
薛景峰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/780,332 priority Critical patent/US10180611B2/en
Publication of WO2017015992A1 publication Critical patent/WO2017015992A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a thin film transistor array substrate.
  • M3 touch sensing line layer
  • a display panel comprising: a color filter substrate; a liquid crystal layer; and a thin film transistor array substrate, the thin film transistor array substrate comprising: a pixel region; and a fan-out region, the fan
  • the thin film transistor array substrate includes: a substrate; a light blocking layer, the light blocking layer is disposed on the substrate; a buffer layer, the buffer layer is disposed on the substrate and the a light blocking layer; a polysilicon layer, the polysilicon layer is disposed on the buffer layer; a first insulating layer, the first insulating layer is disposed on the buffer layer and the polysilicon layer; a scan line a layer, the scan line layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer and the scan line layer; a data line layer, The data line layer is disposed on the second insulating layer, and the data line layer is connected to the polysilicon layer through a first via hole; a third insulating layer
  • a portion of the touch sensing line layer located in the second sub-area bypasses the groove from the bottom of the groove through the data line layer and the scan line layer.
  • the scan line layer includes: a first signal line array, the first signal line array is disposed in the first sub-area and the second sub-area, and located in the second sub-area The first signal line array is located below the groove in a first direction;
  • the data line layer includes: a second signal line array, the second signal line array is disposed in the first sub a region, and the second signal line array is connected to the first signal line array through a second through hole, the second through hole is located in the first sub-area, wherein the second through hole is disposed in the In the second insulating layer
  • the touch sensing line layer includes: a third signal line array, the third signal line array is disposed in the first sub-area, and the third signal line array passes through the third pass a hole is connected to the second signal line array, the third through hole is located in the first sub-area, wherein the third through hole is disposed in the third insulating layer; wherein the first direction Is perpendicular to the plane in which the substrate is located and directed from the substrate Direction
  • the first signal line array includes: at least one first sub-signal line; and at least one second sub-signal line;
  • the data line layer further includes: a fourth signal line array, the The fourth signal line array is disposed in the second sub-area, and the fourth signal line array is connected to the second sub-signal line through a fourth through hole; wherein the fourth through hole is located in the second sub-area
  • the fourth via hole is disposed in the second insulating layer.
  • a boundary of the groove is located at a boundary between the first sub-region and the second sub-region.
  • a display panel comprising: a color filter substrate; a liquid crystal layer; and a thin film transistor array substrate, the thin film transistor array substrate comprising: a pixel region; and a fan-out region, the fan a recessed portion;
  • the thin film transistor array substrate comprises: a substrate; a light blocking layer, the light blocking layer is disposed on the substrate; a buffer layer, the buffer layer is disposed at the On the substrate and the light blocking layer; a polysilicon layer, the polysilicon layer is disposed on the buffer layer; a first insulating layer, the first insulating layer is disposed on the buffer layer and the polysilicon layer a scan line layer, the scan line layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer and the scan line layer; a data line layer, the data line layer is disposed on the second insulating layer, and the data line layer is connected to the polysilicon layer through a first via; a third insul
  • the fan-out area includes: a first sub-area; and a second sub-area; wherein the groove is disposed at the third insulating layer, and the groove is located at the In the second sub-area.
  • a portion of the touch sensing line layer located in the second sub-area bypasses the groove from the bottom of the groove through the data line layer and the scan line layer.
  • the scan line layer includes: a first signal line array, the first signal line array is disposed in the first sub-area and the second sub-area, and located in the second sub-area The first signal line array is located below the groove in a first direction;
  • the data line layer includes: a second signal line array, the second signal line array is disposed in the first sub a region, and the second signal line array is connected to the first signal line array through a second through hole, the second through hole is located in the first sub-area, wherein the second through hole is disposed in the In the second insulating layer
  • the touch sensing line layer includes: a third signal line array, the third signal line array is disposed in the first sub-area, and the third signal line array passes through the third pass a hole is connected to the second signal line array, the third through hole is located in the first sub-area, wherein the third through hole is disposed in the third insulating layer; wherein the first direction Is perpendicular to the plane in which the substrate is located and directed from the substrate Direction
  • the first signal line array includes: at least one first sub-signal line; and at least one second sub-signal line;
  • the data line layer further includes: a fourth signal line array, the The fourth signal line array is disposed in the second sub-area, and the fourth signal line array is connected to the second sub-signal line through a fourth through hole; wherein the fourth through hole is located in the second sub-area
  • the fourth via hole is disposed in the second insulating layer.
  • a boundary of the groove is located at a boundary between the first sub-region and the second sub-region.
  • the groove is located in the third insulating layer in the fan-out region.
  • a thin film transistor array substrate comprising: a pixel region; and a fan-out region, wherein the fan-out region has a recess; wherein the thin film transistor array substrate comprises: a substrate; a light blocking layer, the light blocking layer is disposed on the substrate; a buffer layer, the buffer layer is disposed on the substrate and the light blocking layer; a polysilicon layer, the polysilicon layer is disposed on the a buffer layer; a first insulating layer, the first insulating layer is disposed on the buffer layer and the polysilicon layer; a scan line layer, the scan line layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer and the scan line layer; a data line layer, the data line layer is disposed on the second insulating layer, and the The data line layer is connected to the polysilicon layer through a first via; a third insulating layer, the third insulating layer is disposed on the second insulating layer
  • the fan-out region includes: a first sub-region; and a second sub-region; wherein the groove is disposed at the third insulating layer, and the groove is located In the second sub-area.
  • a portion of the touch sensing line layer located in the second sub-region bypasses the groove from the bottom of the groove through the data line layer and the scan line layer .
  • the scan line layer includes: a first signal line array, the first signal line array is disposed in the first sub-area and the second sub-area, in the second The first signal line array in the sub-area is located below the groove in the first direction;
  • the data line layer includes: a second signal line array, the second signal line array is disposed in the first a sub-area, and the second signal line array is connected to the first signal line array through a second through hole, the second through hole is located in the first sub-area, wherein the second through hole is disposed
  • the touch sensing line layer includes: a third signal line array, the third signal line array is disposed in the first sub-area, and the third signal line array passes through a third via hole is connected to the second signal line array, the third via hole is located in the first sub-region, wherein the third via hole is disposed in the third insulating layer;
  • One direction is perpendicular to a plane in which the substrate is located and from the base Pointing direction of the
  • the first signal line array includes: at least one first sub-signal line; and at least one second sub-signal line;
  • the data line layer further includes: a fourth signal line array, The fourth signal line array is disposed in the second sub-area, and the fourth signal line array is connected to the second sub-signal line through a fourth through hole; wherein the fourth through hole is located in the second a sub-region, the fourth via hole being disposed in the second insulating layer.
  • a boundary of the groove is located at a boundary between the first sub-region and the second sub-region.
  • the groove is located in the third insulating layer in the fan-out region.
  • the present invention is advantageous for avoiding metal residue in the boundary of the trench region in the third insulating layer due to deposition of traces in the touch sensing line layer, thereby effectively preventing the fan.
  • FIG. 1 is a schematic view showing the occurrence of metal residue in a groove of a fan-out region in a conventional thin film transistor array substrate
  • Figure 2 is a partial enlarged view of Figure 1;
  • FIG. 3 is a cross-sectional view showing a display region of a thin film transistor array substrate of the present invention.
  • FIG. 4 is a plan view of a fan-out region of a thin film transistor array substrate of the present invention.
  • Figure 5 is a schematic view of the A-A' section of Figure 4.
  • Figure 6 is a schematic view of the section B-B' in Figure 4.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel, etc.
  • TFT-LCD Thin Film Transistor Liquid
  • LCD Thin Film Transistor Liquid
  • the display panel of the present invention includes a color filter substrate, a liquid crystal layer, and a thin film transistor array substrate.
  • the color filter substrate and the thin film transistor array substrate are superimposed and integrated, and the liquid crystal layer is disposed between the color filter substrate and the thin film transistor array substrate.
  • FIG. 3 is a cross-sectional view showing a display region of a thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate includes a pixel area and a fan-out area, and the fan-out area has a groove. Specifically, a groove is provided in the third insulating layer (planarization layer) 309 in the fan-out region.
  • the thin film transistor array substrate includes a substrate 301, a light blocking layer 302, a buffer layer 303, a polysilicon layer 304, a first insulating layer 305, a scan line layer 306, a second insulating layer 307, and a data line layer 308.
  • the light blocking layer 302 is disposed on the substrate 301.
  • the buffer layer 303 is disposed on the substrate 301 and the light blocking layer 302.
  • the polysilicon layer 304 is disposed on the buffer layer 303.
  • the first insulating layer 305 is disposed on the buffer layer 303 and the polysilicon layer 304.
  • the scan line layer 306 is disposed on the first insulating layer 305.
  • the second insulating layer 307 is disposed on the first insulating layer 305 and the scan line layer 306.
  • the data line layer 308 is disposed on the second insulating layer 307, and the data line layer 308 is connected to the polysilicon layer 304 through the first via 315.
  • the third insulating layer 309 is disposed on the second insulating layer 307 and the data line layer 308.
  • the common line layer 310 is disposed on the third insulating layer 309.
  • a fifth insulating layer 311 is disposed on the common line layer 310.
  • the touch sensing line layer 312 is disposed on the fifth insulating layer 311.
  • the fourth insulating layer 313 is disposed on the touch sensing line layer 312.
  • the pixel electrode layer 314 is disposed on the fourth insulating layer 313.
  • FIG. 4 is a plan view of a fan-out area of the thin film transistor array substrate of the present invention
  • FIG. 5 is a schematic view of the AA' cross section of FIG. 4
  • FIG. 6 is a B-B of FIG. 'Schematic illustration of the section.
  • the fan-out area includes a first sub-area 401 and a second sub-area 402.
  • the groove is disposed at the third insulating layer 309, and the groove is located in the second sub-region 402, the boundary 403 of the groove is located in the first sub-region 401 and the The junction of the second sub-area 402.
  • a portion of the touch sensing line layer 312 located in the second sub-region 402 is bypassed from the bottom of the groove by the data line layer 308 and the scan line layer 306. Groove.
  • the scan line layer 306 includes a first signal line array 306.
  • the first signal line array 306 is disposed in the first sub-area 401 and the second sub-area 402, and the first signal line array 306 located in the second sub-area 402 is in the groove Below the first direction.
  • the data line layer 308 includes a second signal line array 3081.
  • the second signal line array 3081 is disposed in the first sub-area 401, and the second signal line array 3081 is connected to the first signal line array 306 through a second through hole 405, the second through hole 405 is located in the first sub-region 401, wherein the second via 405 is disposed in the second insulating layer 307.
  • the touch sensing line layer 312 includes a third signal line array 309.
  • the third signal line array 309 is disposed in the first sub-area 401, and the third signal line array 309 is connected to the second signal line array 3081 through a third through hole 404, the third through hole 404
  • the first sub-region 401 is disposed in the third insulating layer 309.
  • the first direction is a direction perpendicular to a plane where the substrate 301 is located and directed from the substrate 301 to the pixel electrode layer 314.
  • the first signal line array 306 includes a first sub-signal line 3061 and a second sub-signal line 3062.
  • the data line layer 308 also includes a fourth signal line array 3082.
  • the fourth signal line array 3082 is disposed in the second sub-area 402, and the fourth signal line array 3082 is connected to the second sub-signal line 3062 through the fourth through hole 406.
  • the fourth via 406 is located in the second sub-region 402, and the fourth via 406 is disposed in the second insulating layer 307.
  • the grooved region of the third insulating layer 309 of the fan-out region adopts an M1 trace (the trace in the scan line layer 306). Because the M1 trace is located below the third insulating layer 309, the traces in the fan-out area can be taken out from the trench area, and then extended through the second insulating layer 307.
  • the hole jumper is connected to the M2 trace (the trace in the data line layer 308), and then connected to the M3 trace through the reaming jumper in the third insulating layer 309 (the touch sensing layer Traces in 312) to pass signals.

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Abstract

一种显示面板及薄膜晶体管阵列基板，薄膜晶体管阵列基板包括像素区和扇出区，扇出区处具有凹槽；薄膜晶体管阵列基板包括：基板（301）；挡光层（302）；缓冲层（303）；多晶硅层（304）；第一绝缘层（305）；扫描线层（306）；第二绝缘层（307）；数据线层（308）；第三绝缘层（309）；公共线层（310）；触控感应线层（312）；第四绝缘层（313）；像素电极层（314），可以防止线路短路。

Description

显示面板及薄膜晶体管阵列基板 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板及薄膜晶体管阵列基板。
 背景技术
传统的显示面板（例如，LTPS-LCD（Low Temperature Poly-Silicon Liquid Crystal Display，低温多晶硅液晶显示面板））一般采用M3（触控感应线层）走线来作为扇出区的走线，在所述显示面板的制作过程中，由于平坦化层较厚，因此在所述平坦化层挖槽区域经常会出现曝光后残留的光阻，这会导致M3层中的部分金属残留，如图1和图2所示，而残留的金属极易会导致扇出区中的M3走线短路，这会影响所述显示面板的触控感应效果。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板及薄膜晶体管阵列基板，其能避免挖槽区域的边界出现金属残留，防止因金属残留而导致线路短路。
 技术解决方案
一种显示面板，所述显示面板包括：一彩色滤光片基板；一液晶层；以及一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一像素区；以及一扇出区，所述扇出区处具有凹槽；所述薄膜晶体管阵列基板包括：一基板；一挡光层，所述挡光层设置在所述基板上；一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；一多晶硅层，所述多晶硅层设置在所述缓冲层上；一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；一扫描线层，所述扫描线层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；一公共线层，所述公共线层设置在所述第三绝缘层上；一触控感应线层；一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及一像素电极层，所述像素电极层设置在所述第四绝缘层上；其中，所述扇出区包括：一第一子区域；以及一第二子区域；其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中；所述凹槽位于所述扇出区中的所述第三绝缘层中；所述彩色滤光片基板和所述薄膜晶体管阵列基板叠加组合为一体，所述液晶层设置于所述彩色滤光片基板和所述薄膜晶体管阵列基板之间。
在上述显示面板中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
在上述显示面板中，所述扫描线层包括：一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；所述数据线层包括：一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；所述触控感应线层包括：一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
在上述显示面板中，所述第一信号线阵列包括：至少一第一子信号线；以及至少一第二子信号线；所述数据线层还包括：一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
在上述显示面板中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
一种显示面板，所述显示面板包括：一彩色滤光片基板；一液晶层；以及一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一像素区；以及一扇出区，所述扇出区处具有凹槽；其特征在于，所述薄膜晶体管阵列基板包括：一基板；一挡光层，所述挡光层设置在所述基板上；一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；一多晶硅层，所述多晶硅层设置在所述缓冲层上；一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；一扫描线层，所述扫描线层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；一公共线层，所述公共线层设置在所述第三绝缘层上；一触控感应线层；一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及一像素电极层，所述像素电极层设置在所述第四绝缘层上。
在上述显示面板中，所述扇出区包括：一第一子区域；以及一第二子区域；其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中。
在上述显示面板中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
在上述显示面板中，所述扫描线层包括：一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；所述数据线层包括：一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；所述触控感应线层包括：一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
在上述显示面板中，所述第一信号线阵列包括：至少一第一子信号线；以及至少一第二子信号线；所述数据线层还包括：一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
在上述显示面板中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
在上述显示面板中，所述凹槽位于所述扇出区中的所述第三绝缘层中。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一像素区；以及一扇出区，所述扇出区处具有凹槽；其特征在于，所述薄膜晶体管阵列基板包括：一基板；一挡光层，所述挡光层设置在所述基板上；一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；一多晶硅层，所述多晶硅层设置在所述缓冲层上；一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；一扫描线层，所述扫描线层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；一公共线层，所述公共线层设置在所述第三绝缘层上；一触控感应线层；一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及一像素电极层，所述像素电极层设置在所述第四绝缘层上。
在上述薄膜晶体管阵列基板中，所述扇出区包括：一第一子区域；以及一第二子区域；其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中。
在上述薄膜晶体管阵列基板中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
在上述薄膜晶体管阵列基板中，所述扫描线层包括：一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；所述数据线层包括：一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；所述触控感应线层包括：一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
在上述薄膜晶体管阵列基板中，所述第一信号线阵列包括：至少一第一子信号线；以及至少一第二子信号线；所述数据线层还包括：一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
在上述薄膜晶体管阵列基板中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
在上述薄膜晶体管阵列基板中，所述凹槽位于所述扇出区中的所述第三绝缘层中。
 有益效果
相对现有技术，本发明有利于避免所述第三绝缘层中的所述挖槽区域的边界由于沉积所述触控感应线层中的走线而出现金属残留，有效地防止了所述扇出区因金属残留引起的线路短路风险。
 附图说明
图1为传统的薄膜晶体管阵列基板中的扇出区的凹槽中出现金属残留的示意图；
图2为图1中的局部放大示意图；
图3为本发明的薄膜晶体管阵列基板的显示区的截面图；
图4为本发明的薄膜晶体管阵列基板的扇出区的俯视图；
图5为图4中A-A’截面的示意图；
图6为图4中B-B’截面的示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）等。
本发明的显示面板包括：彩色滤光片基板、液晶层和薄膜晶体管阵列基板。所述彩色滤光片基板和所述薄膜晶体管阵列基板叠加组合为一体，所述液晶层设置于所述彩色滤光片基板和所述薄膜晶体管阵列基板之间。
参考图3，图3为本发明的薄膜晶体管阵列基板的显示区的截面图。所述薄膜晶体管阵列基板包括像素区和扇出区，所述扇出区处具有凹槽。具体地，所述扇出区中的第三绝缘层（平坦化层）309中设置有凹槽。
在本实施例中，所述薄膜晶体管阵列基板包括基板301、挡光层302、缓冲层303、多晶硅层304、第一绝缘层305、扫描线层306、第二绝缘层307、数据线层308、第三绝缘层309、公共线层310、触控感应线层312、第四绝缘层313和像素电极层314。
其中，所述挡光层302设置在所述基板301上。所述缓冲层303设置在所述基板301和所述挡光层302上。所述多晶硅层304设置在所述缓冲层303上。所述第一绝缘层305设置在所述缓冲层303和所述多晶硅层304上。所述扫描线层306设置在所述第一绝缘层305上。所述第二绝缘层307设置在所述第一绝缘层305和所述扫描线层306上。所述数据线层308设置在所述第二绝缘层307上，并且所述数据线层308通过第一通孔315与所述多晶硅层304连接。所述第三绝缘层309设置在所述第二绝缘层307和所述数据线层308上。所述公共线层310设置在所述第三绝缘层309上。第五绝缘层311设置在所述公共线层310上。所述触控感应线层312设置在所述第五绝缘层311上。所述第四绝缘层313设置在所述触控感应线层312上。所述像素电极层314设置在所述第四绝缘层313上。
参考图4、图5和图6，图4为本发明的薄膜晶体管阵列基板的扇出区的俯视图，图5为图4中A-A’截面的示意图，图6为图4中B-B’截面的示意图。
在本实施例中，所述扇出区包括第一子区域401和第二子区域402。
其中，所述凹槽设置于所述第三绝缘层309处，并且所述凹槽位于所述第二子区域402中，所述凹槽的边界403位于所述第一子区域401和所述第二子区域402交界处。
在本实施例中，所述触控感应线层312中位于所述第二子区域402中的部分通过所述数据线层308和所述扫描线层306从所述凹槽底部绕开所述凹槽。
在本实施例中，所述扫描线层306包括第一信号线阵列306。所述第一信号线阵列306设置于所述第一子区域401和所述第二子区域402，位于所述第二子区域402中的所述第一信号线阵列306处于所述凹槽在第一方向上的下方。
所述数据线层308包括第二信号线阵列3081。所述第二信号线阵列3081设置于所述第一子区域401，并且所述第二信号线阵列3081通过第二通孔405与所述第一信号线阵列306连接，所述第二通孔405位于所述第一子区域401，其中，所述第二通孔405设置于所述第二绝缘层307中。
所述触控感应线层312包括第三信号线阵列309。所述第三信号线阵列309设置于所述第一子区域401，所述第三信号线阵列309通过第三通孔404与所述第二信号线阵列3081连接，所述第三通孔404位于所述第一子区域401，其中，所述第三通孔404设置于所述第三绝缘层309中。
其中，所述第一方向为垂直于所述基板301所在的平面并从所述基板301指向所述像素电极层314的方向。
在本实施例中，所述第一信号线阵列306包括第一子信号线3061以及第二子信号线3062。所述数据线层308还包括第四信号线阵列3082。所述第四信号线阵列3082设置于所述第二子区域402，所述第四信号线阵列3082通过第四通孔406与所述第二子信号线3062连接。
其中，所述第四通孔406位于所述第二子区域402，所述第四通孔406设置于所述第二绝缘层307中。
在本发明的实施例中，在所述扇出区的所述第三绝缘层309的挖槽区域（所述凹槽所在的区域）采用M1走线（所述扫描线层306中的走线），由于所述M1走线位于所述第三绝缘层309的下方，因此可以将扇出区中的走线从所述挖槽区域引出，之后再通过所述第二绝缘层307中的扩孔跳线连接至M2走线（所述数据线层308中的走线），然后再通过所述第三绝缘层309中的扩孔跳线连接至M3走线（所述触控感应线层312中的走线），以传递信号。
这样有利于避免所述第三绝缘层309中的所述挖槽区域的边界403由于沉积所述M3走线而出现金属残留，有效地防止了所述扇出区因金属残留引起的线路短路风险。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种显示面板，所述显示面板包括：
    一彩色滤光片基板；
    一液晶层；以及
    一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    一像素区；以及
    一扇出区，所述扇出区处具有凹槽；
    其中，所述薄膜晶体管阵列基板包括：
    一基板；
    一挡光层，所述挡光层设置在所述基板上；
    一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；
    一多晶硅层，所述多晶硅层设置在所述缓冲层上；
    一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；
    一扫描线层，所述扫描线层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；
    一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；
    一公共线层，所述公共线层设置在所述第三绝缘层上；
    一触控感应线层；
    一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及
    一像素电极层，所述像素电极层设置在所述第四绝缘层上；
    其中，所述扇出区包括：
    一第一子区域；以及
    一第二子区域；
    其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中；
    所述凹槽位于所述扇出区中的所述第三绝缘层中；
    所述彩色滤光片基板和所述薄膜晶体管阵列基板叠加组合为一体，所述液晶层设置于所述彩色滤光片基板和所述薄膜晶体管阵列基板之间。
  2. 根据权利要求1所述的显示面板，其中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
  3. 根据权利要求2所述的显示面板，其中，所述扫描线层包括：
    一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；
    所述数据线层包括：
    一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；
    所述触控感应线层包括：
    一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；
    其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
  4. 根据权利要求3所述的显示面板，其中，所述第一信号线阵列包括：
    至少一第一子信号线；以及
    至少一第二子信号线；
    所述数据线层还包括：
    一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；
    其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
  5. 根据权利要求1所述的显示面板，其中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
  6. 一种显示面板，所述显示面板包括：
    一彩色滤光片基板；
    一液晶层；以及
    一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    一像素区；以及
    一扇出区，所述扇出区处具有凹槽；
    其中，所述薄膜晶体管阵列基板包括：
    一基板；
    一挡光层，所述挡光层设置在所述基板上；
    一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；
    一多晶硅层，所述多晶硅层设置在所述缓冲层上；
    一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；
    一扫描线层，所述扫描线层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；
    一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；
    一公共线层，所述公共线层设置在所述第三绝缘层上；
    一触控感应线层；
    一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及
    一像素电极层，所述像素电极层设置在所述第四绝缘层上。
  7. 根据权利要求6所述的显示面板，其中，所述扇出区包括：
    一第一子区域；以及
    一第二子区域；
    其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中。
  8. 根据权利要求7所述的显示面板，其中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
  9. 根据权利要求8所述的显示面板，其中，所述扫描线层包括：
    一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；
    所述数据线层包括：
    一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；
    所述触控感应线层包括：
    一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；
    其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
  10. 根据权利要求9所述的显示面板，其中，所述第一信号线阵列包括：
    至少一第一子信号线；以及
    至少一第二子信号线；
    所述数据线层还包括：
    一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；
    其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
  11. 根据权利要求7所述的显示面板，其中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
  12. 根据权利要求6所述的显示面板，其中，所述凹槽位于所述扇出区中的所述第三绝缘层中。
  13. 一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    一像素区；以及
    一扇出区，所述扇出区处具有凹槽；
    其中，所述薄膜晶体管阵列基板包括：
    一基板；
    一挡光层，所述挡光层设置在所述基板上；
    一缓冲层，所述缓冲层设置在所述基板和所述挡光层上；
    一多晶硅层，所述多晶硅层设置在所述缓冲层上；
    一第一绝缘层，所述第一绝缘层设置在所述缓冲层和所述多晶硅层上；
    一扫描线层，所述扫描线层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述扫描线层上；
    一数据线层，所述数据线层设置在所述第二绝缘层上，并且所述数据线层通过第一通孔与所述多晶硅层连接；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述数据线层上；
    一公共线层，所述公共线层设置在所述第三绝缘层上；
    一触控感应线层；
    一第四绝缘层，所述第四绝缘层设置在所述触控感应线层上；以及
    一像素电极层，所述像素电极层设置在所述第四绝缘层上。
  14. 根据权利要求13所述的薄膜晶体管阵列基板，其中，所述扇出区包括：
    一第一子区域；以及
    一第二子区域；
    其中，所述凹槽设置于所述第三绝缘层处，并且所述凹槽位于所述第二子区域中。
  15. 根据权利要求14所述的薄膜晶体管阵列基板，其中，所述触控感应线层中位于所述第二子区域中的部分通过所述数据线层和所述扫描线层从所述凹槽底部绕开所述凹槽。
  16. 根据权利要求15所述的薄膜晶体管阵列基板，其中，所述扫描线层包括：
    一第一信号线阵列，所述第一信号线阵列设置于所述第一子区域和所述第二子区域，位于所述第二子区域中的所述第一信号线阵列处于所述凹槽在第一方向上的下方；
    所述数据线层包括：
    一第二信号线阵列，所述第二信号线阵列设置于所述第一子区域，并且所述第二信号线阵列通过第二通孔与所述第一信号线阵列连接，所述第二通孔位于所述第一子区域，其中，所述第二通孔设置于所述第二绝缘层中；
    所述触控感应线层包括：
    一第三信号线阵列，所述第三信号线阵列设置于所述第一子区域，所述第三信号线阵列通过第三通孔与所述第二信号线阵列连接，所述第三通孔位于所述第一子区域，其中，所述第三通孔设置于所述第三绝缘层中；
    其中，所述第一方向为垂直于所述基板所在的平面并从所述基板指向所述像素电极层的方向。
  17. 根据权利要求16所述的薄膜晶体管阵列基板，其中，所述第一信号线阵列包括：
    至少一第一子信号线；以及
    至少一第二子信号线；
    所述数据线层还包括：
    一第四信号线阵列，所述第四信号线阵列设置于所述第二子区域，所述第四信号线阵列通过第四通孔与所述第二子信号线连接；
    其中，所述第四通孔位于所述第二子区域，所述第四通孔设置于所述第二绝缘层中。
  18. 根据权利要求14所述的薄膜晶体管阵列基板，其中，所述凹槽的边界位于所述第一子区域和所述第二子区域交界处。
  19. 根据权利要求13所述的薄膜晶体管阵列基板，其中，所述凹槽位于所述扇出区中的所述第三绝缘层中。
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