WO2017010164A1 - Dispositif d'alimentation semi-conducteur - Google Patents

Dispositif d'alimentation semi-conducteur Download PDF

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WO2017010164A1
WO2017010164A1 PCT/JP2016/064634 JP2016064634W WO2017010164A1 WO 2017010164 A1 WO2017010164 A1 WO 2017010164A1 JP 2016064634 W JP2016064634 W JP 2016064634W WO 2017010164 A1 WO2017010164 A1 WO 2017010164A1
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region
trench
semiconductor region
electrode
semiconductor
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PCT/JP2016/064634
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English (en)
Japanese (ja)
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健介 田口
泰宏 香川
梨菜 田中
裕 福井
勝俊 菅原
史郎 日野
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三菱電機株式会社
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Priority to JP2017528315A priority Critical patent/JP6400202B2/ja
Publication of WO2017010164A1 publication Critical patent/WO2017010164A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a gate electrode and a gate insulating film.
  • a trench gate type MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • the wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon (Si), which is a typical semiconductor, and is, for example, silicon carbide (SiC), gallium nitride (GaN), or diamond.
  • the avalanche electric field strength at the pn junction between the base region where the channel is formed and the drift layer is low in the gate insulating film made of silicon oxide. Greater than breakdown field strength. Therefore, when a high voltage is applied to the MOSFET in the off state, the highest electric field is applied to the gate insulating film that separates the bottom of the trench provided in the semiconductor layer from the gate electrode provided in the trench. Join. Therefore, the place where the breakdown of the MOSFET is most concerned is the portion of the gate insulating film that covers the bottom of the trench. Therefore, in order to alleviate the electric field applied to the portion of the gate insulating film that covers the bottom of the trench, a protective diffusion region having a conductivity type opposite to the conductivity type of the drift layer is provided at a position below the trench. There is.
  • a pn diode structure When a pn diode structure is built in between a source electrode and a drain electrode in a semiconductor device provided with a MOSFET element, this structure can be used as a free-wheeling diode for a MOSFET element as a switching element.
  • a pn diode uses a bipolar current, its recovery loss is large when used as a freewheeling diode. Therefore, in order to suppress recovery loss, it has been proposed to incorporate a Schottky barrier diode, which is an element using a unipolar current, in a semiconductor device.
  • a Schottky barrier diode which is an element using a unipolar current
  • the parasitic pn diode is also turned on when the current exceeds a specific value.
  • the bipolar current when the current processed by the freewheeling diode exceeds the maximum value of the current that can flow only by the unipolar current without the bipolar current (hereinafter referred to as “maximum unipolar current”).
  • maximum unipolar current This means that an increased recovery loss occurs. Therefore, it is desirable that the maximum unipolar current is large in order to reduce recovery loss.
  • a method for increasing the maximum unipolar current in a semiconductor device having a structure in which the breakdown of the gate insulating film in the off state is prevented by having the above-described protective diffusion region has been sufficiently studied so far. There wasn't.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to prevent breakdown of the gate insulating film in the off state and to provide the maximum unipolar of the built-in Schottky barrier diode. An object of the present invention is to provide a power semiconductor device capable of increasing current.
  • the power semiconductor device of the present invention includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate insulating film, a gate electrode, and a first main region. It has an electrode, a second main electrode, and a Schottky electrode.
  • the first semiconductor region has the first conductivity type.
  • the second semiconductor region is provided on the first semiconductor region and has a second conductivity type different from the first conductivity type.
  • the third semiconductor region is provided on the second semiconductor region, is separated from the first semiconductor region by the second semiconductor region, and has the first conductivity type.
  • the fourth semiconductor region is in contact with the first semiconductor region, has a portion provided deeper than the second semiconductor region, and has the second conductivity type.
  • the gate insulating film is provided in the first trench having an inner surface facing the third semiconductor region, the second semiconductor region, and the first semiconductor region, and covers the inner surface of the first trench. .
  • the gate electrode is provided on the gate insulating film in the first trench.
  • the first main electrode is electrically connected to the first semiconductor region.
  • the second main electrode is provided apart from the first main electrode, is ohmically connected to the third semiconductor region, and has a bottom portion facing the first semiconductor region and the fourth semiconductor region. 2 and has a portion disposed in the second trench, and is ohmically connected to the fourth semiconductor region on the bottom of the second trench.
  • the Schottky electrode is short-circuited with the second main electrode and is Schottky connected to the first semiconductor region on the bottom of the second trench.
  • the depletion layer extends from the pn junction between the first semiconductor region and the fourth semiconductor region, so that the first The electric field applied to the gate insulating film is relaxed at the bottom of the trench. Thereby, the dielectric breakdown of the gate insulating film in the off state can be prevented.
  • a Schottky electrode is Schottky connected to the first semiconductor region on the bottom of the second trench.
  • the shot path is similar to the current path of the parasitic pn diode formed by the first semiconductor region and the fourth semiconductor region.
  • the current path of the key barrier diode does not have a resistance component corresponding to the depth of the second trench.
  • the maximum unipolar current of the Schottky barrier diode built in the power semiconductor device can be increased by the Schottky electrode. From the above, it is possible to prevent the dielectric breakdown of the gate insulating film in the off state and increase the maximum unipolar current of the built-in Schottky barrier diode.
  • FIG. 3 is a partial cross-sectional view schematically showing the configuration of the power semiconductor device according to the first embodiment of the present invention in a cross section taken along line II in FIG. 2;
  • FIG. 1 is a partial plan view schematically showing a configuration of a power semiconductor device according to a first embodiment of the present invention while omitting a part of a configuration on a surface side. It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention.
  • FIG. 3 is a partial plan view schematically showing a first trench in FIG. 2. It is a fragmentary top view which shows the modification of FIG. It is a fragmentary top view which shows the modification of FIG.
  • FIG. 20 is a schematic partial sectional view taken along a line XX-XX in FIG.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXI-XXI in FIG. 19.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXI-XXI in FIG. 19.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXII-XXII in FIG. 19. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG.
  • FIG. 1 and FIG. 2 are a partial cross-sectional view and a partial plan view schematically showing the configuration of MOSFET 91 (power semiconductor device) in the present embodiment, respectively.
  • the cross section of FIG. 1 is along the line II of FIG. In FIG. 2, the source electrode 32 and the interlayer insulating film 21 in FIG. 1 are not shown.
  • MOSFET 91 is provided with a MOS region RG1 and a contact region RG2 in a planar layout.
  • the MOS region RG1 functions as a MOSFET element that is a switching element.
  • Contact region RG2 has a function of ohmic connecting p protection diffusion region 14 to source electrode 32 and a function of Schottky connection of Schottky electrode 34 to n ⁇ drift region 11.
  • a specific configuration of the MOSFET 91 will be described.
  • the MOSFET 91 includes a substrate 1 (buffer layer), a semiconductor layer 10, a gate insulating film 20, an interlayer insulating film 21, a gate electrode 30, a drain electrode 31 (first main electrode), and a source electrode 32 (first electrode). 2 main electrodes) and a Schottky electrode 34.
  • the semiconductor layer 10 includes an n ⁇ drift region 11 (first semiconductor region), a p base region 12 (second semiconductor region), an n source region 13 (third semiconductor region), and a p protective diffusion region 14. (Fourth semiconductor region).
  • the semiconductor layer 10 is provided with a MOS trench TR1 (first trench).
  • the semiconductor layer 10 is provided with a composite trench TR2 (second trench) so as to include the contact region RG2.
  • MOS trench TR1 and composite trench TR2 have approximately the same depth as shown in FIG. 1, and MOS trench TR1 and composite trench TR2 are connected to each other as shown in FIG. ing.
  • the substrate 1 is a SiC single crystal substrate.
  • Substrate 1 has n-type (first conductivity type), and has an impurity concentration higher than that of n ⁇ drift region 11.
  • the semiconductor layer 10 is formed epitaxially on one surface (the upper surface in FIG. 1) of the substrate 1.
  • the n ⁇ drift region 11 of the semiconductor layer 10 is preferably made of a wide band gap semiconductor, and the entire semiconductor layer 10 may be made of a wide band gap semiconductor.
  • the semiconductor layer 10 is an epitaxial layer made of SiC.
  • the n ⁇ drift region 11 is provided on the upper surface of the substrate 1 and has n type.
  • the p base region 12 is provided on the n ⁇ drift region 11 and has a p type (second conductivity type different from the first conductivity type).
  • the n source region 13 is provided on the p base region 12, is separated from the n ⁇ drift region 11 by the p base region 12, and has n type.
  • the p protective diffusion region 14 has a p-type and is in contact with the n ⁇ drift region 11.
  • the p protective diffusion region 14 has a portion deeper than the p base region 12 in the semiconductor layer 10 (portion positioned lower in FIG. 1). In the present embodiment, the entire p protection diffusion region 14 is p. It is arranged deeper than the base region 12.
  • MOS trench TR 1 has an inner surface facing n source region 13, p base region 12 and n ⁇ drift region 11. In other words, the MOS trench TR1 passes through the n source region 13 and the p base region 12 and reaches the n ⁇ drift region 11.
  • composite trench TR 2 also has a side portion facing n source region 13, p base region 12 and n ⁇ drift region 11. In other words, the composite trench TR2 also penetrates the n source region 13 and the p base region 12 and reaches the n ⁇ drift region 11.
  • Composite trench TR2 has a bottom portion facing p protective diffusion region 14 and n ⁇ drift region 11.
  • the p protective diffusion region 14 preferably has a portion provided deeper than the bottom of the MOS trench TR1, and more preferably has a portion in contact with the bottom of the MOS trench TR1 as shown in FIG. preferable.
  • the p protective diffusion region 14 preferably has a portion overlapping the bottom of the MOS trench TR1 in the planar layout.
  • the arrangement of the p protective diffusion region 14 and the MOS in the MOS region RG1 The arrangement of the bottoms of the trench TR1 and the composite trench TR2 is the same.
  • the side portion of the composite trench TR2 is disposed in the MOS region RG1, and the portion of the composite trench TR2 in the MOS region RG1 constitutes a trench gate structure of a MOSFET element, which will be described in detail later. It is used to In this case, p protection diffusion region 14 preferably has a portion in contact with the bottom of composite trench TR2 in MOS region RG1.
  • the p protective diffusion region 14 has a shape that substantially corresponds to the lattice shape constituted by the MOS trench TR1 and the composite trench TR2 connected to each other in a planar layout. Therefore, the part in the MOS region RG1 and the part in the contact region RG2 in the p protection diffusion region 14 are continuously connected to each other so as to form the lattice shape.
  • the gate electrode 30 filling the MOS trench TR1 and the composite trench TR2 via the gate insulating film 20 also has a lattice shape.
  • the arrangement of the p protective diffusion region 14 in the MOS region RG1 is not necessarily the same as the arrangement of the bottoms of the MOS trench TR1 and the composite trench TR2, and is in the width direction (lateral direction in FIG. 1). It may be shifted.
  • the MOS region RG1 it is desirable that at least a part of the p protective diffusion region 14 is arranged immediately below the bottom of each of the MOS trench TR1 and the composite trench TR2 in the width direction. The portion may be arranged directly under the n source region 13.
  • the gate insulating film 20 has a portion provided in the MOS trench TR1, and covers the inner surface of the MOS trench TR1.
  • the gate electrode 30 is provided on the gate insulating film 20 in the MOS trench TR1.
  • Gate insulating film 20 insulates gate electrode 30 from each of n source region 13, p base region 12, and n ⁇ drift region 11 in MOS trench TR1.
  • gate insulating film 20 has, in addition to the portion in MOS trench TR1, a portion that covers the side of composite trench TR2, and a portion that partially covers the bottom of composite trench TR2. Yes.
  • gate electrode 30 also has a portion provided on gate insulating film 20 at the side of composite trench TR2 in addition to the above portion.
  • the gate insulating film 20 insulates the gate electrode 30 from the semiconductor layer 10 on the side portion of the composite trench TR2.
  • the gate insulating film 20 insulates the bottom surface of the gate electrode 30 from the semiconductor layer 10 in the composite trench TR2.
  • composite trench TR2 has a side portion facing n source region 13, p base region 12, and n ⁇ drift region 11, and gate insulating film 20 covering this side portion, thereby A gate electrode 30 insulated from the side of the composite trench TR2 is provided.
  • the present embodiment not only the MOS trench TR1 but also the side portion of the composite trench TR2 is provided with a function as a trench gate of the MOSFET element.
  • the drain electrode 31 is electrically connected to the n ⁇ drift region 11. Specifically, the drain electrode 31 is electrically connected to the n ⁇ drift region 11 through the substrate 1 by being ohmic-bonded on the other surface (the lower surface in FIG. 1) of the substrate 1.
  • the source electrode 32 is provided apart from the drain electrode 31, and is provided on one surface (the upper surface in FIG. 1) of the substrate 1 in the present embodiment. Specifically, the source electrode 32 is ohmically connected to the n source region 13 and the p base region 12 outside the MOS trench TR1 and the composite trench TR2 in the MOS region RG1.
  • the source electrode 32 has a portion disposed in the composite trench TR2, and is ohmically connected to the p protection diffusion region 14 on the bottom of the composite trench TR2. As described above, since the portion in the MOS region RG1 and the portion in the contact region RG2 of the p protection diffusion region 14 are connected to each other, the source electrode 32 is formed on the bottom of the composite trench TR2 in the p protection diffusion region 14.
  • the ohmic-connected portion and the portion of the p protection diffusion region 14 disposed near the bottom of the MOS trench TR1 are connected to each other. Therefore, a portion of the p protection diffusion region 14 included in the MOS region RG1 is ohmically connected to the source electrode 32 via a portion of the p protection diffusion region 14 included in the contact region RG2.
  • the contact region RG2 has a function of ohmic connecting the source electrode 32 and the p protective diffusion region 14 to each other.
  • the potential of the p protective diffusion region 14 is approximately the same as the potential of the source electrode 32.
  • the interlayer insulating film 21 insulates the gate electrode 30 and the source electrode 32 from each other in the opening of the MOS trench TR1.
  • Interlayer insulating film 21 is provided with a source contact hole CH1 exposing n source region 13 and p base region 12 in MOS region RG1.
  • the source electrode 32 reaches the n source region 13 and the p base region 12 through the source contact hole CH1.
  • interlayer insulating film 21 has a portion that reaches the bottom from the outside of composite trench TR2, so that gate electrode 30 and source electrode 32 are insulated from each other in composite trench TR2. Yes.
  • the interlayer insulating film 21 covers the side surface of the source electrode 32 facing the gate electrode 30 in the composite trench TR2, whereby the gate electrode 30 and the source electrode 32 are insulated from each other in the composite trench TR2.
  • Interlayer insulating film 21 is provided with in-trench contact hole CH2 exposing p protective diffusion region 14 and n ⁇ drift region 11 on the bottom of composite trench TR2 in contact region RG2. The source electrode 32 reaches the p protective diffusion region 14 through the contact hole CH2 in the trench.
  • Schottky electrode 34 is Schottky connected to n ⁇ drift region 11 in contact hole CH2 in the trench on the bottom of composite trench TR2.
  • p protective diffusion region 14 includes a first portion and a second portion that respectively cover one end and the other end (the right end and the left end in FIG. 1) of the bottom of composite trench TR2. (The right part and the left part in FIG. 1).
  • the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 between the first and second portions.
  • the p protective diffusion region 14 is provided on the entire portion of the bottom of the composite trench TR2 that is not covered by the Schottky electrode 34. It is preferable.
  • the source electrode 32 is in contact with the Schottky electrode 34 in the composite trench TR2. As a result, the Schottky electrode 34 is short-circuited with the source electrode 32.
  • the source electrode 32 and the Schottky electrode 34 may be short-circuited by other methods.
  • the MOS region RG1 (FIG. 2) has a square shape, whereby the gate electrodes 30 are arranged in a lattice shape.
  • the p protective diffusion regions 14 are also arranged in a lattice pattern.
  • MOS region RG1 may have a polygonal shape other than a square shape, for example, a hexagonal shape.
  • the gate electrode is arranged in a honeycomb shape, and the p-type protective diffusion region can be arranged in a honeycomb shape correspondingly.
  • MOS region RG1 may have a shape other than a polygonal shape, for example, may have a comb shape.
  • semiconductor layer 10 is formed on substrate 1.
  • the entire semiconductor layer 10 has a conductivity type and an impurity concentration corresponding to the n ⁇ drift region 11 described above.
  • SiC is epitaxially grown on the (0001) plane of an n-type SiC substrate having polytype 4H while adding a donor impurity.
  • Epitaxial growth can be performed, for example, by a CVD (Chemical Vapor Deposition) method.
  • the impurity concentration of the semiconductor layer 10 is set lower than the impurity concentration of the substrate 1 and is, for example, about 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the semiconductor layer 10 is, for example, about 5 to 100 ⁇ m.
  • the p base region 12 is formed by adding impurities to a part of the semiconductor layer 10 by selective ion implantation.
  • the portion to which no impurity is added includes a portion that finally becomes n ⁇ drift region 11 as it is.
  • an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like. Using this mask, Al, which is an acceptor impurity, is added by ion implantation.
  • the depth of ion implantation is smaller than the thickness of the semiconductor layer 10 and is, for example, about 0.5 to 3 ⁇ m.
  • the concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the semiconductor layer 10 and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
  • the implantation mask is removed.
  • an impurity is added to a part of p base region 12 by selective ion implantation, thereby forming n source region 13.
  • the portion to which no impurity is added becomes the final p base region 12.
  • an implantation mask is first formed on the surface of the p base region 12 with a photoresist or the like. Using this mask, N as a donor impurity is added by ion implantation. The depth of ion implantation is made smaller than the thickness of the p base region 12.
  • the concentration of the donor impurity to be ion-implanted is higher than the concentration of the acceptor impurity in the p base region 12 and is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • a MOS trench TR ⁇ b> 1 and a composite trench TR ⁇ b> 2 are formed in the semiconductor layer 10.
  • both can be formed together.
  • an etching mask having openings corresponding to the MOS trench TR1 and the composite trench TR2 is formed on the surface of the semiconductor layer 10.
  • Etching mask for example it may be formed by a photoresist or SiO 2.
  • the MOS trench TR1 and the composite trench TR2 are formed by etching using this etching mask. After the etching, the etching mask is removed.
  • impurities are added to n ⁇ drift region 11 on the bottom of MOS trench TR1 and a part of the bottom of composite trench TR2 by selective ion implantation.
  • the p protection diffusion region 14 is formed.
  • an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like.
  • Al which is an acceptor impurity, is added by ion implantation.
  • the concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the n ⁇ drift region 11 and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the p protective diffusion region 14 is partially formed at the bottom of the composite trench TR2 so as to be in contact with the bottom of the composite trench TR2. That is, the p protective diffusion region 14 is formed only partially at the bottom of the composite trench TR2, and a part of the bottom is kept formed by the n ⁇ drift region 11.
  • the p protective diffusion region 14 is preferably formed so as to be in contact with the bottom of the MOS trench TR1, but even if it is not in contact with the bottom of the MOS trench TR1, it may be formed under the MOS trench TR1.
  • the effect of relaxing the electric field of the bottom gate insulating film 20 (FIG. 1) can be obtained to some extent.
  • annealing is performed in an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour by a heat treatment apparatus.
  • an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour.
  • the surface of the semiconductor layer 10 is thermally oxidized. Thereby, a silicon oxide film as the gate insulating film 20 having a desired thickness is formed.
  • a polycrystalline silicon film having conductivity is first formed on gate insulating film 20 by a low pressure CVD method.
  • Gate electrode 30 is formed by patterning this polycrystalline silicon film.
  • an interlayer insulating film 21 is first formed by a low pressure CVD method. Subsequently, the interlayer insulating film 21 is patterned to form the source contact hole CH1 and the in-trench contact hole CH2.
  • Schottky electrode 34 is formed so as to be partially Schottky joined to n ⁇ drift region 11 on the bottom of composite trench TR2 in contact hole CH2 in the trench.
  • the material is preferably Ti, Mo, Ni, or the like.
  • source electrode 32 is formed on semiconductor layer 10 provided with interlayer insulating film 21 and Schottky electrode 34.
  • the source electrode 32 is ohmically joined to the semiconductor layer 10 in the source contact hole CH1 and the in-trench contact hole CH2.
  • drain electrode 31 is formed on the other surface (lower surface in FIG. 1) of substrate 1.
  • MOSFET 91 is obtained.
  • the source electrode 32 and the Schottky electrode 34 are individually manufactured, but they may be continuously formed of the same material.
  • the source electrode 32 and the Schottky electrode 34 may be made of different materials, and the material may continuously change at the boundary between them.
  • the order of the ion implantation steps for forming the p base region 12 and the n source region 13 may be reversed.
  • an inversion channel layer is formed in the p base region 12 (channel region) on the side surface of the gate electrode 30.
  • the inversion channel layer serves as a path for electrons as carriers to flow from the n source region 13 to the n ⁇ drift region 11. Electrons flowing from the n source region 13 to the n ⁇ drift region 11 through the inversion channel layer pass through the substrate 1 and reach the drain electrode 31 according to the electric field generated by the positive voltage of the drain electrode 31. As a result, the MOSFET 91 can flow a current from the drain electrode 31 to the source electrode 32. This state is the ON state of the MOSFET 91.
  • the MOSFET off state when a voltage lower than the threshold voltage is applied to the gate electrode 30, no inversion channel is formed in the channel region, so that no current flows between the drain electrode 31 and the source electrode 32.
  • This state is the MOSFET off state.
  • a high voltage is applied to the MOSFET 91 in the off state, a high electric field can be applied to the gate insulating film 20 at the bottom of the MOS trench TR1 and the composite trench TR2.
  • the p protective diffusion region 14 reduces the electric field applied to the gate insulating film 20 in the off state.
  • a forward electric field (forward bias) is applied to the Schottky junction by the Schottky electrode 34, whereby a unipolar current consisting of an electron current flows from the Schottky electrode 34 to the drain electrode 31.
  • forward bias is small, the return current component of the return diode is only this unipolar component.
  • the potential of the n ⁇ drift region 11 becomes lower than the potential of the p protective diffusion region 14 having substantially the same potential as that of the source electrode 32 due to the ohmic junction.
  • the forward bias applied to the pn junction between the p protective diffusion region 14 and the n ⁇ drift region 11 increases.
  • this forward bias exceeds the diffusion potential of the pn junction, holes are injected from the p protective diffusion region 14 toward the n ⁇ drift region 11. That is, minority carrier injection (bipolar operation) occurs when the parasitic pn diode is operated by the p protection diffusion region 14 and the n-type n ⁇ drift region 11. That is, not only a unipolar current but also a bipolar current is added as a current component of the freewheeling diode.
  • the threshold current at which this phenomenon occurs is the maximum unipolar current of MOSFET 91.
  • MOSFET 90 of the comparative example unlike MOSFET 91 (FIG. 1), composite trench TR ⁇ b> 2 is not provided, and Schottky electrode 34 is disposed on the outermost surface of n ⁇ drift region 11. Yes. In other words, the Schottky electrode 34 is disposed at the height of the opening of the MOS trench TR1. Accordingly, a resistance component corresponding to the depth of the MOS trench TR1 is generated in the current path of the Schottky barrier diode constituted by the Schottky electrode 34.
  • a portion SQ sandwiched between the p base regions 12 and immediately below the Schottky electrode 34 in the current path passing through the n ⁇ drift region 11 is constricted by a depletion layer extending from the p base region 12. Therefore, the increase in resistance component due to the presence of this portion is particularly large.
  • the resistance component of the current path of the Schottky barrier diode increases, the on-resistance of the Schottky barrier diode increases, and as a result, current due to the parasitic pn diode starts to flow easily. Therefore, the maximum unipolar current is reduced.
  • Schottky electrode 34 is joined to n ⁇ drift region 11 at the bottom of composite trench TR2.
  • the Schottky electrode 34 is arranged at the height of the bottom of the composite trench TR2. Therefore, the current path of the Schottky barrier diode constituted by the Schottky electrode 34 does not have a resistance component corresponding to the depth of the trench, like the current path of the parasitic pn diode by the p protection diffusion region 14. In particular, since the current path is not narrowed by the p base region 12, an increase in the resistance component can be avoided.
  • the on-resistance of the Schottky barrier diode is reduced, and as a result, the current due to the parasitic pn diode does not easily start to flow. Therefore, the maximum unipolar current is increased.
  • the MOSFET 91 of the present embodiment first, when the MOSFET 91 is in the OFF state, the depletion layer extends from the pn junction between the n ⁇ drift region 11 and the p protective diffusion region 14, so that the MOS trench TR 1 The electric field applied to the gate insulating film 20 at the bottom is relaxed. Thereby, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented.
  • the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 on the bottom of the composite trench TR2.
  • the current path of the parasitic pn diode by the n ⁇ drift region 11 and the p protective diffusion region 14 is The current path of the Schottky barrier diode does not have a resistance component corresponding to the depth of the composite trench TR2.
  • the maximum unipolar current of the Schottky barrier diode built in the MOSFET 91 can be increased by the Schottky electrode 34. From the above, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented, and the maximum unipolar current of the built-in Schottky barrier diode can be increased.
  • the p protective diffusion region 14 is ohmically connected to the source electrode 32. As a result, the potential of the p protection diffusion region 14 is stabilized even during the switching operation of the MOSFET 91. Therefore, the occurrence of dielectric breakdown of the gate insulating film 20 during a switching operation such as turn-off can be suppressed.
  • the voltage of the drain electrode 31 rises rapidly, so that a displacement current flows through the p protective diffusion region 14 via the parasitic capacitance between the p protective diffusion region 14 and the n ⁇ drift region 11.
  • a voltage drop occurs due to the resistance component of the path through which the displacement current flows, such as the p protection diffusion region 14.
  • this voltage drop becomes large, a phenomenon that leads to a decrease in the reliability of the gate insulating film 20, such as dielectric breakdown of the gate insulating film 20 or generation of a leakage current, is likely to occur. In order to prevent this, it is effective to reduce the resistance value of the path through which the displacement current flows.
  • At least one of the sections (cells) defined by the grid-like gate electrode 30 is provided with a contact that connects between the source electrode 32 and the p protective diffusion region 14. Is used as a contact region RG2.
  • the contact area between the source electrode 32 and the p protective diffusion region 14 can be increased. Therefore, the resistance value between the source electrode 32 and the p protective diffusion region 14 becomes small. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 becomes small. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current.
  • the contact region 14 in the contact region RG2 is connected to all the p protection diffusion regions 14 in the surrounding MOS region RG1, at least one of the sections defined by the lattice-like gate electrode 30 is defined as the contact region.
  • the entire p protection diffusion region 14 can be ohmically connected to the source electrode 32.
  • the contact regions RG2 are preferably arranged at equal intervals so that the current paths in the MOSFET 91 are as uniform as possible.
  • the size of the MOS trench TR1 and the size of the composite trench TR2 can be individually optimized.
  • the contact area between the source electrode 32 and the p protective diffusion region 14 can be optimized by adjusting the size of the composite trench TR2.
  • the contact resistance of the source electrode 32 to the p protection diffusion region 14 can be reduced as necessary. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 can be sufficiently reduced. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current. As a result, the withstand voltage of the MOSFET 91 is increased.
  • the cell pitch (trench width) of the MOS trench TR1 can be made sufficiently small. Thereby, the density of the on-current per unit area of the MOSFET 91 can be increased. Therefore, the current capacity of the MOSFET 91 can be increased. As described above, according to the present embodiment, the withstand voltage can be increased while securing the current capacity.
  • a MOSFET structure is provided not only in the MOS trench TR1 but also in the side portion of the composite trench TR2.
  • the current capacity of the MOSFET 91 can be increased as compared with the case where the MOSFET structure is not provided in the composite trench TR2.
  • the MOS structure in the composite trench TR2 may be omitted. In this case, the structure in the composite trench TR2 can be simplified.
  • the p protective diffusion region 14 (FIG. 1) has a first portion and a second portion that respectively cover one end and the other end of the bottom of the composite trench TR2. Thereby, the electric field at both one end and the other end of the bottom of the composite trench TR2 can be effectively relaxed. Therefore, it is possible to more reliably prevent the dielectric breakdown of the gate insulating film 20 constituting the MOSFET structure provided on the side portion of the composite trench TR2.
  • the n ⁇ drift region 11 is made of a wide band gap semiconductor, since the withstand voltage of the n ⁇ drift region 11 itself is high, the n ⁇ drift region 11 is made of a non-wide band gap semiconductor such as Si. As compared to the case, a high electric field (for example, about 10 times) can be applied to the n ⁇ drift region 11 in the off state. In that case, a high electric field is applied to the gate insulating film 20 at the bottom of the MOS trench TR1. Generation of dielectric breakdown of the gate insulating film 20 due to the high electric field can be effectively suppressed by the p protective diffusion region 14.
  • n - if the drift region 11 is made of wide band gap semiconductor, n - unlike the case of the drift region 11 is made of a non-wide band gap semiconductor, such as Si, a gate insulating film 20 at the time of switching operation Reliability can be a problem.
  • this is because the resistance of the path through which the displacement current flows is large.
  • the displacement current generated during the switching operation at the same switching speed as the MOSFET using Si is large. For example, when the semiconductor material is changed from Si to SiC without changing the withstand voltage performance, the depletion capacity is increased about 10 times, and the displacement current is correspondingly increased correspondingly.
  • the reliability of the gate insulating film 20 during the high-speed switching operation can be achieved even when a wide band gap semiconductor is used. Sex can be maintained more reliably.
  • the depth of the MOS trench TR1 and the depth of the composite trench TR2 are the same, both can be formed at a time.
  • a depletion layer is formed from the p protection diffusion region 14 at the bottom of the composite trench TR2 to the gate insulating film 20 at the bottom of the neighboring MOS trench TR1. Easy to reach. Therefore, the electric field applied to the gate insulating film 20 is further relaxed at the bottom of the MOS trench TR1 adjacent to the composite trench TR2. Therefore, the dielectric breakdown of the gate insulating film 20 can be prevented more reliably.
  • the depth of the MOS trench TR1 and the depth of the composite trench TR2 may be different from each other.
  • the MOS trench TR1 and the composite trench TR2 may be formed in separate steps. Even if the depth of the composite trench TR2 is shallower than the depth of the MOS trench TR1, as long as it is formed deeper than the surface of the p base region 12, the height of the surface of the p base region 12, that is, the height of the trench opening.
  • the Schottky electrode 34 As compared with the case where the Schottky electrode 34 is formed (FIG. 13: comparative example), the effect of increasing the maximum unipolar current can be obtained.
  • the composite trench TR2 is deeper than the MOS trench TR1, an effect of increasing the maximum unipolar current can be obtained.
  • the bottom position of the composite trench TR2 that is, the Schottky connection position of the Schottky electrode 34, is preferably deeper than the bottom of the MOS trench TR1. Moreover, it is preferable that the depth is shallower than the p protective diffusion region 14 disposed at the bottom of the MOS trench TR1.
  • the MOS trench TR1 may have the same width as that of the p protection diffusion region 14 as shown in FIG. Thereby, the p protective diffusion region 14 can be easily formed.
  • the MOS trench TR1 has a grid-like arrangement (FIG. 14) in plan view.
  • the MOS trench TR1 has a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and a plurality of patterns extending in parallel in a direction orthogonal to this direction (vertical direction in the figure).
  • a MOS trench TR1Z (FIG. 15) having a staggered arrangement in plan view may be used.
  • MOS trench TR1Z having a staggered arrangement extends in a zigzag manner in a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and in a direction orthogonal to this direction (vertical direction in the figure).
  • a plurality of patterns for example, a MOS trench TR1S (FIG. 16) having a comb-like arrangement in plan view may be used.
  • the MOS trench TR1S having a comb-like arrangement has a plurality of comb patterns extending in parallel to each other.
  • the pattern which connects each edge part (not shown) of a comb-tooth pattern may be provided.
  • a MOS trench (not shown) having a hexagonal arrangement in plan view may be used.
  • MOSFET 92 power semiconductor device in the present embodiment has n-type n region 11A (in the region where n ⁇ drift region 11d (FIG. 1) is disposed in the first embodiment.
  • the n region 11A has an n ⁇ drift region 11e (drift region) and an n + high concentration region 11h (high concentration region).
  • the n + high concentration region 11 h is in contact with the Schottky electrode 34.
  • the effective impurity concentration of the n + high concentration region 11h is higher than the impurity concentration of the n ⁇ drift region 11e, and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the effective impurity concentration of the n + high concentration region 11 h is lower than the effective impurity concentration of the p protective diffusion region 14.
  • “effective impurity concentration” means the absolute value of the difference between the acceptor concentration and the donor concentration.
  • the n + high concentration region 11 h is separated from the substrate 1.
  • n ⁇ drift region 11e is a region other than the n + high concentration region 11h in the n region 11A.
  • N ⁇ drift region 11 e may have the same impurity concentration as n ⁇ drift region 11 d in the first embodiment.
  • the current path of the built-in Schottky barrier diode formed by the Schottky electrode 34 passes through the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2.
  • an n ⁇ drift region 11 d having a low impurity concentration is disposed in this opening.
  • the depletion layer easily extends from the p protective diffusion region 14 into the opening, and as a result, the maximum unipolar current is reduced due to the current path passing through the opening being narrowed. For this reason, in order to ensure a sufficient maximum unipolar current, the opening of the p protective diffusion region 14 must be enlarged. As a result, the area of the MOSFET 91 is increased.
  • the n + high concentration region 11 h in contact with the Schottky electrode 34 is provided in the opening of the p protective diffusion region 14.
  • the resistance component of the current path of the built-in Schottky barrier diode can be reduced. Therefore, the maximum unipolar current of the built-in Schottky barrier diode can be increased while suppressing the area of the MOSFET 92.
  • MOSFET 93 of this embodiment includes a place n + high concentration region 11i to the n + high-density region 11h.
  • the n + high concentration region 11 i extends from the portion in contact with the Schottky electrode 34 to below the p protective diffusion region 14.
  • the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14.
  • the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14.
  • the electrical resistance of the current path extending from the portion in contact with the Schottky electrode 34 to the portion separated from the bottom of the composite trench TR2 by the p protective diffusion region 14 is reduced.
  • the maximum unipolar current of the built-in Schottky barrier diode can be increased without increasing the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2.
  • FIG. 19 is a partial plan view schematically showing a configuration of MOSFET 94 (power semiconductor device) in the present embodiment.
  • 20 to 22 are schematic sectional views taken along line XX-XX, line XXI-XXI, and line XXII-XXII in FIG. In FIG. 19, the source electrode 32 and the interlayer insulating film 21 are not shown.
  • the MOSFET 94 has a contact region RG2R instead of the contact region RG2 (FIG. 1: embodiment 1).
  • a composite trench TR2R is provided instead of the composite trench TR2.
  • the shape of contact region RG2R that is, the general shape of composite trench TR2R, has a rectangular shape. Therefore, each of the contact region RG2R and the composite trench TR2R has a longitudinal direction (horizontal direction in the figure) along the long side of the rectangular shape and a width direction (vertical direction in the figure) along the short side of the rectangular shape. ).
  • the cross section of the contact region RG2R along the width direction has a different structure depending on the position of the cross section in the longitudinal direction. This will be described in detail below.
  • the source electrode 32 is ohmically connected to the p protection diffusion region 14 via the Schottky electrode 34. Therefore, the region near the line XXI-XXI also has a function of grounding the p protection diffusion region 14 to the source potential, similarly to the region near the line XX-XX.
  • the region having the ground function of the p protection diffusion region 14 and the region having the function of the built-in Schottky barrier diode are alternately arranged in the longitudinal direction.
  • the region where the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the region where the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 are alternately arranged. Has been placed.
  • the Schottky electrode 34 is entirely surrounded by the p protective diffusion region 14 as shown in FIG. Therefore, if the relative position between the mask at the time of forming the p protective diffusion layer 14 and the mask at the time of forming the Schottky electrode 34 is not managed with high accuracy, the area of the region that actually has a function as a built-in Schottky barrier diode. May change or a drain-source leak may occur.
  • the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11.
  • the arranged areas are alternately arranged. In other words, the region for grounding the p protective diffusion layer and the region for forming the Schottky barrier diode are separated from each other. Therefore, tolerance for mask displacement in the photolithography process can be increased.
  • the number of contact regions RG2R is arbitrary.
  • a plurality of contact regions RG2R are periodically arranged in at least one of the longitudinal direction and the width direction. May be arranged.
  • n region 11 ⁇ / b> A (FIG. 17 or FIG. 18: Embodiment 2 or 3) may be provided.
  • the MOS trench TR1 is not limited to the one having the lattice arrangement (FIG. 14).
  • the MOS trench TR1 is arranged in a staggered arrangement (FIG. 15), a comb A hexagonal arrangement (FIG. 16) or a hexagonal arrangement may be used.
  • a MOSFET 94S (power semiconductor device) of a modification has a contact region RG2S.
  • the contact region RG2S is provided with a composite trench TR2S (second trench).
  • the contact region RG2S is obtained by extending the above-described contact region RG2R in the long side direction, and the MOS region RG1 does not exist at the end in the long side direction. Therefore, the shape of the contact region RG2S, that is, the general shape of the composite trench TR2S has a stripe shape. In other words, the composite trench TR2S has a striped arrangement in plan view.
  • each of contact region RG2S and composite trench TR2S has a longitudinal direction (lateral direction in the figure) along the extending direction of the stripe shape and a width direction (vertical direction in the figure) perpendicular to the longitudinal direction.
  • the MOS trench TR1 has a portion extending along the vertical direction and a portion extending along the horizontal direction, and the extending direction of the stripe shape of the composite trench TR2S is one of the directions in which the MOS trench TR1 extends.
  • the MOS trench TR1 is disposed only at a position different from the composite trench TR2S.
  • the width of the MOS region RG1 is determined from the on-resistance, the drain-source breakdown voltage, and the electric field applied to the gate insulating film 20, and the width of the contact region RG2S is determined from the area occupied by the Schottky barrier diode. Can do. For example, in order to increase the occupation area of the Schottky barrier diode, it is only necessary to simply increase the width of the contact region RG2S as shown in FIG.
  • the size of the contact region RG2S may be the same as or smaller than the size of the active region in which the MOS region RG1 and the contact region RG2S are formed.
  • MOSFET 94T power semiconductor device of a further modification has MOS region RG1S instead of MOS region RG1 (FIG. 23).
  • MOS region RG1S instead of MOS region RG1 (FIG. 23).
  • the present modification not only the contact region RG2S but also the MOS region RG1S has a striped arrangement in plan view.
  • a MOS trench TR1P and a composite trench TR2P are provided instead of the MOS trench TR1 and the composite trench TR2S (FIG. 23).
  • the MOS trench TR1P and the composite trench TR2P are combined to form a stripe-shaped trench TRC.
  • a part of the trench TRC is the MOS trench TR1P, and the other part is the composite trench TR2P.
  • the width of the contact region RG2S may be made larger than the width of the MOS region RG1S. Thereby, a large area of the region functioning as the Schottky barrier diode can be secured.
  • the so-called vertical MOSFET in which the drain electrode 31 is disposed on the lower surface of the substrate 1 has been described.
  • the drain electrode 31 is disposed on the upper surface of the n ⁇ drift region 11.
  • a so-called lateral MOSFET such as a RESURF MOSFET may be used.
  • the MOSFET has been described.
  • the power semiconductor device may be a MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor) other than the MOSFET.
  • the power semiconductor device may be a transistor other than a MISFET, for example, an IGBT (Insulated-Gate Bipolar Transistor).
  • the conductivity type of the substrate 1 in FIG. 1 may be a p-type different from the conductivity type of the n ⁇ drift region 11.
  • each of the n source region 13, the source electrode 32, and the drain electrode 31 in the MOSFET 91 corresponds to the emitter region, the emitter electrode, and the collector electrode in the IGBT.
  • SiC gallium nitride
  • other wide band gap semiconductors such as gallium nitride (GaN) -based material and diamond may be used.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Dans la présente invention, une deuxième région semi-conductrice (12) d'un second type de conductivité est prévue sur une première région semi-conductrice (11) d'un premier type de conductivité, et une troisième région semi-conductrice (13) du premier type de conductivité est prévue sur la deuxième région semi-conductrice (12). Une quatrième région semi-conductrice (14) du deuxième type de conductivité comprend des parties plus profondes que la deuxième région semi-conductrice (12). Une électrode de grille (30) est prévue sur un film d'isolation de grille (20) dans une première tranchée (TR1). Une première électrode principale (31) est connectée électriquement à la première région semi-conductrice (11). Une deuxième électrode principale (32) est connectée de manière ohmique à la troisième région semi-conductrice (13) et est connectée de manière ohmique, au niveau de la partie inférieure d'une deuxième tranchée (TR2), à la quatrième région semi-conductrice (14). Une électrode de Schottky (34) est connectée par effet Schottky, au niveau de la partie inférieure de la deuxième tranchée (TR2), à la première région semi-conductrice (11).
PCT/JP2016/064634 2015-07-15 2016-05-17 Dispositif d'alimentation semi-conducteur WO2017010164A1 (fr)

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JP2020004819A (ja) * 2018-06-27 2020-01-09 日産自動車株式会社 半導体装置及びその製造方法
US11489046B2 (en) 2018-09-15 2022-11-01 Kabushiki Kaisha Toshiba Semiconductor device
WO2023165242A1 (fr) * 2022-03-02 2023-09-07 华为数字能源技术有限公司 Mosfet de sic et son procédé de préparation, et circuit intégré

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JP2011114027A (ja) * 2009-11-24 2011-06-09 Toshiba Corp 電力用半導体装置
WO2012077617A1 (fr) * 2010-12-10 2012-06-14 三菱電機株式会社 Dispositif à semi-conducteurs et procédé de production pour celui-ci
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US11489046B2 (en) 2018-09-15 2022-11-01 Kabushiki Kaisha Toshiba Semiconductor device
WO2023165242A1 (fr) * 2022-03-02 2023-09-07 华为数字能源技术有限公司 Mosfet de sic et son procédé de préparation, et circuit intégré

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