WO2017010164A1 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
WO2017010164A1
WO2017010164A1 PCT/JP2016/064634 JP2016064634W WO2017010164A1 WO 2017010164 A1 WO2017010164 A1 WO 2017010164A1 JP 2016064634 W JP2016064634 W JP 2016064634W WO 2017010164 A1 WO2017010164 A1 WO 2017010164A1
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Prior art keywords
region
trench
semiconductor region
electrode
semiconductor
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PCT/JP2016/064634
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French (fr)
Japanese (ja)
Inventor
健介 田口
泰宏 香川
梨菜 田中
裕 福井
勝俊 菅原
史郎 日野
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三菱電機株式会社
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Priority to JP2017528315A priority Critical patent/JP6400202B2/en
Publication of WO2017010164A1 publication Critical patent/WO2017010164A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a gate electrode and a gate insulating film.
  • a trench gate type MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • the wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon (Si), which is a typical semiconductor, and is, for example, silicon carbide (SiC), gallium nitride (GaN), or diamond.
  • the avalanche electric field strength at the pn junction between the base region where the channel is formed and the drift layer is low in the gate insulating film made of silicon oxide. Greater than breakdown field strength. Therefore, when a high voltage is applied to the MOSFET in the off state, the highest electric field is applied to the gate insulating film that separates the bottom of the trench provided in the semiconductor layer from the gate electrode provided in the trench. Join. Therefore, the place where the breakdown of the MOSFET is most concerned is the portion of the gate insulating film that covers the bottom of the trench. Therefore, in order to alleviate the electric field applied to the portion of the gate insulating film that covers the bottom of the trench, a protective diffusion region having a conductivity type opposite to the conductivity type of the drift layer is provided at a position below the trench. There is.
  • a pn diode structure When a pn diode structure is built in between a source electrode and a drain electrode in a semiconductor device provided with a MOSFET element, this structure can be used as a free-wheeling diode for a MOSFET element as a switching element.
  • a pn diode uses a bipolar current, its recovery loss is large when used as a freewheeling diode. Therefore, in order to suppress recovery loss, it has been proposed to incorporate a Schottky barrier diode, which is an element using a unipolar current, in a semiconductor device.
  • a Schottky barrier diode which is an element using a unipolar current
  • the parasitic pn diode is also turned on when the current exceeds a specific value.
  • the bipolar current when the current processed by the freewheeling diode exceeds the maximum value of the current that can flow only by the unipolar current without the bipolar current (hereinafter referred to as “maximum unipolar current”).
  • maximum unipolar current This means that an increased recovery loss occurs. Therefore, it is desirable that the maximum unipolar current is large in order to reduce recovery loss.
  • a method for increasing the maximum unipolar current in a semiconductor device having a structure in which the breakdown of the gate insulating film in the off state is prevented by having the above-described protective diffusion region has been sufficiently studied so far. There wasn't.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to prevent breakdown of the gate insulating film in the off state and to provide the maximum unipolar of the built-in Schottky barrier diode. An object of the present invention is to provide a power semiconductor device capable of increasing current.
  • the power semiconductor device of the present invention includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate insulating film, a gate electrode, and a first main region. It has an electrode, a second main electrode, and a Schottky electrode.
  • the first semiconductor region has the first conductivity type.
  • the second semiconductor region is provided on the first semiconductor region and has a second conductivity type different from the first conductivity type.
  • the third semiconductor region is provided on the second semiconductor region, is separated from the first semiconductor region by the second semiconductor region, and has the first conductivity type.
  • the fourth semiconductor region is in contact with the first semiconductor region, has a portion provided deeper than the second semiconductor region, and has the second conductivity type.
  • the gate insulating film is provided in the first trench having an inner surface facing the third semiconductor region, the second semiconductor region, and the first semiconductor region, and covers the inner surface of the first trench. .
  • the gate electrode is provided on the gate insulating film in the first trench.
  • the first main electrode is electrically connected to the first semiconductor region.
  • the second main electrode is provided apart from the first main electrode, is ohmically connected to the third semiconductor region, and has a bottom portion facing the first semiconductor region and the fourth semiconductor region. 2 and has a portion disposed in the second trench, and is ohmically connected to the fourth semiconductor region on the bottom of the second trench.
  • the Schottky electrode is short-circuited with the second main electrode and is Schottky connected to the first semiconductor region on the bottom of the second trench.
  • the depletion layer extends from the pn junction between the first semiconductor region and the fourth semiconductor region, so that the first The electric field applied to the gate insulating film is relaxed at the bottom of the trench. Thereby, the dielectric breakdown of the gate insulating film in the off state can be prevented.
  • a Schottky electrode is Schottky connected to the first semiconductor region on the bottom of the second trench.
  • the shot path is similar to the current path of the parasitic pn diode formed by the first semiconductor region and the fourth semiconductor region.
  • the current path of the key barrier diode does not have a resistance component corresponding to the depth of the second trench.
  • the maximum unipolar current of the Schottky barrier diode built in the power semiconductor device can be increased by the Schottky electrode. From the above, it is possible to prevent the dielectric breakdown of the gate insulating film in the off state and increase the maximum unipolar current of the built-in Schottky barrier diode.
  • FIG. 3 is a partial cross-sectional view schematically showing the configuration of the power semiconductor device according to the first embodiment of the present invention in a cross section taken along line II in FIG. 2;
  • FIG. 1 is a partial plan view schematically showing a configuration of a power semiconductor device according to a first embodiment of the present invention while omitting a part of a configuration on a surface side. It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention.
  • FIG. 3 is a partial plan view schematically showing a first trench in FIG. 2. It is a fragmentary top view which shows the modification of FIG. It is a fragmentary top view which shows the modification of FIG.
  • FIG. 20 is a schematic partial sectional view taken along a line XX-XX in FIG.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXI-XXI in FIG. 19.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXI-XXI in FIG. 19.
  • FIG. 20 is a schematic partial cross-sectional view taken along a line XXII-XXII in FIG. 19. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG. It is a partial top view which shows the modification of FIG.
  • FIG. 1 and FIG. 2 are a partial cross-sectional view and a partial plan view schematically showing the configuration of MOSFET 91 (power semiconductor device) in the present embodiment, respectively.
  • the cross section of FIG. 1 is along the line II of FIG. In FIG. 2, the source electrode 32 and the interlayer insulating film 21 in FIG. 1 are not shown.
  • MOSFET 91 is provided with a MOS region RG1 and a contact region RG2 in a planar layout.
  • the MOS region RG1 functions as a MOSFET element that is a switching element.
  • Contact region RG2 has a function of ohmic connecting p protection diffusion region 14 to source electrode 32 and a function of Schottky connection of Schottky electrode 34 to n ⁇ drift region 11.
  • a specific configuration of the MOSFET 91 will be described.
  • the MOSFET 91 includes a substrate 1 (buffer layer), a semiconductor layer 10, a gate insulating film 20, an interlayer insulating film 21, a gate electrode 30, a drain electrode 31 (first main electrode), and a source electrode 32 (first electrode). 2 main electrodes) and a Schottky electrode 34.
  • the semiconductor layer 10 includes an n ⁇ drift region 11 (first semiconductor region), a p base region 12 (second semiconductor region), an n source region 13 (third semiconductor region), and a p protective diffusion region 14. (Fourth semiconductor region).
  • the semiconductor layer 10 is provided with a MOS trench TR1 (first trench).
  • the semiconductor layer 10 is provided with a composite trench TR2 (second trench) so as to include the contact region RG2.
  • MOS trench TR1 and composite trench TR2 have approximately the same depth as shown in FIG. 1, and MOS trench TR1 and composite trench TR2 are connected to each other as shown in FIG. ing.
  • the substrate 1 is a SiC single crystal substrate.
  • Substrate 1 has n-type (first conductivity type), and has an impurity concentration higher than that of n ⁇ drift region 11.
  • the semiconductor layer 10 is formed epitaxially on one surface (the upper surface in FIG. 1) of the substrate 1.
  • the n ⁇ drift region 11 of the semiconductor layer 10 is preferably made of a wide band gap semiconductor, and the entire semiconductor layer 10 may be made of a wide band gap semiconductor.
  • the semiconductor layer 10 is an epitaxial layer made of SiC.
  • the n ⁇ drift region 11 is provided on the upper surface of the substrate 1 and has n type.
  • the p base region 12 is provided on the n ⁇ drift region 11 and has a p type (second conductivity type different from the first conductivity type).
  • the n source region 13 is provided on the p base region 12, is separated from the n ⁇ drift region 11 by the p base region 12, and has n type.
  • the p protective diffusion region 14 has a p-type and is in contact with the n ⁇ drift region 11.
  • the p protective diffusion region 14 has a portion deeper than the p base region 12 in the semiconductor layer 10 (portion positioned lower in FIG. 1). In the present embodiment, the entire p protection diffusion region 14 is p. It is arranged deeper than the base region 12.
  • MOS trench TR 1 has an inner surface facing n source region 13, p base region 12 and n ⁇ drift region 11. In other words, the MOS trench TR1 passes through the n source region 13 and the p base region 12 and reaches the n ⁇ drift region 11.
  • composite trench TR 2 also has a side portion facing n source region 13, p base region 12 and n ⁇ drift region 11. In other words, the composite trench TR2 also penetrates the n source region 13 and the p base region 12 and reaches the n ⁇ drift region 11.
  • Composite trench TR2 has a bottom portion facing p protective diffusion region 14 and n ⁇ drift region 11.
  • the p protective diffusion region 14 preferably has a portion provided deeper than the bottom of the MOS trench TR1, and more preferably has a portion in contact with the bottom of the MOS trench TR1 as shown in FIG. preferable.
  • the p protective diffusion region 14 preferably has a portion overlapping the bottom of the MOS trench TR1 in the planar layout.
  • the arrangement of the p protective diffusion region 14 and the MOS in the MOS region RG1 The arrangement of the bottoms of the trench TR1 and the composite trench TR2 is the same.
  • the side portion of the composite trench TR2 is disposed in the MOS region RG1, and the portion of the composite trench TR2 in the MOS region RG1 constitutes a trench gate structure of a MOSFET element, which will be described in detail later. It is used to In this case, p protection diffusion region 14 preferably has a portion in contact with the bottom of composite trench TR2 in MOS region RG1.
  • the p protective diffusion region 14 has a shape that substantially corresponds to the lattice shape constituted by the MOS trench TR1 and the composite trench TR2 connected to each other in a planar layout. Therefore, the part in the MOS region RG1 and the part in the contact region RG2 in the p protection diffusion region 14 are continuously connected to each other so as to form the lattice shape.
  • the gate electrode 30 filling the MOS trench TR1 and the composite trench TR2 via the gate insulating film 20 also has a lattice shape.
  • the arrangement of the p protective diffusion region 14 in the MOS region RG1 is not necessarily the same as the arrangement of the bottoms of the MOS trench TR1 and the composite trench TR2, and is in the width direction (lateral direction in FIG. 1). It may be shifted.
  • the MOS region RG1 it is desirable that at least a part of the p protective diffusion region 14 is arranged immediately below the bottom of each of the MOS trench TR1 and the composite trench TR2 in the width direction. The portion may be arranged directly under the n source region 13.
  • the gate insulating film 20 has a portion provided in the MOS trench TR1, and covers the inner surface of the MOS trench TR1.
  • the gate electrode 30 is provided on the gate insulating film 20 in the MOS trench TR1.
  • Gate insulating film 20 insulates gate electrode 30 from each of n source region 13, p base region 12, and n ⁇ drift region 11 in MOS trench TR1.
  • gate insulating film 20 has, in addition to the portion in MOS trench TR1, a portion that covers the side of composite trench TR2, and a portion that partially covers the bottom of composite trench TR2. Yes.
  • gate electrode 30 also has a portion provided on gate insulating film 20 at the side of composite trench TR2 in addition to the above portion.
  • the gate insulating film 20 insulates the gate electrode 30 from the semiconductor layer 10 on the side portion of the composite trench TR2.
  • the gate insulating film 20 insulates the bottom surface of the gate electrode 30 from the semiconductor layer 10 in the composite trench TR2.
  • composite trench TR2 has a side portion facing n source region 13, p base region 12, and n ⁇ drift region 11, and gate insulating film 20 covering this side portion, thereby A gate electrode 30 insulated from the side of the composite trench TR2 is provided.
  • the present embodiment not only the MOS trench TR1 but also the side portion of the composite trench TR2 is provided with a function as a trench gate of the MOSFET element.
  • the drain electrode 31 is electrically connected to the n ⁇ drift region 11. Specifically, the drain electrode 31 is electrically connected to the n ⁇ drift region 11 through the substrate 1 by being ohmic-bonded on the other surface (the lower surface in FIG. 1) of the substrate 1.
  • the source electrode 32 is provided apart from the drain electrode 31, and is provided on one surface (the upper surface in FIG. 1) of the substrate 1 in the present embodiment. Specifically, the source electrode 32 is ohmically connected to the n source region 13 and the p base region 12 outside the MOS trench TR1 and the composite trench TR2 in the MOS region RG1.
  • the source electrode 32 has a portion disposed in the composite trench TR2, and is ohmically connected to the p protection diffusion region 14 on the bottom of the composite trench TR2. As described above, since the portion in the MOS region RG1 and the portion in the contact region RG2 of the p protection diffusion region 14 are connected to each other, the source electrode 32 is formed on the bottom of the composite trench TR2 in the p protection diffusion region 14.
  • the ohmic-connected portion and the portion of the p protection diffusion region 14 disposed near the bottom of the MOS trench TR1 are connected to each other. Therefore, a portion of the p protection diffusion region 14 included in the MOS region RG1 is ohmically connected to the source electrode 32 via a portion of the p protection diffusion region 14 included in the contact region RG2.
  • the contact region RG2 has a function of ohmic connecting the source electrode 32 and the p protective diffusion region 14 to each other.
  • the potential of the p protective diffusion region 14 is approximately the same as the potential of the source electrode 32.
  • the interlayer insulating film 21 insulates the gate electrode 30 and the source electrode 32 from each other in the opening of the MOS trench TR1.
  • Interlayer insulating film 21 is provided with a source contact hole CH1 exposing n source region 13 and p base region 12 in MOS region RG1.
  • the source electrode 32 reaches the n source region 13 and the p base region 12 through the source contact hole CH1.
  • interlayer insulating film 21 has a portion that reaches the bottom from the outside of composite trench TR2, so that gate electrode 30 and source electrode 32 are insulated from each other in composite trench TR2. Yes.
  • the interlayer insulating film 21 covers the side surface of the source electrode 32 facing the gate electrode 30 in the composite trench TR2, whereby the gate electrode 30 and the source electrode 32 are insulated from each other in the composite trench TR2.
  • Interlayer insulating film 21 is provided with in-trench contact hole CH2 exposing p protective diffusion region 14 and n ⁇ drift region 11 on the bottom of composite trench TR2 in contact region RG2. The source electrode 32 reaches the p protective diffusion region 14 through the contact hole CH2 in the trench.
  • Schottky electrode 34 is Schottky connected to n ⁇ drift region 11 in contact hole CH2 in the trench on the bottom of composite trench TR2.
  • p protective diffusion region 14 includes a first portion and a second portion that respectively cover one end and the other end (the right end and the left end in FIG. 1) of the bottom of composite trench TR2. (The right part and the left part in FIG. 1).
  • the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 between the first and second portions.
  • the p protective diffusion region 14 is provided on the entire portion of the bottom of the composite trench TR2 that is not covered by the Schottky electrode 34. It is preferable.
  • the source electrode 32 is in contact with the Schottky electrode 34 in the composite trench TR2. As a result, the Schottky electrode 34 is short-circuited with the source electrode 32.
  • the source electrode 32 and the Schottky electrode 34 may be short-circuited by other methods.
  • the MOS region RG1 (FIG. 2) has a square shape, whereby the gate electrodes 30 are arranged in a lattice shape.
  • the p protective diffusion regions 14 are also arranged in a lattice pattern.
  • MOS region RG1 may have a polygonal shape other than a square shape, for example, a hexagonal shape.
  • the gate electrode is arranged in a honeycomb shape, and the p-type protective diffusion region can be arranged in a honeycomb shape correspondingly.
  • MOS region RG1 may have a shape other than a polygonal shape, for example, may have a comb shape.
  • semiconductor layer 10 is formed on substrate 1.
  • the entire semiconductor layer 10 has a conductivity type and an impurity concentration corresponding to the n ⁇ drift region 11 described above.
  • SiC is epitaxially grown on the (0001) plane of an n-type SiC substrate having polytype 4H while adding a donor impurity.
  • Epitaxial growth can be performed, for example, by a CVD (Chemical Vapor Deposition) method.
  • the impurity concentration of the semiconductor layer 10 is set lower than the impurity concentration of the substrate 1 and is, for example, about 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the semiconductor layer 10 is, for example, about 5 to 100 ⁇ m.
  • the p base region 12 is formed by adding impurities to a part of the semiconductor layer 10 by selective ion implantation.
  • the portion to which no impurity is added includes a portion that finally becomes n ⁇ drift region 11 as it is.
  • an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like. Using this mask, Al, which is an acceptor impurity, is added by ion implantation.
  • the depth of ion implantation is smaller than the thickness of the semiconductor layer 10 and is, for example, about 0.5 to 3 ⁇ m.
  • the concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the semiconductor layer 10 and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
  • the implantation mask is removed.
  • an impurity is added to a part of p base region 12 by selective ion implantation, thereby forming n source region 13.
  • the portion to which no impurity is added becomes the final p base region 12.
  • an implantation mask is first formed on the surface of the p base region 12 with a photoresist or the like. Using this mask, N as a donor impurity is added by ion implantation. The depth of ion implantation is made smaller than the thickness of the p base region 12.
  • the concentration of the donor impurity to be ion-implanted is higher than the concentration of the acceptor impurity in the p base region 12 and is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • a MOS trench TR ⁇ b> 1 and a composite trench TR ⁇ b> 2 are formed in the semiconductor layer 10.
  • both can be formed together.
  • an etching mask having openings corresponding to the MOS trench TR1 and the composite trench TR2 is formed on the surface of the semiconductor layer 10.
  • Etching mask for example it may be formed by a photoresist or SiO 2.
  • the MOS trench TR1 and the composite trench TR2 are formed by etching using this etching mask. After the etching, the etching mask is removed.
  • impurities are added to n ⁇ drift region 11 on the bottom of MOS trench TR1 and a part of the bottom of composite trench TR2 by selective ion implantation.
  • the p protection diffusion region 14 is formed.
  • an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like.
  • Al which is an acceptor impurity, is added by ion implantation.
  • the concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the n ⁇ drift region 11 and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the p protective diffusion region 14 is partially formed at the bottom of the composite trench TR2 so as to be in contact with the bottom of the composite trench TR2. That is, the p protective diffusion region 14 is formed only partially at the bottom of the composite trench TR2, and a part of the bottom is kept formed by the n ⁇ drift region 11.
  • the p protective diffusion region 14 is preferably formed so as to be in contact with the bottom of the MOS trench TR1, but even if it is not in contact with the bottom of the MOS trench TR1, it may be formed under the MOS trench TR1.
  • the effect of relaxing the electric field of the bottom gate insulating film 20 (FIG. 1) can be obtained to some extent.
  • annealing is performed in an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour by a heat treatment apparatus.
  • an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour.
  • the surface of the semiconductor layer 10 is thermally oxidized. Thereby, a silicon oxide film as the gate insulating film 20 having a desired thickness is formed.
  • a polycrystalline silicon film having conductivity is first formed on gate insulating film 20 by a low pressure CVD method.
  • Gate electrode 30 is formed by patterning this polycrystalline silicon film.
  • an interlayer insulating film 21 is first formed by a low pressure CVD method. Subsequently, the interlayer insulating film 21 is patterned to form the source contact hole CH1 and the in-trench contact hole CH2.
  • Schottky electrode 34 is formed so as to be partially Schottky joined to n ⁇ drift region 11 on the bottom of composite trench TR2 in contact hole CH2 in the trench.
  • the material is preferably Ti, Mo, Ni, or the like.
  • source electrode 32 is formed on semiconductor layer 10 provided with interlayer insulating film 21 and Schottky electrode 34.
  • the source electrode 32 is ohmically joined to the semiconductor layer 10 in the source contact hole CH1 and the in-trench contact hole CH2.
  • drain electrode 31 is formed on the other surface (lower surface in FIG. 1) of substrate 1.
  • MOSFET 91 is obtained.
  • the source electrode 32 and the Schottky electrode 34 are individually manufactured, but they may be continuously formed of the same material.
  • the source electrode 32 and the Schottky electrode 34 may be made of different materials, and the material may continuously change at the boundary between them.
  • the order of the ion implantation steps for forming the p base region 12 and the n source region 13 may be reversed.
  • an inversion channel layer is formed in the p base region 12 (channel region) on the side surface of the gate electrode 30.
  • the inversion channel layer serves as a path for electrons as carriers to flow from the n source region 13 to the n ⁇ drift region 11. Electrons flowing from the n source region 13 to the n ⁇ drift region 11 through the inversion channel layer pass through the substrate 1 and reach the drain electrode 31 according to the electric field generated by the positive voltage of the drain electrode 31. As a result, the MOSFET 91 can flow a current from the drain electrode 31 to the source electrode 32. This state is the ON state of the MOSFET 91.
  • the MOSFET off state when a voltage lower than the threshold voltage is applied to the gate electrode 30, no inversion channel is formed in the channel region, so that no current flows between the drain electrode 31 and the source electrode 32.
  • This state is the MOSFET off state.
  • a high voltage is applied to the MOSFET 91 in the off state, a high electric field can be applied to the gate insulating film 20 at the bottom of the MOS trench TR1 and the composite trench TR2.
  • the p protective diffusion region 14 reduces the electric field applied to the gate insulating film 20 in the off state.
  • a forward electric field (forward bias) is applied to the Schottky junction by the Schottky electrode 34, whereby a unipolar current consisting of an electron current flows from the Schottky electrode 34 to the drain electrode 31.
  • forward bias is small, the return current component of the return diode is only this unipolar component.
  • the potential of the n ⁇ drift region 11 becomes lower than the potential of the p protective diffusion region 14 having substantially the same potential as that of the source electrode 32 due to the ohmic junction.
  • the forward bias applied to the pn junction between the p protective diffusion region 14 and the n ⁇ drift region 11 increases.
  • this forward bias exceeds the diffusion potential of the pn junction, holes are injected from the p protective diffusion region 14 toward the n ⁇ drift region 11. That is, minority carrier injection (bipolar operation) occurs when the parasitic pn diode is operated by the p protection diffusion region 14 and the n-type n ⁇ drift region 11. That is, not only a unipolar current but also a bipolar current is added as a current component of the freewheeling diode.
  • the threshold current at which this phenomenon occurs is the maximum unipolar current of MOSFET 91.
  • MOSFET 90 of the comparative example unlike MOSFET 91 (FIG. 1), composite trench TR ⁇ b> 2 is not provided, and Schottky electrode 34 is disposed on the outermost surface of n ⁇ drift region 11. Yes. In other words, the Schottky electrode 34 is disposed at the height of the opening of the MOS trench TR1. Accordingly, a resistance component corresponding to the depth of the MOS trench TR1 is generated in the current path of the Schottky barrier diode constituted by the Schottky electrode 34.
  • a portion SQ sandwiched between the p base regions 12 and immediately below the Schottky electrode 34 in the current path passing through the n ⁇ drift region 11 is constricted by a depletion layer extending from the p base region 12. Therefore, the increase in resistance component due to the presence of this portion is particularly large.
  • the resistance component of the current path of the Schottky barrier diode increases, the on-resistance of the Schottky barrier diode increases, and as a result, current due to the parasitic pn diode starts to flow easily. Therefore, the maximum unipolar current is reduced.
  • Schottky electrode 34 is joined to n ⁇ drift region 11 at the bottom of composite trench TR2.
  • the Schottky electrode 34 is arranged at the height of the bottom of the composite trench TR2. Therefore, the current path of the Schottky barrier diode constituted by the Schottky electrode 34 does not have a resistance component corresponding to the depth of the trench, like the current path of the parasitic pn diode by the p protection diffusion region 14. In particular, since the current path is not narrowed by the p base region 12, an increase in the resistance component can be avoided.
  • the on-resistance of the Schottky barrier diode is reduced, and as a result, the current due to the parasitic pn diode does not easily start to flow. Therefore, the maximum unipolar current is increased.
  • the MOSFET 91 of the present embodiment first, when the MOSFET 91 is in the OFF state, the depletion layer extends from the pn junction between the n ⁇ drift region 11 and the p protective diffusion region 14, so that the MOS trench TR 1 The electric field applied to the gate insulating film 20 at the bottom is relaxed. Thereby, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented.
  • the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 on the bottom of the composite trench TR2.
  • the current path of the parasitic pn diode by the n ⁇ drift region 11 and the p protective diffusion region 14 is The current path of the Schottky barrier diode does not have a resistance component corresponding to the depth of the composite trench TR2.
  • the maximum unipolar current of the Schottky barrier diode built in the MOSFET 91 can be increased by the Schottky electrode 34. From the above, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented, and the maximum unipolar current of the built-in Schottky barrier diode can be increased.
  • the p protective diffusion region 14 is ohmically connected to the source electrode 32. As a result, the potential of the p protection diffusion region 14 is stabilized even during the switching operation of the MOSFET 91. Therefore, the occurrence of dielectric breakdown of the gate insulating film 20 during a switching operation such as turn-off can be suppressed.
  • the voltage of the drain electrode 31 rises rapidly, so that a displacement current flows through the p protective diffusion region 14 via the parasitic capacitance between the p protective diffusion region 14 and the n ⁇ drift region 11.
  • a voltage drop occurs due to the resistance component of the path through which the displacement current flows, such as the p protection diffusion region 14.
  • this voltage drop becomes large, a phenomenon that leads to a decrease in the reliability of the gate insulating film 20, such as dielectric breakdown of the gate insulating film 20 or generation of a leakage current, is likely to occur. In order to prevent this, it is effective to reduce the resistance value of the path through which the displacement current flows.
  • At least one of the sections (cells) defined by the grid-like gate electrode 30 is provided with a contact that connects between the source electrode 32 and the p protective diffusion region 14. Is used as a contact region RG2.
  • the contact area between the source electrode 32 and the p protective diffusion region 14 can be increased. Therefore, the resistance value between the source electrode 32 and the p protective diffusion region 14 becomes small. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 becomes small. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current.
  • the contact region 14 in the contact region RG2 is connected to all the p protection diffusion regions 14 in the surrounding MOS region RG1, at least one of the sections defined by the lattice-like gate electrode 30 is defined as the contact region.
  • the entire p protection diffusion region 14 can be ohmically connected to the source electrode 32.
  • the contact regions RG2 are preferably arranged at equal intervals so that the current paths in the MOSFET 91 are as uniform as possible.
  • the size of the MOS trench TR1 and the size of the composite trench TR2 can be individually optimized.
  • the contact area between the source electrode 32 and the p protective diffusion region 14 can be optimized by adjusting the size of the composite trench TR2.
  • the contact resistance of the source electrode 32 to the p protection diffusion region 14 can be reduced as necessary. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 can be sufficiently reduced. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current. As a result, the withstand voltage of the MOSFET 91 is increased.
  • the cell pitch (trench width) of the MOS trench TR1 can be made sufficiently small. Thereby, the density of the on-current per unit area of the MOSFET 91 can be increased. Therefore, the current capacity of the MOSFET 91 can be increased. As described above, according to the present embodiment, the withstand voltage can be increased while securing the current capacity.
  • a MOSFET structure is provided not only in the MOS trench TR1 but also in the side portion of the composite trench TR2.
  • the current capacity of the MOSFET 91 can be increased as compared with the case where the MOSFET structure is not provided in the composite trench TR2.
  • the MOS structure in the composite trench TR2 may be omitted. In this case, the structure in the composite trench TR2 can be simplified.
  • the p protective diffusion region 14 (FIG. 1) has a first portion and a second portion that respectively cover one end and the other end of the bottom of the composite trench TR2. Thereby, the electric field at both one end and the other end of the bottom of the composite trench TR2 can be effectively relaxed. Therefore, it is possible to more reliably prevent the dielectric breakdown of the gate insulating film 20 constituting the MOSFET structure provided on the side portion of the composite trench TR2.
  • the n ⁇ drift region 11 is made of a wide band gap semiconductor, since the withstand voltage of the n ⁇ drift region 11 itself is high, the n ⁇ drift region 11 is made of a non-wide band gap semiconductor such as Si. As compared to the case, a high electric field (for example, about 10 times) can be applied to the n ⁇ drift region 11 in the off state. In that case, a high electric field is applied to the gate insulating film 20 at the bottom of the MOS trench TR1. Generation of dielectric breakdown of the gate insulating film 20 due to the high electric field can be effectively suppressed by the p protective diffusion region 14.
  • n - if the drift region 11 is made of wide band gap semiconductor, n - unlike the case of the drift region 11 is made of a non-wide band gap semiconductor, such as Si, a gate insulating film 20 at the time of switching operation Reliability can be a problem.
  • this is because the resistance of the path through which the displacement current flows is large.
  • the displacement current generated during the switching operation at the same switching speed as the MOSFET using Si is large. For example, when the semiconductor material is changed from Si to SiC without changing the withstand voltage performance, the depletion capacity is increased about 10 times, and the displacement current is correspondingly increased correspondingly.
  • the reliability of the gate insulating film 20 during the high-speed switching operation can be achieved even when a wide band gap semiconductor is used. Sex can be maintained more reliably.
  • the depth of the MOS trench TR1 and the depth of the composite trench TR2 are the same, both can be formed at a time.
  • a depletion layer is formed from the p protection diffusion region 14 at the bottom of the composite trench TR2 to the gate insulating film 20 at the bottom of the neighboring MOS trench TR1. Easy to reach. Therefore, the electric field applied to the gate insulating film 20 is further relaxed at the bottom of the MOS trench TR1 adjacent to the composite trench TR2. Therefore, the dielectric breakdown of the gate insulating film 20 can be prevented more reliably.
  • the depth of the MOS trench TR1 and the depth of the composite trench TR2 may be different from each other.
  • the MOS trench TR1 and the composite trench TR2 may be formed in separate steps. Even if the depth of the composite trench TR2 is shallower than the depth of the MOS trench TR1, as long as it is formed deeper than the surface of the p base region 12, the height of the surface of the p base region 12, that is, the height of the trench opening.
  • the Schottky electrode 34 As compared with the case where the Schottky electrode 34 is formed (FIG. 13: comparative example), the effect of increasing the maximum unipolar current can be obtained.
  • the composite trench TR2 is deeper than the MOS trench TR1, an effect of increasing the maximum unipolar current can be obtained.
  • the bottom position of the composite trench TR2 that is, the Schottky connection position of the Schottky electrode 34, is preferably deeper than the bottom of the MOS trench TR1. Moreover, it is preferable that the depth is shallower than the p protective diffusion region 14 disposed at the bottom of the MOS trench TR1.
  • the MOS trench TR1 may have the same width as that of the p protection diffusion region 14 as shown in FIG. Thereby, the p protective diffusion region 14 can be easily formed.
  • the MOS trench TR1 has a grid-like arrangement (FIG. 14) in plan view.
  • the MOS trench TR1 has a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and a plurality of patterns extending in parallel in a direction orthogonal to this direction (vertical direction in the figure).
  • a MOS trench TR1Z (FIG. 15) having a staggered arrangement in plan view may be used.
  • MOS trench TR1Z having a staggered arrangement extends in a zigzag manner in a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and in a direction orthogonal to this direction (vertical direction in the figure).
  • a plurality of patterns for example, a MOS trench TR1S (FIG. 16) having a comb-like arrangement in plan view may be used.
  • the MOS trench TR1S having a comb-like arrangement has a plurality of comb patterns extending in parallel to each other.
  • the pattern which connects each edge part (not shown) of a comb-tooth pattern may be provided.
  • a MOS trench (not shown) having a hexagonal arrangement in plan view may be used.
  • MOSFET 92 power semiconductor device in the present embodiment has n-type n region 11A (in the region where n ⁇ drift region 11d (FIG. 1) is disposed in the first embodiment.
  • the n region 11A has an n ⁇ drift region 11e (drift region) and an n + high concentration region 11h (high concentration region).
  • the n + high concentration region 11 h is in contact with the Schottky electrode 34.
  • the effective impurity concentration of the n + high concentration region 11h is higher than the impurity concentration of the n ⁇ drift region 11e, and is, for example, about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the effective impurity concentration of the n + high concentration region 11 h is lower than the effective impurity concentration of the p protective diffusion region 14.
  • “effective impurity concentration” means the absolute value of the difference between the acceptor concentration and the donor concentration.
  • the n + high concentration region 11 h is separated from the substrate 1.
  • n ⁇ drift region 11e is a region other than the n + high concentration region 11h in the n region 11A.
  • N ⁇ drift region 11 e may have the same impurity concentration as n ⁇ drift region 11 d in the first embodiment.
  • the current path of the built-in Schottky barrier diode formed by the Schottky electrode 34 passes through the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2.
  • an n ⁇ drift region 11 d having a low impurity concentration is disposed in this opening.
  • the depletion layer easily extends from the p protective diffusion region 14 into the opening, and as a result, the maximum unipolar current is reduced due to the current path passing through the opening being narrowed. For this reason, in order to ensure a sufficient maximum unipolar current, the opening of the p protective diffusion region 14 must be enlarged. As a result, the area of the MOSFET 91 is increased.
  • the n + high concentration region 11 h in contact with the Schottky electrode 34 is provided in the opening of the p protective diffusion region 14.
  • the resistance component of the current path of the built-in Schottky barrier diode can be reduced. Therefore, the maximum unipolar current of the built-in Schottky barrier diode can be increased while suppressing the area of the MOSFET 92.
  • MOSFET 93 of this embodiment includes a place n + high concentration region 11i to the n + high-density region 11h.
  • the n + high concentration region 11 i extends from the portion in contact with the Schottky electrode 34 to below the p protective diffusion region 14.
  • the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14.
  • the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14.
  • the electrical resistance of the current path extending from the portion in contact with the Schottky electrode 34 to the portion separated from the bottom of the composite trench TR2 by the p protective diffusion region 14 is reduced.
  • the maximum unipolar current of the built-in Schottky barrier diode can be increased without increasing the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2.
  • FIG. 19 is a partial plan view schematically showing a configuration of MOSFET 94 (power semiconductor device) in the present embodiment.
  • 20 to 22 are schematic sectional views taken along line XX-XX, line XXI-XXI, and line XXII-XXII in FIG. In FIG. 19, the source electrode 32 and the interlayer insulating film 21 are not shown.
  • the MOSFET 94 has a contact region RG2R instead of the contact region RG2 (FIG. 1: embodiment 1).
  • a composite trench TR2R is provided instead of the composite trench TR2.
  • the shape of contact region RG2R that is, the general shape of composite trench TR2R, has a rectangular shape. Therefore, each of the contact region RG2R and the composite trench TR2R has a longitudinal direction (horizontal direction in the figure) along the long side of the rectangular shape and a width direction (vertical direction in the figure) along the short side of the rectangular shape. ).
  • the cross section of the contact region RG2R along the width direction has a different structure depending on the position of the cross section in the longitudinal direction. This will be described in detail below.
  • the source electrode 32 is ohmically connected to the p protection diffusion region 14 via the Schottky electrode 34. Therefore, the region near the line XXI-XXI also has a function of grounding the p protection diffusion region 14 to the source potential, similarly to the region near the line XX-XX.
  • the region having the ground function of the p protection diffusion region 14 and the region having the function of the built-in Schottky barrier diode are alternately arranged in the longitudinal direction.
  • the region where the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the region where the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11 are alternately arranged. Has been placed.
  • the Schottky electrode 34 is entirely surrounded by the p protective diffusion region 14 as shown in FIG. Therefore, if the relative position between the mask at the time of forming the p protective diffusion layer 14 and the mask at the time of forming the Schottky electrode 34 is not managed with high accuracy, the area of the region that actually has a function as a built-in Schottky barrier diode. May change or a drain-source leak may occur.
  • the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the Schottky electrode 34 is Schottky connected to the n ⁇ drift region 11.
  • the arranged areas are alternately arranged. In other words, the region for grounding the p protective diffusion layer and the region for forming the Schottky barrier diode are separated from each other. Therefore, tolerance for mask displacement in the photolithography process can be increased.
  • the number of contact regions RG2R is arbitrary.
  • a plurality of contact regions RG2R are periodically arranged in at least one of the longitudinal direction and the width direction. May be arranged.
  • n region 11 ⁇ / b> A (FIG. 17 or FIG. 18: Embodiment 2 or 3) may be provided.
  • the MOS trench TR1 is not limited to the one having the lattice arrangement (FIG. 14).
  • the MOS trench TR1 is arranged in a staggered arrangement (FIG. 15), a comb A hexagonal arrangement (FIG. 16) or a hexagonal arrangement may be used.
  • a MOSFET 94S (power semiconductor device) of a modification has a contact region RG2S.
  • the contact region RG2S is provided with a composite trench TR2S (second trench).
  • the contact region RG2S is obtained by extending the above-described contact region RG2R in the long side direction, and the MOS region RG1 does not exist at the end in the long side direction. Therefore, the shape of the contact region RG2S, that is, the general shape of the composite trench TR2S has a stripe shape. In other words, the composite trench TR2S has a striped arrangement in plan view.
  • each of contact region RG2S and composite trench TR2S has a longitudinal direction (lateral direction in the figure) along the extending direction of the stripe shape and a width direction (vertical direction in the figure) perpendicular to the longitudinal direction.
  • the MOS trench TR1 has a portion extending along the vertical direction and a portion extending along the horizontal direction, and the extending direction of the stripe shape of the composite trench TR2S is one of the directions in which the MOS trench TR1 extends.
  • the MOS trench TR1 is disposed only at a position different from the composite trench TR2S.
  • the width of the MOS region RG1 is determined from the on-resistance, the drain-source breakdown voltage, and the electric field applied to the gate insulating film 20, and the width of the contact region RG2S is determined from the area occupied by the Schottky barrier diode. Can do. For example, in order to increase the occupation area of the Schottky barrier diode, it is only necessary to simply increase the width of the contact region RG2S as shown in FIG.
  • the size of the contact region RG2S may be the same as or smaller than the size of the active region in which the MOS region RG1 and the contact region RG2S are formed.
  • MOSFET 94T power semiconductor device of a further modification has MOS region RG1S instead of MOS region RG1 (FIG. 23).
  • MOS region RG1S instead of MOS region RG1 (FIG. 23).
  • the present modification not only the contact region RG2S but also the MOS region RG1S has a striped arrangement in plan view.
  • a MOS trench TR1P and a composite trench TR2P are provided instead of the MOS trench TR1 and the composite trench TR2S (FIG. 23).
  • the MOS trench TR1P and the composite trench TR2P are combined to form a stripe-shaped trench TRC.
  • a part of the trench TRC is the MOS trench TR1P, and the other part is the composite trench TR2P.
  • the width of the contact region RG2S may be made larger than the width of the MOS region RG1S. Thereby, a large area of the region functioning as the Schottky barrier diode can be secured.
  • the so-called vertical MOSFET in which the drain electrode 31 is disposed on the lower surface of the substrate 1 has been described.
  • the drain electrode 31 is disposed on the upper surface of the n ⁇ drift region 11.
  • a so-called lateral MOSFET such as a RESURF MOSFET may be used.
  • the MOSFET has been described.
  • the power semiconductor device may be a MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor) other than the MOSFET.
  • the power semiconductor device may be a transistor other than a MISFET, for example, an IGBT (Insulated-Gate Bipolar Transistor).
  • the conductivity type of the substrate 1 in FIG. 1 may be a p-type different from the conductivity type of the n ⁇ drift region 11.
  • each of the n source region 13, the source electrode 32, and the drain electrode 31 in the MOSFET 91 corresponds to the emitter region, the emitter electrode, and the collector electrode in the IGBT.
  • SiC gallium nitride
  • other wide band gap semiconductors such as gallium nitride (GaN) -based material and diamond may be used.

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Abstract

In the present invention, a second semiconductor region (12) of a second conductive type is provided on a first semiconductor region (11) of a first conductive type, and a third semiconductor region (13) of the first conductive type is provided on the second semiconductor region (12). A fourth semiconductor region (14) of the second conductive type includes portions deeper than the second semiconductor region (12). A gate electrode (30) is provided on a gate insulating film (20) in a first trench (TR1). A first main electrode (31) is electrically connected to the first semiconductor region (11). A second main electrode (32) is ohmic-connected to the third semiconductor region (13), and is ohmic-connected, on the bottom portion of a second trench (TR2), to the fourth semiconductor region (14). A schottky electrode (34) is schottky-connected, on the bottom portion of the second trench (TR2), to the first semiconductor region (11).

Description

電力用半導体装置Power semiconductor device
　本発明は、電力用半導体装置に関し、特に、ゲート電極およびゲート絶縁膜を有する電力用半導体装置に関するものである。 The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a gate electrode and a gate insulating film.
　スイッチング素子としての機能を有する電力用半導体装置として、トレンチゲート型のＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ－Ｔｒａｎｓｉｓｔｏｒ）が従来から広く用いられている。トレンチゲート型ＭＯＳＦＥＴでは高耐電圧化と低オン抵抗化とが一般にトレードオフの関係にある。これらを両立させるための半導体材料としてワイドバンドギャップ半導体が注目されており、特に数百Ｖ程度以上の高耐電圧が求められる分野においてその適用が有望視されている。ワイドバンドギャップ半導体は、代表的な半導体であるシリコン（Ｓｉ）のバンドギャップよりも大きなバンドギャップを有する半導体であり、たとえば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、またはダイヤモンドなどである。 A trench gate type MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) has been widely used as a power semiconductor device having a function as a switching element. In the trench gate type MOSFET, there is generally a trade-off relationship between high withstand voltage and low on-resistance. Wide band gap semiconductors are attracting attention as a semiconductor material for achieving both of these, and their application is particularly promising in fields where a high withstand voltage of about several hundred volts or more is required. The wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon (Si), which is a typical semiconductor, and is, for example, silicon carbide (SiC), gallium nitride (GaN), or diamond.
　トレンチゲート型ＭＯＳＦＥＴにワイドバンドギャップ半導体を適用した場合、典型的には、チャネルが形成されるベース領域と、ドリフト層との間のｐｎ接合におけるアバランシェ電界強度が、酸化珪素からなるゲート絶縁膜の絶縁破壊電界強度よりも大きい。そのため、オフ状態にあるＭＯＳＦＥＴに高電圧が印加されているときに、半導体層に設けられたトレンチの底部と、このトレンチ内に設けられたゲート電極とを隔てるゲート絶縁膜に、最も高い電界が加わる。よって、ＭＯＳＦＥＴの絶縁破壊が最も懸念される箇所は、ゲート絶縁膜のうちトレンチの底部を覆う部分である。そこで、ゲート絶縁膜のうちトレンチの底部を覆う部分へ印加される電界を緩和するために、ドリフト層の導電型と反対の導電型を有する保護拡散領域がトレンチの下方などの位置に設けられることがある。 When a wide band gap semiconductor is applied to the trench gate type MOSFET, typically, the avalanche electric field strength at the pn junction between the base region where the channel is formed and the drift layer is low in the gate insulating film made of silicon oxide. Greater than breakdown field strength. Therefore, when a high voltage is applied to the MOSFET in the off state, the highest electric field is applied to the gate insulating film that separates the bottom of the trench provided in the semiconductor layer from the gate electrode provided in the trench. Join. Therefore, the place where the breakdown of the MOSFET is most concerned is the portion of the gate insulating film that covers the bottom of the trench. Therefore, in order to alleviate the electric field applied to the portion of the gate insulating film that covers the bottom of the trench, a protective diffusion region having a conductivity type opposite to the conductivity type of the drift layer is provided at a position below the trench. There is.
　ＭＯＳＦＥＴ素子が設けられた半導体装置において、ソース電極とドレイン電極との間にｐｎダイオード構造が内蔵されている場合、この構造をスイッチング素子としてのＭＯＳＦＥＴ素子の還流ダイオードとして使用することができる。しかし、ｐｎダイオードはバイポーラ電流を用いるものであることから、還流ダイオードとして用いられる場合、そのリカバリ損失が大きい。そこでリカバリ損失を抑えるために、ユニポーラ電流を用いる素子であるショットキーバリアダイオードを半導体装置に内蔵させることが提案されている。たとえば国際公開第２０１４／０３８１１０号（特許文献１）によれば、ドリフト層の表面上にショットキー電極が設けられる。 When a pn diode structure is built in between a source electrode and a drain electrode in a semiconductor device provided with a MOSFET element, this structure can be used as a free-wheeling diode for a MOSFET element as a switching element. However, since a pn diode uses a bipolar current, its recovery loss is large when used as a freewheeling diode. Therefore, in order to suppress recovery loss, it has been proposed to incorporate a Schottky barrier diode, which is an element using a unipolar current, in a semiconductor device. For example, according to International Publication No. 2014/038110 (Patent Document 1), a Schottky electrode is provided on the surface of the drift layer.
国際公開第２０１４／０３８１１０号International Publication No. 2014/038110
　上記のようにショットキーバリアダイオードが内蔵されたＭＯＳＦＥＴにおいて、ショットキーバリアダイオードを流れる電流を増加させていくと、この電流が特定の値を上回った時点で、寄生ｐｎダイオードもオン状態となる。その結果、還流ダイオードの電流としてユニポーラ電流だけでなくバイポーラ電流も流れ、リカバリ損失が大きくなる。このことは、還流ダイオードによって処理される電流が、バイポーラ電流を伴わずにユニポーラ電流のみで流れることができる電流の最大値（以下、「最大ユニポーラ電流」と称する）を上回ると、バイポーラ電流に起因したリカバリ損失の増大が生じることを意味する。このためリカバリ損失を低減するためには最大ユニポーラ電流が大きいことが望ましい。しかしながら、前述した保護拡散領域を有することによってオフ状態におけるゲート絶縁膜の絶縁破壊が防止される構成を有する半導体装置において、最大ユニポーラ電流を大きくするための方法が、これまで十分に検討されてきていなかった。 As described above, when the current flowing through the Schottky barrier diode is increased in the MOSFET including the Schottky barrier diode, the parasitic pn diode is also turned on when the current exceeds a specific value. As a result, not only a unipolar current but also a bipolar current flows as the current of the freewheeling diode, and the recovery loss increases. This is due to the bipolar current when the current processed by the freewheeling diode exceeds the maximum value of the current that can flow only by the unipolar current without the bipolar current (hereinafter referred to as “maximum unipolar current”). This means that an increased recovery loss occurs. Therefore, it is desirable that the maximum unipolar current is large in order to reduce recovery loss. However, a method for increasing the maximum unipolar current in a semiconductor device having a structure in which the breakdown of the gate insulating film in the off state is prevented by having the above-described protective diffusion region has been sufficiently studied so far. There wasn't.
　本発明は以上のような課題を解決するためになされたものであり、その目的は、オフ状態におけるゲート絶縁膜の絶縁破壊を防止することができ、かつ内蔵されたショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる電力用半導体装置を提供することである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent breakdown of the gate insulating film in the off state and to provide the maximum unipolar of the built-in Schottky barrier diode. An object of the present invention is to provide a power semiconductor device capable of increasing current.
　本発明の電力用半導体装置は、第１の半導体領域と、第２の半導体領域と、第３の半導体領域と、第４の半導体領域と、ゲート絶縁膜と、ゲート電極と、第１の主電極と、第２の主電極と、ショットキー電極とを有する。第１の半導体領域は第１の導電型を有する。第２の半導体領域は、第１の半導体領域上に設けられており、第１の導電型と異なる第２の導電型を有している。第３の半導体領域は、第２の半導体領域上に設けられており、第２の半導体領域によって第１の半導体領域から隔てられており、第１の導電型を有している。第４の半導体領域は、第１の半導体領域と接しており、第２の半導体領域よりも深く設けられた部分を有しており、第２の導電型を有している。ゲート絶縁膜は、第３の半導体領域と第２の半導体領域と第１の半導体領域とに面する内面を有する第１のトレンチ内に設けられており、第１のトレンチの内面を覆っている。ゲート電極は第１のトレンチ内でゲート絶縁膜上に設けられている。第１の主電極は第１の半導体領域に電気的に接続されている。第２の主電極は、第１の主電極から離れて設けられており、第３の半導体領域にオーミック接続されており、第１の半導体領域および第４の半導体領域に面する底部を有する第２のトレンチ内に配置された部分を有しており、第２のトレンチの底部上で第４の半導体領域にオーミック接続されている。ショットキー電極は、第２の主電極と短絡されており、第２のトレンチの底部上で第１の半導体領域にショットキー接続されている。 The power semiconductor device of the present invention includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate insulating film, a gate electrode, and a first main region. It has an electrode, a second main electrode, and a Schottky electrode. The first semiconductor region has the first conductivity type. The second semiconductor region is provided on the first semiconductor region and has a second conductivity type different from the first conductivity type. The third semiconductor region is provided on the second semiconductor region, is separated from the first semiconductor region by the second semiconductor region, and has the first conductivity type. The fourth semiconductor region is in contact with the first semiconductor region, has a portion provided deeper than the second semiconductor region, and has the second conductivity type. The gate insulating film is provided in the first trench having an inner surface facing the third semiconductor region, the second semiconductor region, and the first semiconductor region, and covers the inner surface of the first trench. . The gate electrode is provided on the gate insulating film in the first trench. The first main electrode is electrically connected to the first semiconductor region. The second main electrode is provided apart from the first main electrode, is ohmically connected to the third semiconductor region, and has a bottom portion facing the first semiconductor region and the fourth semiconductor region. 2 and has a portion disposed in the second trench, and is ohmically connected to the fourth semiconductor region on the bottom of the second trench. The Schottky electrode is short-circuited with the second main electrode and is Schottky connected to the first semiconductor region on the bottom of the second trench.
　本電力用半導体装置によれば、第１に、電力用半導体装置がオフ状態のとき、第１の半導体領域と第４の半導体領域との間のｐｎ接合から空乏層が延びることにより、第１のトレンチの底部においてゲート絶縁膜に加わる電界が緩和される。これにより、オフ状態におけるゲート絶縁膜の絶縁破壊を防止することができる。第２に、ショットキー電極が第１の半導体領域に第２のトレンチの底部上でショットキー接続されている。これにより、ショットキー電極がトレンチの外部において第１の半導体領域にショットキー接続される場合と異なり、第１の半導体領域と第４の半導体領域とによる寄生ｐｎダイオードの電流経路と同様に、ショットキーバリアダイオードの電流経路は、第２のトレンチの深さに対応した抵抗成分を有しない。これにより、ショットキー電極によって電力用半導体装置に内蔵されるショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる。以上から、オフ状態におけるゲート絶縁膜の絶縁破壊を防止することができ、かつ内蔵ショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる。 According to the power semiconductor device, first, when the power semiconductor device is in the OFF state, the depletion layer extends from the pn junction between the first semiconductor region and the fourth semiconductor region, so that the first The electric field applied to the gate insulating film is relaxed at the bottom of the trench. Thereby, the dielectric breakdown of the gate insulating film in the off state can be prevented. Second, a Schottky electrode is Schottky connected to the first semiconductor region on the bottom of the second trench. Thus, unlike the case where the Schottky electrode is Schottky connected to the first semiconductor region outside the trench, the shot path is similar to the current path of the parasitic pn diode formed by the first semiconductor region and the fourth semiconductor region. The current path of the key barrier diode does not have a resistance component corresponding to the depth of the second trench. As a result, the maximum unipolar current of the Schottky barrier diode built in the power semiconductor device can be increased by the Schottky electrode. From the above, it is possible to prevent the dielectric breakdown of the gate insulating film in the off state and increase the maximum unipolar current of the built-in Schottky barrier diode.
　この発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.
本発明の実施の形態１における電力用半導体装置の構成を、図２の線Ｉ－Ｉの断面で概略的に示す部分断面図である。FIG. 3 is a partial cross-sectional view schematically showing the configuration of the power semiconductor device according to the first embodiment of the present invention in a cross section taken along line II in FIG. 2; 本発明の実施の形態１における電力用半導体装置の構成を、表面側の構成を一部省略しつつ概略的に示す部分平面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial plan view schematically showing a configuration of a power semiconductor device according to a first embodiment of the present invention while omitting a part of a configuration on a surface side. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 本発明の実施の形態１における電力用半導体装置の製造方法の一の工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically one process of the manufacturing method of the semiconductor device for electric power in Embodiment 1 of this invention. 比較例の電力用半導体装置の構成を示す部分断面図である。It is a fragmentary sectional view which shows the structure of the semiconductor device for electric power of a comparative example. 図２における第１のトレンチを概略的に示す部分平面図である。FIG. 3 is a partial plan view schematically showing a first trench in FIG. 2. 図１４の変形例を示す部分平面図である。It is a fragmentary top view which shows the modification of FIG. 図１４の変形例を示す部分平面図である。It is a fragmentary top view which shows the modification of FIG. 本発明の実施の形態２における電力用半導体装置の構成を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically the structure of the semiconductor device for electric power in Embodiment 2 of this invention. 本発明の実施の形態３における電力用半導体装置の構成を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically the structure of the semiconductor device for electric power in Embodiment 3 of this invention. 本発明の実施の形態４における電力用半導体装置の構成を、表面側の構成を一部省略しつつ概略的に示す部分平面図である。It is a fragmentary top view which shows roughly the structure of the semiconductor device for electric power in Embodiment 4 of this invention, abbreviate | omitting some structures on the surface side. 図１９の線ＸＸ－ＸＸの断面に沿う概略部分断面図である。FIG. 20 is a schematic partial sectional view taken along a line XX-XX in FIG. 図１９の線ＸＸＩ－ＸＸＩの断面に沿う概略部分断面図である。FIG. 20 is a schematic partial cross-sectional view taken along a line XXI-XXI in FIG. 19. 図１９の線ＸＸＩＩ－ＸＸＩＩの断面に沿う概略部分断面図である。FIG. 20 is a schematic partial cross-sectional view taken along a line XXII-XXII in FIG. 19. 図１９の変形例を示す部分平面図である。It is a partial top view which shows the modification of FIG. 図２３の変形例を示す部分平面図である。It is a partial top view which shows the modification of FIG. 図１９の変形例を示す部分平面図である。It is a partial top view which shows the modification of FIG.
　以下、図面に基づいて本発明の実施の形態について説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付しその説明は繰返さない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
　＜実施の形態１＞
　（装置構成）
　図１および図２のそれぞれは、本実施の形態におけるＭＯＳＦＥＴ９１（電力用半導体装置）の構成を概略的に示す部分断面図および部分平面図である。なお、図１の断面は、図２の線Ｉ－Ｉに沿っている。また図２においては、図１におけるソース電極３２および層間絶縁膜２１の図示を省略している。 <Embodiment 1>
(Device configuration)
FIG. 1 and FIG. 2 are a partial cross-sectional view and a partial plan view schematically showing the configuration of MOSFET 91 (power semiconductor device) in the present embodiment, respectively. The cross section of FIG. 1 is along the line II of FIG. In FIG. 2, the source electrode 32 and the interlayer insulating film 21 in FIG. 1 are not shown.
　ＭＯＳＦＥＴ９１には、平面レイアウトにおいて、ＭＯＳ領域ＲＧ１と、コンタクト領域ＲＧ２とが設けられている。ＭＯＳ領域ＲＧ１は、スイッチング素子であるＭＯＳＦＥＴ素子としての機能を有している。コンタクト領域ＲＧ２は、ｐ保護拡散領域１４をソース電極３２にオーミックに接続する機能と、ショットキー電極３４をｎ-ドリフト領域１１にショットキー接続する機能とを有している。以下、ＭＯＳＦＥＴ９１の具体的な構成について説明する。 MOSFET 91 is provided with a MOS region RG1 and a contact region RG2 in a planar layout. The MOS region RG1 functions as a MOSFET element that is a switching element. Contact region RG2 has a function of ohmic connecting p protection diffusion region 14 to source electrode 32 and a function of Schottky connection of Schottky electrode 34 to n − drift region 11. Hereinafter, a specific configuration of the MOSFET 91 will be described.
　ＭＯＳＦＥＴ９１は、基板１（バッファ層）と、半導体層１０と、ゲート絶縁膜２０と、層間絶縁膜２１と、ゲート電極３０と、ドレイン電極３１（第１の主電極）と、ソース電極３２（第２の主電極）と、ショットキー電極３４とを有している。半導体層１０は、ｎ-ドリフト領域１１（第１の半導体領域）と、ｐベース領域１２（第２の半導体領域）と、ｎソース領域１３（第３の半導体領域）と、ｐ保護拡散領域１４（第４の半導体領域）とを有している。ＭＯＳ領域ＲＧ１において半導体層１０にはＭＯＳトレンチＴＲ１（第１のトレンチ）が設けられている。またコンタクト領域ＲＧ２を包含するように半導体層１０には複合トレンチＴＲ２（第２のトレンチ）が設けられている。本実施の形態においては、図１に示すようにＭＯＳトレンチＴＲ１と複合トレンチＴＲ２とがおおよそ同じ深さを有しており、また図２に示すようにＭＯＳトレンチＴＲ１と複合トレンチＴＲ２とが互いにつながっている。 The MOSFET 91 includes a substrate 1 (buffer layer), a semiconductor layer 10, a gate insulating film 20, an interlayer insulating film 21, a gate electrode 30, a drain electrode 31 (first main electrode), and a source electrode 32 (first electrode). 2 main electrodes) and a Schottky electrode 34. The semiconductor layer 10 includes an n − drift region 11 (first semiconductor region), a p base region 12 (second semiconductor region), an n source region 13 (third semiconductor region), and a p protective diffusion region 14. (Fourth semiconductor region). In the MOS region RG1, the semiconductor layer 10 is provided with a MOS trench TR1 (first trench). The semiconductor layer 10 is provided with a composite trench TR2 (second trench) so as to include the contact region RG2. In the present embodiment, MOS trench TR1 and composite trench TR2 have approximately the same depth as shown in FIG. 1, and MOS trench TR1 and composite trench TR2 are connected to each other as shown in FIG. ing.
　基板１はＳｉＣの単結晶基板である。基板１は、ｎ型（第１の導電型）を有しており、ｎ-ドリフト領域１１の不純物濃度よりも高い不純物濃度を有している。半導体層１０は基板１の一方面（図１における上面）上にエピタキシャルに形成されている。半導体層１０のｎ-ドリフト領域１１はワイドバンドギャップ半導体から作られていることが好ましく、半導体層１０全体がワイドバンドギャップ半導体から作られていてもよい。本実施の形態においては、半導体層１０はＳｉＣから作られたエピタキシャル層である。 The substrate 1 is a SiC single crystal substrate. Substrate 1 has n-type (first conductivity type), and has an impurity concentration higher than that of n − drift region 11. The semiconductor layer 10 is formed epitaxially on one surface (the upper surface in FIG. 1) of the substrate 1. The n − drift region 11 of the semiconductor layer 10 is preferably made of a wide band gap semiconductor, and the entire semiconductor layer 10 may be made of a wide band gap semiconductor. In the present embodiment, the semiconductor layer 10 is an epitaxial layer made of SiC.
　ｎ-ドリフト領域１１は、基板１の上面上に設けられており、ｎ型を有している。ｐベース領域１２は、ｎ-ドリフト領域１１上に設けられており、ｐ型（第１の導電型と異なる第２の導電型）を有している。ｎソース領域１３は、ｐベース領域１２上に設けられており、ｐベース領域１２によってｎ-ドリフト領域１１から隔てられており、ｎ型を有している。ｐ保護拡散領域１４は、ｐ型を有しており、ｎ-ドリフト領域１１と接している。ｐ保護拡散領域１４は、半導体層１０においてｐベース領域１２よりも深く設けられた部分（図１において、より下方に位置する部分）を有しており、本実施の形態においてはその全体がｐベース領域１２よりも深く配置されている。 The n − drift region 11 is provided on the upper surface of the substrate 1 and has n type. The p base region 12 is provided on the n − drift region 11 and has a p type (second conductivity type different from the first conductivity type). The n source region 13 is provided on the p base region 12, is separated from the n − drift region 11 by the p base region 12, and has n type. The p protective diffusion region 14 has a p-type and is in contact with the n − drift region 11. The p protective diffusion region 14 has a portion deeper than the p base region 12 in the semiconductor layer 10 (portion positioned lower in FIG. 1). In the present embodiment, the entire p protection diffusion region 14 is p. It is arranged deeper than the base region 12.
　ＭＯＳトレンチＴＲ１は、ｎソース領域１３とｐベース領域１２とｎ-ドリフト領域１１とに面する内面を有している。言い換えれば、ＭＯＳトレンチＴＲ１は、ｎソース領域１３とｐベース領域１２とを貫通してｎ-ドリフト領域１１に達している。また本実施の形態においては、複合トレンチＴＲ２も、ｎソース領域１３とｐベース領域１２とｎ-ドリフト領域１１とに面する側部を有している。言い換えれば、複合トレンチＴＲ２も、ｎソース領域１３とｐベース領域１２とを貫通してｎ-ドリフト領域１１に達している。複合トレンチＴＲ２はｐ保護拡散領域１４およびｎ-ドリフト領域１１に面する底部を有している。 MOS trench TR 1 has an inner surface facing n source region 13, p base region 12 and n − drift region 11. In other words, the MOS trench TR1 passes through the n source region 13 and the p base region 12 and reaches the n − drift region 11. In the present embodiment, composite trench TR 2 also has a side portion facing n source region 13, p base region 12 and n − drift region 11. In other words, the composite trench TR2 also penetrates the n source region 13 and the p base region 12 and reaches the n − drift region 11. Composite trench TR2 has a bottom portion facing p protective diffusion region 14 and n − drift region 11.
　ｐ保護拡散領域１４は、ＭＯＳトレンチＴＲ１の底部よりも深く設けられた部分を有していることが好ましく、図１に示すようにＭＯＳトレンチＴＲ１の底部に接する部分を有していることがより好ましい。またｐ保護拡散領域１４は、平面レイアウトにおいてＭＯＳトレンチＴＲ１の底部と重なる部分を有していることが好ましく、本実施の形態においてはＭＯＳ領域ＲＧ１内で、ｐ保護拡散領域１４の配置と、ＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の底部の配置とが同じとされている。 The p protective diffusion region 14 preferably has a portion provided deeper than the bottom of the MOS trench TR1, and more preferably has a portion in contact with the bottom of the MOS trench TR1 as shown in FIG. preferable. The p protective diffusion region 14 preferably has a portion overlapping the bottom of the MOS trench TR1 in the planar layout. In the present embodiment, the arrangement of the p protective diffusion region 14 and the MOS in the MOS region RG1 The arrangement of the bottoms of the trench TR1 and the composite trench TR2 is the same.
　本実施の形態においては、複合トレンチＴＲ２の側部はＭＯＳ領域ＲＧ１内に配置されており、複合トレンチＴＲ２のうちＭＯＳ領域ＲＧ１内の部分は、詳しくは後述するがＭＯＳＦＥＴ素子のトレンチゲート構造を構成するために用いられている。この場合、ｐ保護拡散領域１４は、ＭＯＳ領域ＲＧ１内において複合トレンチＴＲ２の底部に接する部分を有していることが好ましい。 In the present embodiment, the side portion of the composite trench TR2 is disposed in the MOS region RG1, and the portion of the composite trench TR2 in the MOS region RG1 constitutes a trench gate structure of a MOSFET element, which will be described in detail later. It is used to In this case, p protection diffusion region 14 preferably has a portion in contact with the bottom of composite trench TR2 in MOS region RG1.
　また本実施の形態においては、ｐ保護拡散領域１４は、互いにつながったＭＯＳトレンチＴＲ１および複合トレンチＴＲ２によって構成される格子形状にほぼ対応した形状を平面レイアウトにおいて有している。よって、ｐ保護拡散領域１４のうちＭＯＳ領域ＲＧ１内の部分とコンタクト領域ＲＧ２内の部分とは、上記格子形状を成すように互いに連続的につながっている。またゲート絶縁膜２０を介してＭＯＳトレンチＴＲ１および複合トレンチＴＲ２を埋めるゲート電極３０も格子形状を有している。なお平面レイアウトにおいて、ＭＯＳ領域ＲＧ１内でのｐ保護拡散領域１４の配置は、必ずしもＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の底部の配置と同じである必要はなく、幅方向（図１における横方向）にずらされていてもよい。ＭＯＳ領域ＲＧ１内では、幅方向においてｐ保護拡散領域１４の少なくとも一部がＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の各々の底部の直下に配置されていることが望ましいが、ｐ保護拡散領域１４の少なくとも一部がｎソース領域１３の直下に配置されていてもよい。 In the present embodiment, the p protective diffusion region 14 has a shape that substantially corresponds to the lattice shape constituted by the MOS trench TR1 and the composite trench TR2 connected to each other in a planar layout. Therefore, the part in the MOS region RG1 and the part in the contact region RG2 in the p protection diffusion region 14 are continuously connected to each other so as to form the lattice shape. The gate electrode 30 filling the MOS trench TR1 and the composite trench TR2 via the gate insulating film 20 also has a lattice shape. In the planar layout, the arrangement of the p protective diffusion region 14 in the MOS region RG1 is not necessarily the same as the arrangement of the bottoms of the MOS trench TR1 and the composite trench TR2, and is in the width direction (lateral direction in FIG. 1). It may be shifted. In the MOS region RG1, it is desirable that at least a part of the p protective diffusion region 14 is arranged immediately below the bottom of each of the MOS trench TR1 and the composite trench TR2 in the width direction. The portion may be arranged directly under the n source region 13.
　ゲート絶縁膜２０は、ＭＯＳトレンチＴＲ１内に設けられている部分を有しており、ＭＯＳトレンチＴＲ１の内面を覆っている。ゲート電極３０はＭＯＳトレンチＴＲ１内でゲート絶縁膜２０上に設けられている。ゲート絶縁膜２０は、ＭＯＳトレンチＴＲ１内においてゲート電極３０をｎソース領域１３とｐベース領域１２とｎ-ドリフト領域１１との各々から絶縁している。 The gate insulating film 20 has a portion provided in the MOS trench TR1, and covers the inner surface of the MOS trench TR1. The gate electrode 30 is provided on the gate insulating film 20 in the MOS trench TR1. Gate insulating film 20 insulates gate electrode 30 from each of n source region 13, p base region 12, and n − drift region 11 in MOS trench TR1.
　本実施の形態においては、ゲート絶縁膜２０は、ＭＯＳトレンチＴＲ１内の部分に加えて、複合トレンチＴＲ２の側部を覆う部分と、複合トレンチＴＲ２の底部を部分的に覆う部分とを有している。また本実施の形態においては、ゲート電極３０は、上記部分に加えて、複合トレンチＴＲ２の側部においてゲート絶縁膜２０上に設けられた部分も有している。ゲート絶縁膜２０は複合トレンチＴＲ２の側部上においてゲート電極３０を半導体層１０から絶縁している。またゲート絶縁膜２０は、複合トレンチＴＲ２内においてゲート電極３０の底面を半導体層１０から絶縁している。よって本実施の形態においては、複合トレンチＴＲ２がｎソース領域１３とｐベース領域１２とｎ-ドリフト領域１１とに面する側部を有し、この側部を覆うゲート絶縁膜２０と、それによって複合トレンチＴＲ２の側部から絶縁されたゲート電極３０とが設けられている。この構造により本実施の形態においては、ＭＯＳトレンチＴＲ１だけでなく、複合トレンチＴＲ２の側部にも、ＭＯＳＦＥＴ素子のトレンチゲートとしての機能が設けられている。 In the present embodiment, gate insulating film 20 has, in addition to the portion in MOS trench TR1, a portion that covers the side of composite trench TR2, and a portion that partially covers the bottom of composite trench TR2. Yes. In the present embodiment, gate electrode 30 also has a portion provided on gate insulating film 20 at the side of composite trench TR2 in addition to the above portion. The gate insulating film 20 insulates the gate electrode 30 from the semiconductor layer 10 on the side portion of the composite trench TR2. The gate insulating film 20 insulates the bottom surface of the gate electrode 30 from the semiconductor layer 10 in the composite trench TR2. Therefore, in the present embodiment, composite trench TR2 has a side portion facing n source region 13, p base region 12, and n − drift region 11, and gate insulating film 20 covering this side portion, thereby A gate electrode 30 insulated from the side of the composite trench TR2 is provided. With this structure, in the present embodiment, not only the MOS trench TR1 but also the side portion of the composite trench TR2 is provided with a function as a trench gate of the MOSFET element.
　ドレイン電極３１はｎ-ドリフト領域１１に電気的に接続されている。具体的には、ドレイン電極３１は、基板１の他方面（図１における下面）上にオーミック接合されることによって基板１を介してｎ-ドリフト領域１１に電気的に接続されている。 The drain electrode 31 is electrically connected to the n − drift region 11. Specifically, the drain electrode 31 is electrically connected to the n − drift region 11 through the substrate 1 by being ohmic-bonded on the other surface (the lower surface in FIG. 1) of the substrate 1.
　ソース電極３２は、ドレイン電極３１から離れて設けられており、本実施の形態においては、基板１の一方面（図１における上面）上に設けられている。具体的には、ソース電極３２はＭＯＳ領域ＲＧ１において、ＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の外で、ｎソース領域１３およびｐベース領域１２にオーミック接続されている。またソース電極３２は、複合トレンチＴＲ２内に配置された部分を有しており、複合トレンチＴＲ２の底部上でｐ保護拡散領域１４にオーミック接続されている。前述したようにｐ保護拡散領域１４のうちＭＯＳ領域ＲＧ１内の部分とコンタクト領域ＲＧ２内の部分とは互いにつながっているので、ｐ保護拡散領域１４のうち複合トレンチＴＲ２の底部上でソース電極３２にオーミック接続された部分と、ｐ保護拡散領域１４のうちＭＯＳトレンチＴＲ１の底部近傍に配置された部分とは互いにつながっている。よって、ｐ保護拡散領域１４のうちＭＯＳ領域ＲＧ１に含まれる部分は、ｐ保護拡散領域１４のうちコンタクト領域ＲＧ２に含まれる部分を介して、ソース電極３２にオーミック接続されている。以上のように、コンタクト領域ＲＧ２は、ソース電極３２とｐ保護拡散領域１４とを互いにオーミック接続する機能を有している。これによりｐ保護拡散領域１４の電位はおおよそソース電極３２の電位と同様とされる。 The source electrode 32 is provided apart from the drain electrode 31, and is provided on one surface (the upper surface in FIG. 1) of the substrate 1 in the present embodiment. Specifically, the source electrode 32 is ohmically connected to the n source region 13 and the p base region 12 outside the MOS trench TR1 and the composite trench TR2 in the MOS region RG1. The source electrode 32 has a portion disposed in the composite trench TR2, and is ohmically connected to the p protection diffusion region 14 on the bottom of the composite trench TR2. As described above, since the portion in the MOS region RG1 and the portion in the contact region RG2 of the p protection diffusion region 14 are connected to each other, the source electrode 32 is formed on the bottom of the composite trench TR2 in the p protection diffusion region 14. The ohmic-connected portion and the portion of the p protection diffusion region 14 disposed near the bottom of the MOS trench TR1 are connected to each other. Therefore, a portion of the p protection diffusion region 14 included in the MOS region RG1 is ohmically connected to the source electrode 32 via a portion of the p protection diffusion region 14 included in the contact region RG2. As described above, the contact region RG2 has a function of ohmic connecting the source electrode 32 and the p protective diffusion region 14 to each other. As a result, the potential of the p protective diffusion region 14 is approximately the same as the potential of the source electrode 32.
　層間絶縁膜２１は、ＭＯＳトレンチＴＲ１の開口においてゲート電極３０とソース電極３２とを互いに絶縁している。層間絶縁膜２１には、ＭＯＳ領域ＲＧ１においてｎソース領域１３およびｐベース領域１２を露出するソースコンタクトホールＣＨ１が設けられている。ソースコンタクトホールＣＨ１を通ってソース電極３２はｎソース領域１３およびｐベース領域１２に達している。 The interlayer insulating film 21 insulates the gate electrode 30 and the source electrode 32 from each other in the opening of the MOS trench TR1. Interlayer insulating film 21 is provided with a source contact hole CH1 exposing n source region 13 and p base region 12 in MOS region RG1. The source electrode 32 reaches the n source region 13 and the p base region 12 through the source contact hole CH1.
　また本実施の形態においては、層間絶縁膜２１は複合トレンチＴＲ２の外からその底部に達する部分を有しており、これにより複合トレンチＴＲ２内においてゲート電極３０とソース電極３２とが互いに絶縁されている。言い換えると、複合トレンチＴＲ２内において層間絶縁膜２１がソース電極３２のゲート電極３０に面する側面を覆っており、これにより複合トレンチＴＲ２内においてゲート電極３０とソース電極３２とが互いに絶縁されている。また層間絶縁膜２１には、コンタクト領域ＲＧ２において複合トレンチＴＲ２の底部上でｐ保護拡散領域１４およびｎ-ドリフト領域１１を露出するトレンチ内コンタクトホールＣＨ２が設けられている。トレンチ内コンタクトホールＣＨ２を通ってソース電極３２はｐ保護拡散領域１４に達している。 In the present embodiment, interlayer insulating film 21 has a portion that reaches the bottom from the outside of composite trench TR2, so that gate electrode 30 and source electrode 32 are insulated from each other in composite trench TR2. Yes. In other words, the interlayer insulating film 21 covers the side surface of the source electrode 32 facing the gate electrode 30 in the composite trench TR2, whereby the gate electrode 30 and the source electrode 32 are insulated from each other in the composite trench TR2. . Interlayer insulating film 21 is provided with in-trench contact hole CH2 exposing p protective diffusion region 14 and n − drift region 11 on the bottom of composite trench TR2 in contact region RG2. The source electrode 32 reaches the p protective diffusion region 14 through the contact hole CH2 in the trench.
　ショットキー電極３４は複合トレンチＴＲ２の底部上でトレンチ内コンタクトホールＣＨ２内においてｎ-ドリフト領域１１にショットキー接続されている。本実施の形態においては断面視（図１）でｐ保護拡散領域１４は、複合トレンチＴＲ２の底部の一方端および他方端（図１における右端および左端）のそれぞれを覆う第１の部分および第２の部分（図１における右部および左部）を有している。これら第１および第２の部分の間でショットキー電極３４はｎ-ドリフト領域１１にショットキー接続されている。ソース電極３２とｐ保護拡散領域１４との間のオーミック抵抗を低減するためには、複合トレンチＴＲ２の底部のうちショットキー電極３４によって覆われていない部分の全体にｐ保護拡散領域１４が設けられていることが好ましい。 Schottky electrode 34 is Schottky connected to n − drift region 11 in contact hole CH2 in the trench on the bottom of composite trench TR2. In the present embodiment, in the cross-sectional view (FIG. 1), p protective diffusion region 14 includes a first portion and a second portion that respectively cover one end and the other end (the right end and the left end in FIG. 1) of the bottom of composite trench TR2. (The right part and the left part in FIG. 1). The Schottky electrode 34 is Schottky connected to the n − drift region 11 between the first and second portions. In order to reduce the ohmic resistance between the source electrode 32 and the p protective diffusion region 14, the p protective diffusion region 14 is provided on the entire portion of the bottom of the composite trench TR2 that is not covered by the Schottky electrode 34. It is preferable.
　ソース電極３２は複合トレンチＴＲ２内においてショットキー電極３４に接している。これによりショットキー電極３４はソース電極３２と短絡されている。なおソース電極３２とショットキー電極３４とは、他の方法によって短絡されていてもよい。 The source electrode 32 is in contact with the Schottky electrode 34 in the composite trench TR2. As a result, the Schottky electrode 34 is short-circuited with the source electrode 32. The source electrode 32 and the Schottky electrode 34 may be short-circuited by other methods.
　なお本実施の形態においては、ＭＯＳ領域ＲＧ１（図２）が四角形状を有しており、これによりゲート電極３０が格子状に配置されている。これに対応してｐ保護拡散領域１４も格子状に配置されている。しかしながら、ＭＯＳ領域ＲＧ１は四角形状以外の多角形状を有していてもよく、たとえば六角形状を有していてもよい。この場合、ゲート電極はハニカム状に配置され、それに対応してｐ型保護拡散領域もハニカム状に配置され得る。またＭＯＳ領域ＲＧ１は多角形状以外の形状を有していてもよく、たとえば櫛型形状を有していてもよい。 In the present embodiment, the MOS region RG1 (FIG. 2) has a square shape, whereby the gate electrodes 30 are arranged in a lattice shape. Correspondingly, the p protective diffusion regions 14 are also arranged in a lattice pattern. However, MOS region RG1 may have a polygonal shape other than a square shape, for example, a hexagonal shape. In this case, the gate electrode is arranged in a honeycomb shape, and the p-type protective diffusion region can be arranged in a honeycomb shape correspondingly. MOS region RG1 may have a shape other than a polygonal shape, for example, may have a comb shape.
　（製造方法）
　次に、ＭＯＳＦＥＴ９１の製造方法について、以下に説明する。 (Production method)
Next, a method for manufacturing MOSFET 91 will be described below.
　図３を参照して、まず基板１上に半導体層１０が形成される。この時点では、半導体層１０の全体が、上述したｎ-ドリフト領域１１に対応する導電型および不純物濃度を有する。具体的には、ポリタイプ４Ｈを有するｎ型ＳｉＣ基板の（０００１）面上において、ドナー不純物が添加されながらＳｉＣのエピタキシャル成長が行われる。エピタキシャル成長は、たとえばＣＶＤ（化学気相堆積：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により行い得る。半導体層１０の不純物濃度は、基板１の不純物濃度よりも低くされ、たとえば１×１０15ｃｍ-3～１×１０17ｃｍ-3程度とされる。半導体層１０の厚さは、たとえば５～１００μｍ程度とされる。 Referring to FIG. 3, first, semiconductor layer 10 is formed on substrate 1. At this time, the entire semiconductor layer 10 has a conductivity type and an impurity concentration corresponding to the n − drift region 11 described above. Specifically, SiC is epitaxially grown on the (0001) plane of an n-type SiC substrate having polytype 4H while adding a donor impurity. Epitaxial growth can be performed, for example, by a CVD (Chemical Vapor Deposition) method. The impurity concentration of the semiconductor layer 10 is set lower than the impurity concentration of the substrate 1 and is, for example, about 1 × 10 15 cm −3 to 1 × 10 17 cm −3 . The thickness of the semiconductor layer 10 is, for example, about 5 to 100 μm.
　図４を参照して、次に選択的なイオン注入により半導体層１０の一部へ不純物が添加されることで、ｐベース領域１２が形成される。不純物が添加されなかった部分は、そのまま最終的にｎ-ドリフト領域１１となる部分を含む。具体的には、まず半導体層１０の表面にフォトレジストなどにより注入マスクが形成される。このマスクを用いて、アクセプタ不純物であるＡｌがイオン注入により添加される。イオン注入の深さは、半導体層１０の厚さよりも小さく、たとえば０．５～３μｍ程度である。また、イオン注入されるアクセプタ不純物の濃度は、半導体層１０中のドナー不純物の濃度よりも高く、たとえば１×１０17ｃｍ-3～５×１０19ｃｍ-3程度である。イオン注入後、注入マスクは除去される。 Referring to FIG. 4, the p base region 12 is formed by adding impurities to a part of the semiconductor layer 10 by selective ion implantation. The portion to which no impurity is added includes a portion that finally becomes n − drift region 11 as it is. Specifically, an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like. Using this mask, Al, which is an acceptor impurity, is added by ion implantation. The depth of ion implantation is smaller than the thickness of the semiconductor layer 10 and is, for example, about 0.5 to 3 μm. The concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the semiconductor layer 10 and is, for example, about 1 × 10 17 cm −3 to 5 × 10 19 cm −3 . After the ion implantation, the implantation mask is removed.
　図５を参照して、次に選択的なイオン注入によりｐベース領域１２の一部へ不純物が添加されることで、ｎソース領域１３が形成される。不純物が添加されなかった部分が、最終的なｐベース領域１２となる。具体的には、まずｐベース領域１２の表面にフォトレジストなどにより注入マスクが形成される。このマスクを用いて、ドナー不純物であるＮがイオン注入により添加される。イオン注入の深さは、ｐベース領域１２の厚さよりも小さくされる。また、イオン注入されるドナー不純物の濃度は、ｐベース領域１２中のアクセプタ不純物の濃度よりも高く、たとえば１×１０18ｃｍ-3～１×１０21ｃｍ-3程度である。イオン注入後、注入マスクは除去される。 Referring to FIG. 5, an impurity is added to a part of p base region 12 by selective ion implantation, thereby forming n source region 13. The portion to which no impurity is added becomes the final p base region 12. Specifically, an implantation mask is first formed on the surface of the p base region 12 with a photoresist or the like. Using this mask, N as a donor impurity is added by ion implantation. The depth of ion implantation is made smaller than the thickness of the p base region 12. Further, the concentration of the donor impurity to be ion-implanted is higher than the concentration of the acceptor impurity in the p base region 12 and is, for example, about 1 × 10 18 cm −3 to 1 × 10 21 cm −3 . After the ion implantation, the implantation mask is removed.
　図６を参照して、次に半導体層１０にＭＯＳトレンチＴＲ１および複合トレンチＴＲ２が形成される。本実施の形態においては両者が同じ深さを有するので、両者を一括して形成し得る。具体的には、まず半導体層１０の表面上に、ＭＯＳトレンチＴＲ１および複合トレンチＴＲ２に対応する開口を有するエッチングマスクが形成される。エッチングマスクは、たとえばフォトレジストまたはＳｉＯ２により形成し得る。このエッチングマスクを用いたエッチングによりＭＯＳトレンチＴＲ１および複合トレンチＴＲ２が形成される。エッチング後、エッチングマスクは除去される。 Referring to FIG. 6, next, a MOS trench TR <b> 1 and a composite trench TR <b> 2 are formed in the semiconductor layer 10. In the present embodiment, since both have the same depth, both can be formed together. Specifically, first, an etching mask having openings corresponding to the MOS trench TR1 and the composite trench TR2 is formed on the surface of the semiconductor layer 10. Etching mask, for example it may be formed by a photoresist or SiO 2. The MOS trench TR1 and the composite trench TR2 are formed by etching using this etching mask. After the etching, the etching mask is removed.
　図７を参照して、次に選択的なイオン注入により、ＭＯＳトレンチＴＲ１の底部と、複合トレンチＴＲ２の底部の一部との上で、ｎ-ドリフト領域１１へ不純物が添加される。これによりｐ保護拡散領域１４が形成される。具体的には、まず半導体層１０の表面にフォトレジストなどにより注入マスクが形成される。このマスクを用いて、アクセプタ不純物であるＡｌがイオン注入により添加される。イオン注入されるアクセプタ不純物の濃度は、ｎ-ドリフト領域１１中のドナー不純物の濃度よりも高く、たとえば１×１０17ｃｍ-3～１×１０19ｃｍ-3程度である。 Referring to FIG. 7, impurities are added to n − drift region 11 on the bottom of MOS trench TR1 and a part of the bottom of composite trench TR2 by selective ion implantation. Thereby, the p protection diffusion region 14 is formed. Specifically, an implantation mask is first formed on the surface of the semiconductor layer 10 with a photoresist or the like. Using this mask, Al, which is an acceptor impurity, is added by ion implantation. The concentration of the acceptor impurity to be ion-implanted is higher than the concentration of the donor impurity in the n − drift region 11 and is, for example, about 1 × 10 17 cm −3 to 1 × 10 19 cm −3 .
　ｐ保護拡散領域１４は、複合トレンチＴＲ２の底部に接するように複合トレンチＴＲ２の底部に部分的に形成される。すなわちｐ保護拡散領域１４は、複合トレンチＴＲ２の底部に部分的にのみ形成され、底部の一部はｎ-ドリフト領域１１によって形成されたまま保たれる。ｐ保護拡散領域１４はＭＯＳトレンチＴＲ１の底部にも接するように形成されることが好ましいが、ＭＯＳトレンチＴＲ１の底部に接していなくてもＭＯＳトレンチＴＲ１の下方に形成されていればＭＯＳトレンチＴＲ１の底部のゲート絶縁膜２０（図１）の電界を緩和する効果は、ある程度得られる。 The p protective diffusion region 14 is partially formed at the bottom of the composite trench TR2 so as to be in contact with the bottom of the composite trench TR2. That is, the p protective diffusion region 14 is formed only partially at the bottom of the composite trench TR2, and a part of the bottom is kept formed by the n − drift region 11. The p protective diffusion region 14 is preferably formed so as to be in contact with the bottom of the MOS trench TR1, but even if it is not in contact with the bottom of the MOS trench TR1, it may be formed under the MOS trench TR1. The effect of relaxing the electric field of the bottom gate insulating film 20 (FIG. 1) can be obtained to some extent.
　次に、熱処理装置によって、アルゴン（Ａｒ）ガスなどの不活性ガス雰囲気中で、１３００～１９００℃で、３０秒～１時間にわたって、アニールが行われる。このアニールにより、イオン注入された不純物が電気的に活性化される。 Next, annealing is performed in an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour by a heat treatment apparatus. By this annealing, the ion-implanted impurity is electrically activated.
　図８を参照して、次に、半導体層１０の表面が熱酸化される。これにより、所望の厚さのゲート絶縁膜２０としての酸化珪素膜が形成される。 Referring to FIG. 8, next, the surface of the semiconductor layer 10 is thermally oxidized. Thereby, a silicon oxide film as the gate insulating film 20 having a desired thickness is formed.
　図９を参照して、次に、まずゲート絶縁膜２０の上に、導電性を有する多結晶珪素膜が減圧ＣＶＤ法により形成される。この多結晶珪素膜をパターニングすることによりゲート電極３０が形成される。 Referring to FIG. 9, next, a polycrystalline silicon film having conductivity is first formed on gate insulating film 20 by a low pressure CVD method. Gate electrode 30 is formed by patterning this polycrystalline silicon film.
　図１０を参照して、次に、まず層間絶縁膜２１が減圧ＣＶＤ法により成膜される。続いて、層間絶縁膜２１がパターニングされることにより、ソースコンタクトホールＣＨ１およびトレンチ内コンタクトホールＣＨ２が形成される。 Referring to FIG. 10, next, an interlayer insulating film 21 is first formed by a low pressure CVD method. Subsequently, the interlayer insulating film 21 is patterned to form the source contact hole CH1 and the in-trench contact hole CH2.
　図１１を参照して、次に、トレンチ内コンタクトホールＣＨ２内で複合トレンチＴＲ２の底部上に部分的にショットキー電極３４が、ｎ-ドリフト領域１１にショットキー接合されるように形成される。本実施の形態のようにｎ型を有するｎ-ドリフト領域１１上にショットキー電極が形成される場合、その材料としては、Ｔｉ、ＭｏまたはＮｉなどが好ましい。 Referring to FIG. 11, next, Schottky electrode 34 is formed so as to be partially Schottky joined to n − drift region 11 on the bottom of composite trench TR2 in contact hole CH2 in the trench. When a Schottky electrode is formed on n − drift region 11 having n type as in the present embodiment, the material is preferably Ti, Mo, Ni, or the like.
　図１２を参照して、次に、層間絶縁膜２１およびショットキー電極３４が設けられた半導体層１０上にソース電極３２が形成される。ソース電極３２は、ソースコンタクトホールＣＨ１およびトレンチ内コンタクトホールＣＨ２において半導体層１０にオーミック接合される。 Referring to FIG. 12, next, source electrode 32 is formed on semiconductor layer 10 provided with interlayer insulating film 21 and Schottky electrode 34. The source electrode 32 is ohmically joined to the semiconductor layer 10 in the source contact hole CH1 and the in-trench contact hole CH2.
　再び図１を参照して、次に、基板１の他方面（図１における下面）上にドレイン電極３１が形成される。以上により、ＭＯＳＦＥＴ９１が得られる。 Referring to FIG. 1 again, next, drain electrode 31 is formed on the other surface (lower surface in FIG. 1) of substrate 1. Thus, MOSFET 91 is obtained.
　なお上記方法においてはソース電極３２とショットキー電極３４とが個別に作製されるが、これらが同一材料で連続して形成されてもよい。あるいは、ソース電極３２とショットキー電極３４とが別材料から作られつつ、それらの境界において材料が連続的に変化してもよい。 In the above method, the source electrode 32 and the Schottky electrode 34 are individually manufactured, but they may be continuously formed of the same material. Alternatively, the source electrode 32 and the Schottky electrode 34 may be made of different materials, and the material may continuously change at the boundary between them.
　またｐベース領域１２およびｎソース領域１３を形成するためのイオン注入工程の順番は逆にされてもよい。 Further, the order of the ion implantation steps for forming the p base region 12 and the n source region 13 may be reversed.
　（動作）
　次にＭＯＳＦＥＴ９１の動作について、以下に説明する。 (Operation)
Next, the operation of the MOSFET 91 will be described below.
　ゲート電極３０にしきい値電圧以上の正電圧が印加されると、ゲート電極３０の側面のｐベース領域１２（チャネル領域）に反転チャネル層が形成される。この反転チャネル層は、ｎソース領域１３からｎ-ドリフト領域１１へとキャリアとしての電子が流れる経路となる。反転チャネル層を通ってｎソース領域１３からｎ-ドリフト領域１１へ流れ込んだ電子は、ドレイン電極３１の正電圧により生じた電界に従い、基板１を通過してドレイン電極３１に到達する。その結果、ＭＯＳＦＥＴ９１は、ドレイン電極３１からソース電極３２へと電流を流すことができるようになる。この状態がＭＯＳＦＥＴ９１のオン状態である。 When a positive voltage higher than the threshold voltage is applied to the gate electrode 30, an inversion channel layer is formed in the p base region 12 (channel region) on the side surface of the gate electrode 30. The inversion channel layer serves as a path for electrons as carriers to flow from the n source region 13 to the n − drift region 11. Electrons flowing from the n source region 13 to the n − drift region 11 through the inversion channel layer pass through the substrate 1 and reach the drain electrode 31 according to the electric field generated by the positive voltage of the drain electrode 31. As a result, the MOSFET 91 can flow a current from the drain electrode 31 to the source electrode 32. This state is the ON state of the MOSFET 91.
　一方、ゲート電極３０にしきい値電圧よりも低い電圧が印加されているときは、チャネル領域に反転チャネルが形成されないため、ドレイン電極３１とソース電極３２との間には電流が流れない。この状態がＭＯＳＦＥＴのオフ状態である。オフ状態にあるＭＯＳＦＥＴ９１に高電圧が印加されると、ＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の底部においてゲート絶縁膜２０に高電界が印加され得る。本実施の形態ではｐ保護拡散領域１４によりオフ状態においてゲート絶縁膜２０に印加される電界が緩和される。 On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 30, no inversion channel is formed in the channel region, so that no current flows between the drain electrode 31 and the source electrode 32. This state is the MOSFET off state. When a high voltage is applied to the MOSFET 91 in the off state, a high electric field can be applied to the gate insulating film 20 at the bottom of the MOS trench TR1 and the composite trench TR2. In the present embodiment, the p protective diffusion region 14 reduces the electric field applied to the gate insulating film 20 in the off state.
　さらに、ソース電極３２の電位よりも低い電位がドレイン電極３１にＭＯＳＦＥＴ９１の外部から印加されると、言い換えればＭＯＳＦＥＴ９１に逆起電圧が印加されると、ソース電極３２からドレイン電極３１に向かって還流電流が流れる還流状態が生じる。還流状態においては、ドレイン電極３１に高電圧が印加され、それによりＭＯＳトレンチＴＲ１および複合トレンチＴＲ２の底部においてゲート絶縁膜２０に高電界が印加され得る。本実施の形態ではｐ保護拡散領域１４により、ゲート絶縁膜２０に印加される電界が還流状態においても緩和される。 Furthermore, when a potential lower than the potential of the source electrode 32 is applied to the drain electrode 31 from the outside of the MOSFET 91, in other words, when a counter electromotive voltage is applied to the MOSFET 91, the return current from the source electrode 32 toward the drain electrode 31. A reflux condition occurs. In the reflux state, a high voltage is applied to the drain electrode 31, whereby a high electric field can be applied to the gate insulating film 20 at the bottom of the MOS trench TR1 and the composite trench TR2. In the present embodiment, the p protective diffusion region 14 relieves the electric field applied to the gate insulating film 20 even in the reflux state.
　還流状態においては、ショットキー電極３４によるショットキー接合に順方向の電界（順バイアス）が印加されることで、ショットキー電極３４からドレイン電極３１へ、電子電流からなるユニポーラ電流が流れる。順バイアスが小さいときは、還流ダイオードの還流電流成分はこのユニポーラ成分のみである。ショットキー電極３４を通って流れる電子電流の密度が大きくなると、ユニポーラ電流が流れるショットキー電極３４下方のｎ-ドリフト領域１１における電圧降下が大きくなる。よってｎ-ドリフト領域１１の電位は、オーミック接合によってソース電極３２の電位とほぼ同じ電位を有するｐ保護拡散領域１４の電位に対して低くなる。この結果、ｐ保護拡散領域１４とｎ-ドリフト領域１１との間のｐｎ接合に印加される順バイアスが大きくなる。この順バイアスがｐｎ接合の拡散電位を超えたときに、ｐ保護拡散領域１４からｎ-ドリフト領域１１に向かって正孔（ホール）の注入が生じる。すなわち、ｐ保護拡散領域１４とｎ型のｎ-ドリフト領域１１とによる寄生ｐｎダイオードが動作することで、少数キャリアの注入（バイポーラ動作）が生じる。つまり、還流ダイオードの電流成分として、ユニポーラ電流だけでなくバイポーラ電流が加わる。この現象が生じるしきい値電流がＭＯＳＦＥＴ９１の最大ユニポーラ電流である。 In the reflux state, a forward electric field (forward bias) is applied to the Schottky junction by the Schottky electrode 34, whereby a unipolar current consisting of an electron current flows from the Schottky electrode 34 to the drain electrode 31. When the forward bias is small, the return current component of the return diode is only this unipolar component. As the density of the electron current flowing through the Schottky electrode 34 increases, the voltage drop in the n − drift region 11 below the Schottky electrode 34 through which the unipolar current flows increases. Therefore, the potential of the n − drift region 11 becomes lower than the potential of the p protective diffusion region 14 having substantially the same potential as that of the source electrode 32 due to the ohmic junction. As a result, the forward bias applied to the pn junction between the p protective diffusion region 14 and the n − drift region 11 increases. When this forward bias exceeds the diffusion potential of the pn junction, holes are injected from the p protective diffusion region 14 toward the n − drift region 11. That is, minority carrier injection (bipolar operation) occurs when the parasitic pn diode is operated by the p protection diffusion region 14 and the n-type n − drift region 11. That is, not only a unipolar current but also a bipolar current is added as a current component of the freewheeling diode. The threshold current at which this phenomenon occurs is the maximum unipolar current of MOSFET 91.
　（比較例）
　図１３を参照して、比較例のＭＯＳＦＥＴ９０においては、ＭＯＳＦＥＴ９１（図１）と異なり、複合トレンチＴＲ２が設けられておらず、ショットキー電極３４はｎ-ドリフト領域１１の最表面上に配置されている。言い換えれば、ショットキー電極３４が、ＭＯＳトレンチＴＲ１の開口部の高さに配置されている。これに伴って、ショットキー電極３４によって構成されるショットキーバリアダイオードの電流経路には、ＭＯＳトレンチＴＲ１の深さに応じた抵抗成分が発生する。特に、ｎ-ドリフト領域１１中を通る電流経路のうちショットキー電極３４のすぐ下方の、ｐベース領域１２によって挟まれた部分ＳＱは、ｐベース領域１２から延びる空乏層による狭窄を受ける。よってこの部分の存在による抵抗成分の増大は特に大きい。ショットキーバリアダイオードの電流経路の抵抗成分が大きくなるほど、ショットキーバリアダイオードのオン抵抗が増大し、その結果、寄生ｐｎダイオードによる電流が流れ始めやすくなる。よって最大ユニポーラ電流が小さくなる。 (Comparative example)
Referring to FIG. 13, in MOSFET 90 of the comparative example, unlike MOSFET 91 (FIG. 1), composite trench TR <b> 2 is not provided, and Schottky electrode 34 is disposed on the outermost surface of n − drift region 11. Yes. In other words, the Schottky electrode 34 is disposed at the height of the opening of the MOS trench TR1. Accordingly, a resistance component corresponding to the depth of the MOS trench TR1 is generated in the current path of the Schottky barrier diode constituted by the Schottky electrode 34. In particular, a portion SQ sandwiched between the p base regions 12 and immediately below the Schottky electrode 34 in the current path passing through the n − drift region 11 is constricted by a depletion layer extending from the p base region 12. Therefore, the increase in resistance component due to the presence of this portion is particularly large. As the resistance component of the current path of the Schottky barrier diode increases, the on-resistance of the Schottky barrier diode increases, and as a result, current due to the parasitic pn diode starts to flow easily. Therefore, the maximum unipolar current is reduced.
　これに対して本実施の形態のＭＯＳＦＥＴ９１（図１）においては、ショットキー電極３４がｎ-ドリフト領域１１に複合トレンチＴＲ２の底部で接合されている。言い換えれば、ショットキー電極３４が、複合トレンチＴＲ２の底部の高さに配置されている。よって、ショットキー電極３４によって構成されるショットキーバリアダイオードの電流経路は、ｐ保護拡散領域１４による寄生ｐｎダイオードの電流経路と同様に、トレンチの深さに応じた抵抗成分を有しない。特に、電流経路がｐベース領域１２によって狭窄されないことで、抵抗成分の増大が避けられる。ショットキーバリアダイオードの電流経路の抵抗成分が抑えられるほど、ショットキーバリアダイオードのオン抵抗が減少し、その結果、寄生ｐｎダイオードによる電流が流れ始めにくくなる。よって、最大ユニポーラ電流が大きくなる。 In contrast, in MOSFET 91 (FIG. 1) of the present embodiment, Schottky electrode 34 is joined to n − drift region 11 at the bottom of composite trench TR2. In other words, the Schottky electrode 34 is arranged at the height of the bottom of the composite trench TR2. Therefore, the current path of the Schottky barrier diode constituted by the Schottky electrode 34 does not have a resistance component corresponding to the depth of the trench, like the current path of the parasitic pn diode by the p protection diffusion region 14. In particular, since the current path is not narrowed by the p base region 12, an increase in the resistance component can be avoided. As the resistance component of the current path of the Schottky barrier diode is suppressed, the on-resistance of the Schottky barrier diode is reduced, and as a result, the current due to the parasitic pn diode does not easily start to flow. Therefore, the maximum unipolar current is increased.
　（効果のまとめ）
　本実施の形態のＭＯＳＦＥＴ９１によれば、第１に、ＭＯＳＦＥＴ９１がオフ状態のとき、ｎ-ドリフト領域１１とｐ保護拡散領域１４との間のｐｎ接合から空乏層が延びることにより、ＭＯＳトレンチＴＲ１の底部においてゲート絶縁膜２０に加わる電界が緩和される。これにより、オフ状態におけるゲート絶縁膜２０の絶縁破壊を防止することができる。第２に、ショットキー電極３４がｎ-ドリフト領域１１に複合トレンチＴＲ２の底部上でショットキー接続されている。これにより、ショットキー電極３４がトレンチの外部においてｎ-ドリフト領域１１にショットキー接続される場合と異なり、ｎ-ドリフト領域１１とｐ保護拡散領域１４とによる寄生ｐｎダイオードの電流経路と同様に、ショットキーバリアダイオードの電流経路は、複合トレンチＴＲ２の深さに対応した抵抗成分を有しない。これにより、ショットキー電極３４によってＭＯＳＦＥＴ９１に内蔵されるショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる。以上から、オフ状態におけるゲート絶縁膜２０の絶縁破壊を防止することができ、かつ内蔵ショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる。 (Summary of effects)
According to the MOSFET 91 of the present embodiment, first, when the MOSFET 91 is in the OFF state, the depletion layer extends from the pn junction between the n − drift region 11 and the p protective diffusion region 14, so that the MOS trench TR 1 The electric field applied to the gate insulating film 20 at the bottom is relaxed. Thereby, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented. Second, the Schottky electrode 34 is Schottky connected to the n − drift region 11 on the bottom of the composite trench TR2. As a result, unlike the case where the Schottky electrode 34 is Schottky connected to the n − drift region 11 outside the trench, the current path of the parasitic pn diode by the n − drift region 11 and the p protective diffusion region 14 is The current path of the Schottky barrier diode does not have a resistance component corresponding to the depth of the composite trench TR2. Thereby, the maximum unipolar current of the Schottky barrier diode built in the MOSFET 91 can be increased by the Schottky electrode 34. From the above, the dielectric breakdown of the gate insulating film 20 in the off state can be prevented, and the maximum unipolar current of the built-in Schottky barrier diode can be increased.
　最大ユニポーラ電流が大きいことにより、ユニポーラ電流のみからなる還流電流の電流容量を大きくすることができる。これにより、大きな還流電流が流れても、バイポーラ電流が流れないか、またはその大きさが抑制される。これよりリカバリ損失が抑えられる。よってＭＯＳＦＥＴ９１における電力損失を抑えることができる。 大 き い Since the maximum unipolar current is large, it is possible to increase the current capacity of the return current consisting only of the unipolar current. Thereby, even if a large return current flows, the bipolar current does not flow or its magnitude is suppressed. This reduces recovery loss. Therefore, power loss in MOSFET 91 can be suppressed.
　ｐ保護拡散領域１４はソース電極３２とオーミックに接続されている。これにより、ＭＯＳＦＥＴ９１のスイッチング動作時においてもｐ保護拡散領域１４の電位が安定化される。よってターンオフなどのスイッチング動作時におけるゲート絶縁膜２０の絶縁破壊の発生を抑制することができる。 The p protective diffusion region 14 is ohmically connected to the source electrode 32. As a result, the potential of the p protection diffusion region 14 is stabilized even during the switching operation of the MOSFET 91. Therefore, the occurrence of dielectric breakdown of the gate insulating film 20 during a switching operation such as turn-off can be suppressed.
　スイッチング動作時には、ドレイン電極３１の電圧が急激に上昇するため、ｐ保護拡散領域１４とｎ-ドリフト領域１１との間の寄生容量を介して変位電流がｐ保護拡散領域１４を流れる。このときｐ保護拡散領域１４など変位電流が流れる経路の抵抗成分によって電圧降下が生じる。この電圧降下が大きくなると、ゲート絶縁膜２０の絶縁破壊またはリーク電流の発生など、ゲート絶縁膜２０の信頼性の低下につながる現象が生じやすくなる。これを防止するためには、変位電流が流れる経路の抵抗値を小さくすることが有効である。 During the switching operation, the voltage of the drain electrode 31 rises rapidly, so that a displacement current flows through the p protective diffusion region 14 via the parasitic capacitance between the p protective diffusion region 14 and the n − drift region 11. At this time, a voltage drop occurs due to the resistance component of the path through which the displacement current flows, such as the p protection diffusion region 14. When this voltage drop becomes large, a phenomenon that leads to a decrease in the reliability of the gate insulating film 20, such as dielectric breakdown of the gate insulating film 20 or generation of a leakage current, is likely to occur. In order to prevent this, it is effective to reduce the resistance value of the path through which the displacement current flows.
　図１および図２に示された構成においては、格子状のゲート電極３０により規定される区画（セル）の少なくとも１つが、ソース電極３２とｐ保護拡散領域１４との間を接続するコンタクトを設けるためのコンタクト領域ＲＧ２として用いられている。これによりソース電極３２とｐ保護拡散領域１４との間の接触面積を大きくとることができる。よってソース電極３２とｐ保護拡散領域１４との間の抵抗値が小さくなる。よってｐ保護拡散領域１４からソース電極３２へと流れる変位電流の経路の抵抗値が小さくなる。よって、変位電流に起因するゲート絶縁膜２０の破壊をより確実に防止することができる。 In the configuration shown in FIGS. 1 and 2, at least one of the sections (cells) defined by the grid-like gate electrode 30 is provided with a contact that connects between the source electrode 32 and the p protective diffusion region 14. Is used as a contact region RG2. As a result, the contact area between the source electrode 32 and the p protective diffusion region 14 can be increased. Therefore, the resistance value between the source electrode 32 and the p protective diffusion region 14 becomes small. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 becomes small. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current.
　コンタクト領域ＲＧ２内のｐ保護拡散領域１４がその周囲のＭＯＳ領域ＲＧ１内のすべてのｐ保護拡散領域１４とつながっているので、格子状のゲート電極３０で規定される区画の少なくとも１つをコンタクト領域ＲＧ２のために用いれば、ｐ保護拡散領域１４全体をソース電極３２にオーミック接続することができる。ただし、多くのＭＯＳＦＥＴセルを有する装置においては、各ＭＯＳＦＥＴセルからコンタクト領域ＲＧ２までの距離が過度に長くならないように、単数ではなく複数のコンタクト領域ＲＧ２が設けられることが好ましい。その場合、ＭＯＳＦＥＴ９１における電流の経路がなるべく均一になるように、コンタクト領域ＲＧ２は等間隔に配置されることが好ましい。 Since the p protection diffusion region 14 in the contact region RG2 is connected to all the p protection diffusion regions 14 in the surrounding MOS region RG1, at least one of the sections defined by the lattice-like gate electrode 30 is defined as the contact region. When used for RG2, the entire p protection diffusion region 14 can be ohmically connected to the source electrode 32. However, in a device having many MOSFET cells, it is preferable to provide a plurality of contact regions RG2 instead of a single one so that the distance from each MOSFET cell to contact region RG2 does not become excessively long. In that case, the contact regions RG2 are preferably arranged at equal intervals so that the current paths in the MOSFET 91 are as uniform as possible.
　また本実施の形態によれば、ＭＯＳトレンチＴＲ１の大きさと、複合トレンチＴＲ２の大きさとを個別に最適化することができる。第１に、複合トレンチＴＲ２の大きさの調整によってソース電極３２とｐ保護拡散領域１４との間の接触面積を最適化することができる。これにより、ｐ保護拡散領域１４へのソース電極３２のコンタクト抵抗を、必要に応じて小さくすることができる。よってｐ保護拡散領域１４からソース電極３２へと流れる変位電流の経路の抵抗値を十分に小さくすることができる。よって、変位電流に起因するゲート絶縁膜２０の破壊をより確実に防止することができる。これによりＭＯＳＦＥＴ９１の耐電圧が高められる。第２に、ＭＯＳトレンチＴＲ１の大きさの最適化によってＭＯＳトレンチＴＲ１のセルピッチ（トレンチの幅）を十分に小さくすることができる。これにより、ＭＯＳＦＥＴ９１の単位面積当たりのオン電流の密度を高めることができる。よって、ＭＯＳＦＥＴ９１の電流容量を大きくすることができる。以上のように本実施の形態によれば、電流容量を確保しつつ、耐電圧を高めることができる。 Further, according to the present embodiment, the size of the MOS trench TR1 and the size of the composite trench TR2 can be individually optimized. First, the contact area between the source electrode 32 and the p protective diffusion region 14 can be optimized by adjusting the size of the composite trench TR2. Thereby, the contact resistance of the source electrode 32 to the p protection diffusion region 14 can be reduced as necessary. Therefore, the resistance value of the path of the displacement current flowing from the p protection diffusion region 14 to the source electrode 32 can be sufficiently reduced. Therefore, it is possible to more reliably prevent the gate insulating film 20 from being destroyed due to the displacement current. As a result, the withstand voltage of the MOSFET 91 is increased. Second, by optimizing the size of the MOS trench TR1, the cell pitch (trench width) of the MOS trench TR1 can be made sufficiently small. Thereby, the density of the on-current per unit area of the MOSFET 91 can be increased. Therefore, the current capacity of the MOSFET 91 can be increased. As described above, according to the present embodiment, the withstand voltage can be increased while securing the current capacity.
　また、図１に示すように、ＭＯＳトレンチＴＲ１だけでなく、複合トレンチＴＲ２の側部にもＭＯＳＦＥＴ構造が設けられる。これにより、複合トレンチＴＲ２にＭＯＳＦＥＴ構造が設けられない場合に比して、ＭＯＳＦＥＴ９１の電流容量を大きくすることができる。なお、複合トレンチＴＲ２内のＭＯＳ構造は省略されてもよく、この場合、複合トレンチＴＲ２中の構造を簡素化することができる。 Further, as shown in FIG. 1, a MOSFET structure is provided not only in the MOS trench TR1 but also in the side portion of the composite trench TR2. Thereby, the current capacity of the MOSFET 91 can be increased as compared with the case where the MOSFET structure is not provided in the composite trench TR2. Note that the MOS structure in the composite trench TR2 may be omitted. In this case, the structure in the composite trench TR2 can be simplified.
　またｐ保護拡散領域１４（図１）は、複合トレンチＴＲ２の底部の一方端および他方端のそれぞれを覆う第１の部分および第２の部分を有している。これにより、複合トレンチＴＲ２の底部の一方端および他方端の両方での電界を効果的に緩和することができる。よって、複合トレンチＴＲ２の側部に設けられたＭＯＳＦＥＴ構造を構成するゲート絶縁膜２０の絶縁破壊を、より確実に防止することができる。 The p protective diffusion region 14 (FIG. 1) has a first portion and a second portion that respectively cover one end and the other end of the bottom of the composite trench TR2. Thereby, the electric field at both one end and the other end of the bottom of the composite trench TR2 can be effectively relaxed. Therefore, it is possible to more reliably prevent the dielectric breakdown of the gate insulating film 20 constituting the MOSFET structure provided on the side portion of the composite trench TR2.
　ｎ-ドリフト領域１１がワイドバンドギャップ半導体から作られている場合、ｎ-ドリフト領域１１自体の耐電圧が高いことから、ｎ-ドリフト領域１１がＳｉなどの非ワイドバンドギャップ半導体から作られている場合に比して、オフ状態においてｎ-ドリフト領域１１に高い電界（たとえば約１０倍）が印加され得る。その場合、ＭＯＳトレンチＴＲ１の底部においてゲート絶縁膜２０に高い電界が印加される。この高電界に起因したゲート絶縁膜２０の絶縁破壊の発生をｐ保護拡散領域１４によって効果的に抑制することができる。 When the n − drift region 11 is made of a wide band gap semiconductor, since the withstand voltage of the n − drift region 11 itself is high, the n − drift region 11 is made of a non-wide band gap semiconductor such as Si. As compared to the case, a high electric field (for example, about 10 times) can be applied to the n − drift region 11 in the off state. In that case, a high electric field is applied to the gate insulating film 20 at the bottom of the MOS trench TR1. Generation of dielectric breakdown of the gate insulating film 20 due to the high electric field can be effectively suppressed by the p protective diffusion region 14.
　またｎ-ドリフト領域１１がワイドバンドギャップ半導体から作られている場合は、ｎ-ドリフト領域１１がＳｉなどの非ワイドバンドギャップ半導体から作られている場合と異なり、スイッチング動作時におけるゲート絶縁膜２０の信頼性が問題となり得る。これは、第１に、変位電流が流れる経路の抵抗が大きいことによる。第２に、Ｓｉを用いたＭＯＳＦＥＴと同じスイッチング速度でのスイッチング動作時に生じる変位電流が大きいことによる。たとえば、耐電圧の性能を変えずに半導体材料をＳｉからＳｉＣに変更した場合、空乏容量が約１０倍大きくなるため、それに対応して変位電流も大幅に大きくなる。本実施の形態によれば、前述したように変位電流が流れる経路の抵抗値を小さくすることができるので、ワイドバンドギャップ半導体を用いた場合においても、高速スイッチング動作時におけるゲート絶縁膜２０の信頼性をより確実に保つことができる。 The n - if the drift region 11 is made of wide band gap semiconductor, n - unlike the case of the drift region 11 is made of a non-wide band gap semiconductor, such as Si, a gate insulating film 20 at the time of switching operation Reliability can be a problem. First, this is because the resistance of the path through which the displacement current flows is large. Second, the displacement current generated during the switching operation at the same switching speed as the MOSFET using Si is large. For example, when the semiconductor material is changed from Si to SiC without changing the withstand voltage performance, the depletion capacity is increased about 10 times, and the displacement current is correspondingly increased correspondingly. According to the present embodiment, since the resistance value of the path through which the displacement current flows can be reduced as described above, the reliability of the gate insulating film 20 during the high-speed switching operation can be achieved even when a wide band gap semiconductor is used. Sex can be maintained more reliably.
　またＭＯＳトレンチＴＲ１の深さと複合トレンチＴＲ２の深さとが同じであることにより、両者を一括して形成することができる。またＭＯＳトレンチＴＲ１の深さと複合トレンチＴＲ２の深さとが同程度の場合、複合トレンチＴＲ２の底部のｐ保護拡散領域１４から、近傍のＭＯＳトレンチＴＲ１の底部のゲート絶縁膜２０へと、空乏層が到達しやすい。よって、複合トレンチＴＲ２と隣り合うＭＯＳトレンチＴＲ１の底部において、ゲート絶縁膜２０に印加される電界がさらに緩和される。よってゲート絶縁膜２０の絶縁破壊をより確実に防止することができる。 Further, since the depth of the MOS trench TR1 and the depth of the composite trench TR2 are the same, both can be formed at a time. When the depth of the MOS trench TR1 and the depth of the composite trench TR2 are approximately the same, a depletion layer is formed from the p protection diffusion region 14 at the bottom of the composite trench TR2 to the gate insulating film 20 at the bottom of the neighboring MOS trench TR1. Easy to reach. Therefore, the electric field applied to the gate insulating film 20 is further relaxed at the bottom of the MOS trench TR1 adjacent to the composite trench TR2. Therefore, the dielectric breakdown of the gate insulating film 20 can be prevented more reliably.
　ただし、ＭＯＳトレンチＴＲ１の深さと複合トレンチＴＲ２の深さとは互いに異なっていてもよく、この場合、ＭＯＳトレンチＴＲ１と複合トレンチＴＲ２とが個別の工程で形成されればよい。複合トレンチＴＲ２の深さがＭＯＳトレンチＴＲ１の深さより浅くても、ｐベース領域１２の表面より深く形成されさえしていれば、ｐベース領域１２の表面の高さ、すなわちトレンチ開口部の高さにショットキー電極３４が形成される場合（図１３：比較例）と比較して最大ユニポーラ電流を増大する効果が得られる。複合トレンチＴＲ２がＭＯＳトレンチＴＲ１よりも深い場合には、最大ユニポーラ電流をより大きくする効果が得られる。ただしショットキー電極３４の位置が深過ぎると、ショットキー電極３４がドレイン電極３１に近くなるので、ショットキー電極３４の耐電圧あるいはＭＯＳＦＥＴの耐電圧の低下につながる。最大ユニポーラ電流を十分に大きくしつつ耐電圧を確保するためには、複合トレンチＴＲ２の底部の位置、すなわちショットキー電極３４のショットキー接続の位置、は、ＭＯＳトレンチＴＲ１の底部より深いことが好ましく、またＭＯＳトレンチＴＲ１の底部に配置されたｐ保護拡散領域１４よりも浅いことが好ましい。 However, the depth of the MOS trench TR1 and the depth of the composite trench TR2 may be different from each other. In this case, the MOS trench TR1 and the composite trench TR2 may be formed in separate steps. Even if the depth of the composite trench TR2 is shallower than the depth of the MOS trench TR1, as long as it is formed deeper than the surface of the p base region 12, the height of the surface of the p base region 12, that is, the height of the trench opening. As compared with the case where the Schottky electrode 34 is formed (FIG. 13: comparative example), the effect of increasing the maximum unipolar current can be obtained. When the composite trench TR2 is deeper than the MOS trench TR1, an effect of increasing the maximum unipolar current can be obtained. However, if the position of the Schottky electrode 34 is too deep, the Schottky electrode 34 is close to the drain electrode 31, leading to a decrease in the withstand voltage of the Schottky electrode 34 or the withstand voltage of the MOSFET. In order to ensure a withstand voltage while sufficiently increasing the maximum unipolar current, the bottom position of the composite trench TR2, that is, the Schottky connection position of the Schottky electrode 34, is preferably deeper than the bottom of the MOS trench TR1. Moreover, it is preferable that the depth is shallower than the p protective diffusion region 14 disposed at the bottom of the MOS trench TR1.
　ＭＯＳトレンチＴＲ１は、図１に示すように、ｐ保護拡散領域１４の幅と同じ幅を有していてよい。これにより、ｐ保護拡散領域１４を容易に形成することができる。 The MOS trench TR1 may have the same width as that of the p protection diffusion region 14 as shown in FIG. Thereby, the p protective diffusion region 14 can be easily formed.
　なお上記においては、ＭＯＳトレンチＴＲ１が平面視で格子状（図１４）の配置を有する場合について説明した。言い換えれば、ＭＯＳトレンチＴＲ１が、一の方向（図中、横方向）において平行に延びる複数のパターンと、この方向に直交する方向（図中、縦方向）において平行に延びる複数のパターンとを有する場合について説明した。しかしながら、他の配置が用いられてもよい。たとえば、平面視で千鳥格子状の配置を有するＭＯＳトレンチＴＲ１Ｚ（図１５）が用いられてもよい。千鳥格子状の配置を有するＭＯＳトレンチＴＲ１Ｚは、一の方向（図中、横方向）において平行に延びる複数のパターンと、この方向に直交する方向（図中、縦方向）において千鳥状に延びる複数のパターンとを有している。また、たとえば、平面視で櫛状の配置を有するＭＯＳトレンチＴＲ１Ｓ（図１６）が用いられてもよい。櫛状の配置を有するＭＯＳトレンチＴＲ１Ｓは、互いに平行に延びる複数の櫛歯パターンを有している。なお、櫛歯パターンの各々の端部（図示せず）をつなぐパターンが設けられていてもよい。また、たとえば、平面視で六角形状の配置を有するＭＯＳトレンチ（図示せず）が用いられてもよい。 In the above description, the case where the MOS trench TR1 has a grid-like arrangement (FIG. 14) in plan view has been described. In other words, the MOS trench TR1 has a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and a plurality of patterns extending in parallel in a direction orthogonal to this direction (vertical direction in the figure). Explained the case. However, other arrangements may be used. For example, a MOS trench TR1Z (FIG. 15) having a staggered arrangement in plan view may be used. MOS trench TR1Z having a staggered arrangement extends in a zigzag manner in a plurality of patterns extending in parallel in one direction (lateral direction in the figure) and in a direction orthogonal to this direction (vertical direction in the figure). A plurality of patterns. Further, for example, a MOS trench TR1S (FIG. 16) having a comb-like arrangement in plan view may be used. The MOS trench TR1S having a comb-like arrangement has a plurality of comb patterns extending in parallel to each other. In addition, the pattern which connects each edge part (not shown) of a comb-tooth pattern may be provided. Further, for example, a MOS trench (not shown) having a hexagonal arrangement in plan view may be used.
　＜実施の形態２＞
　図１７を参照して、本実施の形態におけるＭＯＳＦＥＴ９２（電力用半導体装置）は、実施の形態１においてｎ-ドリフト領域１１ｄ（図１）が配置されていた領域に、ｎ型のｎ領域１１Ａ（第１の半導体領域）を有している。ｎ領域１１Ａは、ｎ-ドリフト領域１１e（ドリフト領域）と、ｎ+高濃度領域１１ｈ（高濃度領域）とを有している。 <Embodiment 2>
Referring to FIG. 17, MOSFET 92 (power semiconductor device) in the present embodiment has n-type n region 11A (in the region where n − drift region 11d (FIG. 1) is disposed in the first embodiment. A first semiconductor region). The n region 11A has an n − drift region 11e (drift region) and an n + high concentration region 11h (high concentration region).
　ｎ+高濃度領域１１ｈは、ショットキー電極３４に接している。ｎ+高濃度領域１１ｈの実効的な不純物濃度は、ｎ-ドリフト領域１１ｅの不純物濃度よりも高く、たとえば１×１０17ｃｍ-3～１×１０19ｃｍ-3程度である。好ましくは、ｎ+高濃度領域１１ｈの実効的な不純物濃度は、ｐ保護拡散領域１４の実効的な不純物濃度よりも低い。ここで「実効的な不純物濃度」とは、アクセプタ濃度とドナー濃度との差分の絶対値を意味する。好ましくは、ｎ+高濃度領域１１ｈは、基板１から離れている。 The n + high concentration region 11 h is in contact with the Schottky electrode 34. The effective impurity concentration of the n + high concentration region 11h is higher than the impurity concentration of the n − drift region 11e, and is, for example, about 1 × 10 17 cm −3 to 1 × 10 19 cm −3 . Preferably, the effective impurity concentration of the n + high concentration region 11 h is lower than the effective impurity concentration of the p protective diffusion region 14. Here, “effective impurity concentration” means the absolute value of the difference between the acceptor concentration and the donor concentration. Preferably, the n + high concentration region 11 h is separated from the substrate 1.
　ｎ-ドリフト領域１１eは、ｎ領域１１Ａのうちｎ+高濃度領域１１ｈ以外の領域である。ｎ-ドリフト領域１１eは、実施の形態１におけるｎ-ドリフト領域１１ｄと同様の不純物濃度を有していてよい。 The n − drift region 11e is a region other than the n + high concentration region 11h in the n region 11A. N − drift region 11 e may have the same impurity concentration as n − drift region 11 d in the first embodiment.
　なお、上記以外の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.
　ショットキー電極３４によって構成された内蔵ショットキーバリアダイオードの電流経路は、複合トレンチＴＲ２の底部に設けられたｐ保護拡散領域１４の開口部を通る。前述したＭＯＳＦＥＴ９１（図１：実施の形態１）においては、この開口部に、低い不純物濃度を有するｎ-ドリフト領域１１ｄが配置されている。この場合、還流状態において、ｐ保護拡散領域１４から開口部内へ空乏層が延びやすく、その結果、開口部を通る電流経路が狭窄されることに起因して最大ユニポーラ電流が小さくなる。このため、十分な最大ユニポーラ電流を確保するためには、ｐ保護拡散領域１４の開口部を大きくしなければならない。この結果、ＭＯＳＦＥＴ９１の面積が大きくなる。 The current path of the built-in Schottky barrier diode formed by the Schottky electrode 34 passes through the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2. In the above-described MOSFET 91 (FIG. 1: Embodiment 1), an n − drift region 11 d having a low impurity concentration is disposed in this opening. In this case, in the reflux state, the depletion layer easily extends from the p protective diffusion region 14 into the opening, and as a result, the maximum unipolar current is reduced due to the current path passing through the opening being narrowed. For this reason, in order to ensure a sufficient maximum unipolar current, the opening of the p protective diffusion region 14 must be enlarged. As a result, the area of the MOSFET 91 is increased.
　これに対して本実施の形態によれば、ｐ保護拡散領域１４の開口部内に、ショットキー電極３４に接するｎ+高濃度領域１１ｈが設けられる。これにより、内蔵ショットキーバリアダイオードの電流経路の抵抗成分を低減することができる。よって、ＭＯＳＦＥＴ９２の面積を抑えつつ、内蔵ショットキーバリアダイオードの最大ユニポーラ電流をより大きくすることができる。 On the other hand, according to the present embodiment, the n + high concentration region 11 h in contact with the Schottky electrode 34 is provided in the opening of the p protective diffusion region 14. Thereby, the resistance component of the current path of the built-in Schottky barrier diode can be reduced. Therefore, the maximum unipolar current of the built-in Schottky barrier diode can be increased while suppressing the area of the MOSFET 92.
　ｎ+高濃度領域１１ｈの不純物濃度がｐ保護拡散領域１４の不純物濃度よりも低い場合、ショットキー電極３４近傍に過度に高い電界が加わることが避けられる。これにより、ＭＯＳＦＥＴ９２の信頼性を高めることができる。 When the impurity concentration of the n + high concentration region 11 h is lower than the impurity concentration of the p protective diffusion region 14, an excessively high electric field is avoided from being applied in the vicinity of the Schottky electrode 34. Thereby, the reliability of MOSFET92 can be improved.
　＜実施の形態３＞
　図１８を参照して、本実施の形態におけるＭＯＳＦＥＴ９３（電力用半導体装置）は、ｎ+高濃度領域１１ｈに代わりｎ+高濃度領域１１ｉを有している。ｎ+高濃度領域１１ｉは、ショットキー電極３４に接する箇所から、ｐ保護拡散領域１４の下方へと延びている。言い換えれば、ｎ+高濃度領域１１ｉは、ショットキー電極３４に接する箇所から、ｐ保護拡散領域１４によって複合トレンチＴＲ２の底部と隔てられた箇所へと延びている。 <Embodiment 3>
Referring to FIG. 18, MOSFET 93 of this embodiment (power semiconductor device) includes a place n + high concentration region 11i to the n + high-density region 11h. The n + high concentration region 11 i extends from the portion in contact with the Schottky electrode 34 to below the p protective diffusion region 14. In other words, the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14.
　なお、上記以外の構成については、上述した実施の形態２の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.
　本実施の形態によれば、ｎ+高濃度領域１１ｉは、ショットキー電極３４に接する箇所から、ｐ保護拡散領域１４によって複合トレンチＴＲ２の底部と隔てられた箇所へと延びている。これにより、ショットキー電極３４に接する箇所から、ｐ保護拡散領域１４によって複合トレンチＴＲ２の底部と隔てられた箇所へと拡がる電流経路の電気抵抗が小さくなる。これにより、複合トレンチＴＲ２の底部に設けられたｐ保護拡散領域１４の開口部を大きくすることなく、内蔵ショットキーバリアダイオードの最大ユニポーラ電流を大きくすることができる。 According to the present embodiment, the n + high concentration region 11 i extends from a location in contact with the Schottky electrode 34 to a location separated from the bottom of the composite trench TR 2 by the p protective diffusion region 14. As a result, the electrical resistance of the current path extending from the portion in contact with the Schottky electrode 34 to the portion separated from the bottom of the composite trench TR2 by the p protective diffusion region 14 is reduced. Thus, the maximum unipolar current of the built-in Schottky barrier diode can be increased without increasing the opening of the p protective diffusion region 14 provided at the bottom of the composite trench TR2.
　＜実施の形態４＞
　図１９は、本実施の形態におけるＭＯＳＦＥＴ９４（電力用半導体装置）の構成を概略的に示す部分平面図である。図２０～図２２のそれぞれは、図１９の線ＸＸ－ＸＸ、線ＸＸＩ－ＸＸＩおよび線ＸＸＩＩ－ＸＸＩＩに沿う概略断面図である。なお、図１９においては、ソース電極３２および層間絶縁膜２１の図示を省略している。 <Embodiment 4>
FIG. 19 is a partial plan view schematically showing a configuration of MOSFET 94 (power semiconductor device) in the present embodiment. 20 to 22 are schematic sectional views taken along line XX-XX, line XXI-XXI, and line XXII-XXII in FIG. In FIG. 19, the source electrode 32 and the interlayer insulating film 21 are not shown.
　ＭＯＳＦＥＴ９４は、コンタクト領域ＲＧ２（図１：実施の形態１）に代わりコンタクト領域ＲＧ２Ｒを有している。コンタクト領域ＲＧ２Ｒには、複合トレンチＴＲ２に代わり複合トレンチＴＲ２Ｒが設けられている。コンタクト領域ＲＧ２Ｒの形状、すなわち複合トレンチＴＲ２Ｒの概形、は、長方形状を有している。よって、コンタクト領域ＲＧ２Ｒおよび複合トレンチＴＲ２Ｒの各々は、この長方形状の長辺に沿った長手方向（図中、横方向）と、この長方形状の短辺に沿った幅方向（図中、縦方向）とを有している。 The MOSFET 94 has a contact region RG2R instead of the contact region RG2 (FIG. 1: embodiment 1). In the contact region RG2R, a composite trench TR2R is provided instead of the composite trench TR2. The shape of contact region RG2R, that is, the general shape of composite trench TR2R, has a rectangular shape. Therefore, each of the contact region RG2R and the composite trench TR2R has a longitudinal direction (horizontal direction in the figure) along the long side of the rectangular shape and a width direction (vertical direction in the figure) along the short side of the rectangular shape. ).
　コンタクト領域ＲＧ２Ｒの、幅方向に沿った断面は、長手方向における断面位置に依存して、異なる構造を有している。このことについて、以下に詳しく説明する。 The cross section of the contact region RG2R along the width direction has a different structure depending on the position of the cross section in the longitudinal direction. This will be described in detail below.
　線ＸＸ－ＸＸ（図１９）に沿う断面（図２０）には、トレンチ内コンタクトホールＣＨ２を介してソース電極３２がｐ保護拡散領域１４にオーミック接続された領域が存在している。よってこの領域は、ｐ保護拡散領域１４をソース電位に接地する機能を有している。線ＸＸＩ－ＸＸＩ（図１９）に沿う断面（図２１）には、トレンチ内コンタクトホールＣＨ２を介してショットキー電極３４がｐ保護拡散領域１４に接続された領域が存在している。ここで、ショットキー電極３４は、ｎ型半導体に対するショットキー接合を形成する一方、ｐ型半導体に対してはオーミック接合を形成するものである。このため、ソース電極３２は、ショットキー電極３４を介してｐ保護拡散領域１４にオーミック接続されている。よって線ＸＸＩ－ＸＸＩ近傍の領域も、線ＸＸ－ＸＸ近傍の領域と同様、ｐ保護拡散領域１４をソース電位に接地する機能を有している。 In the cross section (FIG. 20) along the line XX-XX (FIG. 19), there is a region in which the source electrode 32 is ohmically connected to the p protective diffusion region 14 via the contact hole CH2 in the trench. Therefore, this region has a function of grounding the p protection diffusion region 14 to the source potential. In the cross section (FIG. 21) along the line XXI-XXI (FIG. 19), there is a region where the Schottky electrode 34 is connected to the p protection diffusion region 14 via the contact hole CH2 in the trench. Here, the Schottky electrode 34 forms a Schottky junction with respect to the n-type semiconductor, and forms an ohmic junction with respect to the p-type semiconductor. Therefore, the source electrode 32 is ohmically connected to the p protection diffusion region 14 via the Schottky electrode 34. Therefore, the region near the line XXI-XXI also has a function of grounding the p protection diffusion region 14 to the source potential, similarly to the region near the line XX-XX.
　一方で、線ＸＸＩＩ－ＸＸＩＩ（図１９）に沿う断面（図２２）には、ｐ保護拡散領域１４の開口部においてｎ-ドリフト領域１１にショットキー電極３４がショットキー接続された領域が存在している。よってこの領域は、内蔵ショットキーバリアダイオードとしての機能を有している。 On the other hand, in the cross section (FIG. 22) along the line XXII-XXII (FIG. 19), there is a region where the Schottky electrode 34 is Schottky connected to the n − drift region 11 in the opening of the p protective diffusion region 14. ing. Therefore, this region has a function as a built-in Schottky barrier diode.
　以上のように、ｐ保護拡散領域１４の接地機能を有する領域と、内蔵ショットキーバリアダイオードの機能を有する領域とが、長手方向において交互に配置されている。言い換えれば、複合トレンチＴＲ２Ｒには長手方向において、ソース電極３２がｐ保護拡散領域１４にオーミック接続された領域と、ショットキー電極３４がｎ-ドリフト領域１１にショットキー接続された領域とが交互に配置されている。 As described above, the region having the ground function of the p protection diffusion region 14 and the region having the function of the built-in Schottky barrier diode are alternately arranged in the longitudinal direction. In other words, in the longitudinal direction of the composite trench TR2R, the region where the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the region where the Schottky electrode 34 is Schottky connected to the n − drift region 11 are alternately arranged. Has been placed.
　なお上記以外の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.
　前述した実施の形態１によれば、トレンチ内コンタクトホールＣＨ２（図１）において、図２に示すように、ショットキー電極３４はその周囲全てをｐ保護拡散領域１４に囲まれている。このため、ｐ保護拡散層１４形成時のマスクとショットキー電極３４形成時のマスクとの相対的な位置が高精度に管理されないと、内蔵ショットキーバリアダイオードとしての機能を実際に有する領域の面積が変化したり、ドレイン－ソース間のリークが生じたりする恐れがある。 According to the first embodiment described above, in the contact hole CH2 in the trench (FIG. 1), the Schottky electrode 34 is entirely surrounded by the p protective diffusion region 14 as shown in FIG. Therefore, if the relative position between the mask at the time of forming the p protective diffusion layer 14 and the mask at the time of forming the Schottky electrode 34 is not managed with high accuracy, the area of the region that actually has a function as a built-in Schottky barrier diode. May change or a drain-source leak may occur.
　これに対して本実施の形態の構造によれば、上述したように、ソース電極３２がｐ保護拡散領域１４にオーミック接続された領域と、ショットキー電極３４がｎ-ドリフト領域１１にショットキー接続された領域とが交互に配置されている。言い換えれば、ｐ保護拡散層を接地するための領域と、ショットキーバリアダイオードを形成するための領域とが、互いに区分されている。よって、フォトリソグラフィ工程におけるマスクずれに対する許容度を大きくすることができる。 On the other hand, according to the structure of the present embodiment, as described above, the source electrode 32 is ohmically connected to the p protective diffusion region 14 and the Schottky electrode 34 is Schottky connected to the n − drift region 11. The arranged areas are alternately arranged. In other words, the region for grounding the p protective diffusion layer and the region for forming the Schottky barrier diode are separated from each other. Therefore, tolerance for mask displacement in the photolithography process can be increased.
　なお、図１９においてはコンタクト領域ＲＧ２Ｒが１つだけ示されているが、コンタクト領域ＲＧ２Ｒの数は任意であり、たとえば、複数のコンタクト領域ＲＧ２Ｒが、長手方向および幅方向の少なくともいずれかにおいて周期的に配置されてもよい。また、ｎ-ドリフト領域１１に代わり、ｎ領域１１Ａ（図１７または図１８：実施の形態２または３）が設けられてもよい。また、実施の形態１の場合と同様に、ＭＯＳトレンチＴＲ１は、格子状の配置（図１４）を有するものに限定されるわけではなく、たとえば、千鳥格子状の配置（図１５）、櫛状の配置（図１６）、または六角形状の配置が用いられてもよい。 Although only one contact region RG2R is shown in FIG. 19, the number of contact regions RG2R is arbitrary. For example, a plurality of contact regions RG2R are periodically arranged in at least one of the longitudinal direction and the width direction. May be arranged. Instead of n − drift region 11, n region 11 </ b> A (FIG. 17 or FIG. 18: Embodiment 2 or 3) may be provided. Further, as in the case of the first embodiment, the MOS trench TR1 is not limited to the one having the lattice arrangement (FIG. 14). For example, the MOS trench TR1 is arranged in a staggered arrangement (FIG. 15), a comb A hexagonal arrangement (FIG. 16) or a hexagonal arrangement may be used.
　（変形例）
　図２３を参照して、変形例のＭＯＳＦＥＴ９４Ｓ（電力用半導体装置）は、コンタクト領域ＲＧ２Ｓを有している。コンタクト領域ＲＧ２Ｓには複合トレンチＴＲ２Ｓ（第２のトレンチ）が設けられている。コンタクト領域ＲＧ２Ｓは、前述したコンタクト領域ＲＧ２Ｒを、その長辺方向において延長したものであり、長辺方向の端にＭＯＳ領域ＲＧ１が存在していない。よって、コンタクト領域ＲＧ２Ｓの形状、すなわち複合トレンチＴＲ２Ｓの概形、は、ストライプ形状を有している。言い換えれば、複合トレンチＴＲ２Ｓは、平面視でストライプ状の配置を有している。よって、コンタクト領域ＲＧ２Ｓおよび複合トレンチＴＲ２Ｓの各々は、このストライプ形状の延在方向に沿った長手方向（図中、横方向）と、それに垂直な幅方向（図中、縦方向）とを有している。図中、ＭＯＳトレンチＴＲ１は、縦方向に沿って延びる部分と横方向に沿って延びる部分とを有しており、複合トレンチＴＲ２Ｓのストライプ形状の延在方向は、ＭＯＳトレンチＴＲ１が延びる方向のひとつである横方向に沿っている。幅方向（図中、縦方向）において、ＭＯＳトレンチＴＲ１は、複合トレンチＴＲ２Ｓと異なる位置にのみ配置されている。 (Modification)
Referring to FIG. 23, a MOSFET 94S (power semiconductor device) of a modification has a contact region RG2S. The contact region RG2S is provided with a composite trench TR2S (second trench). The contact region RG2S is obtained by extending the above-described contact region RG2R in the long side direction, and the MOS region RG1 does not exist at the end in the long side direction. Therefore, the shape of the contact region RG2S, that is, the general shape of the composite trench TR2S has a stripe shape. In other words, the composite trench TR2S has a striped arrangement in plan view. Therefore, each of contact region RG2S and composite trench TR2S has a longitudinal direction (lateral direction in the figure) along the extending direction of the stripe shape and a width direction (vertical direction in the figure) perpendicular to the longitudinal direction. ing. In the figure, the MOS trench TR1 has a portion extending along the vertical direction and a portion extending along the horizontal direction, and the extending direction of the stripe shape of the composite trench TR2S is one of the directions in which the MOS trench TR1 extends. Along the lateral direction. In the width direction (vertical direction in the figure), the MOS trench TR1 is disposed only at a position different from the composite trench TR2S.
　前述したＭＯＳＦＥＴ９４（図１９）においては、ＭＯＳ領域ＲＧ１の周期構造を乱さないようにするためには、コンタクト領域ＲＧ２Ｒの幅を、この周期構造に合わせて定める必要が生じる。具体的には、コンタクト領域ＲＧ２Ｒの幅を、この周期の整数倍に合わせる必要が生じる。この点で設計上の自由度が制限される。これに対して本変形例によれば、ＭＯＳ領域ＲＧ１の幅とコンタクト領域ＲＧ２Ｓの幅とを独立に決めることができる。このため、設計上の自由度が大きくなる。具体的には、ＭＯＳ領域ＲＧ１の幅を、オン抵抗、ドレイン－ソース間耐圧、ゲート絶縁膜２０にかかる電界から決定し、コンタクト領域ＲＧ２Ｓの幅を、ショットキーバリアダイオードの占有面積から決定することができる。たとえば、ショットキーバリアダイオードの占有面積をより大きくするためには、図２４に示されているように、単純にコンタクト領域ＲＧ２Ｓの幅を大きくするだけでよい。 In the above-described MOSFET 94 (FIG. 19), in order not to disturb the periodic structure of the MOS region RG1, it is necessary to determine the width of the contact region RG2R according to this periodic structure. Specifically, it is necessary to adjust the width of the contact region RG2R to an integral multiple of this period. This limits the degree of freedom in design. On the other hand, according to this modification, the width of the MOS region RG1 and the width of the contact region RG2S can be determined independently. This increases the degree of freedom in design. Specifically, the width of the MOS region RG1 is determined from the on-resistance, the drain-source breakdown voltage, and the electric field applied to the gate insulating film 20, and the width of the contact region RG2S is determined from the area occupied by the Schottky barrier diode. Can do. For example, in order to increase the occupation area of the Schottky barrier diode, it is only necessary to simply increase the width of the contact region RG2S as shown in FIG.
　なお長手方向において、コンタクト領域ＲＧ２Ｓの寸法は、ＭＯＳ領域ＲＧ１およびコンタクト領域ＲＧ２Ｓが形成される活性領域の寸法と同じであってもよいし、それより小さくともよい。 In the longitudinal direction, the size of the contact region RG2S may be the same as or smaller than the size of the active region in which the MOS region RG1 and the contact region RG2S are formed.
　図２５を参照して、さらなる変形例のＭＯＳＦＥＴ９４Ｔ（電力用半導体装置）は、ＭＯＳ領域ＲＧ１（図２３）に代わり、ＭＯＳ領域ＲＧ１Ｓを有している。本変形例においては、コンタクト領域ＲＧ２Ｓだけでなく、ＭＯＳ領域ＲＧ１Ｓも、平面視でストライプ状の配置を有している。 Referring to FIG. 25, MOSFET 94T (power semiconductor device) of a further modification has MOS region RG1S instead of MOS region RG1 (FIG. 23). In the present modification, not only the contact region RG2S but also the MOS region RG1S has a striped arrangement in plan view.
　本変形例においては、ＭＯＳトレンチＴＲ１および複合トレンチＴＲ２Ｓ（図２３）に代わり、ＭＯＳトレンチＴＲ１Ｐおよび複合トレンチＴＲ２Ｐが設けられている。ＭＯＳトレンチＴＲ１Ｐおよび複合トレンチＴＲ２Ｐは、それらが一体となることで、ストライプ状のトレンチＴＲＣを構成している。言い換えれば、トレンチＴＲＣの一部がＭＯＳトレンチＴＲ１Ｐであり、他部が複合トレンチＴＲ２Ｐである。 In this modification, a MOS trench TR1P and a composite trench TR2P are provided instead of the MOS trench TR1 and the composite trench TR2S (FIG. 23). The MOS trench TR1P and the composite trench TR2P are combined to form a stripe-shaped trench TRC. In other words, a part of the trench TRC is the MOS trench TR1P, and the other part is the composite trench TR2P.
　本変形例によれば、ＭＯＳ領域ＲＧ１Ｓの幅を小さくしやすい。なお、図示されているように、ＭＯＳ領域ＲＧ１Ｓの幅に比して、コンタクト領域ＲＧ２Ｓの幅が大きくされてもよい。これにより、ショットキーバリアダイオードとして機能する領域の面積を大きく確保することができる。 According to this modification, it is easy to reduce the width of the MOS region RG1S. As shown in the drawing, the width of the contact region RG2S may be made larger than the width of the MOS region RG1S. Thereby, a large area of the region functioning as the Schottky barrier diode can be secured.
　なお上記各実施の形態では、ドレイン電極３１が基板１の下面に配置される、いわゆる縦型ＭＯＳＦＥＴについて説明したが、電力用半導体装置は、ドレイン電極３１がｎ-ドリフト領域１１の上面に配置されるＲＥＳＵＲＦ型ＭＯＳＦＥＴなど、いわゆる横型ＭＯＳＦＥＴであってもよい。また上記各実施の形態ではＭＯＳＦＥＴについて説明したが、電力用半導体装置はＭＯＳＦＥＴ以外のＭＩＳＦＥＴ（Ｍｅｔａｌ－Ｉｎｓｕｌａｔｏｒ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ－Ｔｒａｎｓｉｓｔｏｒ）であってもよい。また電力用半導体装置はＭＩＳＦＥＴ以外のトランジスタであってもよく、たとえばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ－Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）であってもよい。ＩＧＢＴを構成するためには、たとえば、図１における基板１の導電型を、ｎ-ドリフト領域１１の導電型と異なるものであるｐ型とすればよい。その場合、ＭＯＳＦＥＴ９１におけるｎソース領域１３、ソース電極３２およびドレイン電極３１のそれぞれは、ＩＧＢＴにおけるエミッタ領域、エミッタ電極およびコレクタ電極に対応する。また上記各実施の形態では、ワイドバンドギャップ半導体としてＳｉＣを用いる場合について説明したが、窒化ガリウム（ＧａＮ）系材料、ダイヤモンドなど、他のワイドバンドギャップ半導体が用いられてもよい。 In each of the above embodiments, the so-called vertical MOSFET in which the drain electrode 31 is disposed on the lower surface of the substrate 1 has been described. However, in the power semiconductor device, the drain electrode 31 is disposed on the upper surface of the n − drift region 11. A so-called lateral MOSFET such as a RESURF MOSFET may be used. In each of the above embodiments, the MOSFET has been described. However, the power semiconductor device may be a MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor) other than the MOSFET. The power semiconductor device may be a transistor other than a MISFET, for example, an IGBT (Insulated-Gate Bipolar Transistor). In order to configure the IGBT, for example, the conductivity type of the substrate 1 in FIG. 1 may be a p-type different from the conductivity type of the n − drift region 11. In that case, each of the n source region 13, the source electrode 32, and the drain electrode 31 in the MOSFET 91 corresponds to the emitter region, the emitter electrode, and the collector electrode in the IGBT. In each of the above embodiments, the case where SiC is used as the wide band gap semiconductor has been described. However, other wide band gap semiconductors such as gallium nitride (GaN) -based material and diamond may be used.
　本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。この発明は詳細に説明されたが、上記した説明は、すべての局面において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。 In the present invention, it is possible to freely combine the respective embodiments within the scope of the invention, and to appropriately modify and omit the respective embodiments. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.
　ＣＨ１　ソースコンタクトホール、ＣＨ２　トレンチ内コンタクトホール、ＲＧ１，ＲＧ１Ｓ　ＭＯＳ領域、ＲＧ２，ＲＧ２Ｓ　コンタクト領域、ＴＲ１，ＴＲ１Ｐ，ＴＲ１Ｓ，ＴＲ１Ｚ　ＭＯＳトレンチ（第１のトレンチ）、ＴＲ２，ＴＲ２Ｐ　複合トレンチ（第２のトレンチ）、１　基板、１０　半導体層、１１　ｎ-ドリフト領域（第１の半導体領域）、１１Ａ　ｎ領域（第１の半導体領域）、１１ｄ，１１ｅ　ｎ-ドリフト領域（ドリフト領域）、１１ｈ，１１ｉ　ｎ+高濃度領域（高濃度領域）、１２　ｐベース領域（第２の半導体領域）、１３　ｎソース領域（第３の半導体領域）、１４　ｐ保護拡散領域（第４の半導体領域）、２０　ゲート絶縁膜、２１　層間絶縁膜、３０　ゲート電極、３１　ドレイン電極（第１の主電極）、３２　ソース電極（第２の主電極）、３４　ショットキー電極、９１～９４，９４Ｓ，９４Ｔ　ＭＯＳＦＥＴ（電力用半導体装置）。 CH1 source contact hole, CH2 contact hole in trench, RG1, RG1S MOS region, RG2, RG2S contact region, TR1, TR1P, TR1S, TR1Z MOS trench (first trench), TR2, TR2P compound trench (second trench) 1 substrate, 10 semiconductor layer, 11 n - drift region (first semiconductor region), 11A n region (first semiconductor region), 11d, 11e n - drift region (drift region), 11h, 11i n + high Concentration region (high concentration region), 12 p base region (second semiconductor region), 13 n source region (third semiconductor region), 14 p protective diffusion region (fourth semiconductor region), 20 gate insulating film, 21 interlayer insulating film, 30 gate electrode, 31 drain electrode (first main electrode), 32 source electrode (second Electrode), 34 Schottky electrode, 91 ~ 94,94S, semiconductor device 94T MOSFET (power).

Claims (13)

  1. 　第１の導電型を有する第１の半導体領域（１１，１１Ａ）と、
    　前記第１の半導体領域（１１，１１Ａ）上に設けられ、前記第１の導電型と異なる第２の導電型を有する第２の半導体領域（１２）と、
    　前記第２の半導体領域（１２）上に設けられ、前記第２の半導体領域（１２）によって前記第１の半導体領域（１１，１１Ａ）から隔てられ、前記第１の導電型を有する第３の半導体領域（１３）と、
    　前記第１の半導体領域（１１，１１Ａ）と接し、前記第２の半導体領域（１２）よりも深く設けられた部分を有し、前記第２の導電型を有する第４の半導体領域（１４）と、
    　前記第３の半導体領域（１３）と前記第２の半導体領域（１２）と前記第１の半導体領域（１１，１１Ａ）とに面する内面を有する第１のトレンチ（ＴＲ１，ＴＲ１Ｚ，ＴＲ１Ｓ，ＴＲ１Ｐ）内に設けられ、前記第１のトレンチ（ＴＲ１，ＴＲ１Ｚ，ＴＲ１Ｓ，ＴＲ１Ｐ）の前記内面を覆うゲート絶縁膜（２０）と、
    　前記第１のトレンチ（ＴＲ１，ＴＲ１Ｚ，ＴＲ１Ｓ，ＴＲ１Ｐ）内で前記ゲート絶縁膜（２０）上に設けられたゲート電極（３０）と、
    　前記第１の半導体領域（１１，１１Ａ）に電気的に接続された第１の主電極（３１）と、
    　前記第１の主電極（３１）から離れて設けられ、前記第３の半導体領域（１３）にオーミック接続され、前記第１の半導体領域（１１，１１Ａ）および前記第４の半導体領域（１４）に面する底部を有する第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）内に配置された部分を有し、前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）の前記底部上で前記第４の半導体領域（１４）にオーミック接続された第２の主電極（３２）と、
    　前記第２の主電極（３２）と短絡され、前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）の前記底部上で前記第１の半導体領域（１１，１１Ａ）にショットキー接続されたショットキー電極（３４）と、
    を備える、電力用半導体装置（９１～９４，９４Ｓ，９４Ｔ）。     A first semiconductor region (11, 11A) having a first conductivity type;
    A second semiconductor region (12) provided on the first semiconductor region (11, 11A) and having a second conductivity type different from the first conductivity type;
    A third semiconductor region provided on the second semiconductor region (12), separated from the first semiconductor region (11, 11A) by the second semiconductor region (12), and having the first conductivity type; A semiconductor region (13);
    A fourth semiconductor region (14) having a portion in contact with the first semiconductor region (11, 11A) and deeper than the second semiconductor region (12) and having the second conductivity type. When,
    First trenches (TR1, TR1Z, TR1S, TR1P) having inner surfaces facing the third semiconductor region (13), the second semiconductor region (12), and the first semiconductor region (11, 11A). ) And a gate insulating film (20) covering the inner surface of the first trench (TR1, TR1Z, TR1S, TR1P),
    A gate electrode (30) provided on the gate insulating film (20) in the first trench (TR1, TR1Z, TR1S, TR1P);
    A first main electrode (31) electrically connected to the first semiconductor region (11, 11A);
    The first semiconductor region (11) and the fourth semiconductor region (14) are provided apart from the first main electrode (31) and are ohmically connected to the third semiconductor region (13). Having a portion disposed in a second trench (TR2, TR2R, TR2S, TR2P) having a bottom facing the first, and on the bottom of the second trench (TR2, TR2R, TR2S, TR2P) A second main electrode (32) ohmically connected to four semiconductor regions (14);
    Shot short-circuited with the second main electrode (32) and Schottky connected to the first semiconductor region (11, 11A) on the bottom of the second trench (TR2, TR2R, TR2S, TR2P) A key electrode (34);
    A power semiconductor device (91 to 94, 94S, 94T).
  2. 　前記第１のトレンチ（ＴＲ１，ＴＲ１Ｚ，ＴＲ１Ｓ）は、前記第４の半導体領域（１４）の幅と同じ幅を有する、請求項１に記載の電力用半導体装置（９１～９４，９４Ｓ）。 The power semiconductor device (91 to 94, 94S) according to claim 1, wherein the first trench (TR1, TR1Z, TR1S) has the same width as the width of the fourth semiconductor region (14).
  3. 　前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ）は、前記第３の半導体領域（１３）と前記第２の半導体領域（１２）と前記第１の半導体領域（１１，１１Ａ）とに面する側部を有し、前記ゲート絶縁膜（２０）は、前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ）の前記側部を覆う部分を有し、前記ゲート電極（３０）は、前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ）内で前記ゲート絶縁膜（２０）上に設けられた部分を有する、請求項１または２に記載の電力用半導体装置（９１～９４，９４Ｓ）。 The second trench (TR2, TR2R, TR2S) faces the third semiconductor region (13), the second semiconductor region (12), and the first semiconductor region (11, 11A). The gate insulating film (20) has a portion covering the side portion of the second trench (TR2, TR2R, TR2S), and the gate electrode (30) is formed of the second trench. The power semiconductor device (91 to 94, 94S) according to claim 1 or 2, comprising a portion provided on the gate insulating film (20) in (TR2, TR2R, TR2S).
  4. 　断面視において、前記第４の半導体領域（１４）は、前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）の前記底部の一方端および他方端のそれぞれを覆う第１の部分および第２の部分を有しており、前記ショットキー電極（３４）は前記第１の半導体領域（１１，１１Ａ）に前記第１の部分と前記第２の部分との間でショットキー接続されている、請求項３に記載の電力用半導体装置（９１～９４，９４Ｓ）。 In a cross-sectional view, the fourth semiconductor region (14) includes a first portion and a second portion that respectively cover one end and the other end of the bottom of the second trench (TR2, TR2R, TR2S, TR2P). The Schottky electrode (34) is Schottky connected to the first semiconductor region (11, 11A) between the first portion and the second portion. Item 4. The power semiconductor device according to Item 3 (91 to 94, 94S).
  5. 　前記第１の半導体領域（１１Ａ）は、
    　ドリフト領域（１１ｅ）と、
    　前記ショットキー電極（３４）に接し、前記ドリフト領域の不純物濃度よりも高い不純物濃度を有する高濃度領域（１１ｈ，１１ｉ）と、
    を含む、請求項１から４のいずれか１項に記載の電力用半導体装置（９２，９３）。     The first semiconductor region (11A)
    A drift region (11e);
    A high concentration region (11h, 11i) in contact with the Schottky electrode (34) and having an impurity concentration higher than that of the drift region;
    5. The power semiconductor device (92, 93) according to claim 1, comprising:
  6. 　前記高濃度領域（１１ｈ，１１ｉ）の不純物濃度は、前記第４の半導体領域（１４）の不純物濃度よりも低い、請求項５に記載の電力用半導体装置（９２，９３）。 The power semiconductor device (92, 93) according to claim 5, wherein an impurity concentration of the high concentration region (11h, 11i) is lower than an impurity concentration of the fourth semiconductor region (14).
  7. 　前記高濃度領域（１１ｉ）は、前記ショットキー電極（３４）に接する箇所から、前記第４の半導体領域（１４）によって前記第２のトレンチ（ＴＲ２，ＴＲ２Ｒ，ＴＲ２Ｓ）の前記底部と隔てられた箇所へと延びている、請求項５または６に記載の電力用半導体装置（９３）。 The high concentration region (11i) is separated from the bottom of the second trench (TR2, TR2R, TR2S) by the fourth semiconductor region (14) from a position in contact with the Schottky electrode (34). The power semiconductor device (93) according to claim 5 or 6, which extends to a location.
  8. 　前記第１のトレンチ（ＴＲ１）は、平面視で格子状の配置を有する、請求項１から７のいずれか１項に記載の電力用半導体装置（９１～９４，９４Ｓ）。 The power semiconductor device (91 to 94, 94S) according to any one of claims 1 to 7, wherein the first trench (TR1) has a grid-like arrangement in plan view.
  9. 　前記第１のトレンチ（ＴＲ１Ｚ）は、平面視で千鳥格子状の配置を有する、請求項１から７のいずれか１項に記載の電力用半導体装置（９１～９４，９４Ｓ）。 The power semiconductor device (91 to 94, 94S) according to any one of claims 1 to 7, wherein the first trench (TR1Z) has a staggered arrangement in a plan view.
  10. 　前記第１のトレンチ（ＴＲ１Ｓ）は、平面視で櫛状の配置を有する、請求項１から７のいずれか１項に記載の電力用半導体装置（９１～９４，９４Ｓ，９４Ｔ）。 The power semiconductor device (91 to 94, 94S, 94T) according to any one of claims 1 to 7, wherein the first trench (TR1S) has a comb-like arrangement in a plan view.
  11. 　前記第２のトレンチ（ＴＲ２Ｓ，ＴＲ２Ｐ）は、平面視でストライプ状の配置を有する、請求項１から１０のいずれか１項に記載の電力用半導体装置（９４Ｓ，９４Ｔ）。 The power semiconductor device (94S, 94T) according to any one of claims 1 to 10, wherein the second trenches (TR2S, TR2P) have a stripe arrangement in a plan view.
  12. 　前記第２のトレンチ（ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）は長手方向を有し、
    　前記第２のトレンチ（ＴＲ２Ｒ，ＴＲ２Ｓ，ＴＲ２Ｐ）には前記長手方向において、前記第２の主電極が前記第４の半導体領域にオーミック接続された領域と、前記ショットキー電極が前記第１の半導体領域にショットキー接続された領域とが交互に配置されている、請求項１から１１のいずれか１項に記載の電力用半導体装置（９４，９４Ｓ，９４Ｔ）。     The second trench (TR2R, TR2S, TR2P) has a longitudinal direction,
    The second trench (TR2R, TR2S, TR2P) has a region in which the second main electrode is ohmically connected to the fourth semiconductor region in the longitudinal direction, and the Schottky electrode is the first semiconductor. The power semiconductor device (94, 94S, 94T) according to any one of claims 1 to 11, wherein the regions Schottky-connected to the regions are alternately arranged.
  13. 　前記第１の半導体領域（１１，１１Ａ）はワイドバンドギャップ半導体から作られている、請求項１から１２のいずれか１項に記載の電力用半導体装置（９１～９４，９４Ｓ，９４Ｔ）。 The power semiconductor device (91 to 94, 94S, 94T) according to any one of claims 1 to 12, wherein the first semiconductor region (11, 11A) is made of a wide band gap semiconductor.
PCT/JP2016/064634 2015-07-15 2016-05-17 Power semiconductor device WO2017010164A1 (en)

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