JP2020004819A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device capable of increasing the capacitance of a capacitor structure formed inside a groove of a semiconductor substrate and a manufacturing method thereof.SOLUTION: A semiconductor device includes a semiconductor substrate 10 that has conductivity and in which a first groove is formed in a first main surface 101, and a second groove is formed in a second main surface 102 whose longitudinal direction intersects with a longitudinal direction of the first groove in a plan view and whose bottom is connected to the bottom of the first groove, a first dielectric film 21 disposed on the inner wall surface of the first groove, a first conductor film 31 disposed inside the first groove and facing the semiconductor substrate 10 via the first dielectric film 21, a second dielectric film 22 disposed on the inner wall surface of the second groove, and a second conductor film 32 disposed inside the second groove, and facing the semiconductor substrate 10 via the second dielectric film 22, and electrically connected to the first conductor film 31 in a region in which the bottom of the first groove and the bottom of the second groove are connected with each other.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having a semiconductor capacitor and a method for manufacturing the same.

  In order to increase the capacity of a semiconductor capacitor, a configuration in which a capacitor structure is formed inside a groove formed in a semiconductor substrate is used. For example, a configuration is disclosed in which a through-hole in a semiconductor substrate is filled with a conductor film via an insulating film (see Patent Document 1). By forming the capacitor structure inside the groove of the semiconductor substrate, a semiconductor capacitor having a large capacity can be realized.

JP 2012-089743 A

  In order to increase the capacity of the capacitor structure formed inside the groove, it is necessary to increase the thickness of the semiconductor substrate and form a large number of narrow grooves. However, there is a limit to the aspect ratio of the depth and width of the groove that can be formed in the semiconductor substrate, and it is difficult to increase the capacitance of the capacitor structure.

  An object of the present invention is to provide a semiconductor device capable of increasing the capacitance of a capacitor structure formed inside a groove of a semiconductor substrate, and a method of manufacturing the semiconductor device.

  In a semiconductor device according to one embodiment of the present invention, a first dielectric film and a first conductor film are stacked inside a first groove formed in a first main surface of a semiconductor substrate having conductivity. Is formed in the second groove formed in the second main surface of the semiconductor substrate such that the first groove and the longitudinal direction intersect in plan view and the bottoms thereof are connected to each other. The dielectric film and the second conductor film are laminated to form a second capacitor structure, and the first conductor film and the second conductor film are electrically connected inside the semiconductor substrate. And

  In a method of manufacturing a semiconductor device according to another aspect of the present invention, a step of forming a first groove in a first main surface of a semiconductor substrate having conductivity, and a step in which a longitudinal direction intersects the first groove in a plan view. Forming a second groove on the second main surface so that the bottoms thereof are connected to each other; laminating a first dielectric film and a first conductor film on the inner wall surface of the first groove; A second dielectric film and a second conductor film are laminated on the inner wall surface of the second groove, and the first conductor film and the second conductor film are formed in a region where the bottom of the first groove is connected to the bottom of the second groove. And electrically connecting the films.

  According to the present invention, it is possible to provide a semiconductor device capable of increasing the capacitance of a capacitor structure formed inside a groove of a semiconductor substrate and a method of manufacturing the semiconductor device.

FIG. 1 is a schematic plan view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing along the II-II direction of FIG. It is sectional drawing along the III-III direction of FIG. FIG. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention as viewed from a first main surface. FIG. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention as viewed from a second main surface. It is a typical sectional view for explaining the manufacturing method of a comparative example. FIG. 9 is a schematic cross-sectional view illustrating a configuration of a semiconductor device of a comparative example. It is a typical sectional view for explaining other manufacturing methods of a comparative example. FIG. 1 is a schematic diagram illustrating a capacitor stack structure using a semiconductor device according to a first embodiment of the present invention. FIG. 9 is a schematic diagram illustrating a capacitor stack structure using a semiconductor device of a comparative example. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 1). FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 2). FIG. 5 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 3). FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 4). FIG. 5 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 5). FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 6). FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 7). FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 8). FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 9). FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 10). FIG. 11 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 11). FIG. 12 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 12). FIG. 13 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 13). FIG. 9 is a schematic plan view illustrating an example of the arrangement of planar electrodes of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 10 is a schematic plan view illustrating another example of the arrangement of the planar electrodes of the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 9 is a schematic plan view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a schematic plan view illustrating a configuration of a semiconductor device of a comparative example.

  Embodiments will be described below with reference to the drawings. In the description of the drawings, the same portions are denoted by the same reference numerals, and description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like include portions different from actual ones. In addition, the drawings include portions having different dimensional relationships and ratios.

(1st Embodiment)
A semiconductor device 1 according to the first embodiment of the present invention shown in FIG. 1 includes a semiconductor substrate 10 having a first main surface 101 and a second main surface 102 facing each other. FIG. 1 shows a semiconductor device 1 in a plan view as viewed from a first main surface 101.

  The first dielectric film 21 is disposed on the inner wall surface of the first groove formed on the first main surface 101, and the first conductive film 31 facing the semiconductor substrate 10 with the first dielectric film 21 interposed therebetween is the first dielectric film. It is arranged inside one groove. FIG. 1 shows the first dielectric film 21 buried in the first groove and penetrating the first conductive film 31 disposed on the first main surface 101 and disposed on the side surface of the first groove. ing.

  The second dielectric film 22 is disposed on the inner wall surface of the second groove formed on the second main surface 102, and the second conductive film 32 facing the semiconductor substrate 10 via the second dielectric film 22 Are arranged inside the second groove. FIG. 1 shows the second dielectric film 22 disposed on the side surface of the second groove and the second conductive film 32 embedded in the second groove, penetrating the semiconductor substrate 10.

  The semiconductor substrate 10 has conductivity, and a first capacitor structure in which the semiconductor substrate 10, the first dielectric film 21, and the first conductive film 31 are stacked is formed in a first groove. Then, a second capacitor structure in which the semiconductor substrate 10, the second dielectric film 22, and the second conductive film 32 are laminated is formed in the second groove. Although details will be described later, the bottom of the first groove and the bottom of the second groove are connected inside the semiconductor substrate 10. In a region where the bottom of the first groove and the bottom of the second groove are connected (hereinafter, referred to as a “connection region”), the first conductive film 31 and the second conductive film 32 are electrically connected to each other. I have.

  In the semiconductor device 1 shown in FIG. 1, a plurality of first grooves are formed in a straight line parallel to each other, and a plurality of second grooves are formed in a straight line parallel to each other. The longitudinal direction of the first groove on the first main surface 101 and the longitudinal direction of the second groove on the second main surface 102 intersect in plan view. FIG. 1 shows an example in which the longitudinal direction of the first groove is orthogonal to the longitudinal direction of the second groove.

  The size of the first groove and the second groove is limited by the manufacturing limit of the manufacturing method for forming the groove. For example, if the manufacturing limit of the aspect ratio of the groove is about 50, the first groove and the second groove having a width of 2 to 3 μm and a depth of 100 to 150 μm are formed.

  FIG. 2 shows a cross-sectional view along the II-II direction in FIG. 1, and FIG. 3 shows a cross-sectional view along the III-III direction in FIG. The bottom and side surfaces of the first groove are covered with a first dielectric film 21, and the first groove is buried with a first conductive film 31. The bottom and side surfaces of the second groove are covered with the second dielectric film 22, and the second groove is buried with the second conductive film 32.

  As shown in FIG. 2, the bottom surface of the second groove extending from the second main surface 102 in the thickness direction of the semiconductor substrate 10 reaches the bottom surface of the first groove. For this reason, the bottom of the first groove and the bottom of the second groove are connected with a portion where the first groove and the second groove intersect as a connection region.

  In this connection region, the first conductive film 31 disposed inside the first groove and the second conductive film 32 disposed inside the second groove are electrically connected. Further, since the first dielectric film 21 and the second dielectric film 22 are continuous in the connection region, the first conductor film 31 and the second conductor film 32 are electrically insulated from the semiconductor substrate 10. .

  As described above, the semiconductor device 1 has a configuration in which the first capacitor structure including the first groove and the second capacitor structure including the second groove are connected in parallel. As described above, in the semiconductor device 1, the capacitance of the capacitor structure formed inside the groove of the semiconductor substrate 10 can be increased.

  As shown in FIGS. 2 and 3, the first conductor electrode 41 and the first substrate electrode 51, which are not shown in FIG. 1, are arranged to face the first main surface 101 via the first surface insulating film 61. Have been. Further, the second conductor electrode 42 and the second substrate electrode 52 are arranged to face the second main surface 102 via the second surface insulating film 62.

  On the first main surface 101, the first conductive film 31 is arranged to cover all the first grooves. The first conductor electrode 41 is electrically connected to the first conductor film 31 via a contact hole 201 opened in the first surface insulating film 61. The first substrate electrode 51 is connected to the first dielectric film 21 and the first surface insulating film 61 through a contact hole 202 which is continuously open in the remaining region of the region where the first conductive film 31 is arranged. It is electrically connected to the semiconductor substrate 10.

  On the second main surface 102, the second conductive film 32 is arranged to cover all the second grooves. The second conductor electrode 42 is electrically connected to the second conductor film 32 via a contact hole 203 opened in the second surface insulating film 62. In the remaining region of the region where the second conductive film 32 is disposed, the second substrate electrode 52 is connected to the second dielectric film 22 and the second surface insulating film 62 through a contact hole 204 that is continuously opened. It is electrically connected to the semiconductor substrate 10.

  Hereinafter, the first conductor electrode 41, the first substrate electrode 51, the second conductor electrode 42, and the second substrate electrode 52 are collectively referred to as “plane electrodes”. A metal film such as an aluminum film or a copper film is used for the plane electrode. The thickness of the flat electrode is, for example, about 1 μm to 3 μm.

  FIG. 4 shows a plan view of the first main surface 101. In FIG. 4, the contact hole 201, the first dielectric film 21, and the first conductive film 31 are shown passing through the first conductive electrode 41. Further, the contact hole 202, the first dielectric film 21, and the first conductive film 31 are displayed through the first substrate electrode 51. The first conductor electrode 41 and the contact hole 201 and the first substrate electrode 51 and the contact hole 202 are arranged in a band shape facing each other.

  FIG. 5 shows a plan view of the second main surface 102. In FIG. 5, the contact hole 203, the second dielectric film 22, and the second conductor film 32 are shown passing through the second conductor electrode 42. Further, the contact hole 204, the second dielectric film 22, and the second conductive film 32 are displayed through the second substrate electrode 52. The second conductor electrode 42 and the contact hole 203 and the second substrate electrode 52 and the contact hole 204 are arranged in a band shape facing each other.

  The first conductor electrode 41 and the contact hole 201 are formed on the first main surface 101 in FIG. 4 so that the first conductor films 31 formed in all the first grooves are connected to the first conductor electrode 41. It extends vertically. The second conductor electrode 42 and the contact hole 203 are arranged to face the first conductor electrode 41 and the contact hole 201 via the semiconductor substrate 10. Further, the second substrate electrode 52 and the contact hole 204 are arranged to face the first substrate electrode 51 and the contact hole 202 via the semiconductor substrate 10.

  The aspect ratio of the depth and width of the groove that can be formed in the semiconductor substrate 10 has a limit depending on the manufacturing method and the like. However, in the semiconductor device 1 shown in FIG. 1, a first groove is formed in the thickness direction from the first main surface 101, and a second groove is formed in the thickness direction from the second main surface 102. Therefore, when the width of the groove is the same as in the case where the groove is formed from one main surface of the semiconductor substrate 10, the total depth of the groove can be increased in the semiconductor device 1.

  For example, when a groove is formed from one main surface of the semiconductor substrate 10, if the thickness of the semiconductor substrate 10 is larger than the depth of the groove having the maximum feasible aspect ratio as in the comparative example shown in FIG. It cannot penetrate the semiconductor substrate 10. Therefore, it is necessary to reduce the thickness of the semiconductor substrate 10 as in the comparative example shown in FIG. For this reason, it is difficult to increase the capacity of the semiconductor capacitor.

  On the other hand, in the semiconductor device 1 shown in FIG. 1, when a groove having the same aspect ratio is formed as compared with the semiconductor substrate 10 shown in FIG. 7, a groove penetrating the semiconductor substrate 10 having twice the thickness is formed. be able to. That is, the capacity of the semiconductor capacitor can be approximately doubled.

  When a first groove is formed in the first main surface 101 of the semiconductor substrate 10 and a second groove is formed in the second main surface 102, the longitudinal direction of the first groove and the longitudinal direction of the second groove are different. Intersect in plan view. This is because when the longitudinal direction of the first groove and the longitudinal direction of the second groove are parallel to each other, the bottom of the first groove 301 and the bottom of the second groove 302 are connected as shown in FIG. Is difficult. That is, since it is difficult to perform high-precision alignment in which the position of the first groove 301 and the position of the second groove 302 are completely matched, the first groove 301 and the second groove 302 may be displaced by the semiconductor substrate. No connection inside 10. As a result, the conductive film embedded in the first groove 301 and the conductive film embedded in the second groove 302 cannot be electrically connected. In particular, when the width and the interval of the groove are narrowed, it is difficult to exactly match the arrangement of the groove such that the dielectric film and the conductor film inside the groove are continuous.

  On the other hand, in the semiconductor device 1, since the longitudinal direction of the first groove and the longitudinal direction of the second groove intersect in a plan view, the first groove and the second groove can be aligned even if the alignment accuracy is not high. The grooves always intersect, and the connection region between the first groove and the second groove can be reliably formed. Therefore, the first conductor film 31 and the second conductor film 32 can be electrically connected.

  In the semiconductor device 1 shown in FIG. 1, the first groove and the second groove have their respective longitudinal directions orthogonal to each other in plan view. By arranging the first groove and the second groove at right angles in a mesh shape as described above, the connection region between the first groove and the second groove is formed most, and the parasitic resistance of the semiconductor capacitor is reduced. Can be reduced.

  As described above, in the semiconductor device 1 according to the first embodiment of the present invention, grooves are formed from the first main surface 101 and the second main surface 102 of the semiconductor substrate 10, respectively. For this reason, the width of the first groove and the second groove can be reduced. Thereby, the number of the first groove and the second groove can be increased. Further, by forming the first groove and the second groove deeply, the surface area of the side surfaces of the first groove and the second groove increases. Then, by electrically connecting the conductive films respectively disposed inside the first groove and the second groove, the capacity of the semiconductor capacitor can be increased.

  Further, in the semiconductor device 1, the longitudinal direction of the first groove and the longitudinal direction of the second groove intersect in plan view. Thereby, the first groove and the second groove can be reliably connected.

  The thicker the semiconductor substrate 10 is, the easier it is to handle. For example, it is difficult to handle the semiconductor substrate 10 having a thickness of 100 μm, but if the thickness is 200 μm, the handling of the semiconductor substrate 10 is easy. For this reason, the semiconductor device 1 in which the thickness of the semiconductor substrate 10 can be increased by forming the groove from both surfaces is also effective in terms of handling.

  The first substrate electrode 51 and the second substrate electrode 52 may be arranged in a region where they overlap in plan view, and the first conductor electrode 41 and the second conductor electrode 42 may be arranged in a region where they overlap in plan view. Good. Thereby, the semiconductor device 1 having the first main surface 101 and the second main surface 102 provided with the planar electrodes serving as the connection terminals of the semiconductor capacitor can be easily overlapped in the thickness direction. That is, by stacking a plurality of semiconductor devices 1 as shown in FIG. 9, a capacitor stack structure in which semiconductor capacitors are connected in parallel to increase the capacitance can be realized.

  On the other hand, in the semiconductor device 1A using the semiconductor substrate 10 of the comparative example shown in FIG. 7 in which a groove is formed from one main surface of the semiconductor substrate, the thickness of the semiconductor substrate 10 is the maximum possible groove depth. Therefore, when realizing a capacitor stack structure having the same capacitance, as shown in FIG. 10, a larger number of semiconductor devices 1A of the comparative example are required than semiconductor devices 1.

  As described above, since the number of semiconductor devices 1 used in the capacitor stack structure can be reduced, the manufacturing process and the manufacturing cost can be suppressed. Furthermore, since the number of bonding portions between the semiconductor devices 1 is reduced, the reliability of bonding can be improved.

  Further, since the plane electrode and the dielectric film are formed on both surfaces of the first main surface 101 and the second main surface 102, the difference in the coefficient of thermal expansion between the metal material used for the plane electrode and the semiconductor substrate 10 and the dielectric film Also, it is possible to suppress the warpage of the semiconductor substrate 10 due to the difference in the coefficient of thermal expansion between the dielectric material used and the semiconductor substrate 10. Therefore, a material having a large difference in thermal expansion coefficient from the semiconductor substrate 10, for example, nickel or the like can be used for the planar electrode, and silicon nitride having a large dielectric constant can be used for the dielectric film.

  Hereinafter, a method for manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 11 (a) and 11 (b) to 23 (a) and 23 (b). . FIGS. 11A to 23A are cross-sectional views along the II-II direction in FIG. 1, and FIGS. 11B to 23B are cross-sectional views along the III-III direction in FIG. 1. FIG. The method of manufacturing the semiconductor device 1 described below is an example, and can be realized by various other manufacturing methods including this modification.

  First, as shown in FIGS. 11A and 11B, a first groove 301 is formed in the first main surface 101 of the semiconductor substrate 10 having conductivity. The first groove 301 is formed, for example, at a depth of １ ／ or more of the thickness of the semiconductor substrate 10. As the semiconductor substrate 10, for example, a silicon substrate having a high impurity concentration with a resistivity of about 1 to 10 Ωcm is used. The semiconductor substrate 10 may be a p-type semiconductor substrate or an n-type semiconductor substrate. However, since electrons have higher mobility than holes as carriers, an n-type semiconductor can have lower electric resistance than a p-type semiconductor. Therefore, an n-type semiconductor substrate can be suitably used for the semiconductor substrate 10.

  Next, as shown in FIGS. 12A and 12B, a second groove 302 is formed in the second main surface 102 of the semiconductor substrate 10. At this time, by forming the second groove 302 such that the bottom of the second groove 302 reaches the bottom of the first groove 301, a connection region between the first groove 301 and the second groove 302 is formed. You. As described above, by intersecting the longitudinal direction of the first groove 301 and the longitudinal direction of the second groove 302 in a plan view, the first groove 301 and the second groove 302 can be reliably connected. it can.

  As shown in FIGS. 13A and 13B, the first dielectric film 21 is formed on the first main surface 101 and the inner wall surface of the first groove 301, and the second main surface 102 and the second The second dielectric film 22 is formed on the inner wall surface of the groove 302.

  At this time, for the semiconductor substrate 10, a material whose surface is formed with an insulating film by heat treatment in a gas atmosphere may be used. In the semiconductor device 1, the first dielectric film 21 and the second dielectric film are formed on the entire surfaces of the first main surface 101 and the second main surface 102 of the semiconductor substrate 10 and the inner wall surfaces of the first groove 301 and the second groove 302. It is preferable to form the film 22 reliably. For this reason, for example, a material that reacts with a gas in a high-temperature atmosphere to form an insulating film is used for the semiconductor substrate 10. Accordingly, the gas comes into contact with the main surface of the semiconductor substrate 10 and the side and bottom surfaces of the groove, so that the insulating film can be reliably formed.

  For example, a silicon substrate may be used as the semiconductor substrate 10. The surface of a silicon substrate is oxidized by performing a high-temperature heat treatment in an oxygen atmosphere. Therefore, the silicon oxide film can be reliably formed on the first main surface 101, the second main surface 102, and the inner wall surfaces of the first groove 301 and the second groove 302 by the thermal oxidation method. As a result, the first dielectric film 21 and the second dielectric film 22 are simultaneously formed, and are continuously formed on the inner wall surfaces of the first groove 301 and the second groove 302 from the first main surface 101 to the second main surface 102. The formed dielectric film is formed.

  Next, as shown in FIGS. 14A and 14B, the first conductive film 31 is laminated on the first dielectric film 21 inside the first main surface 101 and the first groove 301, and The second conductive film 32 is laminated on the second dielectric film 22 inside the second main surface 102 and the second groove 302. For example, a polycrystalline silicon film is formed in the first main surface 101, the second main surface 102, the inside of the first groove 301 and the inside of the second groove 302 to form the first conductor film 31 and the second conductor The film 32 is formed at the same time. As a result, the first conductor film 31 and the second conductor film 32 are electrically connected in a connection region where the bottom of the first groove 301 and the bottom of the second groove 302 are connected.

  Then, as shown in FIGS. 15A and 15B, the first conductive film 31 formed on the first main surface 101 is covered so as to cover the entire region where the first groove 301 is formed. Is patterned. At this time, the portion of the first conductor film 31 that will be a connection region between the first substrate electrode 51 and the semiconductor substrate 10 is removed. Thereby, a part of the first dielectric film 21 is exposed on the first main surface 101.

  After patterning the first conductive film 31, a first surface insulating film 61 is formed on the entire first main surface 101 as shown in FIGS. 16 (a) and 16 (b). For example, an oxide film having a thickness of about 1 μm is formed on the upper surface of the first conductive film 31 and the exposed upper surface of the first dielectric film 21 as the first surface insulating film 61.

  Then, as shown in FIGS. 17A and 17B, the second conductor film 32 formed on the second main surface 102 is patterned in the same manner as the first conductor film 31. That is, a portion of the second conductor film 32 which is to be a connection region between the second substrate electrode 52 and the semiconductor substrate 10 is removed, leaving a portion covering a region where the second groove 302 is formed. Next, as shown in FIGS. 18A and 18B, a second surface insulating film 62 is formed on the entire surface of the second main surface 102. For example, an oxide film having a thickness of about 1 μm is formed as the second surface insulating film 62 on the upper surface of the second conductor film 32 and the exposed upper surface of the second dielectric film 22.

  Next, as shown in FIGS. 19A and 19B, a contact hole 201 is formed in the first surface insulating film 61, and a portion of the first conductor film 31 connected to the first conductor electrode 41 is formed. To expose. Further, a contact hole 202 is formed in the first surface insulating film 61 and the first dielectric film 21 to expose a portion of the first main surface 101 connected to the first substrate electrode 51.

  Thereafter, as shown in FIGS. 20A and 20B, a conductor film 400 such as a metal film is formed on the entire first main surface 101. Then, as shown in FIGS. 21A and 21B, the conductive film 400 is patterned to form the first conductive electrode 41 and the first substrate electrode 51.

  Further, as shown in FIGS. 22A and 22B, a contact hole 203 is formed in the second surface insulating film 62, and a portion of the second conductive film 32 connected to the second conductive electrode 42 is formed. To expose. Further, a contact hole 204 is formed in the second surface insulating film 62 and the second dielectric film 22 to expose a portion of the second main surface 102 connected to the second substrate electrode 52.

  Thereafter, as shown in FIGS. 23A and 23B, a conductor film 500 such as a metal film is formed on the entire surface of the second main surface 102. Then, the conductive film 500 is patterned to form the second conductive electrode 42 and the second substrate electrode 52. As described above, the semiconductor device 1 according to the first embodiment is completed.

  The thickness of the first dielectric film 21 and the second dielectric film 22 is set according to the withstand voltage required for the semiconductor device 1 and is, for example, about several hundred nm to 1 μm. As the first dielectric film 21 and the second dielectric film 22, a silicon oxide film formed by a film forming method other than the thermal oxidation method, a silicon nitride film having a higher dielectric constant than the silicon oxide film, or the like is used. be able to. Since a thermal oxide film can be formed evenly on the inner wall surface of the groove by the thermal oxidation method, a silicon nitride film may be laminated after the thermal oxide film is formed.

  For example, a Bosch process may be used to form a deep groove. After forming the groove, the first dielectric film 21 and the second dielectric film 22 are formed.

  In the above description, a polycrystalline silicon film is used for the first conductive film 31 and the second conductive film 32, but the polycrystalline silicon film is formed by, for example, a CVD method. Alternatively, a metal film such as an aluminum film or a copper film may be used for the first conductor film 31 and the second conductor film 32.

  By the manufacturing method of the semiconductor device 1 described above, the first groove 301 and the second groove 302 whose longitudinal directions intersect and whose bottoms are connected are formed in the semiconductor substrate 10. Since the grooves are formed in the thickness direction of the semiconductor substrate 10 from the first main surface 101 and the second main surface 102, a narrow groove having a small width can be formed. Then, a first capacitor structure sandwiching the first dielectric film 21 between the semiconductor substrate 10 and the first conductive film 31 is formed inside the first groove 301, and the semiconductor substrate 10 and the second conductive film 32 Thus, a second capacitor structure sandwiching the second dielectric film 22 is formed inside the second groove 302.

  According to the above-described manufacturing method, the first groove 301 formed on the first main surface 101 and the second groove 302 formed on the second main surface 102 of the semiconductor substrate 10 can be respectively formed without high alignment accuracy. Can be connected at the bottom. For this reason, the first conductor film 31 and the second conductor film 32 can be reliably electrically connected. As a result, the capacity of the semiconductor capacitor can be increased.

  Note that by forming the first groove 301 and the second groove 302 orthogonally, a resist film or an insulating film used as an etching mask in a photolithography process for forming the first groove 301 and the second groove 302 is formed. A mask reticle for patterning a film can be used in common. That is, the mask reticle used for forming the first groove 301 can be rotated by 90 degrees and used as a mask reticle for forming the second groove 302. As a result, manufacturing costs can be reduced.

  Further, by making the planar electrodes overlap the first principal surface 101 and the second principal surface 102 in plan view, a mask reticle for forming the planar electrodes on the first principal surface 101 and the second principal surface 102 Thus, a mask reticle for forming a planar electrode can be commonly used. Thereby, manufacturing cost can be suppressed. Furthermore, the arrangement region of the first conductive film 31 on the first main surface 101 and the arrangement region of the second conductive film 32 on the second main surface 102 may overlap in plan view. This makes it possible to use a common mask reticle for forming the first conductor film 31 and the second conductor film 32, thereby reducing the manufacturing cost.

  Furthermore, a connection region between the first conductor electrode 41 and the first conductor film 31 on the first main surface 101 and a connection region between the second conductor electrode 42 and the second conductor film 32 on the second main surface 102 May overlap in a plan view. That is, the shape and position of the contact hole 201 and the contact hole 203 may be the same in plan view. Further, the connection region between the first substrate electrode 51 and the semiconductor substrate 10 on the first main surface 101 and the connection region between the second substrate electrode 52 and the semiconductor substrate 10 on the second main surface 102 are overlapped in a plan view. May be. That is, the shapes and positions of the contact holes 202 and 204 may be the same in plan view. This makes it possible to use a mask reticle for forming a contact hole on the first main surface 101 and a mask reticle for forming a contact hole on the second main surface 102 in common, thereby reducing manufacturing costs. it can.

<Modification>
In the above description, an example in which the strip-shaped first conductor electrode 41 and the first substrate electrode 51 face each other on the first main surface 101 is shown, for example, as shown in FIG. The first conductor electrode 41 may be arranged at the portion, and the first substrate electrode 51 may be arranged at the outer edge of the first main surface 101. At this time, similarly, on the second main surface 102, the second conductor electrode 42 is arranged at the center of the second main surface 102, and the second substrate electrode 52 is arranged at the outer edge.

  That is, on the first main surface 101, the first substrate electrode 51 is arranged between the first conductor electrode 41 and the outer edge of the semiconductor substrate 10, and on the second main surface 102, the second substrate electrode 52 is connected to the second conductive electrode 41. It is arranged between the body electrode 42 and the outer edge of the semiconductor substrate 10.

  When the side surface of the semiconductor substrate 10 is exposed without being covered, a gap between the side surface of the semiconductor substrate 10 and the first conductor electrode 41 is provided for insulation between the semiconductor substrate 10 and the first conductor electrode 41. It is necessary to take a sufficient distance (creepage distance) along one main surface 101. On the other hand, the first substrate electrode 51 is an electrode connected to the semiconductor substrate 10 and does not need to be insulated from the side surface of the semiconductor substrate 10. By arranging the planar electrodes shown in FIG. 24, it is easy to ensure insulation between the semiconductor substrate 10 and the first conductor electrodes 41.

  Further, assuming that the semiconductor device 1 is mounted on the PCB substrate using a solder material, the solder material protruding from between the PCB substrate and the semiconductor device 1 may adhere to the side surface of the semiconductor substrate 10. As a result, when the plane electrode close to the side surface of the semiconductor substrate 10 is the first conductor electrode 41, there is a possibility that the side surface of the semiconductor substrate 10 and the first conductor electrode 41 are short-circuited. On the other hand, when the first substrate electrode 51 is close to the side surface of the semiconductor substrate 10 as shown in FIG. 24, there is no problem even if the side surface of the semiconductor substrate 10 and the first substrate electrode 51 are short-circuited.

  Further, as shown in FIG. 25, the first substrate electrode 51 disposed on the outer edge of the first main surface 101 may be disposed so as to surround the first conductor electrode 41. Similarly, the second substrate electrode 52 disposed on the second main surface 102 may be disposed so as to surround the second conductor electrode 42.

  The area of the plane electrode is preferably as large as possible to reduce the parasitic resistance of the semiconductor capacitor and to form a capacitor stack structure by joining the plane electrodes. With the arrangement shown in FIG. 25, the first substrate electrode 51 and the second substrate electrode 52 are brought closer to the outer edge of the semiconductor substrate 10 to increase the area of the planar electrode, and the first conductor electrode 41 and the second conductor electrode 42 Along the side surface of the semiconductor substrate 10.

(Second embodiment)
As shown in FIG. 26, the semiconductor device 1 according to the second embodiment of the present invention includes a first groove dividing portion 71 that divides a first groove into a plurality of regions along a longitudinal direction, and a second groove. Is provided with a second groove dividing portion 72 that divides the second groove into a plurality of regions along the longitudinal direction. In FIG. 26, the second dielectric film 22, the second conductive film 32, and the second groove dividing portion 72 are displayed through the semiconductor substrate 10.

  In the semiconductor device 1 shown in FIG. 26, the point where the linear first groove and the second groove are partially cut in the middle is that the first groove and the second groove are linearly continuous. Is different from the semiconductor device 1 shown in FIG. Other configurations are the same as those of the first embodiment shown in FIG.

  In the semiconductor device 1, for example, a groove having a width of about several μm is formed in a semiconductor substrate 10 having one side of a rectangular shape of about 10 mm. For this reason, when the first groove and the second groove having a large aspect ratio of the depth and width of the groove are formed in parallel, if the distance between the grooves is small, the strength of the wall between the grooves is weak. Become. As a result, there is a possibility that a wall portion between the grooves may be broken in a processing step before embedding the inside of the grooves. For example, in some cases, a thermal oxide film is formed as a sacrificial oxide film on the inner wall surface of the groove to improve characteristics after the groove is formed, and a dielectric film is formed after removing the sacrificial oxide film. At this time, in the cleaning step for removing the sacrificial oxide film, the pressure between the flows of the cleaning liquid may destroy the walls between the grooves.

  On the other hand, in the semiconductor device 1 shown in FIG. 26, by providing the first groove dividing portion 71 and the second groove dividing portion 72 functioning as beams, the linear portion of the groove is shortened. Thereby, the strength of the wall between the grooves can be improved.

  The length of each part of the groove divided by the first groove dividing part 71 and the second groove dividing part 72 is about several tens μm to several hundred μm. The length in the longitudinal direction of the first groove dividing portion 71 and the second groove dividing portion 72 is about 2 μm to 3 μm. The length of each portion of the first groove and the second groove and the length of the first groove dividing portion 71 and the second groove dividing portion 72 are set so that the wall portion between the grooves is not broken by a cleaning process or the like. Is set to

  In FIG. 26, the connection region between the first groove and the second groove is indicated by a black square (■). As shown in FIG. 26, all the grooves of the first groove are connected to any of the second grooves, and all the grooves of the second groove are connected to any of the first grooves.

  By the way, the region where the first groove and the second groove dividing portion 72 overlap and the region where the second groove and the first groove dividing portion 71 overlap do not become the connection region. Then, as shown in FIG. 27, a first groove overlapping all intersecting second grooves and the second groove dividing portion 72, and a first groove overlapping all intersecting first grooves and the first groove dividing portion 71. 2 grooves may occur. In this case, a region where the first conductor film 31 and the second conductor film 32 are not electrically connected occurs, and the parasitic resistance of the semiconductor capacitor increases.

  In order to prevent the occurrence of a region in which the first conductor film 31 and the second conductor film 32 are not electrically connected as described above, as shown in FIG. It is effective to shift the position along the longitudinal direction of the groove without arranging the grooves in parallel. That is, the first groove dividing portions 71 of the first grooves adjacent to each other are not arranged in parallel with the longitudinal direction of the second grooves. Therefore, an imaginary straight line connecting the first groove dividing portions 71 of the adjacent first grooves and the longitudinal direction of the second grooves obliquely intersect in plan view. Then, the second groove dividing portions 72 of the second grooves adjacent to each other are not arranged in parallel with the longitudinal direction of the first groove. For this reason, a virtual straight line connecting the second groove dividing portions 72 of the adjacent second grooves and the longitudinal direction of the first groove obliquely intersect in plan view. This ensures that the first conductor film 31 and the second conductor film 32 are electrically connected.

  To form the semiconductor device 1 shown in FIG. 26, in the process described with reference to FIGS. 11A and 11B, the first groove 301 is divided into a plurality of regions along the longitudinal direction. The first groove dividing portion 71 is arranged so as to perform the above. For example, the first groove is formed in a state where a portion where the first groove dividing portion 71 is formed is masked by an etching mask. At this time, the first groove dividing portions 71 of the first grooves 301 adjacent to each other are not arranged in parallel with the longitudinal direction of the second grooves 302. That is, the first groove dividing portions 71 are arranged such that a virtual straight line connecting the first groove dividing portions 71 of the adjacent first grooves 301 obliquely intersects the longitudinal direction of the second grooves 302 in plan view. . In the process described with reference to FIGS. 12A and 12B, a second groove dividing portion 72 that divides the second groove 302 into a plurality of regions along the longitudinal direction is arranged. Then, the respective second groove dividing portions 72 of the second grooves 302 adjacent to each other are not arranged in parallel with the longitudinal direction of the first grooves 301. That is, the second groove dividing portions 72 are arranged such that a virtual straight line connecting the second groove dividing portions 72 of the adjacent second grooves 302 obliquely intersects the longitudinal direction of the first grooves 301 in plan view. .

  According to the semiconductor device 1 shown in FIG. 26, it is possible to prevent the wall between the grooves from being broken during the manufacturing. Others are substantially the same as the first embodiment, and redundant description will be omitted.

  As described above, the present invention has been described by the embodiments. However, it should not be understood that the description and drawings forming part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 21 ... 1st dielectric film 22 ... 2nd dielectric film 31 ... 1st conductor film 32 ... 2nd conductor film 41 ... 1st conductor electrode 42 ... 2nd conductor electrode 51 ... 1st Substrate electrode 52 Second substrate electrode 61 First surface insulating film 62 Second surface insulating film 71 First groove dividing portion 72 Second groove dividing portion 101 First main surface 102 Second main surface

Claims (20)

It has a first main surface and a second main surface facing each other, a first groove is formed in the first main surface, a longitudinal direction of the first groove intersects with the longitudinal direction of the first groove in a plan view, and a bottom portion is formed. A conductive semiconductor substrate having a second groove connected to the bottom of the first groove formed on the second main surface;
A first dielectric film disposed on an inner wall surface of the first groove;
A first conductor film disposed inside the first groove and facing the semiconductor substrate via the first dielectric film;
A second dielectric film disposed on an inner wall surface of the second groove;
The first groove is disposed inside the second groove, is opposed to the semiconductor substrate via the second dielectric film, and is connected to the bottom of the first groove and the bottom of the second groove. A second conductive film electrically connected to the conductive film,
A semiconductor device, wherein the first conductive film and the second conductive film are electrically insulated from the semiconductor substrate by the first dielectric film and the second dielectric film. A plurality of the first grooves are linearly formed on the first main surface in parallel with each other;
A plurality of the second grooves are linearly formed on the second main surface in parallel with each other;
2. The semiconductor device according to claim 1, wherein a longitudinal direction of the first groove and a longitudinal direction of the second groove are orthogonal to each other in a plan view. A first groove dividing portion that divides the first groove into a plurality of regions along a longitudinal direction;
The semiconductor device according to claim 2, further comprising: a second groove dividing portion that divides the second groove into a plurality of regions along a longitudinal direction. An imaginary straight line connecting the first groove dividing portions of the first grooves adjacent to each other and a longitudinal direction of the second groove obliquely intersect in plan view,
An imaginary straight line connecting the second groove dividing portions of the second grooves adjacent to each other and a longitudinal direction of the first groove obliquely intersect in a plan view. 13. The semiconductor device according to claim 1.   5. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a material having an insulating film formed on a surface thereof by heat treatment in a gas atmosphere. 6.   The semiconductor device according to claim 5, wherein the semiconductor substrate is a silicon substrate. A first conductor electrode disposed on the first main surface and electrically connected to the first conductor film;
A first substrate electrode disposed on the first main surface and electrically connected to the semiconductor substrate;
A second conductor electrode disposed on the second main surface and electrically connected to the second conductor film;
A second substrate electrode disposed on the second main surface and electrically connected to the semiconductor substrate;
The first conductor electrode and the second conductor electrode are arranged in a region where they overlap in a plan view,
The semiconductor device according to claim 1, wherein the first substrate electrode and the second substrate electrode are arranged in a region where the first substrate electrode and the second substrate electrode overlap in a plan view. On the first main surface, the first substrate electrode is disposed between the first conductor electrode and an outer edge of the semiconductor substrate;
The semiconductor device according to claim 7, wherein the second substrate electrode is disposed between the second conductor electrode and an outer edge of the semiconductor substrate on the second main surface. The first substrate electrode is disposed so as to surround the first conductor electrode;
The semiconductor device according to claim 8, wherein the second substrate electrode is arranged so as to surround a periphery of the second conductor electrode. An arrangement region of the first conductor film on the first main surface and an arrangement region of the second conductor film on the second main surface overlap in plan view;
A connection region between the first conductor electrode and the first conductor film on the first main surface and a connection region between the second conductor electrode and the second conductor film on the second main surface are different from each other. Overlap in plan view,
A connection region between the first substrate electrode and the semiconductor substrate on the first main surface and a connection region between the second substrate electrode and the semiconductor substrate on the second main surface overlap in plan view. The semiconductor device according to claim 7, wherein: Forming a first groove in a first main surface of a semiconductor substrate having conductivity;
A second groove is formed on a second main surface of the semiconductor substrate facing the first main surface such that the first groove and the longitudinal direction of the first groove cross each other in plan view and the bottoms thereof are connected. Process and
Forming a first dielectric film on the inner wall surface of the first groove;
Forming a second dielectric film on the inner wall surface of the second groove;
Laminating a first conductive film on the first dielectric film inside the first groove;
A second conductive film is laminated on the second dielectric film inside the second groove, and the first conductive film is formed in a region where a bottom of the first groove is connected to a bottom of the second groove. And a step of electrically connecting the second conductive film,
A method of manufacturing a semiconductor device, wherein the first conductive film and the second conductive film are electrically insulated from the semiconductor substrate by the first dielectric film and the second dielectric film. Forming a plurality of the first grooves on the first main surface in a straight line parallel to each other;
Forming a plurality of the second grooves in a straight line parallel to each other on the second main surface such that the longitudinal direction of the first groove and the longitudinal direction of the second groove are orthogonal to each other in a plan view. The method for manufacturing a semiconductor device according to claim 11, wherein: Arranging a first groove dividing portion for dividing the first groove into a plurality of regions along the longitudinal direction,
The method for manufacturing a semiconductor device according to claim 12, wherein a second groove dividing portion that divides the second groove into a plurality of regions along a longitudinal direction is arranged. The first groove dividing portions are arranged such that a virtual straight line connecting the first groove dividing portions of the first grooves adjacent to each other obliquely intersects the longitudinal direction of the second groove in a plan view. ,
The second groove dividing portions are arranged so that a virtual straight line connecting the respective second groove dividing portions of the adjacent second grooves obliquely intersects the longitudinal direction of the first groove in a plan view. The method for manufacturing a semiconductor device according to claim 13, wherein:   The method for manufacturing a semiconductor device according to claim 11, wherein a material whose surface is formed with an insulating film by heat treatment in a gas atmosphere is used for the semiconductor substrate.   The method according to claim 15, wherein a silicon substrate is used as the semiconductor substrate. Arranging a first conductor electrode electrically connected to the first conductor film on the first main surface;
Disposing a first substrate electrode electrically connected to the semiconductor substrate on the first main surface;
Arranging a second conductor electrode electrically connected to the second conductor film on the second main surface;
Arranging a second substrate electrode electrically connected to the semiconductor substrate on the second main surface;
The first conductor electrode and the second conductor electrode are arranged in a region overlapping in a plan view,
The method for manufacturing a semiconductor device according to claim 11, wherein the first substrate electrode and the second substrate electrode are arranged in a region overlapping in a plan view. On the first main surface, the first substrate electrode is arranged between the first conductor electrode and an outer edge of the semiconductor substrate;
The method according to claim 17, wherein the second substrate electrode is disposed between the second conductor electrode and an outer edge of the semiconductor substrate on the second main surface. Disposing the first substrate electrode so as to surround a periphery of the first conductor electrode;
19. The method according to claim 18, wherein the second substrate electrode is arranged so as to surround a periphery of the second conductor electrode. An arrangement region of the first conductor film on the first main surface and an arrangement region of the second conductor film on the second main surface in a plan view;
A connection region between the first conductor electrode and the first conductor film on the first main surface and a connection region between the second conductor electrode and the second conductor film on the second main surface. Layered in plan view,
A connection region between the first substrate electrode and the semiconductor substrate on the first main surface and a connection region between the second substrate electrode and the semiconductor substrate on the second main surface are overlapped in a plan view. 20. The method of manufacturing a semiconductor device according to claim 17, wherein

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