JP2007095950A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, of which a capacitor is integrated without increasing a chip area. <P>SOLUTION: In a semiconductor device 100, a plurality of elements including a capacitor 20 are configured on a semiconductor substrate 10. The semiconductor substrate 10 has an SOI structure in which a semiconductor layer 13 are stacked on a support board 11 through an insulating layer 12. Among a plurality of elements, the capacitor 20 is formed on the support board 11 side, with other elements 30 formed on the semiconductor layer 13 side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device comprising a plurality of elements including capacitors on a semiconductor substrate, and a method for manufacturing the same.

2. Description of the Related Art Conventionally, in a semiconductor device in which a plurality of elements including a capacitor are formed on a semiconductor substrate, the area occupied by the capacitor is larger than that of other elements, which is a problem in increasing the mounting density (miniaturization). . Therefore, for example, as shown in Patent Document 1, a semiconductor substrate in which a trench (groove) is formed, an insulating layer (dielectric layer) formed on the surface of the trench, and a conductive material formed so as to fill the trench through the insulating layer. A capacitor composed of a body layer (metal layer) has been proposed. According to this so-called vertical capacitor, the area occupied by the capacitor can be reduced as compared with a so-called planar (horizontal) capacitor.
Japanese Patent Publication No. 3-30302

  However, in the case of the configuration shown in Patent Document 1, the capacitor and other elements (for example, transistors) other than the capacitor must be arranged in the planar direction of the semiconductor substrate. The size of the semiconductor substrate in the planar direction) increases.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which capacitors are integrated without increasing the chip area and a method for manufacturing the same.

  In order to achieve the above object, the invention described in claim 1 is a semiconductor device comprising a plurality of elements including capacitors on a semiconductor substrate, the semiconductor substrate being interposed on an insulating layer on a support substrate. A semiconductor substrate having an SOI structure in which semiconductor layers are stacked, wherein a capacitor is formed on a support substrate side among a plurality of elements, and other elements are formed on a semiconductor layer side.

  As described above, according to the present invention, a semiconductor substrate having an SOI structure is adopted as a semiconductor substrate, a capacitor is configured on the support substrate side that has not been applied as a conventional element formation region, and an element other than the capacitor is configured on the semiconductor layer side. ing. That is, the capacitor having a large occupied area and the other elements are configured in different regions. Therefore, this is a semiconductor device in which capacitors are integrated without increasing the chip area (size in the planar direction of the semiconductor substrate).

  According to a second aspect of the present invention, there is provided a support substrate on which a trench extending in the stacking direction of the capacitor is formed, an insulating film formed on the surface of the trench, and a capacitor electrode formed so as to fill the trench through the insulating film. It is preferable to make it the structure included. In this case, if the capacitors have the same capacitance, the chip area can be further reduced. Further, if the chip area is the same, the capacitance of the capacitor can be increased. That is, a semiconductor device in which a large-capacity capacitor is integrated can be obtained without increasing the chip area. As the configuration of the large-capacitance capacitor, a configuration in which a plurality of trenches are arranged and capacitance electrodes are connected to form a repetitive pattern such as a comb-teeth shape or an S-shape as described in claim 3 is adopted. can do.

  Next, a specific configuration example is shown. For example, as described in claim 4, the trench may be formed from the insulating layer lamination surface side of the support substrate. At this time, as described in claim 5, an external connection electrode is formed on the back surface of the insulating layer lamination surface of the support substrate constituting one of the capacitor electrodes of the capacitor, and the back surface of the semiconductor substrate (the surface of the support substrate) Or an external connection disposed through the semiconductor layer and the insulating layer with respect to the support substrate constituting one of the capacitor electrodes as described in claim 6. The through electrodes may be electrically connected. Furthermore, as described in claim 7, the external connection through electrode disposed through the semiconductor layer and the insulating layer is electrically connected to the capacitor electrode constituting the other of the capacitor electrodes. Also good.

  In particular, when the through electrode is electrically connected to the support substrate and the capacitor electrode constituting the capacitor, the two electrodes constituting the capacitor only on the surface side of the semiconductor substrate (the surface side of the semiconductor layer) Conductivity can be obtained. Moreover, since each penetration electrode can be formed at the same process, a manufacturing process can be simplified rather than the structure which forms the electrode for external connection on the back surface (front surface of a support substrate) of a semiconductor substrate.

  Further, as described in claim 8, the trench may be formed from the back side of the insulating layer lamination surface of the support substrate. In this case, the capacitor electrode which is one of the electrodes constituting the capacitor is exposed on the back surface of the semiconductor substrate (the surface of the support substrate). Therefore, according to a ninth aspect of the present invention, there is provided a structure in which a through electrode for external connection formed through the semiconductor layer and the insulating layer is electrically connected to a support substrate that is the other of the electrodes constituting the capacitor. By doing so, it is possible to establish conduction with both electrodes constituting the capacitor.

  Further, as described in claim 10, the trench may be formed from the insulating layer lamination surface side of the support substrate and the back surface side of the insulating layer lamination surface. In this case, different capacitors can be formed at the respective trench formation sites. In this case, as described in claim 11, a configuration in which a through electrode for external connection disposed through the semiconductor layer and the insulating layer is electrically connected to the capacitor electrode formed on the insulating layer lamination surface side It is also good. Further, the conduction with the support substrate may be taken on the front surface side of the semiconductor substrate (semiconductor layer) through the through electrode, or may be taken on the back surface side (front surface of the support substrate) side of the semiconductor substrate. As described in claim 12, when a different capacitor is electrically connected in parallel, a capacitor having a larger capacity can be formed without increasing the chip area.

  According to the thirteenth aspect of the present invention, the through electrode for conducting with the electrode (support substrate or capacitor electrode) constituting the capacitor has an electrical connection function in the semiconductor layer in consideration of the influence on other elements. It is formed in a region that does not provide (so-called field region). Therefore, the potential of the through electrode is the ground potential (ground). On the other hand, as described in claim 14, in a region that does not provide an electrical connection function, when the periphery of the through electrode is surrounded by an insulating region that reaches the insulating layer, the potential of the through electrode is set to other than the ground. The potential can be set. As the insulating region, for example, a trench isolation region can be employed as described in claim 15. In addition, an insulating film formed on the inner wall of the through hole constituting the through electrode can also be employed.

  Note that the number of capacitors formed on the support substrate is not limited to one. According to a sixteenth aspect of the present invention, a plurality of capacitors may be formed on the support substrate, and each capacitor may be electrically insulated and separated by the element isolation region. In this case, as the element isolation region, for example, a configuration including a groove formed in the support substrate can be adopted as described in claim 17. Specifically, a trench formed by a trench isolation region or anisotropic etching can be employed. The formation timing of the element isolation region is not particularly limited.

  Next, the invention described in claims 18 to 32 relates to a manufacturing method for manufacturing the semiconductor device described above. A method for manufacturing a semiconductor device comprising a plurality of elements including a capacitor formed on a semiconductor substrate, wherein the semiconductor layer is laminated on the support substrate via an insulating layer. And a step of preparing an SOI structure semiconductor substrate, a step of forming at least one capacitor on a support substrate, and a step of forming an element excluding the capacitor on a semiconductor layer of the semiconductor substrate. Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 1, the description thereof is omitted.

  Since the operational effects of the inventions according to claims 19 and 20 are the same as the operational effects of the inventions according to claims 2 and 3, the description thereof is omitted.

  In the case where the trench is formed on the support substrate from the insulating layer lamination surface side, the step of preparing the semiconductor substrate may be performed after the step of forming the capacitor. Further, when an element other than a capacitor is formed, an insulating film or the like is also formed on the surface of the support substrate that is the back surface of the semiconductor substrate. Accordingly, in the case where the external connection electrode electrically connected to the support substrate is formed on the back surface of the insulating layer lamination surface of the support substrate, the device is implemented after forming an element other than the capacitor as described in claim 22. Good. In that case, in the step of forming an element, a through hole penetrating at least the semiconductor layer is formed, a conductive member is disposed in the through hole, and one end is electrically connected to the support substrate as described in claim 23. A through electrode for external connection connected to the electrode may be formed, or a through electrode for external connection whose one end is electrically connected to the capacitor electrode as described in claim 24 may be formed. Thereby, electrical connection with the electrode which comprises a capacitor can be established in the surface (semiconductor layer surface) side of a semiconductor substrate. Note that, in the above, when a part of the insulating film constituting the semiconductor substrate is previously opened (so-called partial SOI structure) (that is, when the semiconductor substrate is prepared to have a hole in the preparation step). The through hole may be formed only in the semiconductor layer. In the case where no hole is formed, a through hole penetrating the semiconductor layer and the insulating layer may be formed.

  In the case of forming a capacitor by forming a trench from the back side of the insulating layer lamination surface of the support substrate as described in claim 25, the capacitor forming step may be performed after preparing the semiconductor substrate. Further, when an element other than a capacitor is formed, an insulating film or the like is also formed on the surface of the support substrate that is the back surface of the semiconductor substrate. Therefore, as described in claim 26, a capacitor is preferably formed after the element is formed. In this case, as described in claim 27, in the step of forming an element, a through hole penetrating at least the semiconductor layer is formed, a conductive member is disposed in the through hole, and one end is electrically connected to the support substrate. A through-electrode for external connection that is connected to the outside may be formed. Thereby, electrical connection with the electrode (support substrate) which comprises a capacitor can be established in the surface (surface of a semiconductor layer) side of a semiconductor substrate. Note that, in the above, when a part of the insulating film constituting the semiconductor substrate is previously opened (so-called partial SOI structure) (that is, when the semiconductor substrate is prepared to have a hole in the preparation step). The through hole may be formed only in the semiconductor layer. In the case where no hole is formed, a through hole penetrating the semiconductor layer and the insulating layer may be formed.

  Since the operational effects of the inventions according to claims 28 to 30 are the same as the operational effects of the inventions according to claims 13 to 15, respectively, the description thereof is omitted.

  According to a thirty-first aspect of the present invention, an element isolation region that divides a capacitor into a plurality of parts may be formed on the support substrate. In this manner, by forming the element isolation region, a structure having a plurality of capacitors can be obtained. The formation timing of the element isolation region is not particularly limited. It may be before or after the formation of the capacitor, or may be formed in parallel with the capacitor. Specifically, as described in claim 32, a groove may be formed in the support substrate as at least a part of the element isolation region.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, a semiconductor device 100 according to the present embodiment is a semiconductor device in which a plurality of elements including a capacitor 20 are configured on a semiconductor substrate 10. In FIG. 1, for convenience, electrodes, wirings, interlayer insulating films, protective films and the like are omitted.

The semiconductor substrate 10 is an SOI (Silicon On Insulator) substrate in which an insulating film is embedded, and includes a support substrate 11 in which impurities (for example, phosphorus) are introduced into silicon (Si), and a silicon oxide film (SiO ₂ ). The insulating layer 12 includes an n-type semiconductor layer 13 stacked on the support substrate 11 with the insulating layer 12 interposed therebetween. The semiconductor layer 13 includes an n + type semiconductor layer 13a disposed on the side of the laminated surface with the insulating layer 12, and an n− type semiconductor layer 13b which is an upper layer thereof.

  The capacitor 20 is formed on the support substrate 11 side in the semiconductor substrate 10. A trench (groove) 21 extending in the stacking direction from the insulating layer stack surface side is formed in the support substrate 11. In addition, an insulating film 22 (a silicon oxide film in the present embodiment) as a dielectric is formed on the surface of the trench 21, and a capacitor electrode 23 is formed so as to fill the trench 21 via the insulating film 22. Yes. That is, the capacitor 20 is configured in which the support substrate 11 in which the trench 21 is formed and the capacitor electrode 23 are used as electrodes and the insulating film 22 is a dielectric between the electrodes. In the present embodiment, a plurality of trenches 21 are arranged, and capacitive electrodes 23 disposed in the respective trenches 21 are connected to form a comb shape. In addition to the comb-teeth shape, a repetitive pattern such as an S shape may be adopted to increase the area of the capacitor 20. In FIG. 1, reference numeral 24 denotes a back electrode for external connection formed on the back surface of the insulating layer lamination surface of the support substrate 11 (that is, electrically connected to the support substrate 11), and reference numeral 25 denotes the insulating layer 12. In addition, a through electrode for external connection is provided through the semiconductor layer 13 and has one end connected to the capacitor electrode 23.

  A plurality of elements 30 (for example, transistors) other than the capacitor 20 are formed on the semiconductor substrate 10. In FIG. 1, an NPN bipolar transistor is shown as an example of the element 30. Reference numeral 31 denotes a p-type diffusion region as a base formed in the surface layer portion of the n − -type semiconductor layer 13b, and reference numeral 32. Is an n + type diffusion region as an emitter formed in the surface layer part of the p type diffusion region, and numeral 33 is an n + type diffusion region as a collector formed in the surface layer part of the n− type semiconductor layer 13b. In FIG. 1, reference numeral 40 denotes a trench isolation region formed so as to reach the insulating layer 12 in order to isolate and isolate a plurality of elements 30, and reference numeral 41 denotes a LOCOS oxide formed on the surface layer of the semiconductor layer 13. It is a membrane.

  As described above, the semiconductor device 100 according to the present embodiment employs the semiconductor substrate 10 having the SOI structure, configures the capacitor 20 on the support substrate 11 side that has not been applied as a conventional element formation region, and configures the capacitor on the semiconductor layer 13 side. The elements 30 other than 20 are configured. That is, the capacitor 20 having a large occupied area and the other elements 30 are configured in different regions. Therefore, the semiconductor device 100 in which the capacitors 20 are integrated is obtained without increasing the chip area (size in the planar direction of the semiconductor substrate).

  The capacitor 20 includes a support substrate 11 in which a trench 21 extending in the stacking direction is formed, an insulating film 22 formed on the surface of the trench 21, and a capacitive electrode formed so as to fill the trench 21 via the insulating film 22. 23 is included. Therefore, if the capacitance of the capacitor 20 is the same, the chip area can be further reduced. Further, if the chip area is the same, the capacitance of the capacitor 20 can be increased. In particular, in the present embodiment, since a plurality of trenches 21 are arranged and the capacitance electrode 23 is comb-shaped, the semiconductor device 100 is integrated with a large-capacity capacitor 20 without increasing the chip area. Since the facing area between the support substrate 11 and the capacitor electrode 23 and the film thickness of the insulating film 22 (especially adjustment by the facing area) are determined according to the required capacity, it is possible to cope with a small capacity to a large capacity. is there.

  In the present embodiment, the through electrode 25 for conducting with the capacitor electrode 23 is a region that does not provide an electrical connection function in the semiconductor layer 13 in consideration of the influence on the other element 30 (so-called field region). ). Specifically, the semiconductor layer 13 is formed in a region separated from the formation region of the element 30 by the trench isolation region 40 while penetrating the LOCOS oxide film. Therefore, the potential of the through electrode 25 is the ground potential (ground).

  Next, an example of a method for manufacturing the semiconductor device 100 having the above configuration will be described with reference to FIG. 2A and 2B are cross-sectional views by process for explaining an outline of a method for manufacturing the semiconductor device 100, wherein FIG. 2A is a capacitor formation process, FIG. 2B is a semiconductor substrate preparation process, FIG. 2C is an element formation process, d) shows the back electrode forming step. In the semiconductor device 100 according to the present embodiment, since the trench 21 formed in the support substrate 11 extends from the insulating layer stacking surface side in the stacking direction, the support substrate is prepared before preparing the SOI structure semiconductor substrate 10. 11 is formed with a capacitor 20.

  As shown in FIG. 2A, first, a trench mask is formed on the insulating layer stack surface of the support substrate 11, and is formed with a predetermined depth from the insulating layer stack surface side of the support substrate 11, for example, by reactive ion etching. A plurality of trenches 21 are formed. Then, a silicon oxide film as the insulating film 22 is formed on the surface of the trench 21 by, for example, a thermal oxidation method, and polysilicon doped with impurities so as to fill the trench 21 is introduced through the insulating film 22. At this time, since polysilicon is also disposed on the surface of the support substrate 11, the polysilicon in each trench 21 is integrated into a comb-like capacitor electrode 23. The capacitor electrode 23 may be formed by diffusing impurities after introducing polysilicon. As a result, the capacitor 20 is formed in which the support substrate 11 in which the trench 21 is formed and the capacitor electrode 23 are used as electrodes and the insulating film 22 is sandwiched between the electrodes.

  After the capacitor 20 is formed, the semiconductor substrate 10 having an SOI structure is formed. A silicon oxide film as the insulating layer 12 is formed on the surface of the support substrate 11 on the capacitor electrode 23 forming surface side by, for example, a thermal oxidation method. Separately from the support substrate 11 having the above-described structure, a semiconductor layer 13 in which an n + type semiconductor layer 13a is formed on the stacked surface side and an n− type semiconductor layer 13b is formed thereon is separately prepared. Then, as shown in FIG. 2 (b), the semiconductor layer 13 is laminated on the support substrate 11 via the insulating layer 12 by a bonding method (adhesion by heat and pressure), and the semiconductor layer 13 is ground and removed. Set to a predetermined thickness. Thus, the semiconductor substrate 10 is formed.

  Next, as shown in FIG. 2C, an element 30 other than the capacitor 20 is formed in the semiconductor layer 13. In addition to the formation of the element 30, a capacitor electrode 23 constituting the capacitor 20 and a through electrode 25 for external connection for conducting on the surface side of the semiconductor layer 13 are also formed.

  First, a trench isolation region 40 which is an element isolation region is formed, and then a LOCOS oxide film 41 is formed. Specifically, a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed in this order on the surface of the semiconductor layer 13 by thermal oxidation, CVD, or the like, and the uppermost silicon oxide film is patterned to form trench isolation. The trench constituting the region 40 is formed by, for example, reactive ion etching. Then, after removing the patterned silicon oxide film, a silicon oxide film is formed on the surface of the trench by thermal oxidation, and polysilicon is embedded through the silicon oxide film. Thereby, the trench isolation region 40 is formed. Next, the uppermost polysilicon is removed, the silicon nitride film is patterned to form a mask for the LOCOS oxide film 41, and a silicon oxide film is grown by thermal oxidation to form the LOCOS oxide film 41.

  After the LOCOS oxide film 41 is formed, a trench is formed in the field region of the semiconductor layer 13 that penetrates the LOCOS oxide film 41 by, for example, reactive ion etching and is isolated from the element formation region by the trench isolation region 40. Then, the insulating film 12 on the extension of the trench is selectively etched, and polysilicon doped with impurities (so-called doped poly) is buried in the trench penetrating the semiconductor layer 13 and the insulating layer 12, so that one end has a capacitance. A through electrode 25 connected to the electrode 23 is formed. Note that polysilicon may be embedded after an insulating film is formed on the surface of the trench.

  Then, after excess polysilicon on the surface of the semiconductor layer 13 is etched back, the element 30 is formed. Since a known semiconductor manufacturing technique can be applied to the formation method of the element 30 and it is not a characteristic part of the invention according to the present embodiment, detailed description thereof is omitted. For example, impurities are diffused into the semiconductor layer 13b to form a p-type diffusion region 31 as a base, an n + -type diffusion region 32 as an emitter, and an n + -type diffusion region 33 as a collector. Then, after forming the diffusion regions 31 to 33, an interlayer insulating film, a contact, an electrode, a protective film, and the like are sequentially formed. Thus, the element 30 is formed. Further, in the process of forming the element 30, the through electrode 25 is also connected to the outside.

  After the element 30 is formed, a back electrode 24 for external connection is formed on the back surface of the semiconductor substrate 10 (the surface of the support substrate 11) as shown in FIG. First, the silicon oxide film and polysilicon adhering to the surface of the support substrate 11 are polished and removed, and then an electrode constituent material is deposited on the surface of the support substrate 11 by using, for example, a sputtering method. In the present embodiment, the back electrode 24 made of TiNiAu is formed. Through the above steps, the semiconductor device 100 shown in FIG. 1 can be formed.

  In the present embodiment, an example in which the insulating layer 12 is selectively etched in order to form the through electrode 25 in the step of forming the element 30 has been described. However, in the process of forming the semiconductor substrate 10, the insulating layer 12 may be formed on the support substrate 11 so that the position corresponding to the through electrode 25 is opened. In other words, the semiconductor substrate 10 having a partial SOI structure may be applied.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. 3A and 3B are diagrams showing a schematic configuration of the semiconductor device 100 according to the present embodiment, in which FIG. 3A is a cross-sectional view and FIG. 3B is a plan view of the support substrate 11 as viewed from the insulating layer 12 side.

  Since the semiconductor device 100 and the manufacturing method thereof in the second embodiment are often in common with those according to the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly. In the first embodiment, an example in which the back electrode 24 is formed on the back surface of the semiconductor substrate 10 (the front surface of the support substrate 11) as an external connection electrode electrically connected to the support substrate 11 has been described. However, in the present embodiment, as shown in FIG. 3A, as an external connection electrode electrically connected to the support substrate 11, the insulating layer 12 and the semiconductor layer 13 are disposed so as to penetrate one end. A through electrode 26 connected to the substrate 11 is employed. The through electrode 26 has the same configuration as that of the through electrode 25 having one end connected to the capacitor electrode 23 shown in the first embodiment, and is formed at a position that does not overlap with the site where the capacitor electrode 23 is formed. FIG. 3B is a plan view of the support substrate 11 as viewed from the insulating layer 12 side. Reference numeral 25 a indicates a connection position with the through electrode 25, and reference numeral 26 a indicates a connection position with the through electrode 26.

  As described above, according to the semiconductor device 100 according to the present embodiment, the conduction between the two electrodes (the support substrate 11 and the capacitor electrode 23) constituting the capacitor 20 is performed only on the surface side of the semiconductor substrate 10 (surface side of the semiconductor layer 13). Can take. In addition, since each of the through electrodes 25 and 26 can be formed in the same process, the manufacturing process is simpler than the configuration in which the back electrode 24 for external connection is formed on the back surface of the semiconductor substrate 10 (the surface of the support substrate 11). Can be

  The semiconductor device 100 can be formed in almost the same process as the method for manufacturing the semiconductor device 100 shown in the first embodiment. The difference is that in the process of forming the capacitor 20, after the capacitor electrode 23 is formed, a planarization process (etch back) is performed so that polysilicon does not remain on the surface of the support substrate 11, and then the insulating layer 12 is formed. In the step of forming the element 30, the through electrode 26 is formed together with the through electrode 25. Therefore, the step of forming the back electrode 24 can be omitted.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing a schematic configuration of the semiconductor device 100 according to the present embodiment. 5A and 5B are cross-sectional views for each process for explaining an outline of the manufacturing method of the semiconductor device 100, where FIG. 5A is an element isolation region forming step, FIG. 5B is a through electrode forming step, and FIG. , (D) shows a capacitor formation step.

  Since the semiconductor device 100 and the manufacturing method thereof in the third embodiment are often in common with those of the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  In the present embodiment, as shown in FIG. 4, the trench 21 is formed from the back side of the insulating layer lamination surface of the support substrate 11 (that is, the back side of the semiconductor substrate 10). The capacitor electrode 23, which is one of the electrodes constituting the capacitor 20, is exposed on the back surface of the semiconductor substrate 10 (the surface of the support substrate 11). Therefore, it is not necessary to provide an electrode for external connection separately. In addition, one end of a through-electrode 26 for external connection formed through the semiconductor layer 13 and the insulating layer 12 is electrically connected to the support substrate 11 which is the other electrode constituting the capacitor 20. The other configuration is the same as that of the semiconductor device 100 shown in the first embodiment. The semiconductor device 100 having the above configuration can be formed as follows. In the semiconductor device 100 according to the present embodiment, the trench 21 formed in the support substrate 11 is configured to extend in the stacking direction from the back surface side of the insulating layer stacking surface. Therefore, after the SOI structure semiconductor substrate 10 is prepared, the support is performed. A capacitor 20 is formed on the substrate 11. Further, when the element 30 other than the capacitor 20 is formed, an insulating film or the like is also formed on the surface of the support substrate 11 that is the back surface of the semiconductor substrate 10. Therefore, an example in which the capacitor 20 is formed after the element 30 is formed will be described.

  An element 30 is formed on the prepared semiconductor substrate 10 having an SOI structure. As shown in FIG. 5A, as in the first embodiment, first, a trench isolation region 40 which is an element isolation region is formed, and then a LOCOS oxide film 41 is formed. The formation method is the same as in the first embodiment. Next, as shown in FIG. 5B, the through electrode 26 is formed so that one end is connected to the support substrate 11. This is also the same as the formation of the through electrode 25 shown in the first embodiment. Then, after the through electrode 26 is formed, the element 30 is formed. The formation method of the element 30 is the same as that of the first embodiment.

  After the element 30 is formed, the silicon oxide film or polysilicon adhered to the back surface of the semiconductor substrate 10 (the surface of the support substrate 11) is polished and removed, and a trench mask (not shown) is used as the insulating layer lamination surface of the support substrate 11 Form on top. Then, a plurality of trenches 21 having a predetermined depth are formed from the back surface side of the insulating layer lamination surface of the support substrate 11 by, for example, reactive ion etching. Here, after the element 30 is formed, the capacitor 20 is formed. Therefore, it is preferable to consider the diffusion region, the wiring, etc. constituting the element 30 so as not to be affected by the heat at the time of capacitor formation. Therefore, in the present embodiment, after forming the trench, a silicon oxide film as the insulating film 22 is formed on the surface of the trench 21 by, for example, CVD, and the trench 21 is formed through the insulating film 22 by, for example, sputtering or plating. An electrode forming material (for example, Cu, Al, etc.) is introduced so as to be buried. At this time, since the electrode forming material is also disposed on the surface of the support substrate 11, the electrode forming material in each trench 21 is integrated into a comb-shaped capacitive electrode 23.

  As described above, also in the semiconductor device 100 according to the present embodiment, the semiconductor substrate 10 having the SOI structure is adopted, the capacitor 20 is configured on the support substrate 11 side, which has not been applied as a conventional element formation region, and the semiconductor layer 13 side. An element 30 other than the capacitor 20 is configured. That is, the capacitor 20 having a large occupied area and the other elements 30 are configured in different regions. Therefore, the semiconductor device 100 in which the capacitors 20 are integrated is obtained without increasing the chip area (size in the planar direction of the semiconductor substrate).

  The capacitor 20 includes a support substrate 11 in which a trench 21 extending in the stacking direction is formed, an insulating film 22 formed on the surface of the trench 21, and a capacitive electrode formed so as to fill the trench 21 via the insulating film 22. 23 is included. Therefore, if the capacitance of the capacitor 20 is the same, the chip area can be further reduced. Further, if the chip area is the same, the capacitance of the capacitor 20 can be increased. In particular, in the present embodiment, since a plurality of the trains 21 are arranged and the capacitor electrode 23 is comb-shaped, the semiconductor device 100 is integrated with the large-capacity capacitor 20 without increasing the chip area.

  Further, in the present embodiment, since the capacitor electrode 23 constituting the capacitor 20 is exposed to the outside, it is not necessary to separately form an electrode for external connection (the through electrode 25 in the first embodiment). Moreover, since it is not necessary to manufacture the semiconductor substrate 10 in its own process, the manufacturing process can be simplified.

  In the present embodiment, an example is shown in which the capacitor 20 is formed after the element 30 is formed. However, the element 30 may be formed after the capacitor 20 is formed. In addition, in the process of forming the element 30, the example in which the insulating layer 12 is selectively etched to form the through electrode 26 has been shown. However, the semiconductor substrate 10 having a partial SOI structure having the insulating layer 12 opened at a position corresponding to the through electrode 26 may be prepared (purchased) in advance. In this case, since the process of etching the insulating layer 12 can be eliminated, the manufacturing process can be simplified.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. 6A and 6B are diagrams illustrating a schematic configuration of the semiconductor device 100 according to the present embodiment. FIG. 6A is a cross-sectional view, and FIG. 6B is a schematic diagram illustrating a formation region of the through electrode 25 in the semiconductor layer 13.

  Since the semiconductor device 100 and the manufacturing method thereof according to the fourth embodiment are often in common with those according to the first to third embodiments, the detailed description of the common parts will be omitted below, and different parts will be mainly described. To do.

  In the first to third embodiments, in consideration of the influence on the other elements 30, the through electrodes 25 and 26 for establishing conduction with the electrode (the support substrate 11 or the capacitor electrode 23) constituting the capacitor 20 are provided. An example is shown in which the semiconductor layer 13 is formed in a region that does not provide an electrical connection function (so-called field region). Therefore, the potentials of the through electrodes 25 and 26 are the ground potential (ground). On the other hand, in the present embodiment, in the field region, the through electrodes 25 and 26 are surrounded by the insulating region reaching the insulating layer 12 so that the through electrodes 25 and 26 are independent from the field region. Specifically, as shown in FIGS. 6A and 6B, in the field region 50 partitioned from the formation region of the element 30 by the trench isolation region 40, one end of the through electrode 25 connected to the capacitor electrode 23. A trench isolation region 51 is formed around the through electrode 25, and a region 52 electrically separated from the field region 50 is formed around the through electrode 25. As described above, according to the semiconductor device 100 according to the present embodiment, the potentials of the through electrodes 25 and 26 can be set to a potential other than the ground.

  The semiconductor device 100 having the above configuration can be formed without increasing the number of manufacturing steps by forming the trench isolation region 51 together with the formation of the trench isolation region 40. In the present embodiment, the example in which the trench isolation region 51 is formed around the through electrode 25 as the insulating region partitioned from the field region 50 is shown. However, the electrically partitioned insulating region is not limited to the above example. In addition, for example, an insulating film can be formed on the surface of the trench that constitutes the through electrodes 25 and 26, and the insulating film can be used as an insulating region.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIG. 7A and 7B are diagrams illustrating a schematic configuration of the semiconductor device 100 according to the present embodiment, in which FIG. 7A is a cross-sectional view and FIG. 7B is an equivalent circuit diagram.

  Since the semiconductor device 100 and the manufacturing method thereof in the fifth embodiment are often in common with those in the first to fourth embodiments, detailed description of the common parts will be omitted, and different parts will be mainly described below. To do.

  As shown in FIG. 7A, the semiconductor device 100 according to this embodiment includes a capacitor 20a based on the trench 21a formed from the insulating layer laminated surface side of the support substrate 11 and a back surface side of the insulating layer laminated surface. It has a capacitor 20b based on the formed trench 21b. The capacitor 20a is the same as the capacitor 20 shown in the first embodiment, and the capacitor 20b is the same as the capacitor 20 shown in the third embodiment. Further, in the present embodiment, the through electrode 26 having one end connected to the support substrate 11 is used as a common external connection electrode, and the through electrode 25 and the capacitor electrode 23b that are electrically connected to the capacitor electrode 23a are illustrated. Although not electrically connected, as shown in FIG. 7B, the two capacitors 20a and 20b are connected in parallel. Therefore, according to the semiconductor device 100 according to the present embodiment, a capacitor having a larger capacity can be configured without increasing the chip area.

  The semiconductor device 100 having the above configuration can be formed by combining the method for manufacturing the capacitor 20 shown in the second (first) embodiment and the method for manufacturing the capacitor 20 shown in the third embodiment. Specifically, the process from the formation of the capacitor 20a to the formation of the element 30 is the same as in the second (1) embodiment. Thereafter, as shown in the third embodiment, the capacitor 20b may be formed on the back surface of the semiconductor substrate 10 (the surface of the support substrate 11).

  In the present embodiment, the configuration in which the two capacitors 20a and 20b are connected in parallel is shown. However, it is good also as a structure connected in series.

  Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be implemented with various modifications.

  In the present embodiment, only the capacitor 20 having the trench structure is shown, but the configuration of the capacitor 20 is not limited to the above example as long as it is formed on the support substrate 11. For example, a capacitor having a planar structure (horizontal type) may be used. Also, the number is not limited to one.

  Moreover, in this embodiment, the example which comprises one capacitor 20 (20a, 20b) on the insulating layer laminated surface side of the support substrate 11 and the back surface side of the insulating layer laminated surface was shown. However, a plurality of capacitors 20 may be configured on one side. By forming an element isolation region reaching the insulating layer 12 on the support substrate 11, this configuration is possible.

  For example, as shown in FIG. 8, it is good also as a structure provided with two or more capacitors 20 shown in 1st Embodiment by forming the trench isolation | separation area | region 60. FIG. In this case, in the step of forming the capacitor 20, a plurality of capacitors 20 are formed, and a trench isolation region 60 having a depth greater than the thickness left by polishing of the surface of the support substrate 11 when forming the back electrode is formed. It ’s fine. The trench isolation region 60 is exposed at the time of back surface polishing, and the plurality of capacitors 20 (two in FIG. 8) can be insulated and separated. In addition, after the back electrode 24 is formed, the support substrate 11 can be etched to form the trench isolation region 60. FIG. 8 is a cross-sectional view showing a modification.

  Moreover, as shown in FIG. 9, it is good also as a structure provided with two or more capacitors 20 shown in 3rd Embodiment by forming the trench isolation | separation area | region 60. FIG. In this case, in the step of forming the capacitor 20, a plurality of capacitors 20 may be formed and the trench isolation region 60 reaching the insulating film 22 may be formed. FIG. 9 is a sectional view showing a modification.

  The element isolation region for insulating and isolating the capacitors 20 is not limited to the trench isolation region 60. For example, as shown in FIG. 10, a groove 61 formed so as to reach the insulating film 22 from the surface of the support substrate 11 can be employed. The trench 61 etches back the polysilicon on the surface of the support substrate 11 in the formation process of the capacitor 20, and makes the support substrate 11 anisotropic by using an alkaline solution (for example, KOH, TMAH, etc.) after forming the back electrode, for example. It can be formed by etching. In addition, it is possible to form the back electrode 24 after anisotropic etching after the element 30 is formed, but it is difficult to remove the electrode forming material disposed on the surface of the groove 61. It is preferable to perform anisotropic etching later. FIG. 10 is a cross-sectional view showing a modification. Although FIG. 10 shows the capacitor 20 in which the trench 21 is formed from the insulating layer lamination surface side, the same applies to the capacitor 20 in which the trench 21 is formed from the back surface side of the insulating layer lamination surface.

  In the second embodiment, a configuration example is shown in which the through electrodes 25 and 26 are used to conduct both electrodes (the support substrate 11 and the capacitor electrode 23) constituting the capacitor 20 on the surface side of the semiconductor substrate 10. . However, it is also possible to configure such that both electrodes are conductive on the back side of the semiconductor substrate 10. That is, the conduction direction of the electrodes (support substrate 11 or capacitor electrode 23) constituting capacitor 20 is not particularly limited. However, the configuration on the surface side is preferable in terms of mounting.

1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is sectional drawing according to process for demonstrating the outline of the manufacturing method of a semiconductor device, (a) is a capacitor formation process, (b) is a semiconductor substrate preparation process, (c) is an element formation process, (d) is a back surface electrode. The formation process is shown. It is a figure which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment, (a) is sectional drawing, (b) is the top view which looked at the support substrate from the insulating layer side. It is a figure which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing according to process for demonstrating the outline of the manufacturing method of a semiconductor device, (a) is an element isolation region formation process, (b) is a penetration electrode formation process, (c) is a diffusion region formation process, (d) Indicates a capacitor forming step. It is a figure which shows schematic structure of the semiconductor device which concerns on 4th Embodiment, (a) is sectional drawing, (b) is a schematic diagram which shows the formation area of the penetration electrode in a semiconductor layer. It is a figure which shows schematic structure of the semiconductor device which concerns on 5th Embodiment, (a) is sectional drawing, (b) is an equivalent circuit schematic. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11 ... Support substrate 12 ... Insulating layer 13 ... Semiconductor layer 20, 20a, 20b ... Capacitors 21, 21a, 21b ... Trench 22, 22a, 22b ... Insulating films 23, 23a, 23b... Capacitance electrode 24... Back electrode 25... (For capacitance electrode) Through electrode 26... (For support substrate) Through electrode 30. 40 ... trench isolation region 41 ... LOCOS oxide film 100 ... semiconductor device

Claims (32)

A semiconductor device comprising a plurality of elements including capacitors on a semiconductor substrate,
The semiconductor substrate is a semiconductor substrate having an SOI structure in which a semiconductor layer is stacked on an insulating layer on a support substrate,
Among the plurality of elements, the capacitor is formed on the support substrate side, and the other elements are formed on the semiconductor layer side.   The capacitor includes the support substrate in which a trench extending in the stacking direction is formed, an insulating film formed on a surface of the trench, and a capacitor electrode formed so as to fill the trench through the insulating film. The semiconductor device according to claim 1. A plurality of the trenches are arranged,
The semiconductor device according to claim 2, wherein the capacitor electrodes are connected to form a repetitive pattern such as a comb shape or an S shape.   The semiconductor device according to claim 2, wherein the trench is formed from the insulating layer lamination surface side of the support substrate.   The semiconductor device according to claim 4, wherein the support substrate has an external connection electrode electrically connected to the support substrate on a back surface of the insulating layer lamination surface.   5. The semiconductor device according to claim 4, wherein a through-electrode for external connection disposed through the semiconductor layer and the insulating layer is electrically connected to the support substrate.   7. The semiconductor device according to claim 5, wherein a through electrode for external connection disposed through the semiconductor layer and the insulating layer is electrically connected to the capacitor electrode. 8. .   4. The semiconductor device according to claim 2, wherein the trench is formed from a back surface side of an insulating layer lamination surface of the support substrate. 5.   The semiconductor device according to claim 8, wherein an external connection through electrode formed through the semiconductor layer and the insulating layer is electrically connected to the support substrate.   4. The semiconductor according to claim 2, wherein the trench is formed from an insulating layer lamination surface side of the supporting substrate and a back surface side of the insulating layer lamination surface, and constitutes the different capacitors. 5. apparatus.   11. The through-electrode for external connection disposed through the semiconductor layer and the insulating layer is electrically connected to the capacitor electrode formed on the insulating layer lamination surface side. A semiconductor device according to 1.   The semiconductor device according to claim 10, wherein the different capacitors are electrically connected in parallel.   The semiconductor device according to claim 6, wherein the through electrode is formed in a region that does not provide an electrical connection function in the semiconductor layer.   The semiconductor device according to claim 13, wherein the through electrode is surrounded by an insulating region that reaches the insulating layer in a region that does not provide the electrical connection function.   The semiconductor device according to claim 14, wherein the insulating region is a trench isolation region. A plurality of the capacitors are formed on the support substrate,
The semiconductor device according to claim 1, wherein each capacitor is electrically insulated and separated by an element isolation region.   The semiconductor device according to claim 16, wherein the element isolation region includes a groove formed in the support substrate. A method of manufacturing a semiconductor device in which a plurality of elements including capacitors are formed on a semiconductor substrate,
Preparing a semiconductor substrate having an SOI structure in which a semiconductor layer is laminated on a support substrate via an insulating layer as the semiconductor substrate;
Forming at least one capacitor on the support substrate;
And a step of forming an element excluding the capacitor in a semiconductor layer of the semiconductor substrate.   The step of forming the capacitor includes a step of forming a trench extending in the stacking direction on the support substrate, a step of forming an insulating film on the surface of the trench, and a capacitive electrode so as to fill the trench through the insulating film. The method for manufacturing a semiconductor device according to claim 18, further comprising a step of forming the semiconductor device. A plurality of the trenches are formed in a row,
The method of manufacturing a semiconductor device according to claim 19, wherein the capacitor electrode is formed in a repetitive pattern such as a comb shape or an S shape. Forming the trench from the insulating layer lamination surface side in the support substrate;
21. The method of manufacturing a semiconductor device according to claim 19, wherein the semiconductor substrate is prepared after the capacitor is formed.   The semiconductor device according to claim 21, wherein after the element is formed, an external connection electrode that is electrically connected to the support substrate is formed on the back surface of the insulating layer lamination surface of the support substrate. Production method.   In the step of forming the element, a through hole penetrating at least the semiconductor layer is formed, a conductive member is disposed in the through hole, and one end is electrically connected to the support substrate. 23. The method of manufacturing a semiconductor device according to claim 21, wherein a through electrode is formed.   In the step of forming the element, a through hole penetrating at least the semiconductor layer is formed, a conductive member is disposed in the through hole, and one end is electrically connected to the capacitor electrode. The method for manufacturing a semiconductor device according to claim 21, wherein a through electrode is formed.   The semiconductor device according to any one of claims 19 to 24, wherein after preparing the semiconductor substrate, the trench is formed from the back side of the insulating layer lamination surface of the support substrate to form the capacitor. Manufacturing method.   26. The method of manufacturing a semiconductor device according to claim 25, wherein the capacitor is formed after the element is formed.   In the step of forming the element, a through hole penetrating at least the semiconductor layer is formed, a conductive member is disposed in the through hole, and one end is electrically connected to the support substrate. 27. The method of manufacturing a semiconductor device according to claim 25 or 26, wherein a through electrode is formed.   28. The method of manufacturing a semiconductor device according to claim 23, wherein the through electrode is formed in a region that does not provide an electrical connection function in the semiconductor layer.   29. The method of manufacturing a semiconductor device according to claim 28, wherein an insulating region reaching the insulating layer is formed so as to surround the through electrode in the region having no electrical connection function.   30. The method of manufacturing a semiconductor device according to claim 29, wherein a trench isolation region is formed in the semiconductor layer as the insulating region.   31. The method of manufacturing a semiconductor device according to claim 18, wherein an element isolation region for dividing the capacitor into a plurality of parts is formed on the support substrate.   32. The method of manufacturing a semiconductor device according to claim 31, wherein the element isolation region includes a groove formed in the support substrate.

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