JP4540895B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which insulation isolation between elements formed on a substrate is performed using a trench isolation technique, and in particular, a semiconductor device suitable for forming a capacitor having a relatively large capacity on a substrate. About.
[0002]
[Problems to be solved by the invention]
Conventionally, when a capacitor having a relatively large capacity is formed on a semiconductor integrated circuit, an MIM (Metal Insulator Metal) structure in which a lower electrode film, a dielectric thin film, and an upper electrode film are stacked on a semiconductor substrate is used. However, with this structure, there is a problem that the area occupied by the capacitor is relatively enlarged and the chip area is increased, and in order to increase the capacity, the thickness of the dielectric thin film is set small. However, since the distance between the electrodes becomes smaller as the setting is made in this way, there is a problem that it is difficult to increase the withstand voltage of the capacitor.
[0003]
The present invention has been made to solve the above-described problems, and an object of the present invention is to increase the electrode area for the capacitor without increasing the chip size, thereby increasing the capacitance. It is an object of the present invention to provide a semiconductor device capable of forming a capacitor that achieves a shape and a high breakdown voltage.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, the means described in claim 1 can be adopted. When a capacitor using the sidewall insulating film of the insulating isolation trench as a dielectric thin film is formed as in this means, the insulating isolation trench is originally provided for the isolation of the element. There is no risk of increasing the chip size of the device. In addition, the insulation isolation trench is integrally formed in a form surrounding a plurality of element formation regions, and since the total extension is relatively long, it is possible to set a large effective electrode area of the capacitor, This is advantageous in increasing the capacitor capacity. In addition, as a result of securing the capacitor capacity by increasing the effective electrode area in this way, it is not necessary to increase the capacitor capacity by reducing the film thickness of the sidewall insulating film functioning as a dielectric thin film. Capacitors that can withstand voltage can be formed.
[0005]
The first electrode portion of the capacitor is formed by filling an insulating isolation trench with a conductive material (for example, polysilicon doped with impurities) through a sidewall insulating film, and the second electrode portion of the capacitor is When a plurality of element formation regions are provided in a semiconductor layer, a semiconductor region formed in a state remaining in the semiconductor layer , that is, a dead space in the semiconductor device (a space that is necessary for a semiconductor device but does not function as an element) ) To introduce impurities. Therefore, it is not necessary to prepare a new space for each electrode portion, and the chip size of the semiconductor device is not increased. In addition, the first electrode portion can be formed at the same time as the formation of the originally required isolation trench, and the second electrode portion can be formed by using a manufacturing process for the semiconductor element in the element formation region. Since it can be formed at the same time, it is useful for reducing the manufacturing cost.
[0006]
According to the measures of claim 2, wherein a diode formed with the capacitor, will be available for, for example, protect the semiconductor element in the element formation region, may enhance the added value. In addition, when a plurality of element formation regions are provided in the semiconductor layer , the diode has a second electrode on the cathode in a part of the semiconductor region (dead space in the semiconductor device) formed in the state remaining in the semiconductor layer. Since the anode is formed of a conductive impurity region different from that of the cathode and connected to the ground terminal , the chip size is not increased.
[0007]
According to the third aspect of the present invention , since the semiconductor oxide film is used as the sidewall insulating film constituting the dielectric thin film of the capacitor, the dielectric thin film can be easily formed and stable dielectric characteristics can be obtained. Be able to.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment in which the present invention is applied to an IC chip formed by BiCMOS process technology will be described below with reference to FIGS.
FIG. 5 shows a planar layout of the IC chip 1 (corresponding to a semiconductor device in the present invention). In FIG. 5 , an IC chip 1 is manufactured using an SOI (Silicon On Insulator) substrate 2 in which a single crystal silicon layer is formed on a silicon substrate via an insulating isolation layer. On top of this, an element formation region 3 for CMOS, an element formation region 4 for LDMOS (Lateral Double-diffusion MOS), and an element formation region 5 for bipolar transistors are formed. A predetermined number of regions 3, 4, and 5 are formed so as to remain sewn, and a group of insulating isolation trenches 6 are formed in a state in which the element formation regions 3, 4, and 5 are surrounded independently. It has become. Each insulating isolation trench 6 is formed so as to reach the insulating isolation layer of the SOI substrate 2. Further, the semiconductor region 2A has a shape integrally provided with a rectangular frame-shaped portion (no reference) in a form surrounding the whole of the plurality of element forming regions 3 to 5 at the outer peripheral portion of the single crystal silicon layer, A frame-shaped insulating isolation trench 6 reaching the insulating isolation layer of the SOI substrate 2 is also formed on the outer periphery of the rectangular frame-shaped portion.
[0009]
FIG. 1 schematically shows a cross-sectional structure of a portion along the line XX in FIG. 5 , and FIGS. 2 to 4 show the manufacturing process in schematic cross-sectional views. First, the manufacturing process will be described. 1 to 4 are not accurate.
In FIG. 2, an N-type single crystal silicon substrate 7 whose main surface is mirror-polished is prepared, and antimony is diffused to a depth of about 3 μm on the main surface using a vapor phase diffusion method to form an N + layer 8. . Apart from this N-type single crystal silicon substrate 7, a P-type single crystal silicon substrate 9 (corresponding to a support substrate) whose main surface is mirror-polished is prepared, and the main surface is thermally oxidized to a thickness of about 1 μm. The silicon oxide film 10 is formed. Next, the main surface sides of the silicon substrates 7 and 9 are bonded together in a clean atmosphere, and heated to about 1100 ° C. for bonding. Thereafter, the N-type single crystal silicon substrate 7 is polished to, for example, a state indicated by a two-dot chain line in the drawing to obtain a film thickness of about 17 μm. As a result, the SOI substrate 2 in a state in which the single crystal silicon layer 11 (corresponding to the semiconductor layer) is formed on the P-type single crystal silicon substrate 9 serving as the support substrate via the silicon oxide film 10 as the insulating separation layer is manufactured. The The single crystal silicon layer 11 is formed by laminating an N− layer 11a having a thickness of about 14 μm on an N + layer 8 having a thickness of about 3 μm.
[0010]
Then, an element formation region partitioned by the insulating isolation trench 6 is formed on the SOI substrate 2 by using a well-known trench formation technique. 1, 3, and 4, two bipolar transistor element formation regions 5 and a part of the semiconductor region 2 </ b> A appear. When forming the isolation trench 6, although not specifically shown, the following steps are performed. However, the following process examples show general procedures, and it is needless to say that other procedures may be adopted.
[0011]
(A) Mask formation step A silicon oxide film serving as a base is formed on the single crystal silicon layer 11, a silicon nitride film is formed thereon, and a silicon oxide functioning as an etching mask is formed thereon. A film is formed, and this three-layer structure film is patterned using a photo-etching technique, thereby forming an opening at a position corresponding to the trench 6, thereby forming a layer-structured trench etching mask. In this case, the silicon nitride film serves as a stopper when the uppermost silicon oxide film (etching mask) is removed.
[0012]
(B) Trench etching step By performing anisotropic dry etching using a trench etching mask on the single crystal silicon layer 11, a trench reaching the silicon oxide film 10 is formed at a position corresponding to the opening of the trench etching mask. To do.
[0013]
(C) Side wall oxidation process A side wall oxide film is formed by thermally oxidizing the side wall of the trench. If there is a processing defect in which the bottom of the trench does not reach the silicon oxide film 10, the single crystal silicon layer 11 remaining on the bottom is thermally oxidized from the surface side in this sidewall oxidation step.
[0014]
(D) Trench backfilling process A polysilicon film in a state where the trench is backfilled is formed on the entire surface of the trench etching mask (on the silicon oxide film) by depositing polysilicon by, for example, the CVD method. In this film formation, N-type impurities (for example, phosphorus and arsenic) are introduced into the polysilicon film, and the polysilicon film functions as a conductive material in the present invention.
[0015]
(E) Planarization process The polysilicon film is etched back to the surface of the silicon oxide film by performing a dry etching process or a chemical mechanical polishing process using the uppermost silicon oxide film of the trench etching mask as a stopper.
[0016]
(F) Mask removal process The uppermost silicon oxide film of the trench etching mask is removed by wet etching using the underlying silicon nitride film as a stopper.
[0017]
(G) Polysilicon film removal step The polysilicon film remaining in a state protruding from the upper portion of the trench is removed by dry etching using the silicon nitride film as a mask.
[0018]
(H) Polysilicon film oxidation process The polysilicon film corresponding to the upper part of the trench is subjected to a thermal oxidation process so that the upper part of the trench is covered with a silicon oxide film integrated with the lowermost silicon oxide film of the trench etching mask. State.
[0019]
(I) Silicon nitride film removal step The silicon nitride film is removed by wet etching with a processing liquid having etching selectivity with respect to the underlying silicon oxide film, thereby removing the sidewall oxide film 6a (sidewall as shown in FIG. 3). Insulating isolation trenches 6 are formed in a trench in which an N-type impurity has been introduced and filled with buried polysilicon 6b (corresponding to a conductive material) in a trench in which an insulating film is formed. Note that a silicon oxide film 12 is formed on the entire top surface of the single crystal silicon layer 11 (including the insulating isolation trench 6 portion).
[0020]
After execution of each process as described above, semiconductor elements corresponding to the respective element formation regions 3, 4, and 5 are formed. FIG. 4 shows an example in which an NPN transistor is formed in the bipolar transistor element formation region 5 in accordance with execution of a known photolithography process, ion implantation process, diffusion process, and the like. This NPN transistor has a structure including a P + diffusion layer 13 serving as a base region, an N + diffusion layer 14 serving as an emitter region, and an N + diffusion layer 15 constituting a collector region together with the N− layer 11a. In this case, in the step of forming the N + diffusion layer 15, the N-layer 11a in the semiconductor region 2A located between the adjacent element formation regions (between the bipolar transistor element formation regions 5 in the example of FIG. 4) is also N-type simultaneously. Impurities are introduced to form the N + diffusion layer 16.
[0021]
Next, as shown in FIG. 1, a contact hole is formed in the silicon oxide film 12, and the P ⁺ diffusion layer 13, the N ⁺ diffusion layers 14, 15 and 16, and the buried polysilicon 6b are electrically connected through the contact hole. Connected electrode pads 17 to 21 are formed. In practice, it is desirable to form an interlayer insulating film made of, for example, BPSG, BSG or the like on the silicon oxide film 12, and to form contact holes in the silicon oxide film 12 and the interlayer insulating film.
[0022]
Thus, the buried polysilicon 6b formed at a plurality of locations is the first electrode portion referred to in the present invention, the N + diffusion layer 16 is the second electrode portion referred to in the present invention, and the sidewall oxide film 6a is the dielectric referred to in the present invention. Capacitors (denoted by reference numeral C in FIG. 6) that function as body thin films are formed. In this case, the electrode pad 20 of the N + diffusion layer 16 is connected to a power supply terminal + Vcc for an integrated circuit (indicated by reference numeral 22 in FIG. 6) formed on the IC chip 1, and embedded polysilicon. The plurality of electrode pads 21 in the group 6b are all connected to the ground terminal. Therefore, as shown in FIG. 6, the capacitor C and the integrated circuit 22 are connected in parallel to the power supply terminal + Vcc. a state, the resulting so that to function a capacitor C as a noise absorbing element Te following.
[0023]
According to the above-described embodiment, the following effects can be obtained. That is, when forming the capacitor C, the dielectric thin film uses the side wall oxide film 6a of the insulation isolation trench 6 originally provided for insulation isolation of the semiconductor element, and the insulation as the first electrode portion. Using the buried polysilicon 6b of the isolation trench 6, the single crystal silicon layer 11 (dead space in the IC chip 1) located between adjacent element formation regions is used as the second electrode portion. Therefore, it is not necessary to prepare a new space for the dielectric thin film and each electrode part. As a result, there is no possibility that the chip size of the IC chip 1 is enlarged.
[0024]
In addition, since the extension of the insulating isolation trench 6 is relatively long, the effective electrode area of the capacitor C can be set large, which is advantageous in increasing the capacitance. In addition, as a result of securing the capacitance of the capacitor C by increasing the effective electrode area in this way, it is not necessary to increase the thickness of the sidewall oxide film 6a functioning as a dielectric thin film to increase the capacitance. For this reason, it is possible to form a capacitor C that realizes a high breakdown voltage as well as an increase in capacity. The buried polysilicon 6b serving as the first electrode portion can be formed simultaneously with the formation of the insulating isolation trench 6, and the N ⁺ diffusion layer 16 serving as the second electrode portion is formed of a semiconductor element in the element formation region. Since it can be formed simultaneously with the semiconductor element using a manufacturing process for (for example, a bipolar transistor), it is useful for reducing the manufacturing cost. Further, since the side wall oxide film 6a made of a silicon thermal oxide film is used as the side wall insulating film constituting the dielectric thin film of the capacitor C, the dielectric thin film can be easily formed and stable dielectric characteristics can be obtained. It will be obtained.
[0025]
(Second Embodiment)
7 and 8 show a second embodiment of the present invention. Hereinafter, only portions different from the first embodiment will be described.
FIG. 7 shows a schematic perspective view of a part of the IC chip 1 being cut out, and FIG. 8 shows a circuit configuration diagram equivalent to FIG. 6 in the first embodiment. . In FIG. 7, an IC chip 23 (corresponding to a semiconductor device) has the same basic element configuration as that of the first embodiment, but the formation region of the second electrode portion (N + diffusion layer 16) for the capacitor C. In other words, a structure in which a diode (indicated by reference symbol D in FIG. 8) is formed in the semiconductor region 2A located between adjacent element forming regions (between the bipolar transistor element forming regions 5 in the example of FIG. 7). With the above features. Specifically, when the P + diffusion layer 13 for the NPN transistor is formed, the P + diffusion layer 24 is formed by partially introducing a P-type impurity into the N− layer 11a of the single crystal silicon layer 11 at the same time. Thus, the diode D (see FIG. 8) in which the cathode is connected to the second electrode portion (N + diffusion layer 16) is configured between the N + diffusion layer 16 and the N + layer 8 and the P + diffusion layer 24. Is done. In this case, the N + diffusion layer 16 is connected to the power supply terminal + Vcc, and the P + diffusion layer 24 is connected to the ground terminal. Therefore, the diode D is connected to the power supply terminal + Vcc as shown in FIG. And the anode is connected to the ground terminal.
[0026]
According to this embodiment, the diode D formed together with the capacitor C can be used, for example, for protecting the integrated circuit 22, and the added value can be increased. In addition, since the diode D is formed in the semiconductor region 2A (dead space in the semiconductor device) located between the adjacent element formation regions, the chip size is not increased.
[0027]
(Other embodiments)
The present invention is not limited to the above-described embodiment, and the following modifications or expansions are possible.
Although the example using the SOI substrate 2 using the single crystal silicon substrate 9 as a support substrate has been described, the material of the support substrate is not limited to the single crystal silicon substrate, but other semiconductor substrates or semiconductor substrates or ceramics having insulation properties. A substrate (for example, an alumina substrate) or a glass substrate can be used. Specifically, for example, the single crystal silicon layer 11 is directly formed on the silicon substrate 25 (support substrate) having a large specific resistance as shown in FIG. It can be considered that the semiconductor substrate 26 is used. In particular, when such a support substrate having an insulating property is used, an insulating isolation layer (in the case of the first and second embodiments described above, the silicon oxide film 10) becomes unnecessary (SOS (Silicon On Sapphire)). This also applies when using a substrate). Further, although the SOI substrate 2 formed by the bonding method is used, it is needless to say that an SOI substrate formed by another method such as an insulating film embedding method (for example, SIMOX) may be used.
[0028]
The diode in the present invention is a concept including a Zener diode. In particular, when forming a Zener diode, the breakdown voltage can be increased by forming a plurality of Zener diodes and connecting them in series.
The present invention is not limited to an IC chip formed by BiCMOS process technology, and can be widely applied to all semiconductor devices having an insulating isolation trench.
[Brief description of the drawings]
FIG. 1 is a schematic longitudinal sectional view of an essential part showing a first embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view showing a state in the middle of manufacturing, part 1
FIG. 3 is a schematic longitudinal sectional view showing a state in the middle of manufacturing, part 2
FIG. 4 is a schematic longitudinal sectional view showing a state in the middle of manufacturing, part 3
FIG. 5 is a schematic layout diagram of an IC chip. FIG. 6 is a schematic circuit configuration diagram of the IC chip. FIG. 7 shows a second embodiment of the present invention, and a part of the IC chip being manufactured is cut out. FIG. 8 is a diagram corresponding to FIG. 6. FIG. 9 is a diagram corresponding to FIG. 1 showing another embodiment.
1 is an IC chip (semiconductor device), 2 is an SOI substrate, 2A is a semiconductor region, 3 is an element formation region for CMOS, 4 is an element formation region for LDMOS, 5 is an element formation region for bipolar transistors, 6 is an isolation trench, 6a is a sidewall oxide film (dielectric thin film), 6b is buried polysilicon (conductive material, first electrode portion), 9 is a single crystal silicon substrate (support substrate), and 11 is a single crystal silicon layer (semiconductor layer). , 16 is an N + diffusion layer (second electrode portion), 23 is an IC chip (semiconductor device), 25 is a support substrate, C is a capacitor, and D is a diode.

Claims (3)

A plurality of element formation regions provided in a semiconductor layer formed on the support substrate in a state of being electrically insulated from the support substrate, and disposed so that a semiconductor region of the semiconductor layer remains as a unit between them;
A plurality of insulating isolation trenches formed between the plurality of element forming regions and the semiconductor region in the semiconductor layer so as to surround each element forming region and reach an insulating functional portion between the support substrate and the semiconductor layer; ,
A plurality of first electrode portions formed by filling the plurality of insulating isolation trenches with a conductive material via a sidewall insulating film;
A second electrode portion formed by introducing impurities into the semiconductor region;
With
By connecting all of the plurality of first electrode portions to a ground terminal and connecting the second electrode portion to a power supply terminal, the first electrode portion and the second electrode portion can be connected to each other. A semiconductor device, wherein the sidewall insulating film functions as a dielectric thin film. The semiconductor device according to claim 1 ,
A diode having a cathode connected to the second electrode portion and an anode formed of a conductive impurity region different from the cathode and connected to a ground terminal is formed in a part of the semiconductor region. Semiconductor device. The sidewall insulating film, a semiconductor device according to claim 1 or 2, wherein the is an oxide film formed by oxidizing the exposed semiconductor layer in isolation trench.

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