JP7021021B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device having a semiconductor capacitor and a method for manufacturing the same.

As the semiconductor capacitor, a configuration in which a capacitor structure is formed inside a groove formed on the surface of a semiconductor substrate is used. For example, a method of laminating a plurality of conductive layers on the side surface of a groove while sandwiching a dielectric layer between them to form a capacitor structure is disclosed (see Non-Patent Document 1).

Houri Johari, 1 outside, "High-Density Embedded Deep Trench Capacitors in Silicon With Enhanced Breakdown Voltage", IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGY, VOL. 32, NO. 4, December 2009, p. 808-815

However, in the structure described in Non-Patent Document 1, the main groove (wide trench) for generating capacitance and the other groove (narrow trench, medium trench) for contacting the electrodes arranged on the substrate are on the same surface. Form. Therefore, the area where the main groove can be formed is limited, and the increase in the capacitance of the capacitor structure is suppressed. Further, in Non-Patent Document 1, the conductive layer formed inside the groove is extended to the surface of the semiconductor substrate, and the electrode is arranged on the conductive layer on the surface of the semiconductor substrate. That is, a contact region between the positive electrode and the negative electrode is formed on the surface of the semiconductor substrate. Therefore, the size of the semiconductor device increases.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device, which increases the capacity of a capacitor structure formed inside a groove of a semiconductor substrate and suppresses an increase in size.

The semiconductor device according to one aspect of the present invention includes a first conductive layer and a second conductive layer laminated inside a groove formed on a first main surface of a semiconductor substrate via a dielectric layer, and a first conductive layer. The gist is to include a first electrode that is electrically connected and a second electrode that is connected to the second conductive layer via an embedded electrode that extends from the second main surface and reaches the bottom of the groove.

A method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of laminating a first conductive layer and a second conductive layer via a dielectric layer inside a groove formed on a first main surface of a semiconductor substrate. A step of forming a contact hole from the second main surface of the semiconductor substrate to reach the bottom of the groove and forming an embedded electrode connected to the second conductive layer at the bottom of the groove inside the contact hole is included. The gist is to simultaneously form a second conductive layer connected to the embedded electrode.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device in which the capacity of the capacitor structure formed inside the groove of the semiconductor substrate is increased and the increase in size is suppressed.

It is a schematic sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 1). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 2). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 3). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 4). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 5). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 6). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 7). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 8). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 9). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 10). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 11). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 12). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 13). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 14). It is a schematic sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 1). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 2). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 3). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 4). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 5). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 6). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 7). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 8). It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 9). It is a schematic plan view which shows the arrangement example of the embedded electrode. It is a schematic cross-sectional view which shows the structural example of the embedded electrode, FIG. 27 (a) is a cross-sectional view along the I-I direction of FIG. It is a cross-sectional view taken along the line, and FIG. 27 (c) is a cross-sectional view taken along the direction III-III of FIG. 26. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 3rd Embodiment of this invention. 28 is a cross-sectional view of the semiconductor device shown in FIG. 28, FIG. 29 (a) is a cross-sectional view taken along the IV-IV direction of FIG. 28, and FIG. 29 (b) is taken along the V-V direction of FIG. 28. It is a cross-sectional view, and FIG. 29 (c) is a cross-sectional view taken along the VI-VI direction of FIG. 28. It is a schematic diagram which shows the structure of the semiconductor device which concerns on 4th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device which concerns on other embodiment of this invention.

Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. include parts that are different from the actual ones. In addition, there are parts where the relationships and ratios of the dimensions of the drawings are different from each other.

(First Embodiment)
As shown in FIG. 1, the semiconductor device 1 according to the first embodiment of the present invention has a first main surface 11 and a second main surface 12 facing each other, and a groove is formed in the first main surface 11. The semiconductor substrate 10 is provided with a plurality of conductive layers 20 laminated along the surface normal direction of the side surface of the groove. FIG. 1 is a cross-sectional view taken along the lateral direction of the groove formed on the first main surface 11.

Each of the conductive layers 20 arranged inside the groove is either the first conductive layer 2A or the second conductive layer 2B. In the semiconductor device 1, the conductive layer closest to the side surface of the groove in the conductive layer 20 is the first conductive layer, and the odd-numbered conductive layer in the conductive layer 20 is the first conductive layer 2A. That is, the conductive layer 21 and the conductive layer 23 are the first conductive layer 2A. In the configuration shown in FIG. 1, the conductive layer 21 is in contact with the side surface of the groove. Further, the conductive layer 23 is the conductive layer arranged farthest from the side surface of the groove. On the other hand, the even-numbered conductive layer in the conductive layer 20 is the second conductive layer 2B. That is, the conductive layer 22 is the second conductive layer 2B.

As shown in FIG. 1, the dielectric layers 31 to 32 are arranged between the conductive layers 20. That is, the dielectric layer 31 is arranged between the conductive layer 21 and the conductive layer 22, and the dielectric layer 32 is arranged between the conductive layer 22 and the conductive layer 23. In the following, the dielectric layers arranged between the conductive layers 20 inside the groove are collectively referred to as “dielectric layer 30”. The first conductive layer 2A and the second conductive layer 2B are electrically insulated by the dielectric layer 30. Then, the capacitor is formed by laminating the first conductive layer 2A, the dielectric layer 30, and the second conductive layer 2B.

The semiconductor device 1 further includes an embedded electrode 40 embedded in a contact hole formed so as to reach the bottom of the groove from the second main surface 12. The embedded electrode 40 is electrically connected to the second conductive layer 2B at the bottom of the groove. An insulating separation membrane 60 is arranged on the side surface of the contact hole, and the semiconductor substrate 10 and the embedded electrode 40 are electrically insulated by the insulating separation membrane 60. As shown in FIG. 1, the width of the contact hole is narrower than the width of the groove in the cross section along the lateral direction of the groove.

Further, the semiconductor device 1 includes a first electrode 51 that is electrically connected to the first conductive layer 2A and a second electrode 52 that is electrically connected to the second conductive layer 2B. The first electrode 51 and the second electrode 52 are arranged outside the groove.

In the semiconductor device 1 shown in FIG. 1, the first electrode 51 is arranged on the first main surface 11 of the semiconductor substrate 10 via the first insulating film 71. Then, in the opening provided in the first insulating film 71, the first conductive layer 2A extending from the inside of the groove to the first main surface 11 and the first electrode 51 are electrically connected. Further, the second electrode 52 is arranged on the second main surface 12 of the semiconductor substrate 10 via the second insulating film 72. The embedded electrode 40 and the second electrode 52 are electrically connected to each other in the opening provided in the second insulating film 72. The conductive layer 21 closest to the side surface of the groove and the conductive layer 23 arranged farthest from the side surface of the groove are the first conductive layer 2A and are electrically connected to the first electrode 51 arranged on the first main surface 11. Has been done. The conductive layer 21 is the second conductive layer 2B, and is electrically connected to the second electrode 52 arranged on the second main surface 12 via the embedded electrode 40.

The operation of the semiconductor device 1 shown in FIG. 1 will be described below. By applying a positive voltage to the first electrode 51 and a negative voltage to the second electrode 52, the first conductive layer 2A is charged with a positive charge, and the second conductive layer 2B is charged with a negative charge. .. At this time, polarization occurs inside the dielectric layer 30, and capacitance is generated. Since a plurality of dielectric layers 30 are laminated in the groove and a capacitance can be generated in each of the dielectric layers 30, the capacitance density per substrate area can be increased.

In the semiconductor device shown in FIG. 1, the conductive layer 21 which is the first conductive layer 2A and the conductive layer 23 are electrically connected to the first electrode 51, and the conductive layer 22 which is the second conductive layer 2B is the second electrode 52. Is electrically connected to. Therefore, the semiconductor device 1 has a configuration in which two capacitors having a dielectric layer 31 and a dielectric layer 32 are connected in parallel. As described above, according to the semiconductor device 1, it is possible to realize a capacitor structure in which the capacitance density per unit area is greatly improved.

The first conductive layer 2A is electrically connected to the first electrode 51 arranged on the first main surface 11. On the other hand, the second conductive layer 2B, which is electrically insulated from the first conductive layer 2A, is electrically connected to the second electrode 52 arranged on the second main surface 12. In this way, by arranging the positive electrode and the negative electrode of the capacitor structure formed inside the groove separately on the first main surface 11 and the second main surface 12, short circuit between the positive and negative electrodes is suppressed. can.

In the above, the case where the total number of the conductive layers 20 laminated inside the groove is three is exemplified. However, the number of conductive layers 20 is not limited to three. For example, the first conductive layer 2A and the second conductive layer 2B may be one layer each. As a result, the manufacturing process can be shortened. On the other hand, as the number of layers of the conductive layers 20 to be laminated increases, the capacitance density per unit area can be further increased. Therefore, the total number of conductive layers 20 may be 4 or more. The number of layers of the dielectric layers 30 arranged between the conductive layers 20 is one less than the number of layers of the conductive layers 20.

In the semiconductor device 1 shown in FIG. 1, the conductive layer closest to the side surface of the groove is used as the first conductive layer, and the odd-numbered first conductive layer 2A is electrically connected to each other to be even-numbered. The second conductive layer 2B is electrically connected to each other. By alternately laminating the first conductive layer 2A and the second conductive layer 2B via the dielectric layer 30 in this way, the capacitance density per unit area can be maximized.

As described above, in the semiconductor device 1 according to the first embodiment of the present invention, the first electrode 51 electrically connected to the first conductive layer 2A is arranged on the first main surface 11 of the semiconductor substrate 10. , The second electrode 52 electrically connected to the second conductive layer 2B is arranged on the second main surface 12. Therefore, the area of the region forming the groove can be increased as compared with the case where a plurality of conductive layers of the capacitor structure are arranged on the first main surface 11 in order to connect to the positive and negative electrodes respectively. As a result, it is possible to provide the semiconductor device 1 having a high capacitance density per substrate area. Further, as compared with the configuration in which the positive and negative electrodes are arranged on the first main surface 11, it is possible to suppress an increase in the size of the semiconductor device 1 when the capacitance density per substrate area is the same.

Hereinafter, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to the drawings. The method for manufacturing the semiconductor device 1 described below is an example, and can be realized by various other manufacturing methods including this modification.

First, as shown in FIG. 2, a groove 100 is formed on the first main surface 11 of the semiconductor substrate 10. For the semiconductor substrate 10, for example, a silicon substrate is used. The groove 100 can be formed as follows. That is, after the silicon oxide film is formed on the entire surface of the first main surface 11 by a CVD method or the like, the silicon oxide film is patterned by using a photolithography technique so that the region forming the groove 100 is exposed. Then, the groove 100 is formed by dry etching or wet etching using the silicon oxide film as the etching mask. After forming the groove 100, the silicon oxide film used for the etching mask is removed.

As shown in FIG. 3, the conductive layer 21 is formed on the inner wall surface of the groove 100 and the first main surface 11. A polycrystalline silicon film doped with impurities such as phosphorus can be used for the conductive layer 20. The polycrystalline silicon film is formed by using a CVD method or the like.

Next, as shown in FIG. 4, a contact hole 120 that reaches the bottom of the groove 100 is formed on the second main surface 12 of the semiconductor substrate 10. For example, a silicon nitride film is formed on the entire surface of the second main surface by a CVD method or the like. Then, the contact hole 120 is formed by dry etching or wet etching using the silicon oxide film patterned by the photolithography technique as the etching mask. The contact hole 120 is formed so as to penetrate the conductive layer 21 at the bottom of the groove 100, and the contact hole 120 and the groove 100 are connected to each other.

After that, as shown in FIG. 5, the dielectric layer 31 is formed so as to cover the conductive layer 21. As the dielectric layer 30, a silicon oxide film or a silicon nitride film formed by a CVD method or the like can be used. At this time, at the same time as the formation of the dielectric layer 31, the insulating separation film 60 is formed on the inner wall surface of the contact hole 120.

Further, as shown in FIG. 6, the conductive layer 22 is formed so as to cover the dielectric layer 31. At this time, the contact hole 120 is embedded at the same time as the formation of the conductive layer 22, and the embedded electrode 40 is formed. In this case, the materials of the conductive layer 22 and the embedded electrode 40 are the same. For example, the embedded electrode 40 is a polycrystalline silicon film doped with impurities such as phosphorus.

Next, as shown in FIG. 7, the groove 100 is embedded by the photoresist film 111. For example, by applying the photoresist film 111 to the first main surface 11 by a spin coating method or a spray method, the groove 100 is embedded in the photoresist film 111.

Then, as shown in FIG. 8, the conductive layer 22 on the first main surface 11 is removed by anisotropic etching such as reactive ion etching (RIE). The inside of the groove 100 is protected by the photoresist film 111.

Further, as shown in FIG. 9, the dielectric layer 31 on the first main surface 11 is removed by anisotropic etching such as RIE. At this time, the upper end of the conductive layer 22 near the opening of the groove 100 is also etched. Then, as shown in FIG. 10, the photoresist film 111 is removed. The photoresist film 111 is removed using, for example, acetone or sulfuric acid.

As shown in FIG. 11, the dielectric layer 32 is formed so as to cover the conductive layer 20. Then, as shown in FIG. 12, the groove 100 is embedded by the photoresist film 112. The photoresist film 112 is applied by using a spin coating method or a spray method in the same manner as the photoresist film 111.

Then, as shown in FIG. 13, the dielectric layer 32 on the first main surface 11 is removed while protecting the inside of the groove 100 with the photoresist film 112. For example, the dielectric layer 32 is removed by etching by dry etching or wet etching. Then, as shown in FIG. 14, the photoresist film 112 is removed using acetone or sulfuric acid.

Next, as shown in FIG. 15, the conductive layer 23 is formed on the first main surface 11 and inside the groove 100. For example, the groove 100 is embedded by a conductive layer 23 which is a polycrystalline silicon film doped with impurities such as phosphorus. Further, the conductive layer 21 and the conductive layer 23 are electrically connected in a region formed on the first main surface 11 of the conductive layer 23.

After that, the first insulating film 71 is formed on the first main surface 11 of the semiconductor substrate 10, and the second insulating film 72 is formed on the second main surface 12. The material of the first insulating film 71 and the second insulating film 72 may be the same as that of the dielectric layer 30, or may be different materials. For example, a silicon oxide film, a silicon nitride film, or the like is used for the first insulating film 71 and the second insulating film 72. Then, after providing an opening at a predetermined position of the first insulating film 71, a first electrode 51 is formed so as to embed the opening, and the first electrode 51 and the conductive layer 23 are electrically connected. Further, after the opening is provided at a predetermined position of the second insulating film 72, the second electrode 52 is formed so as to embed the opening, and the second electrode 52 and the embedded electrode 40 are electrically connected. As a result, the semiconductor device 1 shown in FIG. 1 is completed.

Metal is generally used as the material for the first electrode 51 and the second electrode 52. For example, a metal material such as titanium (Ti), nickel (Ni), molybdenum (Mo), or a laminated film such as titanium / nickel / silver (Ti / Ni / Ag) is used for the first electrode 51 and the second electrode 52. can.

In the semiconductor device 1, the width of the contact hole 120 in which the embedded electrode 40 is embedded is narrower than the width of the groove 100. Therefore, the surface unevenness of the second main surface 12 is smaller than that of the first main surface 11. By forming the second electrode 52 on the second main surface 12 having less unevenness, patterning such as a photolithography technique can be performed without performing a flattening step. Therefore, it is possible to provide the semiconductor device 1 having fewer manufacturing steps than the case where the electrode is formed on the first main surface 11 on which the groove is formed.

Further, the contact hole 120 for forming the embedded electrode 40 may reach from the second main surface 12 to the bottom of the groove 100. That is, it is not necessary to form a deep groove in order to electrically connect the second conductive layer 2B and the second electrode 52. Therefore, according to the semiconductor device 1 shown in FIG. 1, the time required for the manufacturing process can be shortened as compared with the case of forming a deep groove.

In the cross section of the groove 100 along the lateral direction, the width of the contact hole 120 is made smaller than twice the film thickness of the second conductive layer 2B connected to the embedded electrode 40 embedded in the contact hole 120. You may. That is, the width of the contact hole 120 is made smaller than the total film thickness of the second conductive layer 2B formed on both sides of the side surface of the groove 100. Thereby, when the second conductive layer 2B and the embedded electrode 40 are formed at the same time as described with reference to FIG. 6, the contact hole 120 can be embedded without any gap by the embedded electrode 40. Therefore, it is possible to suppress the occurrence of unevenness on the second main surface 12, and it is possible to omit the flattening step as a pretreatment such as a step using a photolithography technique. Therefore, the manufacturing process of the semiconductor device 1 can be shortened.

Further, by forming the second conductive layer 2B and the embedded electrode 40 at the same time, the manufacturing process can be shortened as compared with the case where they are formed separately. Further, as compared with the case where the second conductive layer 2B and the embedded electrode 40 are separately formed and electrically connected, it is possible to suppress a connection failure due to a defect in the manufacturing process. Therefore, the manufacturing yield can be improved.

For the semiconductor substrate 10, for example, a single crystal silicon substrate or a polycrystalline silicon substrate can be used. By using a silicon substrate, which is a highly processable material, integration can be achieved by microfabrication. Therefore, the semiconductor device 1 having a high capacitance density can be manufactured.

Further, by using a polycrystalline silicon film for the conductive layer 20 and the embedded electrode 40, a low-pressure chemical vapor deposition method for forming a film having good coverage can be used. Therefore, the conductive layer 20 can be formed inside the groove 100 having a high aspect ratio, and the semiconductor device 1 having a high capacitance density can be manufactured.

Further, in the above, a silicon oxide film or a silicon nitride film was used for the dielectric layer 30. By using a material having a dielectric breakdown electric field and a high relative permittivity, the dielectric layer 30 having a high withstand voltage and a high dielectric constant can be formed. Therefore, the semiconductor device 1 having a high withstand voltage and a high capacitance density can be realized.

Alternatively, a dielectric layer 30 having a structure in which a plurality of dielectric films made of different materials are laminated may be used. For example, a silicon nitride film having a relatively high dielectric constant but a large film stress and a silicon oxide film having a relatively low dielectric constant but a small film stress are laminated to form a dielectric layer 30. This makes it possible to form a dielectric layer 30 having a high dielectric constant, which secures a desired thickness and has a good balance between dielectric constant and stress.

Further, as described with reference to FIG. 5, the dielectric layer 31 formed between the conductive layer 21 and the conductive layer 22 and the insulating separation film 60 covering the inner wall surface of the contact hole 120 are simultaneously formed. You may. In this way, the dielectric layer 30 on which the second conductive layer 2B connected to the embedded electrode 40 is formed on the surface and the insulating separation film 60 formed between the semiconductor substrate 10 and the embedded electrode 40 are simultaneously formed. Therefore, the manufacturing process can be shortened. As a result, the manufacturing cost of the semiconductor device 1 can be reduced.

As described above, according to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the first electrode 51 is formed on the first main surface 11 of the semiconductor substrate 10, and the second electrode 52 is the second electrode 52. 2 Formed on the main surface 12. Therefore, it is possible to provide the semiconductor device 1 having a high capacitance density per substrate area and a small size. Although one groove 100 is shown above, a plurality of grooves 100 may be formed on the first main surface 11. Further, although the configuration in which the first conductive layer 2A is two layers and the second conductive layer 2B is one layer has been exemplified, the configuration of the conductive layer 20 is not limited to this.

A conductive substrate may be used for the semiconductor substrate 10. For example, a silicon substrate having a resistivity of about 1E-4 to 1E-5Ωcm ² and a high impurity concentration is used for the semiconductor substrate 10. The semiconductor substrate 10 may be a p-type semiconductor substrate or an n-type semiconductor substrate. The semiconductor substrate 10 has conductivity, and as shown in FIG. 1, the conductive layer 21 closest to the side surface of the groove is in contact with the semiconductor substrate 10 on the side surface of the groove, so that the first conductive layer 2A and the first are present. Equivalent series resistance (ESR) with the electrode 51 can be reduced.

Further, an insulating separation membrane 60 is arranged between the semiconductor substrate 10 and the embedded electrode 40, and the semiconductor substrate 10 and the embedded electrode 40 are electrically insulated from each other. Therefore, when the potential of the semiconductor substrate 10 and the potential of the embedded electrode 40 are different, it is possible to suppress a short circuit or generation of a leak current between the semiconductor substrate 10 and the embedded electrode 40. This makes it possible to prevent a short-circuit failure of the semiconductor device 1 and a loss due to a leak current. Further, when the potential of the semiconductor substrate 10 and the potential of the embedded electrode 40 are different, the capacitance is formed between the semiconductor substrate 10 and the embedded electrode 40, so that the capacitance of the semiconductor device 1 can be increased.

(Second embodiment)
The semiconductor device 1 according to the second embodiment of the present invention is different from the first embodiment in that the first electrode 51 has a portion arranged on the second main surface 12 apart from the second electrode 52. different. That is, as shown in FIG. 16, the semiconductor device 1 has a first electrode 51a arranged on the first main surface 11 of the semiconductor substrate 10, a first electrode 51b1 arranged on the second main surface 12, and a first electrode. 51b2 is provided.

The first electrode 51a is electrically connected to the conductive layer 23 at the opening of the first insulating film 71 arranged on the first main surface 11.

The first electrode 51b1 is electrically connected to the embedded electrode 40 which is electrically connected to the conductive layer 21 at the bottom of the groove in the opening provided in the second insulating film 72 arranged on the second main surface 12. There is. The first electrode 51b2 is electrically connected to the embedded electrode 40 which is electrically connected to the conductive layer 23 at the bottom of the groove in the opening provided in the second insulating film 72.

Further, on the second main surface 12, the second electrode 52b1 and the second electrode 52b2 are arranged apart from the first electrode 51b1 and the first electrode 51b2. The second electrode 52b1 is electrically connected to the embedded electrode 40 which is electrically connected to the conductive layer 22 at the bottom of the groove in the opening provided in the second insulating film 72. The second electrode 52b2 is connected to the conductive semiconductor substrate 10 at the opening provided in the second insulating film 72.

The first electrode 51b1 and the first electrode 51b2 are electrically connected to each other. For example, the first electrode 51b1 and the first electrode 51b2 are connected by a metal wiring formed on the surface of the second insulating film 72. Similarly, the second electrode 52b1 and the second electrode 52b2 are electrically connected.

Inside the groove, the conductive layer 20 is laminated via the dielectric layer 30. That is, the dielectric layer 31 is arranged between the conductive semiconductor substrate 10 and the conductive layer 21, the dielectric layer 32 is arranged between the conductive layer 21 and the conductive layer 22, and the dielectric is dielectric between the conductive layer 22 and the conductive layer 23. The layer 33 is arranged. In this way, each layer of the conductive layer 20 is electrically insulated from each other by the dielectric layer 30.

The basic operation of the semiconductor device 1 shown in FIG. 16 will be described. A positive voltage H is applied to the first electrode 51b1 and the first electrode 51b2, and a negative voltage L is applied to the second electrode 52b1 and the second electrode 52b2. As a result, the conductive layer 21 and the conductive layer 23 are charged with a positive charge, and the semiconductor substrate 10 and the conductive layer 22 are charged with a negative charge. At this time, polarization occurs inside the dielectric layer 30, and capacitance is generated. Since a plurality of dielectric layers 30 are laminated in the groove and a capacitance is generated in each of the dielectric layers 30, the capacitance density per substrate area can be improved.

Further, according to the semiconductor device 1 shown in FIG. 16, the first main surface 11 is formed by forming electrodes electrically connected to the first conductive layer 2A and the second conductive layer 2B on the second main surface 12. The area of the groove formed in the can be maximized. Therefore, the capacitance density per substrate area can be further improved. Further, since the positive and negative electrodes are arranged on the second main surface 12, the semiconductor device 1 can be used as a capacitive element without connecting the electrodes on the first main surface 11 to the circuit. Thereby, it is possible to provide the semiconductor device 1 having less restrictions on the mounting form.

Hereinafter, a method for manufacturing the semiconductor device 1 according to the second embodiment will be described with reference to the drawings. The method for manufacturing the semiconductor device 1 described below is an example, and can be realized by various other manufacturing methods including this modification.

First, as shown in FIG. 17, grooves 100a to 100c (hereinafter collectively referred to as grooves 100) are formed on the first main surface 11 of the semiconductor substrate 10. Further, a contact hole 120 that reaches the bottom of the groove 100a is formed on the second main surface 12. The grooves 100 and the contact holes 120 are formed by dry etching or wet etching using, for example, a silicon oxide film patterned using a photolithography technique as an etching mask (the same applies hereinafter).

Next, as shown in FIG. 18, the dielectric layer 31 is formed on the side surface of the groove 100, the first main surface 11 and the second main surface 12. At this time, the insulating separation film 60 is simultaneously formed on the inner wall surface of the contact hole 120. Next, as shown in FIG. 19, the conductive layer 21 is formed so as to cover the dielectric layer 31 with the side surface of the groove 100 and the first main surface 11. At the same time, the embedded electrode 40 is formed inside the contact hole 120.

Then, as shown in FIG. 20, a contact hole 120 is formed on the second main surface 12 so as to reach the bottom of the groove 100b and connect with the groove 100b. Then, as shown in FIG. 21, the dielectric layer 32 is formed so as to cover the conductive layer 21. At this time, the insulating separation film 60 is simultaneously formed on the inner wall surface of the contact hole 120.

Next, as shown in FIG. 22, the conductive layer 22 is formed so as to cover the dielectric layer 32. At the same time, the embedded electrode 40 is formed inside the contact hole 120.

Next, as shown in FIG. 23, a contact hole 120 is formed on the second main surface 12 so as to reach the bottom of the groove 100c and connect with the groove 100c. Then, as shown in FIG. 24, the dielectric layer 33 is formed so as to cover the conductive layer 22. At this time, the insulating separation film 60 is simultaneously formed on the inner wall surface of the contact hole 120. Further, as shown in FIG. 25, the groove 100 is embedded so as to cover the dielectric layer 33 to form the conductive layer 23. At the same time, the embedded electrode 40 is formed inside the contact hole 120.

After that, the first insulating film 71 is formed on the first main surface 11 of the semiconductor substrate 10. At the same time that the dielectric layers 31 to 33 are formed, the second insulating film 72 is formed on the second main surface 12. Then, after providing an opening at a predetermined position of the first insulating film 71, a first electrode 51a is formed so as to embed the opening, and the first electrode 51a and the conductive layer 23 are electrically connected. Further, an opening is provided in the second insulating film 72 at the position where the embedded electrode 40 is formed, and the first electrode 51b1, the first electrode 51b2, and the second electrode 52b1 are formed so as to electrically connect the embedded electrode 40. .. Further, an opening in which a part of the semiconductor substrate 10 is exposed is provided at a predetermined position of the second insulating film 72, and the second electrode 52b2 is formed so as to be connected to the semiconductor substrate 10. As a result, the semiconductor device 1 shown in FIG. 16 is completed.

It should be noted that a plurality of embedded electrodes 40 that are electrically connected to each layer of the conductive layer 20 formed inside the same groove may be formed. That is, a plurality of embedded electrodes 40 arranged apart from each other along the bottom of the same groove are formed. Then, each of the conductive layers 20 arranged spatially separated from each other via the dielectric layer 30 inside the groove may be connected to different embedded electrodes 40.

For example, as shown in FIG. 26, a plurality of embedded electrodes 40 are arranged with respect to the groove 100. In FIG. 26, the embedded electrode 40 is indicated by a broken line through the semiconductor substrate 10. 27 (a) to 27 (c) show cross-sectional views taken along the I-I direction, II-II direction, and III-III direction of FIG. 26, respectively.

The embedded electrode 40 shown in FIG. 27 (a) is electrically connected to the conductive layer 21. The embedded electrode 40 shown in FIG. 27B is electrically connected to the conductive layer 22. The embedded electrode 40 shown in FIG. 27 (c) is electrically connected to the conductive layer 23.

By applying the above configuration, the conductive layers 20 electrically insulated inside the groove can be electrically connected to each other by means of metal wiring or the like arranged on the second main surface 12. Therefore, the area of the groove on the first main surface 11 can be expanded. Therefore, it is possible to provide the semiconductor device 1 having a high capacitance density per substrate area. For example, as shown in FIG. 16, regarding the conductive layers 21 to 23 formed inside the plurality of grooves, the conductive layer 21 and the conductive layer 21 formed in different grooves, the conductive layer 22 and the conductive layer 22, and the conductive layer 23 The conductive layer 23 can be electrically connected.

Although FIG. 16 shows only three grooves formed on the first main surface 11, four or more grooves may be formed. Further, although the example in which the conductive layer 20 is three layers is shown, the conductive layer 20 may be four or more layers. The number of layers of the dielectric layer 30 is the same as that of the conductive layer 20. Further, although the number of the embedded electrodes 40 is indicated by 3, it may be 4 or more.

(Third embodiment)
As shown in FIG. 28, in the semiconductor device 1 according to the third embodiment of the present invention, a plurality of striped grooves 100 extending in parallel with each other in the vertical direction of the paper surface are formed on the first main surface 11. .. A conductive layer 20 is laminated inside each groove 100. Then, a plurality of contact holes 120 are formed so as to intersect the stretching direction of the groove 100 and stretch in the left-right direction of the paper surface, and the embedded electrodes 40 are arranged in each of the contact holes 120. Therefore, each of the embedded electrodes 40 intersects the plurality of grooves 100. In FIG. 28, the embedded electrode 40 is shown by a broken line through the semiconductor substrate 10.

The embedded electrode 40 is electrically connected to any of the conductive layers 20 arranged inside the groove 100. Sectional views along the IV-IV direction, VV direction, and VI-VI direction of FIG. 28 are shown in FIGS. 29 (a) to 29 (c), respectively. At the position shown in FIG. 29 (a), the embedded electrode 40 is electrically connected to the conductive layer 21. At the position shown in FIG. 29 (b), the embedded electrode 40 is electrically connected to the conductive layer 22. At the position shown in FIG. 29 (c), the embedded electrode 40 is electrically connected to the conductive layer 23.

The basic operation of the semiconductor device 1 shown in FIG. 28 is the same as that of the semiconductor device 1 according to the second embodiment shown in FIG. However, since the surface area of the insulating separation membrane 60 is larger than that of the semiconductor device 1 shown in FIG. 16, the capacitance density can be improved.

The manufacturing method of the semiconductor device 1 shown in FIG. 28 is the same as the manufacturing method of the semiconductor device 1 shown in FIG. 16 described with reference to FIGS. 17 to 25. However, since the groove 100 and the contact hole 120 only need to overlap at any position of the contact hole 120 extending in the direction intersecting the groove 100, the alignment accuracy can be lowered with respect to the position of the contact hole 120. Therefore, the manufacturing of the semiconductor device 1 becomes easy.

Although FIG. 28 shows an example in which the groove formed on the first main surface 11 and the embedded electrode 40 are orthogonal to each other, the groove and the embedded electrode 40 may intersect diagonally at a constant angle. ..

(Fourth Embodiment)
In the semiconductor device 1 shown in FIG. 1, the first electrode 51 is arranged only on the first main surface 11 of the semiconductor substrate 10, and the second electrode 52 is arranged only on the second main surface 12. However, each of the first electrode 51 and the second electrode 52 may have a portion arranged on the first main surface 11 and a portion arranged on the second main surface 12.

For example, as shown in FIG. 30, the first electrode 51a and the second electrode 52a are arranged on the first main surface 11 of the semiconductor substrate 10 so as to be separated from each other, and the first electrode 51b and the second electrode are arranged on the second main surface 12. 52b are arranged apart from each other. The first electrode 51a and the first electrode 51b are each part of the first electrode 51 that is electrically connected to the first conductive layer 2A. The second electrode 52a and the second electrode 52b are each part of the second electrode 52 that is electrically connected to the second conductive layer 2B. By stacking the semiconductor devices 1 having this configuration as shown in FIG. 30, the capacitor structures formed in the semiconductor devices 1 can be connected in parallel.

As described above, in the semiconductor device 1 according to the fourth embodiment, positive and negative electrodes are arranged on each of the first main surface 11 and the second main surface 12 of the semiconductor substrate 10. Therefore, a mounting form in which the semiconductor devices 1 are laminated and the capacitor structures are connected in parallel becomes possible. That is, it is possible to provide the semiconductor device 1 with few restrictions on the mounting form.

(Other embodiments)
As mentioned above, embodiments of the invention have been described, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

For example, when the semiconductor substrate 10 has conductivity, as shown in FIG. 31, the dielectric layer 31 is arranged between the conductive layer 21 closest to the side surface of the groove and the side surface of the groove. Then, of the conductive layers 20, the conductive layer electrically insulated from the conductive layer 21 is electrically connected to the semiconductor substrate 10. As a result, a capacity is formed between the semiconductor substrate 10 and the conductive layer 21, so that the capacity of the semiconductor device 1 can be increased.

Further, although the example in which the first conductive layer 2A and the second conductive layer 2B are alternately arranged is shown above, the arrangement of the conductive layer 20 is not limited to this configuration. For example, there may be a portion where the first conductive layer 2A and the first conductive layer 2A are adjacent to each other via the dielectric layer 30, or the second conductive layer 2B and the second conductive layer 2B are adjacent to each other via the dielectric layer 30. There may be a part that has been made to.

Although the case where the conductive layer 20 is a polycrystalline silicon film has been described above, the conductive layer 20 may be another conductive semiconductor film or metal film. For example, conductive polycrystalline silicon carbide, silicon germanium (SiGe), aluminum, or the like may be used as the material of the conductive layer 20.

1 ... Semiconductor device 10 ... Semiconductor substrate 11 ... First main surface 12 ... Second main surface 21-23 ... Conductive layer 2A ... First conductive layer 2B ... Second conductive layer 31-33 ... Dielectric layer 40 ... Embedded electrode 51 ... 1st electrode 52 ... 2nd electrode 60 ... Insulation separation film 71 ... 1st insulating film 72 ... 2nd insulating film 100 ... Groove 120 ... Contact hole

Claims (17)

A semiconductor substrate having a first main surface and a second main surface facing each other and having a groove formed on the first main surface,
A plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, laminated along the surface normal direction of the side surface of the groove.
Dielectric layers arranged between the plurality of conductive layers, and
An embedded electrode embedded in a contact hole formed so as to reach the bottom of the groove from the second main surface and electrically connected to the second conductive layer at the bottom of the groove.
A first electrode arranged on the semiconductor substrate outside the groove and electrically connected to the first conductive layer,
A semiconductor device which is arranged on the second main surface and includes a second electrode which is electrically connected to the second conductive layer via the embedded electrode. Of the plurality of conductive layers, the conductive layer closest to the side surface of the groove is used as the first conductive layer.
The odd-numbered conductive layers of the plurality of conductive layers are electrically connected to each other, and the conductive layers are electrically connected to each other.
The even-numbered conductive layers of the plurality of conductive layers are electrically connected to each other, and the conductive layers are electrically connected to each other.
The semiconductor device according to claim 1, wherein the odd-numbered conductive layer and the even-numbered conductive layer are electrically insulated by the dielectric layer. The first electrode is arranged on the first main surface, and the first electrode is arranged on the first main surface.
Of the plurality of conductive layers, the conductive layer arranged farthest from the side surface of the groove is electrically connected to the first electrode.
Claim 1 or 2 characterized in that the second conductive layer electrically insulated from the first conductive layer is electrically connected to the second electrode arranged on the second main surface. The semiconductor device described in. A plurality of the first electrodes are provided.
The semiconductor device according to any one of claims 1 to 3, wherein at least one of the first electrodes is arranged on the second main surface apart from the second electrode. It has a plurality of the embedded electrodes arranged apart from each other along the bottom of the groove.
The invention according to any one of claims 1 to 4, wherein the respective conductive layers arranged apart from each other via the dielectric layer inside the groove are connected to different embedded electrodes. Semiconductor device. A plurality of the first electrodes and a plurality of the second electrodes are provided.
At least one of the first electrodes is placed on the first main surface and the other at least one is placed on the second main surface.
At least one of the second electrodes is arranged on the first main surface at a distance from the first electrode, and at least one of the other electrodes is arranged on the second main surface at a distance from the first electrode. The semiconductor device according to any one of claims 1 to 5. The semiconductor substrate has conductivity and
The semiconductor according to any one of claims 1 to 6, wherein the conductive layer closest to the side surface of the groove of the plurality of conductive layers is in contact with the semiconductor substrate on the side surface of the groove. Device. The semiconductor substrate has conductivity and
Among the plurality of conductive layers, the dielectric layer is arranged between the conductive layer closest to the side surface of the groove and the side surface of the groove.
The present invention according to any one of claims 1 to 6, wherein the conductive layer electrically insulated from the closest conductive layer among the plurality of conductive layers is electrically connected to the semiconductor substrate. The semiconductor device described. The semiconductor substrate has conductivity and
The invention according to any one of claims 1 to 8, wherein an insulating separation membrane is arranged between the semiconductor substrate and the embedded electrode, and the semiconductor substrate and the embedded electrode are electrically insulated from each other. Semiconductor equipment. A plurality of the grooves extending in parallel with each other are formed on the first main surface, and the grooves are formed.
The contact hole is formed along a direction intersecting the extending direction of the groove.
One of claims 1 to 9, wherein the embedded electrode is electrically connected to any one of the plurality of conductive layers arranged inside the plurality of grooves, respectively, at the bottom of the plurality of grooves. The semiconductor device described in the section. In the cross section along the lateral direction of the groove, the width of the contact hole is smaller than twice the thickness of the conductive layer connected to the embedded electrode embedded in the contact hole among the plurality of conductive layers. The semiconductor device according to any one of claims 1 to 10. The semiconductor device according to any one of claims 1 to 11, wherein the semiconductor substrate is a single crystal silicon substrate or a polycrystalline silicon substrate. The semiconductor device according to any one of claims 1 to 12, wherein the plurality of conductive layers and the embedded electrode are polycrystalline silicon films. The semiconductor device according to any one of claims 1 to 13, wherein the dielectric layer contains at least one of a silicon oxide film and a silicon nitride film. The semiconductor device according to any one of claims 1 to 14, wherein the dielectric layer has a structure in which a plurality of dielectric films made of different materials are laminated. The process of forming a groove on the first main surface of the semiconductor substrate,
A plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, are formed along the surface normal direction of the side surface of the groove while forming a dielectric layer between the plurality of conductive layers. The process of laminating and
A step of forming a contact hole reaching the bottom of the groove from the second main surface of the semiconductor substrate facing the first main surface.
A step of forming an embedded electrode inside the contact hole so as to connect to the second conductive layer at the bottom of the groove.
A step of forming a first electrode electrically connected to the first conductive layer on the outside of the groove, and a step of forming the first electrode.
A step of forming a second electrode electrically connected to the second conductive layer via the embedded electrode on the second main surface is included.
A method for manufacturing a semiconductor device, which comprises simultaneously forming the embedded electrode and the second conductive layer connected to the embedded electrode. Further including a step of forming an insulating separation film between the semiconductor substrate and the embedded electrode
The method for manufacturing a semiconductor device according to claim 16, wherein the dielectric layer having the second conductive layer connected to the embedded electrode formed on the surface thereof and the insulating separation membrane are simultaneously formed.

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