WO2017008333A1 - Tft基板结构的制作方法 - Google Patents

Tft基板结构的制作方法 Download PDF

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Publication number
WO2017008333A1
WO2017008333A1 PCT/CN2015/085161 CN2015085161W WO2017008333A1 WO 2017008333 A1 WO2017008333 A1 WO 2017008333A1 CN 2015085161 W CN2015085161 W CN 2015085161W WO 2017008333 A1 WO2017008333 A1 WO 2017008333A1
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layer
depositing
via hole
tft substrate
fabricating
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French (fr)
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吕晓文
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6725—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having supplementary regions or layers for improving the flatness of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate structure.
  • a liquid crystal display includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing.
  • the liquid crystal panel is composed of a color filter substrate (CF), a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (filled between the two substrates).
  • CF color filter substrate
  • TFT Array Substrate thin film transistor array substrate
  • a transparent electrode is provided on the opposite inner side of the CF substrate and the TFT substrate.
  • the liquid crystal display controls the orientation of the liquid crystal molecules by the electric field, changes the polarization state of the light, and realizes the penetration and blocking of the optical path by the polarizing plate, thereby achieving the purpose of display.
  • Fringe Field Switching (FFS) technology is one of the technologies that have improved LCD image quality in recent years, enabling high penetration and large viewing angles.
  • 1 is a schematic cross-sectional view of a TFT substrate of a conventional FFS liquid crystal display panel, which includes a substrate 100, a buffer layer 200 disposed on the substrate 100, and a gate electrode disposed on the buffer layer 200. 300.
  • the gate insulating layer 400 covering the gate 300 on the buffer layer 200, the island-shaped conductor layer 500 disposed on the gate insulating layer 400, and the gate insulating layer 400 are disposed on the gate insulating layer 400.
  • a source 600 and a drain 700 respectively contacting the two sides of the island-shaped conductor layer 500, and first electrodes provided on the gate insulating layer 400, the island-shaped semiconductor layer 500, the source 600 and the drain 700 a passivation layer 800, a flat layer 900 disposed on the first passivation layer 800, a first pixel electrode 1000 disposed on the flat layer 900, and the flat layer 900 and the first pixel electrode 1000 a second passivation layer 1100, and a second pixel electrode 1200 disposed on the second passivation layer 1100; a corresponding layer on the second passivation layer 1100, the flat layer 900, and the first passivation layer 800 A via 1300 is formed over the drain 700, and the second pixel electrode 1200 is in contact with the drain 700 via the via 1300.
  • a method for fabricating a TFT substrate structure of a conventional FFS liquid crystal display panel includes the following steps;
  • Step 1 as shown in FIG. 2, providing a substrate 100, depositing a buffer layer 200 on the substrate 100; depositing a first metal layer on the buffer layer 200, and patterning the first metal layer, Forming a gate 300;
  • Step 2 depositing gate insulation on the buffer layer 200 and the gate 300 a layer 400; depositing an oxide semiconductor layer on the gate insulating layer 400, and patterning the oxide semiconductor layer to form an island-shaped semiconductor layer 500;
  • Step 3 depositing a second metal layer on the gate insulating layer 400 and the island-shaped semiconductor layer 500, and patterning the second metal layer to obtain a source 600, and Drain 700;
  • Step 4 depositing a first passivation layer 800 on the gate insulating layer 400, the island-shaped semiconductor layer 500, the source 600, and the drain 700, and in the first passivation layer a first via 810 is formed on the 800 corresponding to the drain 700;
  • Step 5 as shown in FIG. 6, a flat layer 900 is formed on the first passivation layer 800, and a second via hole 910 is formed on the flat layer 900 corresponding to the first via hole 810;
  • Step 6 depositing a first transparent conductive film on the flat layer 900, and coating a photoresist layer 1101 on the first transparent conductive film;
  • the photoresist layer 1101 is easily deposited in the first and second via holes 810, 910;
  • Step 7 as shown in FIG. 8, the photoresist layer 1101 is exposed and developed
  • the photoresist layer 1101 deposited in the first and second via holes 810 and 910 is not easily developed, and the photoresist layer 1101 is in the first and second via holes 810 and 910. Residue
  • Step 8 as shown in FIG. 9, the photoresist layer 1101 is used as a shielding layer, and the first transparent conductive film not blocked by the photoresist layer 1101 is etched to obtain a first pixel electrode 1000;
  • first transparent conductive film located in the first and second via holes 810 and 910 is covered with a residual photoresist, it cannot be completely etched away during the etching process, thereby causing the first transparent conductive film to be in the first 1.
  • the second via holes 810 and 910 remain, which may affect subsequent processes and adversely affect the quality of the TFT substrate.
  • An object of the present invention is to provide a method for fabricating a TFT substrate structure, which can effectively prevent the first transparent conductive film from remaining at the via hole and improve the production yield of the TFT substrate.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps;
  • Step 1 providing a substrate, depositing a buffer layer on the substrate; depositing a first metal layer on the buffer layer, and patterning the first metal layer to form a gate;
  • Step 2 depositing a gate insulating layer on the buffer layer and the gate; depositing an oxide semiconductor layer on the gate insulating layer, and patterning the oxide semiconductor layer to form an island semiconductor Floor;
  • Step 3 depositing a second metal layer on the gate insulating layer and the island-shaped semiconductor layer, and patterning the second metal layer to obtain a source and a drain;
  • Step 4 depositing a first passivation layer on the gate insulating layer, the island-shaped semiconductor layer, the source, and the drain;
  • Step 5 forming a flat layer on the first passivation layer
  • Step 6 depositing a first transparent conductive film on the flat layer, and patterning the first transparent conductive film to form a first pixel electrode;
  • Step 7 Form a first via hole and a second via hole on the first passivation layer and the flat layer corresponding to the drain, and the first via hole and the second via hole are exposed. Partial drain
  • Step 8 Depositing a second passivation layer on the first pixel electrode and the planar layer, and patterning the second passivation layer to form a corresponding one on the second passivation layer. a first via hole and a third via hole of the second via hole;
  • Step 9 Depositing a second transparent conductive film on the second passivation layer, and patterning the second transparent conductive film to form a second pixel electrode, where the second pixel electrode passes through the first Second, the third via is connected to the drain.
  • the material of the oxide semiconductor layer is IGZO.
  • the step 4 deposits the first passivation layer by chemical vapor deposition.
  • the step 5 forms a flat layer by a coating process; the material of the flat layer is PFA.
  • the step 6 deposits the first transparent conductive film by physical vapor deposition; and forms the first pixel electrode by a wet etching process.
  • Step 7 first adopting a yellow light process to expose a first via hole on the flat layer corresponding to the drain, and then using the flat layer as a self-aligned photomask, using a dry etching process in the first A second via is etched on a passivation layer corresponding to the first via.
  • the material of the gate is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the source and drain is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer, the first passivation layer, and the second passivation layer is silicon oxide, silicon nitride, or a stacked combination of the two.
  • the materials of the first pixel electrode and the second pixel electrode are both ITO.
  • the present invention also provides a method for fabricating a TFT substrate structure, comprising the following steps;
  • Step 1 providing a substrate, depositing a buffer layer on the substrate; depositing a first metal layer on the buffer layer, and patterning the first metal layer to form a gate;
  • Step 2 depositing a gate insulating layer on the buffer layer and the gate; depositing an oxide semiconductor layer on the gate insulating layer, and patterning the oxide semiconductor layer to form an island semiconductor Floor;
  • Step 3 depositing a second metal layer on the gate insulating layer and the island-shaped semiconductor layer, and patterning the second metal layer to obtain a source and a drain;
  • Step 4 depositing a first passivation layer on the gate insulating layer, the island-shaped semiconductor layer, the source, and the drain;
  • Step 5 forming a flat layer on the first passivation layer
  • Step 6 depositing a first transparent conductive film on the flat layer, and patterning the first transparent conductive film to form a first pixel electrode;
  • Step 7 Form a first via hole and a second via hole on the first passivation layer and the flat layer corresponding to the drain, and the first via hole and the second via hole are exposed. Partial drain
  • Step 8 Depositing a second passivation layer on the first pixel electrode and the planar layer, and patterning the second passivation layer to form a corresponding one on the second passivation layer. a first via hole and a third via hole of the second via hole;
  • Step 9 Depositing a second transparent conductive film on the second passivation layer, and patterning the second transparent conductive film to form a second pixel electrode, where the second pixel electrode passes through the first Second, the third via is connected to the drain;
  • step 4 deposits the first passivation layer by chemical vapor deposition
  • the step 5 is formed by a coating process to form the flat layer;
  • the material of the flat layer is PFA;
  • step 6 is to deposit the first transparent conductive film by physical vapor deposition; forming the first pixel electrode by a wet etching process;
  • the step 7 first adopts a yellow light process to expose the first via hole on the flat layer corresponding to the drain, and then uses the flat layer as a self-aligned photomask, and adopts a dry etching process in the A second via is etched on the first passivation layer corresponding to the first via.
  • the first transparent conductive film is patterned to form a first a pixel electrode, and then a yellow light process is used to expose the first via hole above the corresponding drain on the flat layer, and then the flat layer is used as a self-aligned mask, and the dry etching process is performed on the first passivation layer.
  • a via hole etches the second via hole, thereby effectively preventing the first transparent conductive film from remaining at the first and second via holes, improving the production yield, and reducing a mask, thereby avoiding the misalignment caused by the alignment.
  • the reduction of the aperture ratio increases the production efficiency, reduces the production cost, and increases the competitiveness of the product price.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional TFT substrate
  • FIG. 2 is a schematic view showing a step 1 of a method for fabricating a conventional TFT substrate structure
  • FIG. 3 is a schematic view showing a step 2 of a method for fabricating a conventional TFT substrate structure
  • FIG. 4 is a schematic view showing a step 3 of a method for fabricating a conventional TFT substrate structure
  • FIG. 5 is a schematic view showing a step 4 of a method for fabricating a conventional TFT substrate structure
  • FIG. 6 is a schematic view showing a step 5 of a method for fabricating a conventional TFT substrate structure
  • FIG. 7 is a schematic view showing a step 6 of a method for fabricating a conventional TFT substrate structure
  • FIG. 8 is a schematic view showing a step 7 of a method for fabricating a conventional TFT substrate structure
  • FIG. 9 is a schematic view showing a step 8 of a method for fabricating a conventional TFT substrate structure
  • FIG. 10 is a flow chart showing a method of fabricating a TFT substrate structure of the present invention.
  • FIG. 11 is a schematic view showing the first step of the method for fabricating the TFT substrate structure of the present invention.
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT substrate structure according to the present invention.
  • Figure 13 is a schematic view showing the third step of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 14 is a schematic view showing a step 4 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 15 is a schematic view showing a step 5 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 16 to FIG. 17 are schematic diagrams showing the step 6 of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 18 is a schematic view showing a step 7 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 19 is a schematic view showing a step 8 of a method for fabricating a TFT substrate structure according to the present invention.
  • Figure 20 is a schematic view showing the step 9 of the method of fabricating the TFT substrate structure of the present invention.
  • the present invention provides a method for fabricating a TFT substrate structure, including the following steps;
  • Step 1 as shown in FIG. 11, providing a substrate 1, depositing a buffer layer 2 on the substrate 1, depositing a first metal layer on the buffer layer 2, and patterning the first metal layer, A gate electrode 3 is formed.
  • the material of the gate 3 is a stack combination of one or more of molybdenum, titanium, aluminum and copper.
  • Step 2 depositing a gate insulating layer 4 on the buffer layer 2 and the gate 3; depositing an oxide semiconductor layer on the gate insulating layer 4, and depositing the oxide semiconductor The layer is patterned to form the island-shaped semiconductor layer 5.
  • the material of the gate insulating layer 4 is silicon oxide, silicon nitride, or a stacked combination of the two.
  • the material of the island-shaped semiconductor layer 5 is IGZO (Indium Gallium Zinc Oxide).
  • Step 3 depositing a second metal layer on the gate insulating layer 4 and the island-shaped semiconductor layer 5, and patterning the second metal layer to obtain a source electrode 6, and Drain 7.
  • the source electrode 6 and the drain electrode 7 are in contact with both sides of the island-shaped semiconductor layer 5, respectively.
  • the material of the source 6 and the drain 7 is a stack combination of one or more of molybdenum, titanium, aluminum and copper.
  • Step 4 depositing a first passivation layer 8 on the gate insulating layer 4, the island-shaped semiconductor layer 5, the source 6, and the drain 7.
  • the first passivation layer 8 is deposited by chemical vapor deposition (CVD).
  • the material of the first passivation layer 8 is silicon oxide, silicon nitride, or a stacked combination of the two.
  • Step 5 As shown in FIG. 15, a flat layer 9 is formed on the first passivation layer 8.
  • the flat layer 9 is formed by a coating process; the material of the flat layer 9 is PFA (soluble polytetrafluoroethylene).
  • Step 6 depositing a first transparent conductive film on the flat layer 9, and patterning the first transparent conductive film to form a first pixel electrode 10.
  • the first transparent conductive film is deposited by physical vapor deposition (PVD); the first pixel electrode 10 is formed by a wet etching (Wet Etch) process; the material of the first pixel electrode 10 is ITO ( Indium tin oxide).
  • Step 7 as shown in FIG. 18, a first via 91 and a second via 92 are sequentially formed on the first passivation layer 8 and the flat layer 9 corresponding to the drain 7.
  • a via 91 and a second via 92 expose a portion of the drain 7.
  • the first via 91 is exposed on the flat layer 9 corresponding to the drain 7 by using a yellow light process, and then the flat layer 9 is used as a self-aligning mask, and dry etching is used (Dry The Etch process etches the second via 92 on the first passivation layer 8 corresponding to the first via 91.
  • Step 8 as shown in FIG. 19, depositing a second passivation layer 11 on the first pixel electrode 10 and the flat layer 9, and patterning the second passivation layer 11 in the second A third via 93 corresponding to the first via 91 and the second via 92 is formed on the passivation layer 11.
  • the material of the second passivation layer 11 is silicon oxide, silicon nitride, or a stacked combination of the two.
  • Step 9 as shown in FIG. 20, depositing a second transparent conductive film on the second passivation layer 11, and patterning the second transparent conductive film to form a second pixel electrode 12, the first
  • the two-pixel electrode 12 is connected to the drain 7 via the first, second, and third via holes 91, 92, and 93.
  • the material of the first pixel electrode 12 is ITO (Indium Tin Oxide).
  • the first transparent conductive film is patterned to form the first a pixel electrode, and then a yellow light process is used to expose the first via hole above the corresponding drain on the flat layer, and then the flat layer is used as a self-aligned photomask, and the dry etching process is performed on the first passivation layer corresponding to the first pass.
  • the via hole etches the second via hole, thereby effectively preventing the residue of the first transparent conductive film at the first and second via holes, improving the production yield, and reducing a mask to avoid the misalignment caused by the alignment.
  • the reduction of the aperture ratio increases the production efficiency, reduces the production cost, and increases the competitiveness of the product price.

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Abstract

本发明提供一种TFT基板结构的制作方法，在依次形成第一钝化层、平坦层、及第一透明导电膜之后，先对第一透明导电膜进行图案化处理，形成第一像素电极，之后再采用黄光制程在平坦层上对应漏极上方曝光出第一过孔，然后以平坦层为自对准光罩，采用干法蚀刻制程在第一钝化层上对应第一过孔蚀刻出第二过孔，从而有效防止第一透明导电膜在第一、第二过孔处的残留，提高了生产良率，同时减少一道光罩，避免了由于对位不准造成的开口率降低，提高了生产效率，降低了生产成本，提高了产品价格的竞争力。

Description

TFT基板结构的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构的制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组。通常液晶面板由一彩色滤光片基板(Color Filter，CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一填充于两基板间的液晶层(Liquid Crystal Layer)所构成。CF基板和TFT基板的相对内侧设有透明电极。液晶显示器通过电场对液晶分子的取向进行控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，达到显示的目的。
边缘场开关(Fringe Field Switching，FFS)技术是近年来出现的改善LCD画质的技术之一，能同时实现高穿透性和大视角的要求。图1所示为一种现有FFS型液晶显示面板的TFT基板的剖面结构示意图，其包括基板100、设于所述基板100上的缓冲层200、设于所述缓冲层200上的栅极300、设于所述缓冲层200上覆盖所述栅极300的栅极绝缘层400、设于所述栅极绝缘层400上的岛状导体层500、设于所述栅极绝缘层400上分别与所述岛状导体层500的两侧相接触的源极600与漏极700、设于所述栅极绝缘层400、岛状半导体层500、源极600与漏极700上的第一钝化层800、设于所述第一钝化层800上的平坦层900、设于所述平坦层900上的第一像素电极1000、设于所述平坦层900与第一像素电极1000上的第二钝化层1100、及设于所述第二钝化层1100上的第二像素电极1200；所述第二钝化层1100、平坦层900、及第一钝化层800上对应所述漏极700的上方形成有过孔1300，所述第二像素电极1200经由所述过孔1300与所述漏极700相接触。
请参阅图2至图9，现有FFS型液晶显示面板的TFT基板结构的制作方法包括如下步骤；
步骤1、如图2所示，提供基板100，在所述基板100上沉积缓冲层200；在所述缓冲层200上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极300；
步骤2、如图3所示，在所述缓冲层200、及栅极300上沉积栅极绝缘 层400；在所述栅极绝缘层400上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层500；
步骤3、如图4所示，在所述栅极绝缘层400、及岛状半导体层500上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极600、及漏极700；
步骤4、如图5所示，在所述栅极绝缘层400、岛状半导体层500、源极600、及漏极700上沉积第一钝化层800，并在所述第一钝化层800上对应所述漏极700上方形成第一过孔810；
步骤5、如图6所示，在所述第一钝化层800上形成平坦层900，并在所述平坦层900上对应所述第一过孔810上方形成第二过孔910；
步骤6、如图7所示，在所述平坦层900上沉积第一透明导电膜，并在所述第一透明导电膜上涂布光阻层1101；
由于第一、第二过孔810、910较深，因此光阻层1101容易在所述第一、第二过孔810、910内堆积；
步骤7、如图8所示，对所述光阻层1101进行曝光、显影；
具体的，在曝光、显影时，堆积在所述第一、第二过孔810、910内的光阻层1101容易显影不完全，造成光阻层1101在第一、第二过孔810、910处残留；
步骤8、如图9所示，以所述光阻层1101为遮蔽层，对没有被所述光阻层1101遮挡的第一透明导电膜进行蚀刻处理，得到第一像素电极1000；
由于位于所述第一、第二过孔810、910内的第一透明导电膜上覆盖有残留光阻，因此在蚀刻过程中无法被完全蚀刻掉，从而造成所述第一透明导电膜在第一、第二过孔810、910处残留，因而会影响后续制程，对TFT基板的品质造成不良影响。
因此，基于现有制作方法中存在的问题和缺陷，有必要提供一种改进的TFT基板结构的制作方法，以解决现有技术所存在的问题。
发明内容
本发明的目的在于提供一种TFT基板结构的制作方法，能有效防止第一透明导电膜在过孔处的残留，提高TFT基板的生产良率。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤；
步骤1、提供基板，在所述基板上沉积缓冲层；在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述缓冲层、及栅极上沉积栅极绝缘层；在所述栅极绝缘层上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层；
步骤3、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极、及漏极；
步骤4、在所述栅极绝缘层、岛状半导体层、源极、及漏极上沉积第一钝化层；
步骤5、在所述第一钝化层上形成平坦层；
步骤6、在所述平坦层上沉积第一透明导电膜，并对所述第一透明导电膜进行图案化处理，形成第一像素电极；
步骤7、在所述第一钝化层、及平坦层上对应所述漏极的上方依次形成第一过孔、及第二过孔，所述第一过孔、及第二过孔暴露出部分漏极；
步骤8、在所述第一像素电极及平坦层上沉积第二钝化层，并对所述第二钝化层进行图案化处理，在所述第二钝化层上形成一对应于所述第一过孔与第二过孔的第三过孔；
步骤9、在所述第二钝化层上沉积第二透明导电膜，并对所述第二透明导电膜进行图案化处理，形成第二像素电极，所述第二像素电极经由第一、第二、第三过孔与漏极相连。
所述氧化物半导体层的材料为IGZO。
所述步骤4采用化学气相沉积法沉积所述第一钝化层。
所述步骤5采用涂布制程形成所述平坦层；所述平坦层的材料为PFA。
所述步骤6采用物理气相沉积法沉积所述第一透明导电膜；采用湿法蚀刻制程形成所述第一像素电极。
所述步骤7先采用黄光制程在所述平坦层上对应所述漏极上方曝光出第一过孔，然后以所述平坦层为自对准光罩，采用干法蚀刻制程在所述第一钝化层上对应所述第一过孔蚀刻出第二过孔。
所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述栅极绝缘层、第一钝化层、及第二钝化层的材料为氧化硅、氮化硅、或二者的堆栈组合。
所述第一像素电极、及第二像素电极的材料均为ITO。
本发明还提供一种TFT基板结构的制作方法，包括如下步骤；
步骤1、提供基板，在所述基板上沉积缓冲层；在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述缓冲层、及栅极上沉积栅极绝缘层；在所述栅极绝缘层上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层；
步骤3、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极、及漏极；
步骤4、在所述栅极绝缘层、岛状半导体层、源极、及漏极上沉积第一钝化层；
步骤5、在所述第一钝化层上形成平坦层；
步骤6、在所述平坦层上沉积第一透明导电膜，并对所述第一透明导电膜进行图案化处理，形成第一像素电极；
步骤7、在所述第一钝化层、及平坦层上对应所述漏极的上方依次形成第一过孔、及第二过孔，所述第一过孔、及第二过孔暴露出部分漏极；
步骤8、在所述第一像素电极及平坦层上沉积第二钝化层，并对所述第二钝化层进行图案化处理，在所述第二钝化层上形成一对应于所述第一过孔与第二过孔的第三过孔；
步骤9、在所述第二钝化层上沉积第二透明导电膜，并对所述第二透明导电膜进行图案化处理，形成第二像素电极，所述第二像素电极经由第一、第二、第三过孔与漏极相连；
其中，所述步骤4采用化学气相沉积法沉积所述第一钝化层；
其中，所述步骤5采用涂布制程形成所述平坦层；所述平坦层的材料为PFA；
其中，所述步骤6采用物理气相沉积法沉积所述第一透明导电膜；采用湿法蚀刻制程形成所述第一像素电极；
其中，所述步骤7先采用黄光制程在所述平坦层上对应所述漏极上方曝光出第一过孔，然后以所述平坦层为自对准光罩，采用干法蚀刻制程在所述第一钝化层上对应所述第一过孔蚀刻出第二过孔。
本发明的有益效果：本发明的TFT基板结构的制作方法，在依次形成第一钝化层、平坦层、及第一透明导电膜之后，先对第一透明导电膜进行图案化处理，形成第一像素电极，之后再采用黄光制程在平坦层上对应漏极上方曝光出第一过孔，然后以平坦层为自对准光罩，采用干法蚀刻制程在第一钝化层上对应第一过孔蚀刻出第二过孔，从而有效防止第一透明导电膜在第一、第二过孔处的残留，提高了生产良率，同时减少一道光罩，避免了由于对位不准造成的开口率降低，提高了生产效率，降低了生产成本，提高了产品价格的竞争力。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT基板的剖面结构示意图；
图2为现有的TFT基板结构的制作方法的步骤1的示意图；
图3为现有的TFT基板结构的制作方法的步骤2的示意图；
图4为现有的TFT基板结构的制作方法的步骤3的示意图；
图5为现有的TFT基板结构的制作方法的步骤4的示意图；
图6为现有的TFT基板结构的制作方法的步骤5的示意图；
图7为现有的TFT基板结构的制作方法的步骤6的示意图；
图8为现有的TFT基板结构的制作方法的步骤7的示意图；
图9为现有的TFT基板结构的制作方法的步骤8的示意图；
图10为本发明的TFT基板结构的制作方法的流程图；
图11为本发明的TFT基板结构的制作方法的步骤1的示意图；
图12为本发明的TFT基板结构的制作方法的步骤2的示意图；
图13为本发明的TFT基板结构的制作方法的步骤3的示意图；
图14为本发明的TFT基板结构的制作方法的步骤4的示意图；
图15为本发明的TFT基板结构的制作方法的步骤5的示意图；
图16至图17为本发明的TFT基板结构的制作方法的步骤6的示意图；
图18为本发明的TFT基板结构的制作方法的步骤7的示意图；
图19为本发明的TFT基板结构的制作方法的步骤8的示意图；
图20为本发明的TFT基板结构的制作方法的步骤9的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图10，本发明提供一种TFT基板结构的制作方法，包括如下步骤；
步骤1、如图11所示，提供基板1，在所述基板1上沉积缓冲层2；在所述缓冲层2上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极3。
优选的，所述栅极3的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤2、如图12所示，在所述缓冲层2、及栅极3上沉积栅极绝缘层4；在所述栅极绝缘层4上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层5。
优选的，所述栅极绝缘层4的材料为氧化硅、氮化硅、或二者的堆栈组合。
具体的，所述岛状半导体层5的材料为IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)。
步骤3、如图13所示，在所述栅极绝缘层4、及岛状半导体层5上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极6、及漏极7。所述源极6、及漏极7分别与所述岛状半导体层5的两侧相接触。
优选的，所述源极6与漏极7的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤4、如图14示，在所述栅极绝缘层4、岛状半导体层5、源极6、及漏极7上沉积第一钝化层8。
具体的，采用化学气相沉积法(CVD)沉积所述第一钝化层8。
优选的，所述第一钝化层8的材料为氧化硅、氮化硅、或二者的堆栈组合。
步骤5、如图15所示，在所述第一钝化层8上形成平坦层9。
具体的，采用涂布制程(Coating)形成所述平坦层9；所述平坦层9的材料为PFA(可溶性聚四氟乙烯)。
步骤6、如图16、图17所示，在所述平坦层9上沉积第一透明导电膜，并对所述第一透明导电膜进行图案化处理，形成第一像素电极10。
具体的，采用物理气相沉积法(PVD)沉积所述第一透明导电膜；采用湿法蚀刻(Wet Etch)制程形成所述第一像素电极10；所述第一像素电极10的材料为ITO(氧化铟锡)。
步骤7、如图18所示，在所述第一钝化层8、及平坦层9上对应所述漏极7的上方依次形成第一过孔91、及第二过孔92，所述第一过孔91、及第二过孔92暴露出部分漏极7。
具体的，先采用黄光制程在所述平坦层9上对应所述漏极7上方曝光出第一过孔91，然后以所述平坦层9为自对准光罩，采用干法蚀刻(Dry Etch)制程在所述第一钝化层8上对应所述第一过孔91蚀刻出第二过孔92。
步骤8、如图19所示，在所述第一像素电极10及平坦层9上沉积第二钝化层11，并对所述第二钝化层11进行图案化处理，在所述第二钝化层11上形成一对应于所述第一过孔91与第二过孔92的第三过孔93。
优选的，所述第二钝化层11的材料为氧化硅、氮化硅、或二者的堆栈组合。
步骤9、如图20所示，在所述第二钝化层11上沉积第二透明导电膜，并对所述第二透明导电膜进行图案化处理，形成第二像素电极12，所述第二像素电极12经由第一、第二、第三过孔91、92、93与漏极7相连。
优选的，所述第一像素电极12的材料为ITO(氧化铟锡)。
综上所述，本发明的TFT基板结构的制作方法，在依次形成第一钝化层、平坦层、及第一透明导电膜之后，先对第一透明导电膜进行图案化处理，形成第一像素电极，之后再采用黄光制程在平坦层上对应漏极上方曝光出第一过孔，然后以平坦层为自对准光罩，采用干法蚀刻制程在第一钝化层上对应第一过孔蚀刻出第二过孔，从而有效防止第一透明导电膜在第一、第二过孔处的残留，提高了生产良率，同时减少一道光罩，避免了由于对位不准造成的开口率降低，提高了生产效率，降低了生产成本，提高了产品价格的竞争力。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (16)

  1. 一种TFT基板结构的制作方法，包括如下步骤；
    步骤1、提供基板，在所述基板上沉积缓冲层；在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述缓冲层、及栅极上沉积栅极绝缘层；在所述栅极绝缘层上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层；
    步骤3、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极、及漏极；
    步骤4、在所述栅极绝缘层、岛状半导体层、源极、及漏极上沉积第一钝化层；
    步骤5、在所述第一钝化层上形成平坦层；
    步骤6、在所述平坦层上沉积第一透明导电膜，并对所述第一透明导电膜进行图案化处理，形成第一像素电极；
    步骤7、在所述第一钝化层、及平坦层上对应所述漏极的上方依次形成第一过孔、及第二过孔，所述第一过孔、及第二过孔暴露出部分漏极；
    步骤8、在所述第一像素电极及平坦层上沉积第二钝化层，并对所述第二钝化层进行图案化处理，在所述第二钝化层上形成一对应于所述第一过孔与第二过孔的第三过孔；
    步骤9、在所述第二钝化层上沉积第二透明导电膜，并对所述第二透明导电膜进行图案化处理，形成第二像素电极，所述第二像素电极经由第一、第二、第三过孔与漏极相连。
  2. 如权利要求1所述的TFT基板结构的制作方法，其中，所述氧化物半导体层的材料为IGZO。
  3. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤4采用化学气相沉积法沉积所述第一钝化层。
  4. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤5采用涂布制程形成所述平坦层；所述平坦层的材料为PFA。
  5. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤6采用物理气相沉积法沉积所述第一透明导电膜；采用湿法蚀刻制程形成所述第一像素电极。
  6. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤7 先采用黄光制程在所述平坦层上对应所述漏极上方曝光出第一过孔，然后以所述平坦层为自对准光罩，采用干法蚀刻制程在所述第一钝化层上对应所述第一过孔蚀刻出第二过孔。
  7. 如权利要求1所述的TFT基板结构的制作方法，其中，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  8. 如权利要求1所述的TFT基板结构的制作方法，其中，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  9. 如权利要求1所述的TFT基板结构的制作方法，其中，所述栅极绝缘层、第一钝化层、及第二钝化层的材料为氧化硅、氮化硅、或二者的堆栈组合。
  10. 如权利要求1所述的TFT基板结构的制作方法，其中，所述第一像素电极、及第二像素电极的材料均为ITO。
  11. 一种TFT基板结构的制作方法，包括如下步骤；
    步骤1、提供基板，在所述基板上沉积缓冲层；在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述缓冲层、及栅极上沉积栅极绝缘层；在所述栅极绝缘层上沉积氧化物半导体层，并对所述氧化物半导体层进行图案化处理，形成岛状半导体层；
    步骤3、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到源极、及漏极；
    步骤4、在所述栅极绝缘层、岛状半导体层、源极、及漏极上沉积第一钝化层；
    步骤5、在所述第一钝化层上形成平坦层；
    步骤6、在所述平坦层上沉积第一透明导电膜，并对所述第一透明导电膜进行图案化处理，形成第一像素电极；
    步骤7、在所述第一钝化层、及平坦层上对应所述漏极的上方依次形成第一过孔、及第二过孔，所述第一过孔、及第二过孔暴露出部分漏极；
    步骤8、在所述第一像素电极及平坦层上沉积第二钝化层，并对所述第二钝化层进行图案化处理，在所述第二钝化层上形成一对应于所述第一过孔与第二过孔的第三过孔；
    步骤9、在所述第二钝化层上沉积第二透明导电膜，并对所述第二透明导电膜进行图案化处理，形成第二像素电极，所述第二像素电极经由第一、第二、第三过孔与漏极相连；
    其中，所述步骤4采用化学气相沉积法沉积所述第一钝化层；
    其中，所述步骤5采用涂布制程形成所述平坦层；所述平坦层的材料为PFA；
    其中，所述步骤6采用物理气相沉积法沉积所述第一透明导电膜；采用湿法蚀刻制程形成所述第一像素电极；
    其中，所述步骤7先采用黄光制程在所述平坦层上对应所述漏极上方曝光出第一过孔，然后以所述平坦层为自对准光罩，采用干法蚀刻制程在所述第一钝化层上对应所述第一过孔蚀刻出第二过孔。
  12. 如权利要求11所述的TFT基板结构的制作方法，其中，所述氧化物半导体层的材料为IGZO。
  13. 如权利要求11所述的TFT基板结构的制作方法，其中，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  14. 如权利要求11所述的TFT基板结构的制作方法，其中，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  15. 如权利要求11所述的TFT基板结构的制作方法，其中，所述栅极绝缘层、第一钝化层、及第二钝化层的材料为氧化硅、氮化硅、或二者的堆栈组合。
  16. 如权利要求11所述的TFT基板结构的制作方法，其中，所述第一像素电极、及第二像素电极的材料均为ITO。
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